ceph/src/seastar/dpdk/drivers/net/sfc/base/ef10_tlv_layout.h

   1 /**************************************************************************\
   2 *//*! \file
   3 ** <L5_PRIVATE L5_SOURCE>
   4 ** \author  mjs
   5 **  \brief  TLV item layouts for EF10 static and dynamic config in NVRAM
   6 **   \date  2012/11/20
   7 **    \cop  (c) Solarflare Communications Inc.
   8 ** </L5_PRIVATE>
   9 *//*
  10 \**************************************************************************/
  11
  12 /* These structures define the layouts for the TLV items stored in static and
  13  * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
  14  *
  15  * They contain the same sort of information that was kept in the
  16  * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
  17  * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
  18  * Siena.
  19  *
  20  * These are used directly by the MC and should also be usable directly on host
  21  * systems which are little-endian and do not do strange things with structure
  22  * padding.  (Big-endian host systems will require some byte-swapping.)
  23  *
  24  *                                    -----
  25  *
  26  * Please refer to SF-108797-SW for a general overview of the TLV partition
  27  * format.
  28  *
  29  *                                    -----
  30  *
  31  * The current tag IDs have a general structure: with the exception of the
  32  * special values defined in the document, they are of the form 0xLTTTNNNN,
  33  * where:
  34  *
  35  *   -  L is a location, indicating where this tag is expected to be found:
  36  *        0: static configuration
  37  *        1: dynamic configuration
  38  *        2: firmware internal use
  39  *        3: license partition
  40  *
  41  *   -  TTT is a type, which is just a unique value.  The same type value
  42  *      might appear in both locations, indicating a relationship between
  43  *      the items (e.g. static and dynamic VPD below).
  44  *
  45  *   -  NNNN is an index of some form.  Some item types are per-port, some
  46  *      are per-PF, some are per-partition-type.
  47  *
  48  *                                    -----
  49  *
  50  * As with the previous Siena structures, each structure here is laid out
  51  * carefully: values are aligned to their natural boundary, with explicit
  52  * padding fields added where necessary.  (No, technically this does not
  53  * absolutely guarantee portability.  But, in practice, compilers are generally
  54  * sensible enough not to introduce completely pointless padding, and it works
  55  * well enough.)
  56  */
  57
  58
  59 #ifndef CI_MGMT_TLV_LAYOUT_H
  60 #define CI_MGMT_TLV_LAYOUT_H
  61
  62
  63 /* ----------------------------------------------------------------------------
  64  *  General structure (defined by SF-108797-SW)
  65  * ----------------------------------------------------------------------------
  66  */
  67
  68
  69 /* The "end" tag.
  70  *
  71  * (Note that this is *not* followed by length or value fields: anything after
  72  * the tag itself is irrelevant.)
  73  */
  74
  75 #define TLV_TAG_END                     (0xEEEEEEEE)
  76
  77
  78 /* Other special reserved tag values.
  79  */
  80
  81 #define TLV_TAG_SKIP                    (0x00000000)
  82 #define TLV_TAG_INVALID                 (0xFFFFFFFF)
  83
  84
  85 /* TLV partition header.
  86  *
  87  * In a TLV partition, this must be the first item in the sequence, at offset
  88  * 0.
  89  */
  90
  91 #define TLV_TAG_PARTITION_HEADER        (0xEF10DA7A)
  92
  93 struct tlv_partition_header {
  94   uint32_t tag;
  95   uint32_t length;
  96   uint16_t type_id;
  97 /* 0 indicates the default segment (always located at offset 0), while other values
  98  * are for RFID-selectable presets that should immediately follow the default segment.
  99  * The default segment may also have preset > 0, which means that it is a preset
 100  * selected through an RFID command and copied by FW to the location at offset 0. */
 101   uint16_t preset;
 102   uint32_t generation;
 103   uint32_t total_length;
 104 };
 105
 106
 107 /* TLV partition trailer.
 108  *
 109  * In a TLV partition, this must be the last item in the sequence, immediately
 110  * preceding the TLV_TAG_END word.
 111  */
 112
 113 #define TLV_TAG_PARTITION_TRAILER       (0xEF101A57)
 114
 115 struct tlv_partition_trailer {
 116   uint32_t tag;
 117   uint32_t length;
 118   uint32_t generation;
 119   uint32_t checksum;
 120 };
 121
 122
 123 /* Appendable TLV partition header.
 124  *
 125  * In an appendable TLV partition, this must be the first item in the sequence,
 126  * at offset 0.  (Note that, unlike the configuration partitions, there is no
 127  * trailer before the TLV_TAG_END word.)
 128  */
 129
 130 #define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
 131
 132 struct tlv_appendable_partition_header {
 133   uint32_t tag;
 134   uint32_t length;
 135   uint16_t type_id;
 136   uint16_t reserved;
 137 };
 138
 139
 140 /* ----------------------------------------------------------------------------
 141  *  Configuration items
 142  * ----------------------------------------------------------------------------
 143  */
 144
 145
 146 /* NIC global capabilities.
 147  */
 148
 149 #define TLV_TAG_GLOBAL_CAPABILITIES     (0x00010000)
 150
 151 struct tlv_global_capabilities {
 152   uint32_t tag;
 153   uint32_t length;
 154   uint32_t flags;
 155 };
 156
 157
 158 /* Siena-style per-port MAC address allocation.
 159  *
 160  * There are <count> addresses, starting at <base_address> and incrementing
 161  * by adding <stride> to the low-order byte(s).
 162  *
 163  * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
 164  * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
 165  */
 166
 167 #define TLV_TAG_PORT_MAC(port)          (0x00020000 + (port))
 168
 169 struct tlv_port_mac {
 170   uint32_t tag;
 171   uint32_t length;
 172   uint8_t  base_address[6];
 173   uint16_t reserved;
 174   uint16_t count;
 175   uint16_t stride;
 176 };
 177
 178
 179 /* Static VPD.
 180  *
 181  * This is the portion of VPD which is set at manufacturing time and not
 182  * expected to change.  It is formatted as a standard PCI VPD block. There are
 183  * global and per-pf TLVs for this, the global TLV is new for Medford and is
 184  * used in preference to the per-pf TLV.
 185  */
 186
 187 #define TLV_TAG_PF_STATIC_VPD(pf)       (0x00030000 + (pf))
 188
 189 struct tlv_pf_static_vpd {
 190   uint32_t tag;
 191   uint32_t length;
 192   uint8_t  bytes[];
 193 };
 194
 195 #define TLV_TAG_GLOBAL_STATIC_VPD       (0x001f0000)
 196
 197 struct tlv_global_static_vpd {
 198   uint32_t tag;
 199   uint32_t length;
 200   uint8_t  bytes[];
 201 };
 202
 203
 204 /* Dynamic VPD.
 205  *
 206  * This is the portion of VPD which may be changed (e.g. by firmware updates).
 207  * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
 208  * for this, the global TLV is new for Medford and is used in preference to the
 209  * per-pf TLV.
 210  */
 211
 212 #define TLV_TAG_PF_DYNAMIC_VPD(pf)      (0x10030000 + (pf))
 213
 214 struct tlv_pf_dynamic_vpd {
 215   uint32_t tag;
 216   uint32_t length;
 217   uint8_t  bytes[];
 218 };
 219
 220 #define TLV_TAG_GLOBAL_DYNAMIC_VPD      (0x10200000)
 221
 222 struct tlv_global_dynamic_vpd {
 223   uint32_t tag;
 224   uint32_t length;
 225   uint8_t  bytes[];
 226 };
 227
 228
 229 /* "DBI" PCI config space changes.
 230  *
 231  * This is a set of edits made to the default PCI config space values before
 232  * the device is allowed to enumerate. There are global and per-pf TLVs for
 233  * this, the global TLV is new for Medford and is used in preference to the
 234  * per-pf TLV.
 235  */
 236
 237 #define TLV_TAG_PF_DBI(pf)              (0x00040000 + (pf))
 238
 239 struct tlv_pf_dbi {
 240   uint32_t tag;
 241   uint32_t length;
 242   struct {
 243     uint16_t addr;
 244     uint16_t byte_enables;
 245     uint32_t value;
 246   } items[];
 247 };
 248
 249
 250 #define TLV_TAG_GLOBAL_DBI              (0x00210000)
 251
 252 struct tlv_global_dbi {
 253   uint32_t tag;
 254   uint32_t length;
 255   struct {
 256     uint16_t addr;
 257     uint16_t byte_enables;
 258     uint32_t value;
 259   } items[];
 260 };
 261
 262
 263 /* Partition subtype codes.
 264  *
 265  * A subtype may optionally be stored for each type of partition present in
 266  * the NVRAM.  For example, this may be used to allow a generic firmware update
 267  * utility to select a specific variant of firmware for a specific variant of
 268  * board.
 269  *
 270  * The description[] field is an optional string which is returned in the
 271  * MC_CMD_NVRAM_METADATA response if present.
 272  */
 273
 274 #define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
 275
 276 struct tlv_partition_subtype {
 277   uint32_t tag;
 278   uint32_t length;
 279   uint32_t subtype;
 280   uint8_t  description[];
 281 };
 282
 283
 284 /* Partition version codes.
 285  *
 286  * A version may optionally be stored for each type of partition present in
 287  * the NVRAM.  This provides a standard way of tracking the currently stored
 288  * version of each of the various component images.
 289  */
 290
 291 #define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
 292
 293 struct tlv_partition_version {
 294   uint32_t tag;
 295   uint32_t length;
 296   uint16_t version_w;
 297   uint16_t version_x;
 298   uint16_t version_y;
 299   uint16_t version_z;
 300 };
 301
 302 /* Global PCIe configuration */
 303
 304 #define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
 305
 306 struct tlv_pcie_config {
 307   uint32_t tag;
 308   uint32_t length;
 309   int16_t max_pf_number;                        /**< Largest PF RID (lower PFs may be hidden) */
 310   uint16_t pf_aper;                             /**< BIU aperture for PF BAR2 */
 311   uint16_t vf_aper;                             /**< BIU aperture for VF BAR0 */
 312   uint16_t int_aper;                            /**< BIU aperture for PF BAR4 and VF BAR2 */
 313 #define TLV_MAX_PF_DEFAULT (-1)                 /* Use FW default for largest PF RID  */
 314 #define TLV_APER_DEFAULT (0xFFFF)               /* Use FW default for a given aperture */
 315 };
 316
 317 /* Per-PF configuration. Note that not all these fields are necessarily useful
 318  * as the apertures are constrained by the BIU settings (the one case we do
 319  * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
 320  * tidy things up later */
 321
 322 #define TLV_TAG_PF_PCIE_CONFIG(pf)  (0x10080000 + (pf))
 323
 324 struct tlv_per_pf_pcie_config {
 325   uint32_t tag;
 326   uint32_t length;
 327   uint8_t vfs_total;
 328   uint8_t port_allocation;
 329   uint16_t vectors_per_pf;
 330   uint16_t vectors_per_vf;
 331   uint8_t pf_bar0_aperture;
 332   uint8_t pf_bar2_aperture;
 333   uint8_t vf_bar0_aperture;
 334   uint8_t vf_base;
 335   uint16_t supp_pagesz;
 336   uint16_t msix_vec_base;
 337 };
 338
 339
 340 /* Development ONLY. This is a single TLV tag for all the gubbins
 341  * that can be set through the MC command-line other than the PCIe
 342  * settings. This is a temporary measure. */
 343 #define TLV_TAG_TMP_GUBBINS (0x10090000)        /* legacy symbol - do not use */
 344 #define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
 345
 346 struct tlv_tmp_gubbins {
 347   uint32_t tag;
 348   uint32_t length;
 349   /* Consumed by dpcpu.c */
 350   uint64_t tx0_tags;     /* Bitmap */
 351   uint64_t tx1_tags;     /* Bitmap */
 352   uint64_t dl_tags;      /* Bitmap */
 353   uint32_t flags;
 354 #define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
 355 #define TLV_DPCPU_BIU_TAGS  (2) /* Use BIU tag manager */
 356 #define TLV_DPCPU_TX0_TAGS  (4) /* tx0_tags is valid */
 357 #define TLV_DPCPU_TX1_TAGS  (8) /* tx1_tags is valid */
 358 #define TLV_DPCPU_DL_TAGS  (16) /* dl_tags is valid */
 359   /* Consumed by features.c */
 360   uint32_t dut_features;        /* All 1s -> leave alone */
 361   int8_t with_rmon;             /* 0 -> off, 1 -> on, -1 -> leave alone */
 362   /* Consumed by clocks_hunt.c */
 363   int8_t clk_mode;             /* 0 -> off, 1 -> on, -1 -> leave alone */
 364   /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
 365   int8_t rx_dc_size;           /* -1 -> leave alone */
 366   int8_t tx_dc_size;
 367   int16_t num_q_allocs;
 368 };
 369
 370 /* Global port configuration
 371  *
 372  * This is now deprecated in favour of a platform-provided default
 373  * and dynamic config override via tlv_global_port_options.
 374  */
 375 #define TLV_TAG_GLOBAL_PORT_CONFIG      (0x000a0000)
 376
 377 struct tlv_global_port_config {
 378   uint32_t tag;
 379   uint32_t length;
 380   uint32_t ports_per_core;
 381   uint32_t max_port_speed;
 382 };
 383
 384
 385 /* Firmware options.
 386  *
 387  * This is intended for user-configurable selection of optional firmware
 388  * features and variants.
 389  *
 390  * Initially, this consists only of the satellite CPU firmware variant
 391  * selection, but this tag could be extended in the future (using the
 392  * tag length to determine whether additional fields are present).
 393  */
 394
 395 #define TLV_TAG_FIRMWARE_OPTIONS        (0x100b0000)
 396
 397 struct tlv_firmware_options {
 398   uint32_t tag;
 399   uint32_t length;
 400   uint32_t firmware_variant;
 401 #define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
 402
 403 /* These are the values for overriding the driver's choice; the definitions
 404  * are taken from MCDI so that they don't get out of step.  Include
 405  * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
 406  * you need to use these constants.
 407  */
 408 #define TLV_FIRMWARE_VARIANT_FULL_FEATURED   MC_CMD_FW_FULL_FEATURED
 409 #define TLV_FIRMWARE_VARIANT_LOW_LATENCY     MC_CMD_FW_LOW_LATENCY
 410 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM   MC_CMD_FW_PACKED_STREAM
 411 #define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE    MC_CMD_FW_HIGH_TX_RATE
 412 #define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
 413                                              MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
 414 #define TLV_FIRMWARE_VARIANT_RULES_ENGINE    MC_CMD_FW_RULES_ENGINE
 415 };
 416
 417 /* Voltage settings
 418  *
 419  * Intended for boards with A0 silicon where the core voltage may
 420  * need tweaking. Most likely set once when the pass voltage is
 421  * determined. */
 422
 423 #define TLV_TAG_0V9_SETTINGS (0x000c0000)
 424
 425 struct tlv_0v9_settings {
 426   uint32_t tag;
 427   uint32_t length;
 428   uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
 429 #define TLV_TAG_0V9_REQUIRES_FAN (1)
 430   uint16_t target_voltage; /* In millivolts */
 431   /* Since the limits are meant to be centred to the target (and must at least
 432    * contain it) they need setting as well. */
 433   uint16_t warn_low;       /* In millivolts */
 434   uint16_t warn_high;      /* In millivolts */
 435   uint16_t panic_low;      /* In millivolts */
 436   uint16_t panic_high;     /* In millivolts */
 437 };
 438
 439
 440 /* Clock configuration */
 441
 442 #define TLV_TAG_CLOCK_CONFIG       (0x000d0000) /* legacy symbol - do not use */
 443 #define TLV_TAG_CLOCK_CONFIG_HUNT  TLV_TAG_CLOCK_CONFIG
 444
 445 struct tlv_clock_config {
 446   uint32_t tag;
 447   uint32_t length;
 448   uint16_t clk_sys;        /* MHz */
 449   uint16_t clk_dpcpu;      /* MHz */
 450   uint16_t clk_icore;      /* MHz */
 451   uint16_t clk_pcs;        /* MHz */
 452 };
 453
 454 #define TLV_TAG_CLOCK_CONFIG_MEDFORD      (0x00100000)
 455
 456 struct tlv_clock_config_medford {
 457   uint32_t tag;
 458   uint32_t length;
 459   uint16_t clk_sys;        /* MHz */
 460   uint16_t clk_mc;         /* MHz */
 461   uint16_t clk_rmon;       /* MHz */
 462   uint16_t clk_vswitch;    /* MHz */
 463   uint16_t clk_dpcpu;      /* MHz */
 464   uint16_t clk_pcs;        /* MHz */
 465 };
 466
 467
 468 /* EF10-style global pool of MAC addresses.
 469  *
 470  * There are <count> addresses, starting at <base_address>, which are
 471  * contiguous.  Firmware is responsible for allocating addresses from this
 472  * pool to ports / PFs as appropriate.
 473  */
 474
 475 #define TLV_TAG_GLOBAL_MAC              (0x000e0000)
 476
 477 struct tlv_global_mac {
 478   uint32_t tag;
 479   uint32_t length;
 480   uint8_t  base_address[6];
 481   uint16_t reserved1;
 482   uint16_t count;
 483   uint16_t reserved2;
 484 };
 485
 486 #define TLV_TAG_ATB_0V9_TARGET     (0x000f0000) /* legacy symbol - do not use */
 487 #define TLV_TAG_ATB_0V9_TARGET_HUNT     TLV_TAG_ATB_0V9_TARGET
 488
 489 /* The target value for the 0v9 power rail measured on-chip at the
 490  * analogue test bus */
 491 struct tlv_0v9_atb_target {
 492   uint32_t tag;
 493   uint32_t length;
 494   uint16_t millivolts;
 495   uint16_t reserved;
 496 };
 497
 498 /* Factory settings for amplitude calibration of the PCIE TX serdes */
 499 #define TLV_TAG_TX_PCIE_AMP_CONFIG  (0x00220000)
 500 struct tlv_pcie_tx_amp_config {
 501   uint32_t tag;
 502   uint32_t length;
 503   uint8_t quad_tx_imp2k[4];
 504   uint8_t quad_tx_imp50[4];
 505   uint8_t lane_amp[16];
 506 };
 507
 508
 509 /* Global PCIe configuration, second revision. This represents the visible PFs
 510  * by a bitmap rather than having the number of the highest visible one. As such
 511  * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
 512  * can and it should be used in place of that tag in future (but compatibility with
 513  * the old tag will be left in the firmware indefinitely).  */
 514
 515 #define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
 516
 517 struct tlv_pcie_config_r2 {
 518   uint32_t tag;
 519   uint32_t length;
 520   uint16_t visible_pfs;                         /**< Bitmap of visible PFs */
 521   uint16_t pf_aper;                             /**< BIU aperture for PF BAR2 */
 522   uint16_t vf_aper;                             /**< BIU aperture for VF BAR0 */
 523   uint16_t int_aper;                            /**< BIU aperture for PF BAR4 and VF BAR2 */
 524 };
 525
 526 /* Dynamic port mode.
 527  *
 528  * Allows selecting alternate port configuration for platforms that support it
 529  * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
 530  * number of externally visible ports (and, hence, PF to port mapping), so must
 531  * be done at boot time.
 532  *
 533  * This tag supercedes tlv_global_port_config.
 534  */
 535
 536 #define TLV_TAG_GLOBAL_PORT_MODE         (0x10110000)
 537
 538 struct tlv_global_port_mode {
 539   uint32_t tag;
 540   uint32_t length;
 541   uint32_t port_mode;
 542 #define TLV_PORT_MODE_DEFAULT           (0xffffffff) /* Default for given platform */
 543 #define TLV_PORT_MODE_10G                        (0) /* 10G, single SFP/10G-KR */
 544 #define TLV_PORT_MODE_40G                        (1) /* 40G, single QSFP/40G-KR */
 545 #define TLV_PORT_MODE_10G_10G                    (2) /* 2x10G, dual SFP/10G-KR or single QSFP */
 546 #define TLV_PORT_MODE_40G_40G                    (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */
 547 #define TLV_PORT_MODE_10G_10G_10G_10G            (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport) */
 548 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1         (4) /* 4x10G, single QSFP, cage 0 (Medford) */
 549 #define TLV_PORT_MODE_10G_10G_10G_10G_Q          (5) /* 4x10G, single QSFP, cage 0 (Medford) OBSOLETE DO NOT USE */
 550 #define TLV_PORT_MODE_40G_10G_10G                (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */
 551 #define TLV_PORT_MODE_10G_10G_40G                (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */
 552 #define TLV_PORT_MODE_10G_10G_10G_10G_Q2         (8) /* 4x10G, single QSFP, cage 1 (Medford) */
 553 #define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2      (9) /* 2x10G + 2x10G, dual QSFP (Medford) */
 554 #define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2
 555 };
 556
 557 /* Type of the v-switch created implicitly by the firmware */
 558
 559 #define TLV_TAG_VSWITCH_TYPE(port)       (0x10120000 + (port))
 560
 561 struct tlv_vswitch_type {
 562   uint32_t tag;
 563   uint32_t length;
 564   uint32_t vswitch_type;
 565 #define TLV_VSWITCH_TYPE_DEFAULT        (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
 566 #define TLV_VSWITCH_TYPE_NONE                    (0)
 567 #define TLV_VSWITCH_TYPE_VLAN                    (1)
 568 #define TLV_VSWITCH_TYPE_VEB                     (2)
 569 #define TLV_VSWITCH_TYPE_VEPA                    (3)
 570 #define TLV_VSWITCH_TYPE_MUX                     (4)
 571 #define TLV_VSWITCH_TYPE_TEST                    (5)
 572 };
 573
 574 /* A VLAN tag for the v-port created implicitly by the firmware */
 575
 576 #define TLV_TAG_VPORT_VLAN_TAG(pf)               (0x10130000 + (pf))
 577
 578 struct tlv_vport_vlan_tag {
 579   uint32_t tag;
 580   uint32_t length;
 581   uint32_t vlan_tag;
 582 #define TLV_VPORT_NO_VLAN_TAG                    (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
 583 };
 584
 585 /* Offset to be applied to the 0v9 setting, wherever it came from */
 586
 587 #define TLV_TAG_ATB_0V9_OFFSET           (0x10140000)
 588
 589 struct tlv_0v9_atb_offset {
 590   uint32_t tag;
 591   uint32_t length;
 592   int16_t  offset_millivolts;
 593   uint16_t reserved;
 594 };
 595
 596 /* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
 597  * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
 598  * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
 599  * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
 600  * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
 601
 602 #define TLV_TAG_PRIVILEGE_MASK          (0x10150000) /* legacy symbol - do not use */
 603
 604 struct tlv_privilege_mask {                          /* legacy structure - do not use */
 605   uint32_t tag;
 606   uint32_t length;
 607   uint32_t privilege_mask;
 608 };
 609
 610 #define TLV_TAG_PRIVILEGE_MASK_ADD      (0x10150000)
 611
 612 struct tlv_privilege_mask_add {
 613   uint32_t tag;
 614   uint32_t length;
 615   uint32_t privilege_mask_add;
 616 };
 617
 618 #define TLV_TAG_PRIVILEGE_MASK_REM      (0x10160000)
 619
 620 struct tlv_privilege_mask_rem {
 621   uint32_t tag;
 622   uint32_t length;
 623   uint32_t privilege_mask_rem;
 624 };
 625
 626 /* Additional privileges given to all PFs.
 627  * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
 628
 629 #define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS         (0x10190000)
 630
 631 struct tlv_privilege_mask_add_all_pfs {
 632   uint32_t tag;
 633   uint32_t length;
 634   uint32_t privilege_mask_add;
 635 };
 636
 637 /* Additional privileges given to a selected PF.
 638  * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
 639
 640 #define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf)   (0x101A0000 + (pf))
 641
 642 struct tlv_privilege_mask_add_single_pf {
 643   uint32_t tag;
 644   uint32_t length;
 645   uint32_t privilege_mask_add;
 646 };
 647
 648 /* Turning on/off the PFIOV mode.
 649  * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
 650
 651 #define TLV_TAG_PFIOV(port)             (0x10170000 + (port))
 652
 653 struct tlv_pfiov {
 654   uint32_t tag;
 655   uint32_t length;
 656   uint32_t pfiov;
 657 #define TLV_PFIOV_OFF                    (0) /* Default */
 658 #define TLV_PFIOV_ON                     (1)
 659 };
 660
 661 /* Multicast filter chaining mode selection.
 662  *
 663  * When enabled, multicast packets are delivered to all recipients of all
 664  * matching multicast filters, with the exception that IP multicast filters
 665  * will steal traffic from MAC multicast filters on a per-function basis.
 666  * (New behaviour.)
 667  *
 668  * When disabled, multicast packets will always be delivered only to the
 669  * recipients of the highest priority matching multicast filter.
 670  * (Legacy behaviour.)
 671  *
 672  * The DEFAULT mode (which is the same as the tag not being present at all)
 673  * is equivalent to ENABLED in production builds, and DISABLED in eftest
 674  * builds.
 675  *
 676  * This option is intended to provide run-time control over this feature
 677  * while it is being stabilised and may be withdrawn at some point in the
 678  * future; the new behaviour is intended to become the standard behaviour.
 679  */
 680
 681 #define TLV_TAG_MCAST_FILTER_CHAINING   (0x10180000)
 682
 683 struct tlv_mcast_filter_chaining {
 684   uint32_t tag;
 685   uint32_t length;
 686   uint32_t mode;
 687 #define TLV_MCAST_FILTER_CHAINING_DEFAULT  (0xffffffff)
 688 #define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
 689 #define TLV_MCAST_FILTER_CHAINING_ENABLED  (1)
 690 };
 691
 692 /* Pacer rate limit per PF */
 693 #define TLV_TAG_RATE_LIMIT(pf)    (0x101b0000 + (pf))
 694
 695 struct tlv_rate_limit {
 696   uint32_t tag;
 697   uint32_t length;
 698   uint32_t rate_mbps;
 699 };
 700
 701 /* OCSD Enable/Disable
 702  *
 703  * This setting allows OCSD to be disabled. This is a requirement for HP
 704  * servers to support PCI passthrough for virtualization.
 705  *
 706  * The DEFAULT mode (which is the same as the tag not being present) is
 707  * equivalent to ENABLED.
 708  *
 709  * This option is not used by the MCFW, and is entirely handled by the various
 710  * drivers that support OCSD, by reading the setting before they attempt
 711  * to enable OCSD.
 712  *
 713  * bit0: OCSD Disabled/Enabled
 714  */
 715
 716 #define TLV_TAG_OCSD (0x101C0000)
 717
 718 struct tlv_ocsd {
 719   uint32_t tag;
 720   uint32_t length;
 721   uint32_t mode;
 722 #define TLV_OCSD_DISABLED 0
 723 #define TLV_OCSD_ENABLED 1 /* Default */
 724 };
 725
 726 /* Descriptor cache config.
 727  *
 728  * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
 729  * sets the total number of VIs. When the number of VIs is reduced VIs are taken
 730  * away from the highest numbered port first, so a vi_count of 1024 means 1024
 731  * VIs on the first port and 0 on the second (on a Torino).
 732  */
 733
 734 #define TLV_TAG_DESCRIPTOR_CACHE_CONFIG    (0x101d0000)
 735
 736 struct tlv_descriptor_cache_config {
 737   uint32_t tag;
 738   uint32_t length;
 739   uint8_t rx_desc_cache_size;
 740   uint8_t tx_desc_cache_size;
 741   uint16_t vi_count;
 742 };
 743 #define TLV_DESC_CACHE_DEFAULT (0xff)
 744 #define TLV_VI_COUNT_DEFAULT   (0xffff)
 745
 746 /* RX event merging config (read batching).
 747  *
 748  * Sets the global maximum number of events for the merging bins, and the
 749  * global timeout configuration for the bins.
 750  */
 751
 752 #define TLV_TAG_RX_EVENT_MERGING_CONFIG    (0x101e0000)
 753
 754 struct tlv_rx_event_merging_config {
 755   uint32_t  tag;
 756   uint32_t  length;
 757   uint32_t  max_events;
 758 #define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
 759   uint32_t  timeout_ns;
 760 };
 761 #define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
 762 #define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
 763
 764 #define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
 765 struct tlv_pcie_link_settings {
 766   uint32_t tag;
 767   uint32_t length;
 768   uint16_t gen;   /* Target PCIe generation: 1, 2, 3 */
 769   uint16_t width; /* Number of lanes */
 770 };
 771
 772 /* TX event merging config.
 773  *
 774  * Sets the global maximum number of events for the merging bins, and the
 775  * global timeout configuration for the bins, and the global timeout for
 776  * empty queues.
 777  */
 778 #define TLV_TAG_TX_EVENT_MERGING_CONFIG    (0x10210000)
 779 struct tlv_tx_event_merging_config {
 780   uint32_t  tag;
 781   uint32_t  length;
 782   uint32_t  max_events;
 783 #define TLV_TX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
 784   uint32_t  timeout_ns;
 785   uint32_t  qempty_timeout_ns; /* Medford only */
 786 };
 787 #define TLV_TX_EVENT_MERGING_MAX_EVENTS_DEFAULT (0xffffffff)
 788 #define TLV_TX_EVENT_MERGING_TIMEOUT_NS_DEFAULT (0xffffffff)
 789 #define TLV_TX_EVENT_MERGING_QEMPTY_TIMEOUT_NS_DEFAULT (0xffffffff)
 790
 791 #define TLV_TAG_LICENSE (0x30800000)
 792
 793 typedef struct tlv_license {
 794   uint32_t  tag;
 795   uint32_t  length;
 796   uint8_t   data[];
 797 } tlv_license_t;
 798
 799 /* TSA NIC IP address configuration
 800  *
 801  * Sets the TSA NIC IP address statically via configuration tool or dynamically
 802  * via DHCP via snooping based on the mode selection (0=Static, 1=DHCP, 2=Snoop)
 803  *
 804  * NOTE: This TAG is temporarily placed in the dynamic config partition and will
 805  * be moved to a private partition during TSA development. It is not used in any
 806  * released code yet.
 807  */
 808
 809 #define TLV_TAG_TMP_TSAN_CONFIG         (0x10220000)
 810
 811 #define TLV_TSAN_IP_MODE_STATIC         (0)
 812 #define TLV_TSAN_IP_MODE_DHCP           (1)
 813 #define TLV_TSAN_IP_MODE_SNOOP          (2)
 814 typedef struct tlv_tsan_config {
 815   uint32_t tag;
 816   uint32_t length;
 817   uint32_t mode;
 818   uint32_t ip;
 819   uint32_t netmask;
 820   uint32_t gateway;
 821   uint32_t port;
 822   uint32_t bind_retry;  /* DEPRECATED */
 823   uint32_t bind_bkout;  /* DEPRECATED */
 824 } tlv_tsan_config_t;
 825
 826 /* TSA Controller IP address configuration
 827  *
 828  * Sets the TSA Controller IP address statically via configuration tool
 829  *
 830  * NOTE: This TAG is temporarily placed in the dynamic config partition and will
 831  * be moved to a private partition during TSA development. It is not used in any
 832  * released code yet.
 833  */
 834
 835 #define TLV_TAG_TMP_TSAC_CONFIG         (0x10230000)
 836
 837 #define TLV_MAX_TSACS (4)
 838 typedef struct tlv_tsac_config {
 839   uint32_t tag;
 840   uint32_t length;
 841   uint32_t num_tsacs;
 842   uint32_t ip[TLV_MAX_TSACS];
 843   uint32_t port[TLV_MAX_TSACS];
 844 } tlv_tsac_config_t;
 845
 846 /* Binding ticket
 847  *
 848  * Sets the TSA NIC binding ticket used for binding process between the TSA NIC
 849  * and the TSA Controller
 850  *
 851  * NOTE: This TAG is temporarily placed in the dynamic config partition and will
 852  * be moved to a private partition during TSA development. It is not used in any
 853  * released code yet.
 854  */
 855
 856 #define TLV_TAG_TMP_BINDING_TICKET      (0x10240000)
 857
 858 typedef struct tlv_binding_ticket {
 859   uint32_t tag;
 860   uint32_t length;
 861   uint8_t  bytes[];
 862 } tlv_binding_ticket_t;
 863
 864 /* Solarflare private key  (DEPRECATED)
 865  *
 866  * Sets the Solareflare private key used for signing during the binding process
 867  *
 868  * NOTE: This TAG is temporarily placed in the dynamic config partition and will
 869  * be moved to a private partition during TSA development. It is not used in any
 870  * released code yet.
 871  */
 872
 873 #define TLV_TAG_TMP_PIK_SF              (0x10250000)    /* DEPRECATED */
 874
 875 typedef struct tlv_pik_sf {
 876   uint32_t tag;
 877   uint32_t length;
 878   uint8_t  bytes[];
 879 } tlv_pik_sf_t;
 880
 881 /* CA root certificate
 882  *
 883  * Sets the CA root certificate used for TSA Controller verfication during
 884  * TLS connection setup between the TSA NIC and the TSA Controller
 885  *
 886  * NOTE: This TAG is temporarily placed in the dynamic config partition and will
 887  * be moved to a private partition during TSA development. It is not used in any
 888  * released code yet.
 889  */
 890
 891 #define TLV_TAG_TMP_CA_ROOT_CERT        (0x10260000)
 892
 893 typedef struct tlv_ca_root_cert {
 894   uint32_t tag;
 895   uint32_t length;
 896   uint8_t  bytes[];
 897 } tlv_ca_root_cert_t;
 898
 899 /* Tx vFIFO Low latency configuration
 900  *
 901  * To keep the desired booting behaviour for the switch, it just requires to
 902  * know if the low latency mode is enabled.
 903  */
 904
 905 #define TLV_TAG_TX_VFIFO_ULL_MODE       (0x10270000)
 906 struct tlv_tx_vfifo_ull_mode {
 907   uint32_t tag;
 908   uint32_t length;
 909   uint8_t  mode;
 910 #define TLV_TX_VFIFO_ULL_MODE_DEFAULT    0
 911 };
 912
 913 /* BIU mode
 914  *
 915  * Medford2 tag for selecting VI window decode (see values below)
 916  */
 917 #define TLV_TAG_BIU_VI_WINDOW_MODE       (0x10280000)
 918 struct tlv_biu_vi_window_mode {
 919   uint32_t tag;
 920   uint32_t length;
 921   uint8_t  mode;
 922 #define TLV_BIU_VI_WINDOW_MODE_8K    0  /*  8k per VI, CTPIO not mapped, medford/hunt compatible */
 923 #define TLV_BIU_VI_WINDOW_MODE_16K   1  /* 16k per VI, CTPIO mapped */
 924 #define TLV_BIU_VI_WINDOW_MODE_64K   2  /* 64k per VI, CTPIO mapped, POWER-friendly */
 925 };
 926
 927 /* FastPD mode
 928  *
 929  * Medford2 tag for configuring the FastPD mode (see values below)
 930  */
 931 #define TLV_TAG_FASTPD_MODE(port)       (0x10290000 + (port))
 932 struct tlv_fastpd_mode {
 933   uint32_t tag;
 934   uint32_t length;
 935   uint8_t  mode;
 936 #define TLV_FASTPD_MODE_SOFT_ALL       0  /* All packets to the SoftPD */
 937 #define TLV_FASTPD_MODE_FAST_ALL       1  /* All packets to the FastPD */
 938 #define TLV_FASTPD_MODE_FAST_SUPPORTED 2  /* Supported packet types to the FastPD; everything else to the SoftPD  */
 939 };
 940
 941 #endif /* CI_MGMT_TLV_LAYOUT_H */