ceph/src/seastar/dpdk/drivers/net/sfc/base/efx_regs_mcdi_aoe.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright 2008-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 /*
   8  * This file is automatically generated. DO NOT EDIT IT.
   9  * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
  10  * rebuild this file with "make -C doc mcdiheaders".
  11  */
  12
  13 #ifndef _SIENA_MC_DRIVER_PCOL_AOE_H
  14 #define _SIENA_MC_DRIVER_PCOL_AOE_H
  15
  16
  17
  18 /***********************************/
  19 /* MC_CMD_FC
  20  * Perform an FC operation
  21  */
  22 #define MC_CMD_FC 0x9
  23
  24 /* MC_CMD_FC_IN msgrequest */
  25 #define MC_CMD_FC_IN_LEN 4
  26 #define MC_CMD_FC_IN_OP_HDR_OFST 0
  27 #define MC_CMD_FC_IN_OP_HDR_LEN 4
  28 #define MC_CMD_FC_IN_OP_LBN 0
  29 #define MC_CMD_FC_IN_OP_WIDTH 8
  30 /* enum: NULL MCDI command to FC. */
  31 #define MC_CMD_FC_OP_NULL 0x1
  32 /* enum: Unused opcode */
  33 #define MC_CMD_FC_OP_UNUSED 0x2
  34 /* enum: MAC driver commands */
  35 #define MC_CMD_FC_OP_MAC 0x3
  36 /* enum: Read FC memory */
  37 #define MC_CMD_FC_OP_READ32 0x4
  38 /* enum: Write to FC memory */
  39 #define MC_CMD_FC_OP_WRITE32 0x5
  40 /* enum: Read FC memory */
  41 #define MC_CMD_FC_OP_TRC_READ 0x6
  42 /* enum: Write to FC memory */
  43 #define MC_CMD_FC_OP_TRC_WRITE 0x7
  44 /* enum: FC firmware Version */
  45 #define MC_CMD_FC_OP_GET_VERSION 0x8
  46 /* enum: Read FC memory */
  47 #define MC_CMD_FC_OP_TRC_RX_READ 0x9
  48 /* enum: Write to FC memory */
  49 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa
  50 /* enum: SFP parameters */
  51 #define MC_CMD_FC_OP_SFP 0xb
  52 /* enum: DDR3 test */
  53 #define MC_CMD_FC_OP_DDR_TEST 0xc
  54 /* enum: Get Crash context from FC */
  55 #define MC_CMD_FC_OP_GET_ASSERT 0xd
  56 /* enum: Get FPGA Build registers */
  57 #define MC_CMD_FC_OP_FPGA_BUILD 0xe
  58 /* enum: Read map support commands */
  59 #define MC_CMD_FC_OP_READ_MAP 0xf
  60 /* enum: FC Capabilities */
  61 #define MC_CMD_FC_OP_CAPABILITIES 0x10
  62 /* enum: FC Global flags */
  63 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11
  64 /* enum: FC IO using relative addressing modes */
  65 #define MC_CMD_FC_OP_IO_REL 0x12
  66 /* enum: FPGA link information */
  67 #define MC_CMD_FC_OP_UHLINK 0x13
  68 /* enum: Configure loopbacks and link on FPGA ports */
  69 #define MC_CMD_FC_OP_SET_LINK 0x14
  70 /* enum: Licensing operations relating to AOE */
  71 #define MC_CMD_FC_OP_LICENSE 0x15
  72 /* enum: Startup information to the FC */
  73 #define MC_CMD_FC_OP_STARTUP 0x16
  74 /* enum: Configure a DMA read */
  75 #define MC_CMD_FC_OP_DMA 0x17
  76 /* enum: Configure a timed read */
  77 #define MC_CMD_FC_OP_TIMED_READ 0x18
  78 /* enum: Control UART logging */
  79 #define MC_CMD_FC_OP_LOG 0x19
  80 /* enum: Get the value of a given clock_id */
  81 #define MC_CMD_FC_OP_CLOCK 0x1a
  82 /* enum: DDR3/QDR3 parameters */
  83 #define MC_CMD_FC_OP_DDR 0x1b
  84 /* enum: PTP and timestamp control */
  85 #define MC_CMD_FC_OP_TIMESTAMP 0x1c
  86 /* enum: Commands for SPI Flash interface */
  87 #define MC_CMD_FC_OP_SPI 0x1d
  88 /* enum: Commands for diagnostic components */
  89 #define MC_CMD_FC_OP_DIAG 0x1e
  90 /* enum: External AOE port. */
  91 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0
  92 /* enum: Internal AOE port. */
  93 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40
  94
  95 /* MC_CMD_FC_IN_NULL msgrequest */
  96 #define MC_CMD_FC_IN_NULL_LEN 4
  97 #define MC_CMD_FC_IN_CMD_OFST 0
  98 #define MC_CMD_FC_IN_CMD_LEN 4
  99
 100 /* MC_CMD_FC_IN_PHY msgrequest */
 101 #define MC_CMD_FC_IN_PHY_LEN 5
 102 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 103 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 104 /* FC PHY driver operation code */
 105 #define MC_CMD_FC_IN_PHY_OP_OFST 4
 106 #define MC_CMD_FC_IN_PHY_OP_LEN 1
 107 /* enum: PHY init handler */
 108 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1
 109 /* enum: PHY reconfigure handler */
 110 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2
 111 /* enum: PHY reboot handler */
 112 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3
 113 /* enum: PHY get_supported_cap handler */
 114 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4
 115 /* enum: PHY get_config handler */
 116 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5
 117 /* enum: PHY get_media_info handler */
 118 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6
 119 /* enum: PHY set_led handler */
 120 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7
 121 /* enum: PHY lasi_interrupt handler */
 122 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8
 123 /* enum: PHY check_link handler */
 124 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9
 125 /* enum: PHY fill_stats handler */
 126 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa
 127 /* enum: PHY bpx_link_state_changed handler */
 128 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb
 129 /* enum: PHY get_state handler */
 130 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc
 131 /* enum: PHY start_bist handler */
 132 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd
 133 /* enum: PHY poll_bist handler */
 134 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe
 135 /* enum: PHY nvram_test handler */
 136 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf
 137 /* enum: PHY relinquish handler */
 138 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10
 139 /* enum: PHY read connection from FC - may be not required */
 140 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11
 141 /* enum: PHY read flags from FC - may be not required */
 142 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12
 143
 144 /* MC_CMD_FC_IN_PHY_INIT msgrequest */
 145 #define MC_CMD_FC_IN_PHY_INIT_LEN 4
 146 #define MC_CMD_FC_IN_PHY_CMD_OFST 0
 147 #define MC_CMD_FC_IN_PHY_CMD_LEN 4
 148
 149 /* MC_CMD_FC_IN_MAC msgrequest */
 150 #define MC_CMD_FC_IN_MAC_LEN 8
 151 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 152 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 153 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4
 154 #define MC_CMD_FC_IN_MAC_HEADER_LEN 4
 155 #define MC_CMD_FC_IN_MAC_OP_LBN 0
 156 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8
 157 /* enum: MAC reconfigure handler */
 158 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1
 159 /* enum: MAC Set command - same as MC_CMD_SET_MAC */
 160 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2
 161 /* enum: MAC statistics */
 162 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3
 163 /* enum: MAC RX statistics */
 164 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6
 165 /* enum: MAC TX statistics */
 166 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7
 167 /* enum: MAC Read status */
 168 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8
 169 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8
 170 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8
 171 /* enum: External FPGA port. */
 172 #define MC_CMD_FC_PORT_EXT 0x0
 173 /* enum: Internal Siena-facing FPGA ports. */
 174 #define MC_CMD_FC_PORT_INT 0x1
 175 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16
 176 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8
 177 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24
 178 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8
 179 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
 180  * irrelevant. Port number is derived from pci_fn; passed in FC header.
 181  */
 182 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0
 183 /* enum: Override default port number. Port number determined by fields
 184  * PORT_TYPE and PORT_IDX.
 185  */
 186 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1
 187
 188 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */
 189 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8
 190 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 191 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 192 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
 193 /*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
 194
 195 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */
 196 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32
 197 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 198 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 199 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
 200 /*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
 201 /* MTU size */
 202 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8
 203 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_LEN 4
 204 /* Drain Tx FIFO */
 205 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12
 206 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_LEN 4
 207 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16
 208 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8
 209 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16
 210 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20
 211 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24
 212 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4
 213 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0
 214 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1
 215 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1
 216 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1
 217 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28
 218 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_LEN 4
 219
 220 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */
 221 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8
 222 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 223 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 224 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
 225 /*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
 226
 227 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */
 228 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8
 229 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 230 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 231 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
 232 /*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
 233
 234 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */
 235 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8
 236 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 237 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 238 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
 239 /*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
 240
 241 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */
 242 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20
 243 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 244 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 245 /*            MC_CMD_FC_IN_MAC_HEADER_OFST 4 */
 246 /*            MC_CMD_FC_IN_MAC_HEADER_LEN 4 */
 247 /* MC Statistics index */
 248 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8
 249 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4
 250 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12
 251 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4
 252 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0
 253 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1
 254 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1
 255 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1
 256 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2
 257 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1
 258 /* Number of statistics to read */
 259 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16
 260 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_LEN 4
 261 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */
 262 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */
 263
 264 /* MC_CMD_FC_IN_READ32 msgrequest */
 265 #define MC_CMD_FC_IN_READ32_LEN 16
 266 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 267 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 268 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4
 269 #define MC_CMD_FC_IN_READ32_ADDR_HI_LEN 4
 270 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8
 271 #define MC_CMD_FC_IN_READ32_ADDR_LO_LEN 4
 272 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12
 273 #define MC_CMD_FC_IN_READ32_NUMWORDS_LEN 4
 274
 275 /* MC_CMD_FC_IN_WRITE32 msgrequest */
 276 #define MC_CMD_FC_IN_WRITE32_LENMIN 16
 277 #define MC_CMD_FC_IN_WRITE32_LENMAX 252
 278 #define MC_CMD_FC_IN_WRITE32_LENMAX_MCDI2 1020
 279 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num))
 280 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 281 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 282 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4
 283 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_LEN 4
 284 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8
 285 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_LEN 4
 286 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12
 287 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4
 288 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1
 289 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60
 290 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM_MCDI2 252
 291
 292 /* MC_CMD_FC_IN_TRC_READ msgrequest */
 293 #define MC_CMD_FC_IN_TRC_READ_LEN 12
 294 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 295 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 296 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4
 297 #define MC_CMD_FC_IN_TRC_READ_TRC_LEN 4
 298 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8
 299 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_LEN 4
 300
 301 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */
 302 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28
 303 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 304 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 305 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4
 306 #define MC_CMD_FC_IN_TRC_WRITE_TRC_LEN 4
 307 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8
 308 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_LEN 4
 309 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12
 310 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4
 311 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4
 312
 313 /* MC_CMD_FC_IN_GET_VERSION msgrequest */
 314 #define MC_CMD_FC_IN_GET_VERSION_LEN 4
 315 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 316 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 317
 318 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */
 319 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12
 320 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 321 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 322 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4
 323 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_LEN 4
 324 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8
 325 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_LEN 4
 326
 327 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */
 328 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20
 329 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 330 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 331 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4
 332 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_LEN 4
 333 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8
 334 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_LEN 4
 335 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12
 336 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4
 337 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2
 338
 339 /* MC_CMD_FC_IN_SFP msgrequest */
 340 #define MC_CMD_FC_IN_SFP_LEN 28
 341 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 342 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 343 /* Link speed is 100, 1000, 10000, 40000 */
 344 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4
 345 #define MC_CMD_FC_IN_SFP_SPEED_LEN 4
 346 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */
 347 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8
 348 #define MC_CMD_FC_IN_SFP_COPPER_LEN_LEN 4
 349 /* Not relevant for cards with QSFP modules. For older cards, true if module is
 350  * a dual speed SFP+ module.
 351  */
 352 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12
 353 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_LEN 4
 354 /* True if an SFP Module is present (other fields valid when true) */
 355 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16
 356 #define MC_CMD_FC_IN_SFP_PRESENT_LEN 4
 357 /* The type of the SFP+ Module. For later cards with QSFP modules, this field
 358  * is unused and the type is communicated by other means.
 359  */
 360 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20
 361 #define MC_CMD_FC_IN_SFP_TYPE_LEN 4
 362 /* Capabilities corresponding to 1 bits. */
 363 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24
 364 #define MC_CMD_FC_IN_SFP_CAPS_LEN 4
 365
 366 /* MC_CMD_FC_IN_DDR_TEST msgrequest */
 367 #define MC_CMD_FC_IN_DDR_TEST_LEN 8
 368 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 369 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 370 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4
 371 #define MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4
 372 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0
 373 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8
 374 /* enum: DRAM Test Start */
 375 #define MC_CMD_FC_OP_DDR_TEST_START 0x1
 376 /* enum: DRAM Test Poll */
 377 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2
 378
 379 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */
 380 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12
 381 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 382 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 383 /*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */
 384 /*            MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */
 385 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8
 386 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4
 387 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0
 388 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1
 389 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1
 390 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1
 391 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2
 392 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1
 393 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3
 394 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1
 395
 396 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */
 397 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12
 398 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0
 399 #define MC_CMD_FC_IN_DDR_TEST_CMD_LEN 4
 400 /*            MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */
 401 /*            MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */
 402 /* Clear previous test result and prepare for restarting DDR test */
 403 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8
 404 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_LEN 4
 405
 406 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */
 407 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4
 408 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 409 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 410
 411 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */
 412 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8
 413 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 414 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 415 /* FPGA build info operation code */
 416 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4
 417 #define MC_CMD_FC_IN_FPGA_BUILD_OP_LEN 4
 418 /* enum: Get the build registers */
 419 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1
 420 /* enum: Get the services registers */
 421 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2
 422 /* enum: Get the BSP version */
 423 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3
 424 /* enum: Get build register for V2 (SFA974X) */
 425 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4
 426 /* enum: GEt the services register for V2 (SFA974X) */
 427 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5
 428
 429 /* MC_CMD_FC_IN_READ_MAP msgrequest */
 430 #define MC_CMD_FC_IN_READ_MAP_LEN 8
 431 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 432 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 433 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4
 434 #define MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4
 435 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0
 436 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8
 437 /* enum: Get the number of map regions */
 438 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1
 439 /* enum: Get the specified map */
 440 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2
 441
 442 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */
 443 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8
 444 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 445 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 446 /*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */
 447 /*            MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */
 448
 449 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */
 450 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12
 451 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 452 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 453 /*            MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */
 454 /*            MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */
 455 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8
 456 #define MC_CMD_FC_IN_MAP_INDEX_LEN 4
 457
 458 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */
 459 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4
 460 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 461 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 462
 463 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */
 464 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8
 465 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 466 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 467 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4
 468 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4
 469 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0
 470 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1
 471 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1
 472 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1
 473 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2
 474 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1
 475 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3
 476 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1
 477 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4
 478 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1
 479 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5
 480 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1
 481
 482 /* MC_CMD_FC_IN_IO_REL msgrequest */
 483 #define MC_CMD_FC_IN_IO_REL_LEN 8
 484 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 485 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 486 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4
 487 #define MC_CMD_FC_IN_IO_REL_HEADER_LEN 4
 488 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0
 489 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8
 490 /* enum: Get the base address that the FC applies to relative commands */
 491 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1
 492 /* enum: Read data */
 493 #define MC_CMD_FC_IN_IO_REL_READ32 0x2
 494 /* enum: Write data */
 495 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3
 496 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8
 497 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8
 498 /* enum: Application address space */
 499 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1
 500 /* enum: Flash address space */
 501 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2
 502
 503 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */
 504 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8
 505 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 506 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 507 /*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
 508 /*            MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */
 509
 510 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */
 511 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20
 512 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 513 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 514 /*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
 515 /*            MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */
 516 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8
 517 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_LEN 4
 518 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12
 519 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_LEN 4
 520 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16
 521 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_LEN 4
 522
 523 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */
 524 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20
 525 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252
 526 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX_MCDI2 1020
 527 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num))
 528 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 529 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 530 /*            MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
 531 /*            MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */
 532 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8
 533 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_LEN 4
 534 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12
 535 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_LEN 4
 536 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16
 537 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4
 538 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1
 539 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59
 540 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM_MCDI2 251
 541
 542 /* MC_CMD_FC_IN_UHLINK msgrequest */
 543 #define MC_CMD_FC_IN_UHLINK_LEN 8
 544 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 545 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 546 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4
 547 #define MC_CMD_FC_IN_UHLINK_HEADER_LEN 4
 548 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0
 549 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8
 550 /* enum: Get PHY configuration info */
 551 #define MC_CMD_FC_OP_UHLINK_PHY 0x1
 552 /* enum: Get MAC configuration info */
 553 #define MC_CMD_FC_OP_UHLINK_MAC 0x2
 554 /* enum: Get Rx eye table */
 555 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3
 556 /* enum: Get Rx eye plot */
 557 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4
 558 /* enum: Get Rx eye plot */
 559 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5
 560 /* enum: Retune Rx settings */
 561 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6
 562 /* enum: Set loopback mode on fpga port */
 563 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7
 564 /* enum: Get loopback mode config state on fpga port */
 565 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8
 566 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8
 567 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8
 568 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16
 569 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8
 570 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24
 571 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8
 572 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are
 573  * irrelevant. Port number is derived from pci_fn; passed in FC header.
 574  */
 575 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0
 576 /* enum: Override default port number. Port number determined by fields
 577  * PORT_TYPE and PORT_IDX.
 578  */
 579 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1
 580
 581 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */
 582 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8
 583 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 584 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 585 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
 586 /*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
 587
 588 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */
 589 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8
 590 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 591 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 592 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
 593 /*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
 594
 595 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */
 596 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12
 597 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 598 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 599 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
 600 /*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
 601 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8
 602 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_LEN 4
 603 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */
 604
 605 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */
 606 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8
 607 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 608 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 609 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
 610 /*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
 611
 612 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */
 613 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20
 614 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 615 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 616 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
 617 /*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
 618 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8
 619 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_LEN 4
 620 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12
 621 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_LEN 4
 622 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16
 623 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_LEN 4
 624 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */
 625
 626 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */
 627 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8
 628 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 629 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 630 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
 631 /*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
 632
 633 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */
 634 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16
 635 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 636 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 637 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
 638 /*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
 639 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8
 640 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_LEN 4
 641 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */
 642 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */
 643 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */
 644 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12
 645 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_LEN 4
 646 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */
 647 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */
 648
 649 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */
 650 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12
 651 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 652 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 653 /*            MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */
 654 /*            MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */
 655 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8
 656 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_LEN 4
 657
 658 /* MC_CMD_FC_IN_SET_LINK msgrequest */
 659 #define MC_CMD_FC_IN_SET_LINK_LEN 16
 660 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 661 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 662 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
 663 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4
 664 #define MC_CMD_FC_IN_SET_LINK_MODE_LEN 4
 665 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8
 666 #define MC_CMD_FC_IN_SET_LINK_SPEED_LEN 4
 667 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12
 668 #define MC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4
 669 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0
 670 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1
 671 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1
 672 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1
 673 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2
 674 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1
 675
 676 /* MC_CMD_FC_IN_LICENSE msgrequest */
 677 #define MC_CMD_FC_IN_LICENSE_LEN 8
 678 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 679 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 680 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4
 681 #define MC_CMD_FC_IN_LICENSE_OP_LEN 4
 682 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */
 683 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */
 684
 685 /* MC_CMD_FC_IN_STARTUP msgrequest */
 686 #define MC_CMD_FC_IN_STARTUP_LEN 40
 687 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 688 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 689 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4
 690 #define MC_CMD_FC_IN_STARTUP_BASE_LEN 4
 691 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8
 692 #define MC_CMD_FC_IN_STARTUP_LENGTH_LEN 4
 693 /* Length of identifier */
 694 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12
 695 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_LEN 4
 696 /* Identifier for AOE FPGA */
 697 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16
 698 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1
 699 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24
 700
 701 /* MC_CMD_FC_IN_DMA msgrequest */
 702 #define MC_CMD_FC_IN_DMA_LEN 8
 703 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 704 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 705 #define MC_CMD_FC_IN_DMA_OP_OFST 4
 706 #define MC_CMD_FC_IN_DMA_OP_LEN 4
 707 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */
 708 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */
 709
 710 /* MC_CMD_FC_IN_DMA_STOP msgrequest */
 711 #define MC_CMD_FC_IN_DMA_STOP_LEN 12
 712 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 713 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 714 /*            MC_CMD_FC_IN_DMA_OP_OFST 4 */
 715 /*            MC_CMD_FC_IN_DMA_OP_LEN 4 */
 716 /* FC supplied handle */
 717 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8
 718 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_LEN 4
 719
 720 /* MC_CMD_FC_IN_DMA_READ msgrequest */
 721 #define MC_CMD_FC_IN_DMA_READ_LEN 16
 722 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 723 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 724 /*            MC_CMD_FC_IN_DMA_OP_OFST 4 */
 725 /*            MC_CMD_FC_IN_DMA_OP_LEN 4 */
 726 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8
 727 #define MC_CMD_FC_IN_DMA_READ_OFFSET_LEN 4
 728 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12
 729 #define MC_CMD_FC_IN_DMA_READ_LENGTH_LEN 4
 730
 731 /* MC_CMD_FC_IN_TIMED_READ msgrequest */
 732 #define MC_CMD_FC_IN_TIMED_READ_LEN 8
 733 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 734 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 735 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4
 736 #define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4
 737 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */
 738 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */
 739 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */
 740
 741 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */
 742 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52
 743 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 744 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 745 /*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
 746 /*            MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */
 747 /* Host supplied handle (unique) */
 748 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8
 749 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_LEN 4
 750 /* Address into which to transfer data in host */
 751 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12
 752 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8
 753 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12
 754 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16
 755 /* AOE address from which to transfer data */
 756 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20
 757 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8
 758 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20
 759 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24
 760 /* Length of AOE transfer (total) */
 761 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28
 762 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4
 763 /* Length of host transfer (total) */
 764 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32
 765 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_LEN 4
 766 /* Offset back from aoe_address to apply operation to */
 767 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36
 768 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_LEN 4
 769 /* Data to apply at offset */
 770 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40
 771 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4
 772 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44
 773 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4
 774 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0
 775 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1
 776 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1
 777 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1
 778 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2
 779 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1
 780 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3
 781 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2
 782 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */
 783 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */
 784 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */
 785 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */
 786 /* Period at which reads are performed (100ms units) */
 787 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48
 788 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4
 789
 790 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */
 791 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12
 792 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 793 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 794 /*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
 795 /*            MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */
 796 /* FC supplied handle */
 797 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8
 798 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_LEN 4
 799
 800 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */
 801 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12
 802 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 803 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 804 /*            MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */
 805 /*            MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */
 806 /* FC supplied handle */
 807 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8
 808 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_LEN 4
 809
 810 /* MC_CMD_FC_IN_LOG msgrequest */
 811 #define MC_CMD_FC_IN_LOG_LEN 8
 812 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 813 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 814 #define MC_CMD_FC_IN_LOG_OP_OFST 4
 815 #define MC_CMD_FC_IN_LOG_OP_LEN 4
 816 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */
 817 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */
 818
 819 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */
 820 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20
 821 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 822 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 823 /*            MC_CMD_FC_IN_LOG_OP_OFST 4 */
 824 /*            MC_CMD_FC_IN_LOG_OP_LEN 4 */
 825 /* Partition offset into flash */
 826 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8
 827 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_LEN 4
 828 /* Partition length */
 829 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12
 830 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_LEN 4
 831 /* Partition erase size */
 832 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16
 833 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_LEN 4
 834
 835 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */
 836 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12
 837 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 838 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 839 /*            MC_CMD_FC_IN_LOG_OP_OFST 4 */
 840 /*            MC_CMD_FC_IN_LOG_OP_LEN 4 */
 841 /* Enable/disable printing to JTAG UART */
 842 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8
 843 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4
 844
 845 /* MC_CMD_FC_IN_CLOCK msgrequest: Perform a clock operation */
 846 #define MC_CMD_FC_IN_CLOCK_LEN 12
 847 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 848 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 849 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4
 850 #define MC_CMD_FC_IN_CLOCK_OP_LEN 4
 851 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */
 852 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */
 853 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8
 854 #define MC_CMD_FC_IN_CLOCK_ID_LEN 4
 855 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */
 856 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */
 857
 858 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest: Retrieve the clock value of the
 859  * specified clock
 860  */
 861 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12
 862 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 863 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 864 /*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
 865 /*            MC_CMD_FC_IN_CLOCK_OP_LEN 4 */
 866 /*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
 867 /*            MC_CMD_FC_IN_CLOCK_ID_LEN 4 */
 868
 869 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest: Set the clock value of the specified
 870  * clock
 871  */
 872 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24
 873 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 874 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 875 /*            MC_CMD_FC_IN_CLOCK_OP_OFST 4 */
 876 /*            MC_CMD_FC_IN_CLOCK_OP_LEN 4 */
 877 /*            MC_CMD_FC_IN_CLOCK_ID_OFST 8 */
 878 /*            MC_CMD_FC_IN_CLOCK_ID_LEN 4 */
 879 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12
 880 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8
 881 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12
 882 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16
 883 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20
 884 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4
 885
 886 /* MC_CMD_FC_IN_DDR msgrequest */
 887 #define MC_CMD_FC_IN_DDR_LEN 12
 888 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 889 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 890 #define MC_CMD_FC_IN_DDR_OP_OFST 4
 891 #define MC_CMD_FC_IN_DDR_OP_LEN 4
 892 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */
 893 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */
 894 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */
 895 #define MC_CMD_FC_IN_DDR_BANK_OFST 8
 896 #define MC_CMD_FC_IN_DDR_BANK_LEN 4
 897 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */
 898 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */
 899 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */
 900 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */
 901 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */
 902
 903 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */
 904 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148
 905 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 906 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 907 /*            MC_CMD_FC_IN_DDR_OP_OFST 4 */
 908 /*            MC_CMD_FC_IN_DDR_OP_LEN 4 */
 909 /* Affected bank */
 910 /*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */
 911 /*            MC_CMD_FC_IN_DDR_BANK_LEN 4 */
 912 /* Flags */
 913 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12
 914 #define MC_CMD_FC_IN_DDR_FLAGS_LEN 4
 915 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */
 916 /* 128-byte page of serial presence detect data read from module's EEPROM */
 917 #define MC_CMD_FC_IN_DDR_SPD_OFST 16
 918 #define MC_CMD_FC_IN_DDR_SPD_LEN 1
 919 #define MC_CMD_FC_IN_DDR_SPD_NUM 128
 920 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */
 921 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144
 922 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_LEN 4
 923
 924 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */
 925 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16
 926 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 927 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 928 /*            MC_CMD_FC_IN_DDR_OP_OFST 4 */
 929 /*            MC_CMD_FC_IN_DDR_OP_LEN 4 */
 930 /* Affected bank */
 931 /*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */
 932 /*            MC_CMD_FC_IN_DDR_BANK_LEN 4 */
 933 /* Size of DDR */
 934 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12
 935 #define MC_CMD_FC_IN_DDR_SIZE_LEN 4
 936
 937 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */
 938 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12
 939 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 940 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 941 /*            MC_CMD_FC_IN_DDR_OP_OFST 4 */
 942 /*            MC_CMD_FC_IN_DDR_OP_LEN 4 */
 943 /* Affected bank */
 944 /*            MC_CMD_FC_IN_DDR_BANK_OFST 8 */
 945 /*            MC_CMD_FC_IN_DDR_BANK_LEN 4 */
 946
 947 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */
 948 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8
 949 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 950 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 951 /* FC timestamp operation code */
 952 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4
 953 #define MC_CMD_FC_IN_TIMESTAMP_OP_LEN 4
 954 /* enum: Read transmit timestamp(s) */
 955 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0
 956 /* enum: Read snapshot timestamps */
 957 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1
 958 /* enum: Clear all transmit timestamps */
 959 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2
 960
 961 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */
 962 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28
 963 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 964 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 965 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4
 966 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_LEN 4
 967 /* Control filtering of the returned timestamp and sequence number specified
 968  * here
 969  */
 970 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8
 971 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_LEN 4
 972 /* enum: Return most recent timestamp. No filtering */
 973 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0
 974 /* enum: Match timestamp against the PTP clock ID, port number and sequence
 975  * number specified
 976  */
 977 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1
 978 /* Clock identity of PTP packet for which timestamp required */
 979 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12
 980 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8
 981 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12
 982 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16
 983 /* Port number of PTP packet for which timestamp required */
 984 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20
 985 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4
 986 /* Sequence number of PTP packet for which timestamp required */
 987 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24
 988 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_LEN 4
 989
 990 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */
 991 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8
 992 /*            MC_CMD_FC_IN_CMD_OFST 0 */
 993 /*            MC_CMD_FC_IN_CMD_LEN 4 */
 994 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4
 995 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_LEN 4
 996
 997 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */
 998 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8
 999 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1000 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1001 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4
1002 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_LEN 4
1003
1004 /* MC_CMD_FC_IN_SPI msgrequest */
1005 #define MC_CMD_FC_IN_SPI_LEN 8
1006 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1007 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1008 /* Basic commands for SPI Flash. */
1009 #define MC_CMD_FC_IN_SPI_OP_OFST 4
1010 #define MC_CMD_FC_IN_SPI_OP_LEN 4
1011 /* enum: SPI Flash read */
1012 #define MC_CMD_FC_IN_SPI_READ 0x0
1013 /* enum: SPI Flash write */
1014 #define MC_CMD_FC_IN_SPI_WRITE 0x1
1015 /* enum: SPI Flash erase */
1016 #define MC_CMD_FC_IN_SPI_ERASE 0x2
1017
1018 /* MC_CMD_FC_IN_SPI_READ msgrequest */
1019 #define MC_CMD_FC_IN_SPI_READ_LEN 16
1020 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1021 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1022 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4
1023 #define MC_CMD_FC_IN_SPI_READ_OP_LEN 4
1024 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8
1025 #define MC_CMD_FC_IN_SPI_READ_ADDR_LEN 4
1026 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12
1027 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_LEN 4
1028
1029 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */
1030 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16
1031 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252
1032 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX_MCDI2 1020
1033 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num))
1034 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1035 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1036 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4
1037 #define MC_CMD_FC_IN_SPI_WRITE_OP_LEN 4
1038 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8
1039 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_LEN 4
1040 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12
1041 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4
1042 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1
1043 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60
1044 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM_MCDI2 252
1045
1046 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */
1047 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16
1048 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1049 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1050 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4
1051 #define MC_CMD_FC_IN_SPI_ERASE_OP_LEN 4
1052 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8
1053 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_LEN 4
1054 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12
1055 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_LEN 4
1056
1057 /* MC_CMD_FC_IN_DIAG msgrequest */
1058 #define MC_CMD_FC_IN_DIAG_LEN 8
1059 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1060 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1061 /* Operation code indicating component type */
1062 #define MC_CMD_FC_IN_DIAG_OP_OFST 4
1063 #define MC_CMD_FC_IN_DIAG_OP_LEN 4
1064 /* enum: Power noise generator. */
1065 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0
1066 /* enum: DDR soak test component. */
1067 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1
1068 /* enum: Diagnostics datapath control component. */
1069 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2
1070
1071 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */
1072 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12
1073 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1074 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1075 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4
1076 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_LEN 4
1077 /* Sub-opcode describing the operation to be carried out */
1078 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8
1079 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_LEN 4
1080 /* enum: Read the configuration (the 32-bit values in each of the clock enable
1081  * count and toggle count registers)
1082  */
1083 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0
1084 /* enum: Write a new configuration to the clock enable count and toggle count
1085  * registers
1086  */
1087 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1
1088
1089 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */
1090 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12
1091 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1092 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1093 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4
1094 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_LEN 4
1095 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8
1096 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_LEN 4
1097
1098 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */
1099 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20
1100 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1101 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1102 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4
1103 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_LEN 4
1104 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8
1105 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_LEN 4
1106 /* The 32-bit value to be written to the toggle count register */
1107 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12
1108 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_LEN 4
1109 /* The 32-bit value to be written to the clock enable count register */
1110 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16
1111 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_LEN 4
1112
1113 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */
1114 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12
1115 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1116 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1117 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4
1118 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_LEN 4
1119 /* Sub-opcode describing the operation to be carried out */
1120 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8
1121 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_LEN 4
1122 /* enum: Starts DDR soak test on selected banks */
1123 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0
1124 /* enum: Read status of DDR soak test */
1125 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1
1126 /* enum: Stop test */
1127 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2
1128 /* enum: Set or clear bit that triggers fake errors. These cause subsequent
1129  * tests to fail until the bit is cleared.
1130  */
1131 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3
1132
1133 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */
1134 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24
1135 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1136 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1137 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4
1138 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_LEN 4
1139 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8
1140 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_LEN 4
1141 /* Mask of DDR banks to be tested */
1142 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12
1143 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_LEN 4
1144 /* Pattern to use in the soak test */
1145 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16
1146 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_LEN 4
1147 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */
1148 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */
1149 /* Either multiple automatic tests until a STOP command is issued, or one
1150  * single test
1151  */
1152 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20
1153 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_LEN 4
1154 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */
1155 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */
1156
1157 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */
1158 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16
1159 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1160 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1161 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4
1162 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_LEN 4
1163 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8
1164 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_LEN 4
1165 /* DDR bank to read status from */
1166 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12
1167 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_LEN 4
1168 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */
1169 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */
1170 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */
1171 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */
1172 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */
1173
1174 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */
1175 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16
1176 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1177 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1178 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4
1179 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_LEN 4
1180 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8
1181 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_LEN 4
1182 /* Mask of DDR banks to be tested */
1183 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12
1184 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_LEN 4
1185
1186 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */
1187 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20
1188 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1189 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1190 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4
1191 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_LEN 4
1192 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8
1193 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_LEN 4
1194 /* Mask of DDR banks to set/clear error flag on */
1195 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12
1196 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_LEN 4
1197 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16
1198 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_LEN 4
1199 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */
1200 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */
1201
1202 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */
1203 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12
1204 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1205 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1206 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4
1207 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_LEN 4
1208 /* Sub-opcode describing the operation to be carried out */
1209 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8
1210 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_LEN 4
1211 /* enum: Set a known datapath configuration */
1212 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0
1213 /* enum: Apply raw config to datapath control registers */
1214 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1
1215
1216 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */
1217 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16
1218 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1219 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1220 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4
1221 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_LEN 4
1222 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8
1223 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_LEN 4
1224 /* Datapath configuration identifier */
1225 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12
1226 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_LEN 4
1227 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */
1228 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */
1229
1230 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */
1231 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24
1232 /*            MC_CMD_FC_IN_CMD_OFST 0 */
1233 /*            MC_CMD_FC_IN_CMD_LEN 4 */
1234 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4
1235 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_LEN 4
1236 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8
1237 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_LEN 4
1238 /* Value to write into control register 1 */
1239 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12
1240 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_LEN 4
1241 /* Value to write into control register 2 */
1242 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16
1243 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_LEN 4
1244 /* Value to write into control register 3 */
1245 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20
1246 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_LEN 4
1247
1248 /* MC_CMD_FC_OUT msgresponse */
1249 #define MC_CMD_FC_OUT_LEN 0
1250
1251 /* MC_CMD_FC_OUT_NULL msgresponse */
1252 #define MC_CMD_FC_OUT_NULL_LEN 0
1253
1254 /* MC_CMD_FC_OUT_READ32 msgresponse */
1255 #define MC_CMD_FC_OUT_READ32_LENMIN 4
1256 #define MC_CMD_FC_OUT_READ32_LENMAX 252
1257 #define MC_CMD_FC_OUT_READ32_LENMAX_MCDI2 1020
1258 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num))
1259 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0
1260 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4
1261 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1
1262 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63
1263 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM_MCDI2 255
1264
1265 /* MC_CMD_FC_OUT_WRITE32 msgresponse */
1266 #define MC_CMD_FC_OUT_WRITE32_LEN 0
1267
1268 /* MC_CMD_FC_OUT_TRC_READ msgresponse */
1269 #define MC_CMD_FC_OUT_TRC_READ_LEN 16
1270 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0
1271 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4
1272 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4
1273
1274 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */
1275 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0
1276
1277 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */
1278 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12
1279 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0
1280 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_LEN 4
1281 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4
1282 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8
1283 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4
1284 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8
1285
1286 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */
1287 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8
1288 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0
1289 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4
1290 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2
1291
1292 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */
1293 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0
1294
1295 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */
1296 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0
1297
1298 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */
1299 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0
1300
1301 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */
1302 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4
1303 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0
1304 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_LEN 4
1305
1306 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */
1307 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3)
1308 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0
1309 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8
1310 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0
1311 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4
1312 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS
1313 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */
1314 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */
1315 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */
1316 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
1317 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */
1318 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */
1319 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */
1320 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */
1321 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */
1322 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */
1323 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */
1324 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */
1325 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */
1326 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */
1327 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */
1328 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */
1329 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */
1330 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */
1331 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */
1332 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */
1333 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */
1334 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */
1335 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */
1336 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */
1337 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */
1338 /* enum: (Last entry) */
1339 #define MC_CMD_FC_MAC_RX_NSTATS 0x19
1340
1341 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */
1342 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3)
1343 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0
1344 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8
1345 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0
1346 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4
1347 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS
1348 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */
1349 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */
1350 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */
1351 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */
1352 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */
1353 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */
1354 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */
1355 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */
1356 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */
1357 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */
1358 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */
1359 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */
1360 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */
1361 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */
1362 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */
1363 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */
1364 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */
1365 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */
1366 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */
1367 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */
1368 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */
1369 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */
1370 /* enum: (Last entry) */
1371 #define MC_CMD_FC_MAC_TX_NSTATS 0x16
1372
1373 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */
1374 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3)
1375 /* MAC Statistics */
1376 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0
1377 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8
1378 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0
1379 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4
1380 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK
1381
1382 /* MC_CMD_FC_OUT_MAC msgresponse */
1383 #define MC_CMD_FC_OUT_MAC_LEN 0
1384
1385 /* MC_CMD_FC_OUT_SFP msgresponse */
1386 #define MC_CMD_FC_OUT_SFP_LEN 0
1387
1388 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */
1389 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0
1390
1391 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */
1392 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8
1393 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0
1394 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4
1395 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0
1396 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8
1397 /* enum: Test not yet initiated */
1398 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0
1399 /* enum: Test is in progress */
1400 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1
1401 /* enum: Timed completed */
1402 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2
1403 /* enum: Test did not complete in specified time */
1404 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3
1405 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11
1406 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1
1407 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10
1408 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1
1409 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9
1410 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1
1411 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8
1412 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1
1413 /* Test result from FPGA */
1414 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4
1415 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4
1416 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31
1417 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1
1418 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30
1419 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1
1420 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29
1421 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1
1422 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28
1423 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1
1424 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15
1425 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5
1426 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10
1427 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5
1428 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5
1429 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5
1430 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0
1431 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5
1432 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */
1433 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */
1434 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */
1435 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */
1436 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */
1437
1438 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */
1439 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0
1440
1441 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */
1442 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144
1443 /* Assertion status flag. */
1444 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0
1445 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4
1446 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8
1447 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8
1448 /* enum: No crash data available */
1449 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0
1450 /* enum: New crash data available */
1451 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1
1452 /* enum: Crash data has been sent */
1453 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2
1454 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0
1455 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8
1456 /* enum: No crash has been recorded. */
1457 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0
1458 /* enum: Crash due to exception. */
1459 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1
1460 /* enum: Crash due to assertion. */
1461 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2
1462 /* Failing PC value */
1463 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4
1464 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_LEN 4
1465 /* Saved GP regs */
1466 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8
1467 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4
1468 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31
1469 /* Exception Type */
1470 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132
1471 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_LEN 4
1472 /* Instruction at which exception occurred */
1473 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136
1474 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_LEN 4
1475 /* BAD Address that triggered address-based exception */
1476 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140
1477 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_LEN 4
1478
1479 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */
1480 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32
1481 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0
1482 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4
1483 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31
1484 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1
1485 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30
1486 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1
1487 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16
1488 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14
1489 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12
1490 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4
1491 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4
1492 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8
1493 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0
1494 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4
1495 /* Build timestamp (seconds since epoch) */
1496 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4
1497 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4
1498 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8
1499 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4
1500 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0
1501 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8
1502 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */
1503 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */
1504 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8
1505 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10
1506 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18
1507 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1
1508 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19
1509 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1
1510 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20
1511 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1
1512 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21
1513 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1
1514 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22
1515 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1
1516 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23
1517 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1
1518 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24
1519 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1
1520 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25
1521 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1
1522 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26
1523 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1
1524 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27
1525 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1
1526 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28
1527 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1
1528 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29
1529 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2
1530 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31
1531 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1
1532 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12
1533 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4
1534 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0
1535 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16
1536 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16
1537 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1
1538 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */
1539 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */
1540 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17
1541 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15
1542 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16
1543 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4
1544 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0
1545 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16
1546 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16
1547 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16
1548 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20
1549 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4
1550 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0
1551 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16
1552 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16
1553 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16
1554 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16
1555 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8
1556 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16
1557 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20
1558 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24
1559 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4
1560 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28
1561 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4
1562 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0
1563 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16
1564
1565 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */
1566 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32
1567 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0
1568 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4
1569 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31
1570 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1
1571 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30
1572 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1
1573 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16
1574 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14
1575 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12
1576 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4
1577 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4
1578 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8
1579 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0
1580 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4
1581 /* Build timestamp (seconds since epoch) */
1582 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4
1583 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4
1584 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8
1585 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4
1586 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31
1587 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1
1588 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29
1589 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1
1590 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28
1591 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1
1592 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27
1593 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1
1594 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26
1595 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1
1596 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25
1597 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1
1598 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24
1599 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1
1600 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23
1601 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1
1602 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22
1603 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1
1604 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21
1605 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1
1606 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20
1607 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1
1608 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19
1609 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1
1610 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18
1611 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1
1612 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */
1613 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */
1614 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17
1615 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1
1616 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */
1617 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */
1618 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16
1619 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1
1620 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */
1621 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */
1622 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15
1623 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1
1624 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14
1625 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1
1626 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13
1627 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1
1628 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12
1629 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1
1630 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11
1631 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1
1632 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10
1633 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1
1634 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9
1635 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1
1636 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8
1637 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1
1638 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7
1639 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1
1640 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6
1641 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1
1642 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5
1643 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1
1644 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4
1645 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1
1646 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0
1647 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4
1648 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */
1649 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */
1650 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */
1651 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */
1652 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */
1653 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */
1654 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */
1655 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */
1656 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12
1657 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4
1658 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0
1659 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16
1660 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16
1661 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1
1662 /*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */
1663 /*               MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */
1664 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16
1665 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4
1666 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0
1667 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16
1668 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16
1669 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16
1670 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20
1671 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4
1672 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0
1673 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16
1674 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16
1675 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16
1676 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24
1677 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4
1678 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28
1679 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4
1680 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0
1681 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16
1682
1683 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */
1684 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32
1685 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0
1686 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4
1687 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31
1688 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1
1689 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30
1690 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1
1691 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16
1692 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14
1693 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12
1694 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4
1695 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4
1696 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8
1697 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0
1698 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4
1699 /* Build timestamp (seconds since epoch) */
1700 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4
1701 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4
1702 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8
1703 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4
1704 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8
1705 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1
1706 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27
1707 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1
1708 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28
1709 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1
1710 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29
1711 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1
1712 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30
1713 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1
1714 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31
1715 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1
1716 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12
1717 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4
1718 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0
1719 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16
1720 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16
1721 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1
1722 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16
1723 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4
1724 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0
1725 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16
1726 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16
1727 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16
1728 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20
1729 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4
1730 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0
1731 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16
1732 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16
1733 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16
1734 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24
1735 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4
1736 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28
1737 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4
1738 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0
1739 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16
1740
1741 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */
1742 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32
1743 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0
1744 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4
1745 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31
1746 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1
1747 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30
1748 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1
1749 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16
1750 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14
1751 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12
1752 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4
1753 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4
1754 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8
1755 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0
1756 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4
1757 /* Build timestamp (seconds since epoch) */
1758 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4
1759 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4
1760 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8
1761 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4
1762 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0
1763 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1
1764 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8
1765 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1
1766 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12
1767 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4
1768 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0
1769 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16
1770 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16
1771 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1
1772 /*               MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */
1773 /*               MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */
1774 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24
1775 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4
1776 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28
1777 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4
1778 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0
1779 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16
1780
1781 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */
1782 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4
1783 /* Qsys system ID */
1784 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0
1785 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4
1786 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12
1787 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4
1788 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4
1789 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8
1790 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0
1791 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4
1792
1793 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */
1794 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4
1795 /* Number of maps */
1796 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0
1797 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_LEN 4
1798
1799 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */
1800 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164
1801 /* Index of the map */
1802 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0
1803 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_LEN 4
1804 /* Options for the map */
1805 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4
1806 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4
1807 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */
1808 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */
1809 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */
1810 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */
1811 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */
1812 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */
1813 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */
1814 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */
1815 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */
1816 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */
1817 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */
1818 /* Address of start of map */
1819 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8
1820 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8
1821 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8
1822 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12
1823 /* Length of address map */
1824 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16
1825 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8
1826 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16
1827 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20
1828 /* Component information field */
1829 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24
1830 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4
1831 /* License expiry data for map */
1832 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28
1833 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8
1834 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28
1835 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32
1836 /* Name of the component */
1837 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36
1838 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1
1839 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128
1840
1841 /* MC_CMD_FC_OUT_READ_MAP msgresponse */
1842 #define MC_CMD_FC_OUT_READ_MAP_LEN 0
1843
1844 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */
1845 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8
1846 /* Number of internal ports */
1847 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0
1848 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_LEN 4
1849 /* Number of external ports */
1850 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4
1851 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_LEN 4
1852
1853 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */
1854 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4
1855 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0
1856 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_LEN 4
1857
1858 /* MC_CMD_FC_OUT_IO_REL msgresponse */
1859 #define MC_CMD_FC_OUT_IO_REL_LEN 0
1860
1861 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */
1862 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8
1863 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0
1864 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_LEN 4
1865 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4
1866 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_LEN 4
1867
1868 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */
1869 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4
1870 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252
1871 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX_MCDI2 1020
1872 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num))
1873 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0
1874 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4
1875 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1
1876 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63
1877 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM_MCDI2 255
1878
1879 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */
1880 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0
1881
1882 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */
1883 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48
1884 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0
1885 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4
1886 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0
1887 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16
1888 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16
1889 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16
1890 /* Transceiver Transmit settings */
1891 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4
1892 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4
1893 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0
1894 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16
1895 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16
1896 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16
1897 /* Transceiver Receive settings */
1898 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8
1899 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4
1900 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0
1901 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16
1902 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16
1903 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16
1904 /* Rx eye opening */
1905 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12
1906 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4
1907 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0
1908 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16
1909 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16
1910 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16
1911 /* PCS status word */
1912 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16
1913 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_LEN 4
1914 /* Link status word */
1915 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20
1916 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4
1917 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0
1918 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1
1919 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1
1920 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1
1921 /* Current SFp parameters applied */
1922 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24
1923 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20
1924 /* Link speed is 100, 1000, 10000 */
1925 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24
1926 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_LEN 4
1927 /* Length of copper cable - zero when not relevant */
1928 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28
1929 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_LEN 4
1930 /* True if a dual speed SFP+ module */
1931 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32
1932 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_LEN 4
1933 /* True if an SFP Module is present (other fields valid when true) */
1934 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36
1935 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_LEN 4
1936 /* The type of the SFP+ Module */
1937 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40
1938 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_LEN 4
1939 /* PHY config flags */
1940 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44
1941 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4
1942 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0
1943 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1
1944 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1
1945 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1
1946 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2
1947 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1
1948
1949 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */
1950 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20
1951 /* MAC configuration applied */
1952 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0
1953 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_LEN 4
1954 /* MTU size */
1955 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4
1956 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_LEN 4
1957 /* IF Mode status */
1958 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8
1959 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_LEN 4
1960 /* MAC address configured */
1961 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12
1962 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8
1963 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12
1964 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16
1965
1966 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */
1967 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3)
1968 /* Rx Eye measurements */
1969 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0
1970 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4
1971 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK
1972
1973 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */
1974 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0
1975
1976 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */
1977 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3)
1978 /* Has the eye plot dump completed and data returned is valid? */
1979 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0
1980 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_LEN 4
1981 /* Rx Eye binary plot */
1982 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4
1983 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8
1984 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4
1985 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8
1986 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK
1987
1988 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */
1989 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0
1990
1991 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */
1992 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0
1993
1994 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */
1995 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4
1996 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0
1997 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_LEN 4
1998
1999 /* MC_CMD_FC_OUT_UHLINK msgresponse */
2000 #define MC_CMD_FC_OUT_UHLINK_LEN 0
2001
2002 /* MC_CMD_FC_OUT_SET_LINK msgresponse */
2003 #define MC_CMD_FC_OUT_SET_LINK_LEN 0
2004
2005 /* MC_CMD_FC_OUT_LICENSE msgresponse */
2006 #define MC_CMD_FC_OUT_LICENSE_LEN 12
2007 /* Count of valid keys */
2008 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0
2009 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_LEN 4
2010 /* Count of invalid keys */
2011 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4
2012 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_LEN 4
2013 /* Count of blacklisted keys */
2014 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8
2015 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_LEN 4
2016
2017 /* MC_CMD_FC_OUT_STARTUP msgresponse */
2018 #define MC_CMD_FC_OUT_STARTUP_LEN 4
2019 /* Capabilities of the FPGA/FC */
2020 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0
2021 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4
2022 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0
2023 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1
2024
2025 /* MC_CMD_FC_OUT_DMA_READ msgresponse */
2026 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1
2027 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252
2028 #define MC_CMD_FC_OUT_DMA_READ_LENMAX_MCDI2 1020
2029 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))
2030 /* The data read */
2031 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0
2032 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1
2033 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1
2034 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252
2035 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM_MCDI2 1020
2036
2037 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */
2038 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4
2039 /* Timer handle */
2040 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0
2041 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_LEN 4
2042
2043 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */
2044 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52
2045 /* Host supplied handle (unique) */
2046 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0
2047 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_LEN 4
2048 /* Address into which to transfer data in host */
2049 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4
2050 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8
2051 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4
2052 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8
2053 /* AOE address from which to transfer data */
2054 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12
2055 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8
2056 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12
2057 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16
2058 /* Length of AOE transfer (total) */
2059 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20
2060 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4
2061 /* Length of host transfer (total) */
2062 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24
2063 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_LEN 4
2064 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */
2065 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28
2066 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_LEN 4
2067 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32
2068 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_LEN 4
2069 /* When active, start read time */
2070 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36
2071 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8
2072 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36
2073 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40
2074 /* When active, end read time */
2075 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44
2076 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8
2077 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44
2078 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48
2079
2080 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */
2081 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0
2082
2083 /* MC_CMD_FC_OUT_LOG msgresponse */
2084 #define MC_CMD_FC_OUT_LOG_LEN 0
2085
2086 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */
2087 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24
2088 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0
2089 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_LEN 4
2090 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4
2091 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8
2092 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4
2093 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8
2094 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12
2095 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4
2096 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16
2097 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_LEN 4
2098 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20
2099 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_LEN 4
2100
2101 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */
2102 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0
2103
2104 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */
2105 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0
2106
2107 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */
2108 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0
2109
2110 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */
2111 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4
2112 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0
2113 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4
2114 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0
2115 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1
2116 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1
2117 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1
2118
2119 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */
2120 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8
2121 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0
2122 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_LEN 4
2123 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4
2124 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_LEN 4
2125
2126 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */
2127 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8
2128 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248
2129 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX_MCDI2 1016
2130 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num))
2131 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0
2132 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4
2133 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4
2134 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_LEN 4
2135 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0
2136 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8
2137 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0
2138 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4
2139 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0
2140 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31
2141 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127
2142
2143 /* MC_CMD_FC_OUT_SPI_READ msgresponse */
2144 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4
2145 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252
2146 #define MC_CMD_FC_OUT_SPI_READ_LENMAX_MCDI2 1020
2147 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num))
2148 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0
2149 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4
2150 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1
2151 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63
2152 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM_MCDI2 255
2153
2154 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */
2155 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0
2156
2157 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */
2158 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0
2159
2160 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */
2161 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8
2162 /* The 32-bit value read from the toggle count register */
2163 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0
2164 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_LEN 4
2165 /* The 32-bit value read from the clock enable count register */
2166 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4
2167 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_LEN 4
2168
2169 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */
2170 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0
2171
2172 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */
2173 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0
2174
2175 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */
2176 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8
2177 /* DDR soak test status word; bits [4:0] are relevant. */
2178 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0
2179 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4
2180 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0
2181 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1
2182 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1
2183 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1
2184 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2
2185 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1
2186 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3
2187 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1
2188 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4
2189 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1
2190 /* DDR soak test error count */
2191 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4
2192 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_LEN 4
2193
2194 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */
2195 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0
2196
2197 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */
2198 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0
2199
2200 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */
2201 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0
2202
2203 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */
2204 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0
2205
2206
2207 /***********************************/
2208 /* MC_CMD_AOE
2209  * AOE operations on MC
2210  */
2211 #define MC_CMD_AOE 0xa
2212
2213 /* MC_CMD_AOE_IN msgrequest */
2214 #define MC_CMD_AOE_IN_LEN 4
2215 #define MC_CMD_AOE_IN_OP_HDR_OFST 0
2216 #define MC_CMD_AOE_IN_OP_HDR_LEN 4
2217 #define MC_CMD_AOE_IN_OP_LBN 0
2218 #define MC_CMD_AOE_IN_OP_WIDTH 8
2219 /* enum: FPGA and CPLD information */
2220 #define MC_CMD_AOE_OP_INFO 0x1
2221 /* enum: Currents and voltages read from MCP3424s; DEBUG */
2222 #define MC_CMD_AOE_OP_CURRENTS 0x2
2223 /* enum: Temperatures at locations around the PCB; DEBUG */
2224 #define MC_CMD_AOE_OP_TEMPERATURES 0x3
2225 /* enum: Set CPLD to idle */
2226 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4
2227 /* enum: Read from CPLD register */
2228 #define MC_CMD_AOE_OP_CPLD_READ 0x5
2229 /* enum: Write to CPLD register */
2230 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6
2231 /* enum: Execute CPLD instruction */
2232 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7
2233 /* enum: Reprogram the CPLD on the AOE device */
2234 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8
2235 /* enum: AOE power control */
2236 #define MC_CMD_AOE_OP_POWER 0x9
2237 /* enum: AOE image loading */
2238 #define MC_CMD_AOE_OP_LOAD 0xa
2239 /* enum: Fan monitoring */
2240 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb
2241 /* enum: Fan failures since last reset */
2242 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc
2243 /* enum: Get generic AOE MAC statistics */
2244 #define MC_CMD_AOE_OP_MAC_STATS 0xd
2245 /* enum: Retrieve PHY specific information */
2246 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe
2247 /* enum: Write a number of JTAG primitive commands, return will give data */
2248 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf
2249 /* enum: Control access to the FPGA via the Siena JTAG Chain */
2250 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10
2251 /* enum: Set the MTU offset between Siena and AOE MACs */
2252 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11
2253 /* enum: How link state is handled */
2254 #define MC_CMD_AOE_OP_LINK_STATE 0x12
2255 /* enum: How Siena MAC statistics are reported (deprecated - use
2256  * MC_CMD_AOE_OP_ASIC_STATS)
2257  */
2258 #define MC_CMD_AOE_OP_SIENA_STATS 0x13
2259 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated
2260  * command MC_CMD_AOE_OP_SIENA_STATS
2261  */
2262 #define MC_CMD_AOE_OP_ASIC_STATS 0x13
2263 /* enum: DDR memory information */
2264 #define MC_CMD_AOE_OP_DDR 0x14
2265 /* enum: FC control */
2266 #define MC_CMD_AOE_OP_FC 0x15
2267 /* enum: DDR ECC status reads */
2268 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16
2269 /* enum: Commands for MC-SPI Master emulation */
2270 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17
2271 /* enum: Commands for FC boot control */
2272 #define MC_CMD_AOE_OP_FC_BOOT 0x18
2273 /* enum: Get number of internal ports */
2274 #define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19
2275 /* enum: Get FC assert information and register dump */
2276 #define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a
2277 /* enum: Set MUM startup FUSE byte with extended delay */
2278 #define MC_CMD_AOE_OP_MUM_STARTUP_FUSE 0x1b
2279
2280 /* MC_CMD_AOE_OUT msgresponse */
2281 #define MC_CMD_AOE_OUT_LEN 0
2282
2283 /* MC_CMD_AOE_IN_INFO msgrequest */
2284 #define MC_CMD_AOE_IN_INFO_LEN 4
2285 #define MC_CMD_AOE_IN_CMD_OFST 0
2286 #define MC_CMD_AOE_IN_CMD_LEN 4
2287
2288 /* MC_CMD_AOE_IN_CURRENTS msgrequest */
2289 #define MC_CMD_AOE_IN_CURRENTS_LEN 4
2290 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2291 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2292
2293 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */
2294 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4
2295 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2296 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2297
2298 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */
2299 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4
2300 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2301 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2302
2303 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */
2304 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12
2305 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2306 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2307 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4
2308 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_LEN 4
2309 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8
2310 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_LEN 4
2311
2312 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */
2313 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16
2314 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2315 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2316 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4
2317 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_LEN 4
2318 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8
2319 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_LEN 4
2320 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12
2321 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_LEN 4
2322
2323 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */
2324 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8
2325 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2326 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2327 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4
2328 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_LEN 4
2329
2330 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */
2331 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8
2332 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2333 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2334 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4
2335 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_LEN 4
2336 /* enum: Reprogram CPLD, poll for completion */
2337 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1
2338 /* enum: Reprogram CPLD, send event on completion */
2339 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3
2340 /* enum: Get status of reprogramming operation */
2341 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4
2342
2343 /* MC_CMD_AOE_IN_POWER msgrequest */
2344 #define MC_CMD_AOE_IN_POWER_LEN 8
2345 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2346 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2347 /* Turn on or off AOE power */
2348 #define MC_CMD_AOE_IN_POWER_OP_OFST 4
2349 #define MC_CMD_AOE_IN_POWER_OP_LEN 4
2350 /* enum: Turn off FPGA power */
2351 #define MC_CMD_AOE_IN_POWER_OFF 0x0
2352 /* enum: Turn on FPGA power */
2353 #define MC_CMD_AOE_IN_POWER_ON 0x1
2354 /* enum: Clear peak power measurement */
2355 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2
2356 /* enum: Show current power in sensors output */
2357 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3
2358 /* enum: Show peak power in sensors output */
2359 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4
2360 /* enum: Show current DDR current */
2361 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5
2362 /* enum: Show peak DDR current */
2363 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6
2364 /* enum: Clear peak DDR current */
2365 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7
2366
2367 /* MC_CMD_AOE_IN_LOAD msgrequest */
2368 #define MC_CMD_AOE_IN_LOAD_LEN 8
2369 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2370 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2371 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence
2372  */
2373 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4
2374 #define MC_CMD_AOE_IN_LOAD_IMAGE_LEN 4
2375
2376 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */
2377 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8
2378 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2379 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2380 /* If non zero report measured fan RPM rather than nominal */
2381 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4
2382 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_LEN 4
2383
2384 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */
2385 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4
2386 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2387 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2388
2389 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */
2390 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24
2391 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2392 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2393 /* AOE port */
2394 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4
2395 #define MC_CMD_AOE_IN_MAC_STATS_PORT_LEN 4
2396 /* Host memory address for statistics */
2397 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8
2398 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8
2399 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8
2400 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12
2401 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16
2402 #define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4
2403 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0
2404 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1
2405 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1
2406 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1
2407 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2
2408 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1
2409 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3
2410 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1
2411 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4
2412 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1
2413 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5
2414 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1
2415 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16
2416 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16
2417 /* Length of DMA data (optional) */
2418 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20
2419 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_LEN 4
2420
2421 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */
2422 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12
2423 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2424 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2425 /* AOE port */
2426 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4
2427 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_LEN 4
2428 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8
2429 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_LEN 4
2430
2431 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */
2432 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12
2433 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252
2434 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX_MCDI2 1020
2435 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num))
2436 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2437 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2438 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4
2439 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_LEN 4
2440 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8
2441 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4
2442 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1
2443 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61
2444 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM_MCDI2 253
2445
2446 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */
2447 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8
2448 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2449 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2450 /* Enable or disable access */
2451 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4
2452 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_LEN 4
2453 /* enum: Enable access */
2454 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1
2455 /* enum: Disable access */
2456 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2
2457
2458 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */
2459 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12
2460 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2461 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2462 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */
2463 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4
2464 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_LEN 4
2465 /* enum: Apply to all external ports */
2466 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000
2467 /* enum: Apply to all internal ports */
2468 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000
2469 /* The MTU offset to be applied to the external ports */
2470 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8
2471 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_LEN 4
2472
2473 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */
2474 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8
2475 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2476 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2477 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4
2478 #define MC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4
2479 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0
2480 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8
2481 /* enum: AOE and associated external port */
2482 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0
2483 /* enum: AOE and OR of all external ports */
2484 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1
2485 /* enum: Individual ports */
2486 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2
2487 /* enum: Configure link state mode on given AOE port */
2488 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3
2489 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8
2490 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8
2491 /* enum: No-op */
2492 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0
2493 /* enum: logical OR of all SFP ports link status */
2494 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1
2495 /* enum: logical AND of all SFP ports link status */
2496 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2
2497 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16
2498 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16
2499
2500 /* MC_CMD_AOE_IN_GET_ASIC_PORTS msgrequest */
2501 #define MC_CMD_AOE_IN_GET_ASIC_PORTS_LEN 4
2502 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2503 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2504
2505 /* MC_CMD_AOE_IN_GET_FC_ASSERT_INFO msgrequest */
2506 #define MC_CMD_AOE_IN_GET_FC_ASSERT_INFO_LEN 4
2507 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2508 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2509
2510 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */
2511 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8
2512 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2513 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2514 /* How MAC statistics are reported */
2515 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4
2516 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4
2517 /* enum: Statistics from Siena (default) */
2518 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0
2519 /* enum: Statistics from AOE external ports */
2520 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1
2521
2522 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */
2523 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8
2524 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2525 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2526 /* How MAC statistics are reported */
2527 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4
2528 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4
2529 /* enum: Statistics from the ASIC (default) */
2530 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0
2531 /* enum: Statistics from AOE external ports */
2532 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1
2533
2534 /* MC_CMD_AOE_IN_DDR msgrequest */
2535 #define MC_CMD_AOE_IN_DDR_LEN 12
2536 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2537 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2538 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4
2539 #define MC_CMD_AOE_IN_DDR_BANK_LEN 4
2540 /*            Enum values, see field(s): */
2541 /*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */
2542 /* Page index of SPD data */
2543 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8
2544 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_LEN 4
2545
2546 /* MC_CMD_AOE_IN_FC msgrequest */
2547 #define MC_CMD_AOE_IN_FC_LEN 4
2548 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2549 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2550
2551 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */
2552 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8
2553 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2554 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2555 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4
2556 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_LEN 4
2557 /*            Enum values, see field(s): */
2558 /*               MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */
2559
2560 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */
2561 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8
2562 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2563 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2564 /* Basic commands for MC SPI Master emulation. */
2565 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4
2566 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_LEN 4
2567 /* enum: MC SPI read */
2568 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0
2569 /* enum: MC SPI write */
2570 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1
2571
2572 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */
2573 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12
2574 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2575 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2576 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4
2577 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_LEN 4
2578 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8
2579 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_LEN 4
2580
2581 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */
2582 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16
2583 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2584 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2585 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4
2586 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_LEN 4
2587 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8
2588 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_LEN 4
2589 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12
2590 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_LEN 4
2591
2592 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */
2593 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8
2594 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2595 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2596 /* FC boot control flags */
2597 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4
2598 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4
2599 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0
2600 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1
2601
2602 /* MC_CMD_AOE_IN_MUM_STARTUP_FUSE msgrequest: On AOE2, set MUM startup FUSE
2603  * byte with extended delay of 64ms. On some servers with noisy power rails,
2604  * this ensures that the MUM IO pins do not show spurious transitions while the
2605  * power rails are stabilising. Note that this operation requires a hard-
2606  * powercycle to take effect. See bug76446.
2607  */
2608 #define MC_CMD_AOE_IN_MUM_STARTUP_FUSE_LEN 4
2609 /* Must be MC_CMD_AOE_OP_MUM_STARTUP_FUSE */
2610 /*            MC_CMD_AOE_IN_CMD_OFST 0 */
2611 /*            MC_CMD_AOE_IN_CMD_LEN 4 */
2612
2613 /* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */
2614 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144
2615 /* Assertion status flag. */
2616 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0
2617 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4
2618 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8
2619 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8
2620 /* enum: No crash data available */
2621 /*               MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 */
2622 /* enum: New crash data available */
2623 /*               MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */
2624 /* enum: Crash data has been sent */
2625 /*               MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */
2626 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0
2627 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8
2628 /* enum: No crash has been recorded. */
2629 /*               MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 */
2630 /* enum: Crash due to exception. */
2631 /*               MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 */
2632 /* enum: Crash due to assertion. */
2633 /*               MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 */
2634 /* Failing PC value */
2635 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_OFST 4
2636 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_LEN 4
2637 /* Saved GP regs */
2638 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_OFST 8
2639 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_LEN 4
2640 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_NUM 31
2641 /* Exception Type */
2642 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_OFST 132
2643 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_LEN 4
2644 /* Instruction at which exception occurred */
2645 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_OFST 136
2646 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_LEN 4
2647 /* BAD Address that triggered address-based exception */
2648 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_OFST 140
2649 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_LEN 4
2650
2651 /* MC_CMD_AOE_OUT_INFO msgresponse */
2652 #define MC_CMD_AOE_OUT_INFO_LEN 44
2653 /* JTAG IDCODE of CPLD */
2654 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0
2655 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_LEN 4
2656 /* Version of CPLD */
2657 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4
2658 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_LEN 4
2659 /* JTAG IDCODE of FPGA */
2660 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8
2661 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_LEN 4
2662 /* JTAG USERCODE of FPGA */
2663 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12
2664 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_LEN 4
2665 /* FPGA type - read from CPLD straps */
2666 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16
2667 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4
2668 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */
2669 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */
2670 /* FPGA state (debug) */
2671 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20
2672 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4
2673 /* FPGA image - partition from which loaded */
2674 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24
2675 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_LEN 4
2676 /* FC state */
2677 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28
2678 #define MC_CMD_AOE_OUT_INFO_FC_STATE_LEN 4
2679 /* enum: Set if watchdog working */
2680 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1
2681 /* enum: Set if MC-FC communications working */
2682 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2
2683 /* Random pieces of information */
2684 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32
2685 #define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4
2686 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */
2687 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1
2688 /* enum: CPLD apparently good */
2689 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2
2690 /* enum: FPGA working normally */
2691 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4
2692 /* enum: FPGA is powered */
2693 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8
2694 /* enum: Board has incompatible SODIMMs fitted */
2695 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10
2696 /* enum: Board has ByteBlaster connected */
2697 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20
2698 /* enum: FPGA Boot flash has an invalid header. */
2699 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40
2700 /* enum: FPGA Application flash is accessible. */
2701 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80
2702 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */
2703 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36
2704 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4
2705 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */
2706 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */
2707 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */
2708 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */
2709 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */
2710 /* Result of FC booting - not valid while a ByteBlaster is connected. */
2711 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40
2712 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4
2713 /* enum: No error */
2714 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0
2715 /* enum: Bad address set in CPLD */
2716 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1
2717 /* enum: Bad header */
2718 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2
2719 /* enum: Bad text section details */
2720 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3
2721 /* enum: Bad checksum */
2722 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4
2723 /* enum: Bad BSP */
2724 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5
2725 /* enum: Flash mode is invalid */
2726 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6
2727 /* enum: FC application loaded and execution attempted */
2728 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80
2729 /* enum: FC application Started */
2730 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81
2731 /* enum: No bootrom in FPGA */
2732 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff
2733
2734 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */
2735 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68
2736 /* Set of currents and voltages (mA or mV as appropriate) */
2737 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0
2738 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4
2739 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17
2740 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */
2741 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */
2742 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */
2743 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */
2744 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */
2745 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */
2746 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */
2747 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */
2748 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */
2749 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */
2750 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */
2751 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */
2752 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */
2753 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */
2754 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */
2755 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */
2756 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */
2757
2758 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */
2759 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40
2760 /* Set of temperatures */
2761 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0
2762 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4
2763 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10
2764 /* enum: The first set of enum values are for Modena code. */
2765 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0
2766 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */
2767 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */
2768 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */
2769 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */
2770 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */
2771 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */
2772 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */
2773 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */
2774 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */
2775 /* enum: The second set of enum values are for Sorrento code. */
2776 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0
2777 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */
2778 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */
2779 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */
2780 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */
2781 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */
2782 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */
2783 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */
2784 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */
2785
2786 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */
2787 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4
2788 /* The value read from the CPLD */
2789 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0
2790 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_LEN 4
2791
2792 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */
2793 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4
2794 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252
2795 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX_MCDI2 1020
2796 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))
2797 /* Failure counts for each fan */
2798 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0
2799 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4
2800 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1
2801 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63
2802 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM_MCDI2 255
2803
2804 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */
2805 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4
2806 /* Results of status command (only) */
2807 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0
2808 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_LEN 4
2809
2810 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */
2811 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0
2812
2813 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */
2814 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0
2815
2816 /* MC_CMD_AOE_OUT_LOAD msgresponse */
2817 #define MC_CMD_AOE_OUT_LOAD_LEN 0
2818
2819 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */
2820 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0
2821
2822 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA
2823  * for details
2824  */
2825 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
2826 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0
2827 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8
2828 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0
2829 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4
2830 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
2831
2832 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */
2833 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5
2834 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252
2835 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX_MCDI2 1020
2836 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))
2837 /* in bytes */
2838 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0
2839 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4
2840 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4
2841 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1
2842 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1
2843 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248
2844 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016
2845
2846 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */
2847 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12
2848 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252
2849 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX_MCDI2 1020
2850 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))
2851 /* Used to align the in and out data blocks so the MC can re-use the cmd */
2852 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0
2853 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4
2854 /* out bytes */
2855 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4
2856 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_LEN 4
2857 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8
2858 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4
2859 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1
2860 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61
2861 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM_MCDI2 253
2862
2863 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */
2864 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0
2865
2866 /* MC_CMD_AOE_OUT_DDR msgresponse */
2867 #define MC_CMD_AOE_OUT_DDR_LENMIN 17
2868 #define MC_CMD_AOE_OUT_DDR_LENMAX 252
2869 #define MC_CMD_AOE_OUT_DDR_LENMAX_MCDI2 1020
2870 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))
2871 /* Information on the module. */
2872 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0
2873 #define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4
2874 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0
2875 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1
2876 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1
2877 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1
2878 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2
2879 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1
2880 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3
2881 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1
2882 /* Memory size, in MB. */
2883 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4
2884 #define MC_CMD_AOE_OUT_DDR_CAPACITY_LEN 4
2885 /* The memory type, as reported from SPD information */
2886 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8
2887 #define MC_CMD_AOE_OUT_DDR_TYPE_LEN 4
2888 /* Nominal voltage of the module (as applied) */
2889 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12
2890 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_LEN 4
2891 /* SPD data read from the module */
2892 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16
2893 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1
2894 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1
2895 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236
2896 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM_MCDI2 1004
2897
2898 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */
2899 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0
2900
2901 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */
2902 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0
2903
2904 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */
2905 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0
2906
2907 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */
2908 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0
2909
2910 /* MC_CMD_AOE_OUT_FC msgresponse */
2911 #define MC_CMD_AOE_OUT_FC_LEN 0
2912
2913 /* MC_CMD_AOE_OUT_GET_ASIC_PORTS msgresponse */
2914 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_LEN 4
2915 /* get the number of internal ports */
2916 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_OFST 0
2917 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_LEN 4
2918
2919 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */
2920 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8
2921 /* Flags describing status info on the module. */
2922 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0
2923 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4
2924 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0
2925 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1
2926 /* DDR ECC status on the module. */
2927 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4
2928 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4
2929 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0
2930 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1
2931 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1
2932 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1
2933 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2
2934 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1
2935 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8
2936 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8
2937 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16
2938 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8
2939 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24
2940 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8
2941
2942 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */
2943 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4
2944 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0
2945 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_LEN 4
2946
2947 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */
2948 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0
2949
2950 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */
2951 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0
2952
2953 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */
2954 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0
2955
2956 /* MC_CMD_AOE_OUT_MUM_STARTUP_FUSE msgresponse */
2957 #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_LEN 4
2958 /* Current value of startup FUSE byte (fusebyte#4) read back after the update
2959  * operation.
2960  */
2961 #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_OFST 0
2962 #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_LEN 4
2963
2964 #endif /* _SIENA_MC_DRIVER_PCOL_AOE_H */