ceph/src/seastar/dpdk/drivers/net/sfc/base/hunt_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2012-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9 #if EFSYS_OPT_MON_MCDI
  10 #include "mcdi_mon.h"
  11 #endif
  12
  13 #if EFSYS_OPT_HUNTINGTON
  14
  15 #include "ef10_tlv_layout.h"
  16
  17 static  __checkReturn   efx_rc_t
  18 hunt_nic_get_required_pcie_bandwidth(
  19         __in            efx_nic_t *enp,
  20         __out           uint32_t *bandwidth_mbpsp)
  21 {
  22         uint32_t port_modes;
  23         uint32_t bandwidth;
  24         efx_rc_t rc;
  25
  26         /*
  27          * On Huntington, the firmware may not give us the current port mode, so
  28          * we need to go by the set of available port modes and assume the most
  29          * capable mode is in use.
  30          */
  31
  32         if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
  33                     NULL, NULL)) != 0) {
  34                 /* No port mode info available */
  35                 bandwidth = 0;
  36                 goto out;
  37         }
  38
  39         if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {
  40                 /*
  41                  * This needs the full PCIe bandwidth (and could use
  42                  * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
  43                  */
  44                 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
  45                             EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
  46                         goto fail1;
  47         } else {
  48                 if (port_modes & (1U << TLV_PORT_MODE_40G)) {
  49                         bandwidth = 40000;
  50                 } else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {
  51                         bandwidth = 4 * 10000;
  52                 } else {
  53                         /* Assume two 10G ports */
  54                         bandwidth = 2 * 10000;
  55                 }
  56         }
  57
  58 out:
  59         *bandwidth_mbpsp = bandwidth;
  60
  61         return (0);
  62
  63 fail1:
  64         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  65
  66         return (rc);
  67 }
  68
  69         __checkReturn   efx_rc_t
  70 hunt_board_cfg(
  71         __in            efx_nic_t *enp)
  72 {
  73         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
  74         efx_port_t *epp = &(enp->en_port);
  75         uint32_t flags;
  76         uint32_t sysclk, dpcpu_clk;
  77         uint32_t bandwidth;
  78         efx_rc_t rc;
  79
  80         /*
  81          * Enable firmware workarounds for hardware errata.
  82          * Expected responses are:
  83          *  - 0 (zero):
  84          *      Success: workaround enabled or disabled as requested.
  85          *  - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
  86          *      Firmware does not support the MC_CMD_WORKAROUND request.
  87          *      (assume that the workaround is not supported).
  88          *  - MC_CMD_ERR_ENOENT (reported as ENOENT):
  89          *      Firmware does not support the requested workaround.
  90          *  - MC_CMD_ERR_EPERM  (reported as EACCES):
  91          *      Unprivileged function cannot enable/disable workarounds.
  92          *
  93          * See efx_mcdi_request_errcode() for MCDI error translations.
  94          */
  95
  96         /*
  97          * If the bug35388 workaround is enabled, then use an indirect access
  98          * method to avoid unsafe EVQ writes.
  99          */
 100         rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
 101             NULL);
 102         if ((rc == 0) || (rc == EACCES))
 103                 encp->enc_bug35388_workaround = B_TRUE;
 104         else if ((rc == ENOTSUP) || (rc == ENOENT))
 105                 encp->enc_bug35388_workaround = B_FALSE;
 106         else
 107                 goto fail1;
 108
 109         /*
 110          * If the bug41750 workaround is enabled, then do not test interrupts,
 111          * as the test will fail (seen with Greenport controllers).
 112          */
 113         rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
 114             NULL);
 115         if (rc == 0) {
 116                 encp->enc_bug41750_workaround = B_TRUE;
 117         } else if (rc == EACCES) {
 118                 /* Assume a controller with 40G ports needs the workaround. */
 119                 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
 120                         encp->enc_bug41750_workaround = B_TRUE;
 121                 else
 122                         encp->enc_bug41750_workaround = B_FALSE;
 123         } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
 124                 encp->enc_bug41750_workaround = B_FALSE;
 125         } else {
 126                 goto fail2;
 127         }
 128         if (EFX_PCI_FUNCTION_IS_VF(encp)) {
 129                 /* Interrupt testing does not work for VFs. See bug50084. */
 130                 encp->enc_bug41750_workaround = B_TRUE;
 131         }
 132
 133         /*
 134          * If the bug26807 workaround is enabled, then firmware has enabled
 135          * support for chained multicast filters. Firmware will reset (FLR)
 136          * functions which have filters in the hardware filter table when the
 137          * workaround is enabled/disabled.
 138          *
 139          * We must recheck if the workaround is enabled after inserting the
 140          * first hardware filter, in case it has been changed since this check.
 141          */
 142         rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
 143             B_TRUE, &flags);
 144         if (rc == 0) {
 145                 encp->enc_bug26807_workaround = B_TRUE;
 146                 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
 147                         /*
 148                          * Other functions had installed filters before the
 149                          * workaround was enabled, and they have been reset
 150                          * by firmware.
 151                          */
 152                         EFSYS_PROBE(bug26807_workaround_flr_done);
 153                         /* FIXME: bump MC warm boot count ? */
 154                 }
 155         } else if (rc == EACCES) {
 156                 /*
 157                  * Unprivileged functions cannot enable the workaround in older
 158                  * firmware.
 159                  */
 160                 encp->enc_bug26807_workaround = B_FALSE;
 161         } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
 162                 encp->enc_bug26807_workaround = B_FALSE;
 163         } else {
 164                 goto fail3;
 165         }
 166
 167         /* Get clock frequencies (in MHz). */
 168         if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
 169                 goto fail4;
 170
 171         /*
 172          * The Huntington timer quantum is 1536 sysclk cycles, documented for
 173          * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
 174          */
 175         encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
 176         if (encp->enc_bug35388_workaround) {
 177                 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
 178                 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
 179         } else {
 180                 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
 181                 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 182         }
 183
 184         encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
 185
 186         /* Checksums for TSO sends can be incorrect on Huntington. */
 187         encp->enc_bug61297_workaround = B_TRUE;
 188
 189         encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
 190         encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
 191         encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
 192
 193         /* Alignment for receive packet DMA buffers */
 194         encp->enc_rx_buf_align_start = 1;
 195         encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
 196
 197         encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
 198         encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
 199
 200         encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
 201         encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
 202
 203         /*
 204          * The workaround for bug35388 uses the top bit of transmit queue
 205          * descriptor writes, preventing the use of 4096 descriptor TXQs.
 206          */
 207         encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ?
 208             HUNT_TXQ_MAXNDESCS_BUG35388_WORKAROUND :
 209             HUNT_TXQ_MAXNDESCS;
 210         encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
 211
 212         EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
 213         encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
 214         encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
 215         encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
 216
 217         if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
 218                 goto fail5;
 219         encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 220
 221         /* All Huntington devices have a PCIe Gen3, 8 lane connector */
 222         encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 223
 224         return (0);
 225
 226 fail5:
 227         EFSYS_PROBE(fail5);
 228 fail4:
 229         EFSYS_PROBE(fail4);
 230 fail3:
 231         EFSYS_PROBE(fail3);
 232 fail2:
 233         EFSYS_PROBE(fail2);
 234 fail1:
 235         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 236
 237         return (rc);
 238 }
 239
 240
 241 #endif  /* EFSYS_OPT_HUNTINGTON */