ceph/src/seastar/dpdk/drivers/net/sfc/base/siena_nic.c

   1 /*
   2  * Copyright (c) 2009-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #include "efx.h"
  32 #include "efx_impl.h"
  33 #include "mcdi_mon.h"
  34
  35 #if EFSYS_OPT_SIENA
  36
  37 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
  38
  39 static  __checkReturn           efx_rc_t
  40 siena_nic_get_partn_mask(
  41         __in                    efx_nic_t *enp,
  42         __out                   unsigned int *maskp)
  43 {
  44         efx_mcdi_req_t req;
  45         uint8_t payload[MAX(MC_CMD_NVRAM_TYPES_IN_LEN,
  46                             MC_CMD_NVRAM_TYPES_OUT_LEN)];
  47         efx_rc_t rc;
  48
  49         (void) memset(payload, 0, sizeof (payload));
  50         req.emr_cmd = MC_CMD_NVRAM_TYPES;
  51         req.emr_in_buf = payload;
  52         req.emr_in_length = MC_CMD_NVRAM_TYPES_IN_LEN;
  53         req.emr_out_buf = payload;
  54         req.emr_out_length = MC_CMD_NVRAM_TYPES_OUT_LEN;
  55
  56         efx_mcdi_execute(enp, &req);
  57
  58         if (req.emr_rc != 0) {
  59                 rc = req.emr_rc;
  60                 goto fail1;
  61         }
  62
  63         if (req.emr_out_length_used < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  64                 rc = EMSGSIZE;
  65                 goto fail2;
  66         }
  67
  68         *maskp = MCDI_OUT_DWORD(req, NVRAM_TYPES_OUT_TYPES);
  69
  70         return (0);
  71
  72 fail2:
  73         EFSYS_PROBE(fail2);
  74 fail1:
  75         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  76
  77         return (rc);
  78 }
  79
  80 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
  81
  82 static  __checkReturn   efx_rc_t
  83 siena_board_cfg(
  84         __in            efx_nic_t *enp)
  85 {
  86         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
  87         uint8_t mac_addr[6];
  88         efx_dword_t capabilities;
  89         uint32_t board_type;
  90         uint32_t nevq, nrxq, ntxq;
  91         efx_rc_t rc;
  92
  93         /* External port identifier using one-based port numbering */
  94         encp->enc_external_port = (uint8_t)enp->en_mcdi.em_emip.emi_port;
  95
  96         /* Board configuration */
  97         if ((rc = efx_mcdi_get_board_cfg(enp, &board_type,
  98                     &capabilities, mac_addr)) != 0)
  99                 goto fail1;
 100
 101         EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
 102
 103         encp->enc_board_type = board_type;
 104
 105         /*
 106          * There is no possibility to determine the number of PFs on Siena
 107          * by issuing MCDI request, and it is not an easy task to find the
 108          * value based on the board type, so 'enc_hw_pf_count' is set to 1
 109          */
 110         encp->enc_hw_pf_count = 1;
 111
 112         /* Additional capabilities */
 113         encp->enc_clk_mult = 1;
 114         if (EFX_DWORD_FIELD(capabilities, MC_CMD_CAPABILITIES_TURBO)) {
 115                 enp->en_features |= EFX_FEATURE_TURBO;
 116
 117                 if (EFX_DWORD_FIELD(capabilities,
 118                         MC_CMD_CAPABILITIES_TURBO_ACTIVE)) {
 119                         encp->enc_clk_mult = 2;
 120                 }
 121         }
 122
 123         encp->enc_evq_timer_quantum_ns =
 124                 EFX_EVQ_SIENA_TIMER_QUANTUM_NS / encp->enc_clk_mult;
 125         encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
 126                 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 127
 128         /* When hash header insertion is enabled, Siena inserts 16 bytes */
 129         encp->enc_rx_prefix_size = 16;
 130
 131         /* Alignment for receive packet DMA buffers */
 132         encp->enc_rx_buf_align_start = 1;
 133         encp->enc_rx_buf_align_end = 1;
 134
 135         /* Alignment for WPTR updates */
 136         encp->enc_rx_push_align = 1;
 137
 138         encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
 139         /* Fragments must not span 4k boundaries. */
 140         encp->enc_tx_dma_desc_boundary = 4096;
 141
 142         /* Resource limits */
 143         rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
 144         if (rc != 0) {
 145                 if (rc != ENOTSUP)
 146                         goto fail2;
 147
 148                 nevq = 1024;
 149                 nrxq = EFX_RXQ_LIMIT_TARGET;
 150                 ntxq = EFX_TXQ_LIMIT_TARGET;
 151         }
 152         encp->enc_evq_limit = nevq;
 153         encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
 154         encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
 155
 156         encp->enc_txq_max_ndescs = 4096;
 157
 158         encp->enc_buftbl_limit = SIENA_SRAM_ROWS -
 159             (encp->enc_txq_limit * EFX_TXQ_DC_NDESCS(EFX_TXQ_DC_SIZE)) -
 160             (encp->enc_rxq_limit * EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
 161
 162         encp->enc_hw_tx_insert_vlan_enabled = B_FALSE;
 163         encp->enc_fw_assisted_tso_enabled = B_FALSE;
 164         encp->enc_fw_assisted_tso_v2_enabled = B_FALSE;
 165         encp->enc_fw_assisted_tso_v2_n_contexts = 0;
 166         encp->enc_allow_set_mac_with_installed_filters = B_TRUE;
 167         encp->enc_rx_packed_stream_supported = B_FALSE;
 168         encp->enc_rx_var_packed_stream_supported = B_FALSE;
 169
 170         /* Siena supports two 10G ports, and 8 lanes of PCIe Gen2 */
 171         encp->enc_required_pcie_bandwidth_mbps = 2 * 10000;
 172         encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN2;
 173
 174         encp->enc_fw_verified_nvram_update_required = B_FALSE;
 175
 176         return (0);
 177
 178 fail2:
 179         EFSYS_PROBE(fail2);
 180 fail1:
 181         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 182
 183         return (rc);
 184 }
 185
 186 static  __checkReturn   efx_rc_t
 187 siena_phy_cfg(
 188         __in            efx_nic_t *enp)
 189 {
 190         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 191         efx_rc_t rc;
 192
 193         /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
 194         if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
 195                 goto fail1;
 196
 197 #if EFSYS_OPT_PHY_STATS
 198         /* Convert the MCDI statistic mask into the EFX_PHY_STAT mask */
 199         siena_phy_decode_stats(enp, encp->enc_mcdi_phy_stat_mask,
 200                             NULL, &encp->enc_phy_stat_mask, NULL);
 201 #endif  /* EFSYS_OPT_PHY_STATS */
 202
 203         return (0);
 204
 205 fail1:
 206         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 207
 208         return (rc);
 209 }
 210
 211         __checkReturn   efx_rc_t
 212 siena_nic_probe(
 213         __in            efx_nic_t *enp)
 214 {
 215         efx_port_t *epp = &(enp->en_port);
 216         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 217         siena_link_state_t sls;
 218         unsigned int mask;
 219         efx_oword_t oword;
 220         efx_rc_t rc;
 221
 222         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
 223
 224         /* Test BIU */
 225         if ((rc = efx_nic_biu_test(enp)) != 0)
 226                 goto fail1;
 227
 228         /* Clear the region register */
 229         EFX_POPULATE_OWORD_4(oword,
 230             FRF_AZ_ADR_REGION0, 0,
 231             FRF_AZ_ADR_REGION1, (1 << 16),
 232             FRF_AZ_ADR_REGION2, (2 << 16),
 233             FRF_AZ_ADR_REGION3, (3 << 16));
 234         EFX_BAR_WRITEO(enp, FR_AZ_ADR_REGION_REG, &oword);
 235
 236         /* Read clear any assertion state */
 237         if ((rc = efx_mcdi_read_assertion(enp)) != 0)
 238                 goto fail2;
 239
 240         /* Exit the assertion handler */
 241         if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
 242                 goto fail3;
 243
 244         /* Wrestle control from the BMC */
 245         if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
 246                 goto fail4;
 247
 248         if ((rc = siena_board_cfg(enp)) != 0)
 249                 goto fail5;
 250
 251         if ((rc = siena_phy_cfg(enp)) != 0)
 252                 goto fail6;
 253
 254         /* Obtain the default PHY advertised capabilities */
 255         if ((rc = siena_nic_reset(enp)) != 0)
 256                 goto fail7;
 257         if ((rc = siena_phy_get_link(enp, &sls)) != 0)
 258                 goto fail8;
 259         epp->ep_default_adv_cap_mask = sls.sls_adv_cap_mask;
 260         epp->ep_adv_cap_mask = sls.sls_adv_cap_mask;
 261
 262 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 263         if ((rc = siena_nic_get_partn_mask(enp, &mask)) != 0)
 264                 goto fail9;
 265         enp->en_u.siena.enu_partn_mask = mask;
 266 #endif
 267
 268 #if EFSYS_OPT_MAC_STATS
 269         /* Wipe the MAC statistics */
 270         if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
 271                 goto fail10;
 272 #endif
 273
 274 #if EFSYS_OPT_LOOPBACK
 275         if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
 276                 goto fail11;
 277 #endif
 278
 279 #if EFSYS_OPT_MON_STATS
 280         if ((rc = mcdi_mon_cfg_build(enp)) != 0)
 281                 goto fail12;
 282 #endif
 283
 284         encp->enc_features = enp->en_features;
 285
 286         return (0);
 287
 288 #if EFSYS_OPT_MON_STATS
 289 fail12:
 290         EFSYS_PROBE(fail12);
 291 #endif
 292 #if EFSYS_OPT_LOOPBACK
 293 fail11:
 294         EFSYS_PROBE(fail11);
 295 #endif
 296 #if EFSYS_OPT_MAC_STATS
 297 fail10:
 298         EFSYS_PROBE(fail10);
 299 #endif
 300 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 301 fail9:
 302         EFSYS_PROBE(fail9);
 303 #endif
 304 fail8:
 305         EFSYS_PROBE(fail8);
 306 fail7:
 307         EFSYS_PROBE(fail7);
 308 fail6:
 309         EFSYS_PROBE(fail6);
 310 fail5:
 311         EFSYS_PROBE(fail5);
 312 fail4:
 313         EFSYS_PROBE(fail4);
 314 fail3:
 315         EFSYS_PROBE(fail3);
 316 fail2:
 317         EFSYS_PROBE(fail2);
 318 fail1:
 319         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 320
 321         return (rc);
 322 }
 323
 324         __checkReturn   efx_rc_t
 325 siena_nic_reset(
 326         __in            efx_nic_t *enp)
 327 {
 328         efx_mcdi_req_t req;
 329         efx_rc_t rc;
 330
 331         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
 332
 333         /* siena_nic_reset() is called to recover from BADASSERT failures. */
 334         if ((rc = efx_mcdi_read_assertion(enp)) != 0)
 335                 goto fail1;
 336         if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
 337                 goto fail2;
 338
 339         /*
 340          * Bug24908: ENTITY_RESET_IN_LEN is non zero but zero may be supplied
 341          * for backwards compatibility with PORT_RESET_IN_LEN.
 342          */
 343         EFX_STATIC_ASSERT(MC_CMD_ENTITY_RESET_OUT_LEN == 0);
 344
 345         req.emr_cmd = MC_CMD_ENTITY_RESET;
 346         req.emr_in_buf = NULL;
 347         req.emr_in_length = 0;
 348         req.emr_out_buf = NULL;
 349         req.emr_out_length = 0;
 350
 351         efx_mcdi_execute(enp, &req);
 352
 353         if (req.emr_rc != 0) {
 354                 rc = req.emr_rc;
 355                 goto fail3;
 356         }
 357
 358         return (0);
 359
 360 fail3:
 361         EFSYS_PROBE(fail3);
 362 fail2:
 363         EFSYS_PROBE(fail2);
 364 fail1:
 365         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 366
 367         return (0);
 368 }
 369
 370 static                  void
 371 siena_nic_rx_cfg(
 372         __in            efx_nic_t *enp)
 373 {
 374         efx_oword_t oword;
 375
 376         /*
 377          * RX_INGR_EN is always enabled on Siena, because we rely on
 378          * the RX parser to be resiliant to missing SOP/EOP.
 379          */
 380         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
 381         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_INGR_EN, 1);
 382         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
 383
 384         /* Disable parsing of additional 802.1Q in Q packets */
 385         EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
 386         EFX_SET_OWORD_FIELD(oword, FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES, 0);
 387         EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
 388 }
 389
 390 static                  void
 391 siena_nic_usrev_dis(
 392         __in            efx_nic_t *enp)
 393 {
 394         efx_oword_t     oword;
 395
 396         EFX_POPULATE_OWORD_1(oword, FRF_CZ_USREV_DIS, 1);
 397         EFX_BAR_WRITEO(enp, FR_CZ_USR_EV_CFG, &oword);
 398 }
 399
 400         __checkReturn   efx_rc_t
 401 siena_nic_init(
 402         __in            efx_nic_t *enp)
 403 {
 404         efx_rc_t rc;
 405
 406         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
 407
 408         /* Enable reporting of some events (e.g. link change) */
 409         if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
 410                 goto fail1;
 411
 412         siena_sram_init(enp);
 413
 414         /* Configure Siena's RX block */
 415         siena_nic_rx_cfg(enp);
 416
 417         /* Disable USR_EVents for now */
 418         siena_nic_usrev_dis(enp);
 419
 420         /* bug17057: Ensure set_link is called */
 421         if ((rc = siena_phy_reconfigure(enp)) != 0)
 422                 goto fail2;
 423
 424         enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V1;
 425
 426         return (0);
 427
 428 fail2:
 429         EFSYS_PROBE(fail2);
 430 fail1:
 431         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 432
 433         return (rc);
 434 }
 435
 436                         void
 437 siena_nic_fini(
 438         __in            efx_nic_t *enp)
 439 {
 440         _NOTE(ARGUNUSED(enp))
 441 }
 442
 443                         void
 444 siena_nic_unprobe(
 445         __in            efx_nic_t *enp)
 446 {
 447 #if EFSYS_OPT_MON_STATS
 448         mcdi_mon_cfg_free(enp);
 449 #endif /* EFSYS_OPT_MON_STATS */
 450         (void) efx_mcdi_drv_attach(enp, B_FALSE);
 451 }
 452
 453 #if EFSYS_OPT_DIAG
 454
 455 static efx_register_set_t __siena_registers[] = {
 456         { FR_AZ_ADR_REGION_REG_OFST, 0, 1 },
 457         { FR_CZ_USR_EV_CFG_OFST, 0, 1 },
 458         { FR_AZ_RX_CFG_REG_OFST, 0, 1 },
 459         { FR_AZ_TX_CFG_REG_OFST, 0, 1 },
 460         { FR_AZ_TX_RESERVED_REG_OFST, 0, 1 },
 461         { FR_AZ_SRM_TX_DC_CFG_REG_OFST, 0, 1 },
 462         { FR_AZ_RX_DC_CFG_REG_OFST, 0, 1 },
 463         { FR_AZ_RX_DC_PF_WM_REG_OFST, 0, 1 },
 464         { FR_AZ_DP_CTRL_REG_OFST, 0, 1 },
 465         { FR_BZ_RX_RSS_TKEY_REG_OFST, 0, 1},
 466         { FR_CZ_RX_RSS_IPV6_REG1_OFST, 0, 1},
 467         { FR_CZ_RX_RSS_IPV6_REG2_OFST, 0, 1},
 468         { FR_CZ_RX_RSS_IPV6_REG3_OFST, 0, 1}
 469 };
 470
 471 static const uint32_t __siena_register_masks[] = {
 472         0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF,
 473         0x000103FF, 0x00000000, 0x00000000, 0x00000000,
 474         0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000,
 475         0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF,
 476         0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF,
 477         0x001FFFFF, 0x00000000, 0x00000000, 0x00000000,
 478         0x00000003, 0x00000000, 0x00000000, 0x00000000,
 479         0x000003FF, 0x00000000, 0x00000000, 0x00000000,
 480         0x00000FFF, 0x00000000, 0x00000000, 0x00000000,
 481         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 482         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 483         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 484         0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000
 485 };
 486
 487 static efx_register_set_t __siena_tables[] = {
 488         { FR_AZ_RX_FILTER_TBL0_OFST, FR_AZ_RX_FILTER_TBL0_STEP,
 489             FR_AZ_RX_FILTER_TBL0_ROWS },
 490         { FR_CZ_RX_MAC_FILTER_TBL0_OFST, FR_CZ_RX_MAC_FILTER_TBL0_STEP,
 491             FR_CZ_RX_MAC_FILTER_TBL0_ROWS },
 492         { FR_AZ_RX_DESC_PTR_TBL_OFST,
 493             FR_AZ_RX_DESC_PTR_TBL_STEP, FR_CZ_RX_DESC_PTR_TBL_ROWS },
 494         { FR_AZ_TX_DESC_PTR_TBL_OFST,
 495             FR_AZ_TX_DESC_PTR_TBL_STEP, FR_CZ_TX_DESC_PTR_TBL_ROWS },
 496         { FR_AZ_TIMER_TBL_OFST, FR_AZ_TIMER_TBL_STEP, FR_CZ_TIMER_TBL_ROWS },
 497         { FR_CZ_TX_FILTER_TBL0_OFST,
 498             FR_CZ_TX_FILTER_TBL0_STEP, FR_CZ_TX_FILTER_TBL0_ROWS },
 499         { FR_CZ_TX_MAC_FILTER_TBL0_OFST,
 500             FR_CZ_TX_MAC_FILTER_TBL0_STEP, FR_CZ_TX_MAC_FILTER_TBL0_ROWS }
 501 };
 502
 503 static const uint32_t __siena_table_masks[] = {
 504         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000003FF,
 505         0xFFFF0FFF, 0xFFFFFFFF, 0x00000E7F, 0x00000000,
 506         0xFFFFFFFE, 0x0FFFFFFF, 0x01800000, 0x00000000,
 507         0xFFFFFFFE, 0x0FFFFFFF, 0x0C000000, 0x00000000,
 508         0x3FFFFFFF, 0x00000000, 0x00000000, 0x00000000,
 509         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x000013FF,
 510         0xFFFF07FF, 0xFFFFFFFF, 0x0000007F, 0x00000000,
 511 };
 512
 513         __checkReturn   efx_rc_t
 514 siena_nic_register_test(
 515         __in            efx_nic_t *enp)
 516 {
 517         efx_register_set_t *rsp;
 518         const uint32_t *dwordp;
 519         unsigned int nitems;
 520         unsigned int count;
 521         efx_rc_t rc;
 522
 523         /* Fill out the register mask entries */
 524         EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_register_masks)
 525                     == EFX_ARRAY_SIZE(__siena_registers) * 4);
 526
 527         nitems = EFX_ARRAY_SIZE(__siena_registers);
 528         dwordp = __siena_register_masks;
 529         for (count = 0; count < nitems; ++count) {
 530                 rsp = __siena_registers + count;
 531                 rsp->mask.eo_u32[0] = *dwordp++;
 532                 rsp->mask.eo_u32[1] = *dwordp++;
 533                 rsp->mask.eo_u32[2] = *dwordp++;
 534                 rsp->mask.eo_u32[3] = *dwordp++;
 535         }
 536
 537         /* Fill out the register table entries */
 538         EFX_STATIC_ASSERT(EFX_ARRAY_SIZE(__siena_table_masks)
 539                     == EFX_ARRAY_SIZE(__siena_tables) * 4);
 540
 541         nitems = EFX_ARRAY_SIZE(__siena_tables);
 542         dwordp = __siena_table_masks;
 543         for (count = 0; count < nitems; ++count) {
 544                 rsp = __siena_tables + count;
 545                 rsp->mask.eo_u32[0] = *dwordp++;
 546                 rsp->mask.eo_u32[1] = *dwordp++;
 547                 rsp->mask.eo_u32[2] = *dwordp++;
 548                 rsp->mask.eo_u32[3] = *dwordp++;
 549         }
 550
 551         if ((rc = efx_nic_test_registers(enp, __siena_registers,
 552             EFX_ARRAY_SIZE(__siena_registers))) != 0)
 553                 goto fail1;
 554
 555         if ((rc = efx_nic_test_tables(enp, __siena_tables,
 556             EFX_PATTERN_BYTE_ALTERNATE,
 557             EFX_ARRAY_SIZE(__siena_tables))) != 0)
 558                 goto fail2;
 559
 560         if ((rc = efx_nic_test_tables(enp, __siena_tables,
 561             EFX_PATTERN_BYTE_CHANGING,
 562             EFX_ARRAY_SIZE(__siena_tables))) != 0)
 563                 goto fail3;
 564
 565         if ((rc = efx_nic_test_tables(enp, __siena_tables,
 566             EFX_PATTERN_BIT_SWEEP, EFX_ARRAY_SIZE(__siena_tables))) != 0)
 567                 goto fail4;
 568
 569         return (0);
 570
 571 fail4:
 572         EFSYS_PROBE(fail4);
 573 fail3:
 574         EFSYS_PROBE(fail3);
 575 fail2:
 576         EFSYS_PROBE(fail2);
 577 fail1:
 578         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 579
 580         return (rc);
 581 }
 582
 583 #endif  /* EFSYS_OPT_DIAG */
 584
 585 #endif  /* EFSYS_OPT_SIENA */