ceph/src/seastar/dpdk/drivers/net/vmxnet3/vmxnet3_ethdev.h

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _VMXNET3_ETHDEV_H_
  35 #define _VMXNET3_ETHDEV_H_
  36
  37 #include <rte_io.h>
  38
  39 #define VMXNET3_MAX_MAC_ADDRS 1
  40
  41 /* UPT feature to negotiate */
  42 #define VMXNET3_F_RXCSUM      0x0001
  43 #define VMXNET3_F_RSS         0x0002
  44 #define VMXNET3_F_RXVLAN      0x0004
  45 #define VMXNET3_F_LRO         0x0008
  46
  47 /* Hash Types supported by device */
  48 #define VMXNET3_RSS_HASH_TYPE_NONE      0x0
  49 #define VMXNET3_RSS_HASH_TYPE_IPV4      0x01
  50 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV4  0x02
  51 #define VMXNET3_RSS_HASH_TYPE_IPV6      0x04
  52 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV6  0x08
  53
  54 #define VMXNET3_RSS_HASH_FUNC_NONE      0x0
  55 #define VMXNET3_RSS_HASH_FUNC_TOEPLITZ  0x01
  56
  57 #define VMXNET3_RSS_MAX_KEY_SIZE        40
  58 #define VMXNET3_RSS_MAX_IND_TABLE_SIZE  128
  59
  60 #define VMXNET3_RSS_OFFLOAD_ALL ( \
  61         ETH_RSS_IPV4 | \
  62         ETH_RSS_NONFRAG_IPV4_TCP | \
  63         ETH_RSS_IPV6 | \
  64         ETH_RSS_NONFRAG_IPV6_TCP)
  65
  66 /* RSS configuration structure - shared with device through GPA */
  67 typedef struct VMXNET3_RSSConf {
  68         uint16_t   hashType;
  69         uint16_t   hashFunc;
  70         uint16_t   hashKeySize;
  71         uint16_t   indTableSize;
  72         uint8_t    hashKey[VMXNET3_RSS_MAX_KEY_SIZE];
  73         /*
  74          * indTable is only element that can be changed without
  75          * device quiesce-reset-update-activation cycle
  76          */
  77         uint8_t    indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE];
  78 } VMXNET3_RSSConf;
  79
  80 typedef struct vmxnet3_mf_table {
  81         void          *mfTableBase; /* Multicast addresses list */
  82         uint64_t      mfTablePA;    /* Physical address of the list */
  83         uint16_t      num_addrs;    /* number of multicast addrs */
  84 } vmxnet3_mf_table_t;
  85
  86 struct vmxnet3_hw {
  87         uint8_t *hw_addr0;      /* BAR0: PT-Passthrough Regs    */
  88         uint8_t *hw_addr1;      /* BAR1: VD-Virtual Device Regs */
  89         /* BAR2: MSI-X Regs */
  90         /* BAR3: Port IO    */
  91         void *back;
  92
  93         uint16_t device_id;
  94         uint16_t vendor_id;
  95         uint16_t subsystem_device_id;
  96         uint16_t subsystem_vendor_id;
  97         bool adapter_stopped;
  98
  99         uint8_t perm_addr[ETHER_ADDR_LEN];
 100         uint8_t num_tx_queues;
 101         uint8_t num_rx_queues;
 102         uint8_t bufs_per_pkt;
 103
 104         uint8_t version;
 105
 106         uint16_t txdata_desc_size; /* tx data ring buffer size */
 107         uint16_t rxdata_desc_size; /* rx data ring buffer size */
 108
 109         Vmxnet3_TxQueueDesc   *tqd_start;       /* start address of all tx queue desc */
 110         Vmxnet3_RxQueueDesc   *rqd_start;       /* start address of all rx queue desc */
 111
 112         Vmxnet3_DriverShared  *shared;
 113         uint64_t              sharedPA;
 114
 115         uint64_t              queueDescPA;
 116         uint16_t              queue_desc_len;
 117
 118         VMXNET3_RSSConf       *rss_conf;
 119         uint64_t              rss_confPA;
 120         vmxnet3_mf_table_t    *mf_table;
 121         uint32_t              shadow_vfta[VMXNET3_VFT_SIZE];
 122         Vmxnet3_MemRegs       *memRegs;
 123         uint64_t              memRegsPA;
 124 #define VMXNET3_VFT_TABLE_SIZE     (VMXNET3_VFT_SIZE * sizeof(uint32_t))
 125 };
 126
 127 #define VMXNET3_REV_3           2               /* Vmxnet3 Rev. 3 */
 128 #define VMXNET3_REV_2           1               /* Vmxnet3 Rev. 2 */
 129 #define VMXNET3_REV_1           0               /* Vmxnet3 Rev. 1 */
 130
 131 #define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1)
 132 #define VMXNET3_VERSION_GE_2(hw) ((hw)->version >= VMXNET3_REV_2 + 1)
 133
 134 #define VMXNET3_GET_ADDR_LO(reg)   ((uint32_t)(reg))
 135 #define VMXNET3_GET_ADDR_HI(reg)   ((uint32_t)(((uint64_t)(reg)) >> 32))
 136
 137 /* Config space read/writes */
 138
 139 #define VMXNET3_PCI_REG(reg) rte_read32(reg)
 140
 141 static inline uint32_t
 142 vmxnet3_read_addr(volatile void *addr)
 143 {
 144         return VMXNET3_PCI_REG(addr);
 145 }
 146
 147 #define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
 148
 149 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \
 150         ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
 151 #define VMXNET3_READ_BAR0_REG(hw, reg) \
 152         vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)))
 153 #define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \
 154         VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value))
 155
 156 #define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \
 157         ((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg)))
 158 #define VMXNET3_READ_BAR1_REG(hw, reg) \
 159         vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)))
 160 #define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \
 161         VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value))
 162
 163 static inline uint8_t
 164 vmxnet3_get_ring_idx(struct vmxnet3_hw *hw, uint32 rqID)
 165 {
 166         return (rqID >= hw->num_rx_queues &&
 167                 rqID < 2 * hw->num_rx_queues) ? 1 : 0;
 168 }
 169
 170 static inline bool
 171 vmxnet3_rx_data_ring(struct vmxnet3_hw *hw, uint32 rqID)
 172 {
 173         return (rqID >= 2 * hw->num_rx_queues &&
 174                 rqID < 3 * hw->num_rx_queues);
 175 }
 176
 177 /*
 178  * RX/TX function prototypes
 179  */
 180
 181 void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev);
 182
 183 void vmxnet3_dev_rx_queue_release(void *rxq);
 184 void vmxnet3_dev_tx_queue_release(void *txq);
 185
 186 int  vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
 187                                 uint16_t nb_rx_desc, unsigned int socket_id,
 188                                 const struct rte_eth_rxconf *rx_conf,
 189                                 struct rte_mempool *mb_pool);
 190 int  vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 191                                 uint16_t nb_tx_desc, unsigned int socket_id,
 192                                 const struct rte_eth_txconf *tx_conf);
 193
 194 int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev);
 195
 196 int vmxnet3_rss_configure(struct rte_eth_dev *dev);
 197
 198 uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 199                            uint16_t nb_pkts);
 200 uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 201                            uint16_t nb_pkts);
 202 uint16_t vmxnet3_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 203                         uint16_t nb_pkts);
 204
 205 #endif /* _VMXNET3_ETHDEV_H_ */