ceph/src/seastar/dpdk/kernel/linux/kni/ethtool/igb/e1000_manage.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*******************************************************************************
   3
   4   Intel(R) Gigabit Ethernet Linux driver
   5   Copyright(c) 2007-2013 Intel Corporation.
   6
   7   Contact Information:
   8   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   9   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  10
  11 *******************************************************************************/
  12
  13 #include "e1000_api.h"
  14
  15 /**
  16  *  e1000_calculate_checksum - Calculate checksum for buffer
  17  *  @buffer: pointer to EEPROM
  18  *  @length: size of EEPROM to calculate a checksum for
  19  *
  20  *  Calculates the checksum for some buffer on a specified length.  The
  21  *  checksum calculated is returned.
  22  **/
  23 u8 e1000_calculate_checksum(u8 *buffer, u32 length)
  24 {
  25         u32 i;
  26         u8 sum = 0;
  27
  28         DEBUGFUNC("e1000_calculate_checksum");
  29
  30         if (!buffer)
  31                 return 0;
  32
  33         for (i = 0; i < length; i++)
  34                 sum += buffer[i];
  35
  36         return (u8) (0 - sum);
  37 }
  38
  39 /**
  40  *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
  41  *  @hw: pointer to the HW structure
  42  *
  43  *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
  44  *
  45  *  This function checks whether the HOST IF is enabled for command operation
  46  *  and also checks whether the previous command is completed.  It busy waits
  47  *  in case of previous command is not completed.
  48  **/
  49 s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
  50 {
  51         u32 hicr;
  52         u8 i;
  53
  54         DEBUGFUNC("e1000_mng_enable_host_if_generic");
  55
  56         if (!hw->mac.arc_subsystem_valid) {
  57                 DEBUGOUT("ARC subsystem not valid.\n");
  58                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
  59         }
  60
  61         /* Check that the host interface is enabled. */
  62         hicr = E1000_READ_REG(hw, E1000_HICR);
  63         if (!(hicr & E1000_HICR_EN)) {
  64                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
  65                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
  66         }
  67         /* check the previous command is completed */
  68         for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
  69                 hicr = E1000_READ_REG(hw, E1000_HICR);
  70                 if (!(hicr & E1000_HICR_C))
  71                         break;
  72                 msec_delay_irq(1);
  73         }
  74
  75         if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
  76                 DEBUGOUT("Previous command timeout failed .\n");
  77                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
  78         }
  79
  80         return E1000_SUCCESS;
  81 }
  82
  83 /**
  84  *  e1000_check_mng_mode_generic - Generic check management mode
  85  *  @hw: pointer to the HW structure
  86  *
  87  *  Reads the firmware semaphore register and returns true (>0) if
  88  *  manageability is enabled, else false (0).
  89  **/
  90 bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
  91 {
  92         u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
  93
  94         DEBUGFUNC("e1000_check_mng_mode_generic");
  95
  96
  97         return (fwsm & E1000_FWSM_MODE_MASK) ==
  98                 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
  99 }
 100
 101 /**
 102  *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
 103  *  @hw: pointer to the HW structure
 104  *
 105  *  Enables packet filtering on transmit packets if manageability is enabled
 106  *  and host interface is enabled.
 107  **/
 108 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
 109 {
 110         struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
 111         u32 *buffer = (u32 *)&hw->mng_cookie;
 112         u32 offset;
 113         s32 ret_val, hdr_csum, csum;
 114         u8 i, len;
 115
 116         DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
 117
 118         hw->mac.tx_pkt_filtering = true;
 119
 120         /* No manageability, no filtering */
 121         if (!hw->mac.ops.check_mng_mode(hw)) {
 122                 hw->mac.tx_pkt_filtering = false;
 123                 return hw->mac.tx_pkt_filtering;
 124         }
 125
 126         /* If we can't read from the host interface for whatever
 127          * reason, disable filtering.
 128          */
 129         ret_val = e1000_mng_enable_host_if_generic(hw);
 130         if (ret_val != E1000_SUCCESS) {
 131                 hw->mac.tx_pkt_filtering = false;
 132                 return hw->mac.tx_pkt_filtering;
 133         }
 134
 135         /* Read in the header.  Length and offset are in dwords. */
 136         len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
 137         offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
 138         for (i = 0; i < len; i++)
 139                 *(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
 140                                                            offset + i);
 141         hdr_csum = hdr->checksum;
 142         hdr->checksum = 0;
 143         csum = e1000_calculate_checksum((u8 *)hdr,
 144                                         E1000_MNG_DHCP_COOKIE_LENGTH);
 145         /* If either the checksums or signature don't match, then
 146          * the cookie area isn't considered valid, in which case we
 147          * take the safe route of assuming Tx filtering is enabled.
 148          */
 149         if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
 150                 hw->mac.tx_pkt_filtering = true;
 151                 return hw->mac.tx_pkt_filtering;
 152         }
 153
 154         /* Cookie area is valid, make the final check for filtering. */
 155         if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
 156                 hw->mac.tx_pkt_filtering = false;
 157
 158         return hw->mac.tx_pkt_filtering;
 159 }
 160
 161 /**
 162  *  e1000_mng_write_cmd_header_generic - Writes manageability command header
 163  *  @hw: pointer to the HW structure
 164  *  @hdr: pointer to the host interface command header
 165  *
 166  *  Writes the command header after does the checksum calculation.
 167  **/
 168 s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
 169                                       struct e1000_host_mng_command_header *hdr)
 170 {
 171         u16 i, length = sizeof(struct e1000_host_mng_command_header);
 172
 173         DEBUGFUNC("e1000_mng_write_cmd_header_generic");
 174
 175         /* Write the whole command header structure with new checksum. */
 176
 177         hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
 178
 179         length >>= 2;
 180         /* Write the relevant command block into the ram area. */
 181         for (i = 0; i < length; i++) {
 182                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
 183                                             *((u32 *) hdr + i));
 184                 E1000_WRITE_FLUSH(hw);
 185         }
 186
 187         return E1000_SUCCESS;
 188 }
 189
 190 /**
 191  *  e1000_mng_host_if_write_generic - Write to the manageability host interface
 192  *  @hw: pointer to the HW structure
 193  *  @buffer: pointer to the host interface buffer
 194  *  @length: size of the buffer
 195  *  @offset: location in the buffer to write to
 196  *  @sum: sum of the data (not checksum)
 197  *
 198  *  This function writes the buffer content at the offset given on the host if.
 199  *  It also does alignment considerations to do the writes in most efficient
 200  *  way.  Also fills up the sum of the buffer in *buffer parameter.
 201  **/
 202 s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
 203                                     u16 length, u16 offset, u8 *sum)
 204 {
 205         u8 *tmp;
 206         u8 *bufptr = buffer;
 207         u32 data = 0;
 208         u16 remaining, i, j, prev_bytes;
 209
 210         DEBUGFUNC("e1000_mng_host_if_write_generic");
 211
 212         /* sum = only sum of the data and it is not checksum */
 213
 214         if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
 215                 return -E1000_ERR_PARAM;
 216
 217         tmp = (u8 *)&data;
 218         prev_bytes = offset & 0x3;
 219         offset >>= 2;
 220
 221         if (prev_bytes) {
 222                 data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
 223                 for (j = prev_bytes; j < sizeof(u32); j++) {
 224                         *(tmp + j) = *bufptr++;
 225                         *sum += *(tmp + j);
 226                 }
 227                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
 228                 length -= j - prev_bytes;
 229                 offset++;
 230         }
 231
 232         remaining = length & 0x3;
 233         length -= remaining;
 234
 235         /* Calculate length in DWORDs */
 236         length >>= 2;
 237
 238         /* The device driver writes the relevant command block into the
 239          * ram area.
 240          */
 241         for (i = 0; i < length; i++) {
 242                 for (j = 0; j < sizeof(u32); j++) {
 243                         *(tmp + j) = *bufptr++;
 244                         *sum += *(tmp + j);
 245                 }
 246
 247                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
 248                                             data);
 249         }
 250         if (remaining) {
 251                 for (j = 0; j < sizeof(u32); j++) {
 252                         if (j < remaining)
 253                                 *(tmp + j) = *bufptr++;
 254                         else
 255                                 *(tmp + j) = 0;
 256
 257                         *sum += *(tmp + j);
 258                 }
 259                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
 260                                             data);
 261         }
 262
 263         return E1000_SUCCESS;
 264 }
 265
 266 /**
 267  *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
 268  *  @hw: pointer to the HW structure
 269  *  @buffer: pointer to the host interface
 270  *  @length: size of the buffer
 271  *
 272  *  Writes the DHCP information to the host interface.
 273  **/
 274 s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
 275                                       u16 length)
 276 {
 277         struct e1000_host_mng_command_header hdr;
 278         s32 ret_val;
 279         u32 hicr;
 280
 281         DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
 282
 283         hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
 284         hdr.command_length = length;
 285         hdr.reserved1 = 0;
 286         hdr.reserved2 = 0;
 287         hdr.checksum = 0;
 288
 289         /* Enable the host interface */
 290         ret_val = e1000_mng_enable_host_if_generic(hw);
 291         if (ret_val)
 292                 return ret_val;
 293
 294         /* Populate the host interface with the contents of "buffer". */
 295         ret_val = e1000_mng_host_if_write_generic(hw, buffer, length,
 296                                                   sizeof(hdr), &(hdr.checksum));
 297         if (ret_val)
 298                 return ret_val;
 299
 300         /* Write the manageability command header */
 301         ret_val = e1000_mng_write_cmd_header_generic(hw, &hdr);
 302         if (ret_val)
 303                 return ret_val;
 304
 305         /* Tell the ARC a new command is pending. */
 306         hicr = E1000_READ_REG(hw, E1000_HICR);
 307         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 308
 309         return E1000_SUCCESS;
 310 }
 311
 312 /**
 313  *  e1000_enable_mng_pass_thru - Check if management passthrough is needed
 314  *  @hw: pointer to the HW structure
 315  *
 316  *  Verifies the hardware needs to leave interface enabled so that frames can
 317  *  be directed to and from the management interface.
 318  **/
 319 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
 320 {
 321         u32 manc;
 322         u32 fwsm, factps;
 323
 324         DEBUGFUNC("e1000_enable_mng_pass_thru");
 325
 326         if (!hw->mac.asf_firmware_present)
 327                 return false;
 328
 329         manc = E1000_READ_REG(hw, E1000_MANC);
 330
 331         if (!(manc & E1000_MANC_RCV_TCO_EN))
 332                 return false;
 333
 334         if (hw->mac.has_fwsm) {
 335                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
 336                 factps = E1000_READ_REG(hw, E1000_FACTPS);
 337
 338                 if (!(factps & E1000_FACTPS_MNGCG) &&
 339                     ((fwsm & E1000_FWSM_MODE_MASK) ==
 340                      (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
 341                         return true;
 342         } else if ((manc & E1000_MANC_SMBUS_EN) &&
 343                    !(manc & E1000_MANC_ASF_EN)) {
 344                 return true;
 345         }
 346
 347         return false;
 348 }
 349
 350 /**
 351  *  e1000_host_interface_command - Writes buffer to host interface
 352  *  @hw: pointer to the HW structure
 353  *  @buffer: contains a command to write
 354  *  @length: the byte length of the buffer, must be multiple of 4 bytes
 355  *
 356  *  Writes a buffer to the Host Interface.  Upon success, returns E1000_SUCCESS
 357  *  else returns E1000_ERR_HOST_INTERFACE_COMMAND.
 358  **/
 359 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
 360 {
 361         u32 hicr, i;
 362
 363         DEBUGFUNC("e1000_host_interface_command");
 364
 365         if (!(hw->mac.arc_subsystem_valid)) {
 366                 DEBUGOUT("Hardware doesn't support host interface command.\n");
 367                 return E1000_SUCCESS;
 368         }
 369
 370         if (!hw->mac.asf_firmware_present) {
 371                 DEBUGOUT("Firmware is not present.\n");
 372                 return E1000_SUCCESS;
 373         }
 374
 375         if (length == 0 || length & 0x3 ||
 376             length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {
 377                 DEBUGOUT("Buffer length failure.\n");
 378                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 379         }
 380
 381         /* Check that the host interface is enabled. */
 382         hicr = E1000_READ_REG(hw, E1000_HICR);
 383         if (!(hicr & E1000_HICR_EN)) {
 384                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
 385                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 386         }
 387
 388         /* Calculate length in DWORDs */
 389         length >>= 2;
 390
 391         /* The device driver writes the relevant command block
 392          * into the ram area.
 393          */
 394         for (i = 0; i < length; i++)
 395                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
 396                                             *((u32 *)buffer + i));
 397
 398         /* Setting this bit tells the ARC that a new command is pending. */
 399         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 400
 401         for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
 402                 hicr = E1000_READ_REG(hw, E1000_HICR);
 403                 if (!(hicr & E1000_HICR_C))
 404                         break;
 405                 msec_delay(1);
 406         }
 407
 408         /* Check command successful completion. */
 409         if (i == E1000_HI_COMMAND_TIMEOUT ||
 410             (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {
 411                 DEBUGOUT("Command has failed with no status valid.\n");
 412                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 413         }
 414
 415         for (i = 0; i < length; i++)
 416                 *((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
 417                                                                   E1000_HOST_IF,
 418                                                                   i);
 419
 420         return E1000_SUCCESS;
 421 }
 422 /**
 423  *  e1000_load_firmware - Writes proxy FW code buffer to host interface
 424  *                        and execute.
 425  *  @hw: pointer to the HW structure
 426  *  @buffer: contains a firmware to write
 427  *  @length: the byte length of the buffer, must be multiple of 4 bytes
 428  *
 429  *  Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled
 430  *  in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.
 431  **/
 432 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)
 433 {
 434         u32 hicr, hibba, fwsm, icr, i;
 435
 436         DEBUGFUNC("e1000_load_firmware");
 437
 438         if (hw->mac.type < e1000_i210) {
 439                 DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
 440                 return -E1000_ERR_CONFIG;
 441         }
 442
 443         /* Check that the host interface is enabled. */
 444         hicr = E1000_READ_REG(hw, E1000_HICR);
 445         if (!(hicr & E1000_HICR_EN)) {
 446                 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
 447                 return -E1000_ERR_CONFIG;
 448         }
 449         if (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {
 450                 DEBUGOUT("E1000_HICR_MEMORY_BASE_EN bit disabled.\n");
 451                 return -E1000_ERR_CONFIG;
 452         }
 453
 454         if (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {
 455                 DEBUGOUT("Buffer length failure.\n");
 456                 return -E1000_ERR_INVALID_ARGUMENT;
 457         }
 458
 459         /* Clear notification from ROM-FW by reading ICR register */
 460         icr = E1000_READ_REG(hw, E1000_ICR_V2);
 461
 462         /* Reset ROM-FW */
 463         hicr = E1000_READ_REG(hw, E1000_HICR);
 464         hicr |= E1000_HICR_FW_RESET_ENABLE;
 465         E1000_WRITE_REG(hw, E1000_HICR, hicr);
 466         hicr |= E1000_HICR_FW_RESET;
 467         E1000_WRITE_REG(hw, E1000_HICR, hicr);
 468         E1000_WRITE_FLUSH(hw);
 469
 470         /* Wait till MAC notifies about its readiness after ROM-FW reset */
 471         for (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {
 472                 icr = E1000_READ_REG(hw, E1000_ICR_V2);
 473                 if (icr & E1000_ICR_MNG)
 474                         break;
 475                 msec_delay(1);
 476         }
 477
 478         /* Check for timeout */
 479         if (i == E1000_HI_COMMAND_TIMEOUT) {
 480                 DEBUGOUT("FW reset failed.\n");
 481                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 482         }
 483
 484         /* Wait till MAC is ready to accept new FW code */
 485         for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
 486                 fwsm = E1000_READ_REG(hw, E1000_FWSM);
 487                 if ((fwsm & E1000_FWSM_FW_VALID) &&
 488                     ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==
 489                     E1000_FWSM_HI_EN_ONLY_MODE))
 490                         break;
 491                 msec_delay(1);
 492         }
 493
 494         /* Check for timeout */
 495         if (i == E1000_HI_COMMAND_TIMEOUT) {
 496                 DEBUGOUT("FW reset failed.\n");
 497                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 498         }
 499
 500         /* Calculate length in DWORDs */
 501         length >>= 2;
 502
 503         /* The device driver writes the relevant FW code block
 504          * into the ram area in DWORDs via 1kB ram addressing window.
 505          */
 506         for (i = 0; i < length; i++) {
 507                 if (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {
 508                         /* Point to correct 1kB ram window */
 509                         hibba = E1000_HI_FW_BASE_ADDRESS +
 510                                 ((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *
 511                                 (i / E1000_HI_FW_BLOCK_DWORD_LENGTH));
 512
 513                         E1000_WRITE_REG(hw, E1000_HIBBA, hibba);
 514                 }
 515
 516                 E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
 517                                             i % E1000_HI_FW_BLOCK_DWORD_LENGTH,
 518                                             *((u32 *)buffer + i));
 519         }
 520
 521         /* Setting this bit tells the ARC that a new FW is ready to execute. */
 522         hicr = E1000_READ_REG(hw, E1000_HICR);
 523         E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
 524
 525         for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
 526                 hicr = E1000_READ_REG(hw, E1000_HICR);
 527                 if (!(hicr & E1000_HICR_C))
 528                         break;
 529                 msec_delay(1);
 530         }
 531
 532         /* Check for successful FW start. */
 533         if (i == E1000_HI_COMMAND_TIMEOUT) {
 534                 DEBUGOUT("New FW did not start within timeout period.\n");
 535                 return -E1000_ERR_HOST_INTERFACE_COMMAND;
 536         }
 537
 538         return E1000_SUCCESS;
 539 }