1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*******************************************************************************
4 Intel 10 Gigabit PCI Express Linux driver
5 Copyright(c) 1999 - 2012 Intel Corporation.
8 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
11 *******************************************************************************/
16 #include "ixgbe_type.h"
18 s32
ixgbe_init_shared_code(struct ixgbe_hw
*hw
);
20 extern s32
ixgbe_init_ops_82598(struct ixgbe_hw
*hw
);
21 extern s32
ixgbe_init_ops_82599(struct ixgbe_hw
*hw
);
22 extern s32
ixgbe_init_ops_X540(struct ixgbe_hw
*hw
);
24 s32
ixgbe_set_mac_type(struct ixgbe_hw
*hw
);
25 s32
ixgbe_init_hw(struct ixgbe_hw
*hw
);
26 s32
ixgbe_reset_hw(struct ixgbe_hw
*hw
);
27 s32
ixgbe_start_hw(struct ixgbe_hw
*hw
);
28 s32
ixgbe_clear_hw_cntrs(struct ixgbe_hw
*hw
);
29 enum ixgbe_media_type
ixgbe_get_media_type(struct ixgbe_hw
*hw
);
30 s32
ixgbe_get_mac_addr(struct ixgbe_hw
*hw
, u8
*mac_addr
);
31 s32
ixgbe_get_bus_info(struct ixgbe_hw
*hw
);
32 u32
ixgbe_get_num_of_tx_queues(struct ixgbe_hw
*hw
);
33 u32
ixgbe_get_num_of_rx_queues(struct ixgbe_hw
*hw
);
34 s32
ixgbe_stop_adapter(struct ixgbe_hw
*hw
);
35 s32
ixgbe_read_pba_string(struct ixgbe_hw
*hw
, u8
*pba_num
, u32 pba_num_size
);
37 s32
ixgbe_identify_phy(struct ixgbe_hw
*hw
);
38 s32
ixgbe_reset_phy(struct ixgbe_hw
*hw
);
39 s32
ixgbe_read_phy_reg(struct ixgbe_hw
*hw
, u32 reg_addr
, u32 device_type
,
41 s32
ixgbe_write_phy_reg(struct ixgbe_hw
*hw
, u32 reg_addr
, u32 device_type
,
44 s32
ixgbe_setup_phy_link(struct ixgbe_hw
*hw
);
45 s32
ixgbe_check_phy_link(struct ixgbe_hw
*hw
,
46 ixgbe_link_speed
*speed
,
48 s32
ixgbe_setup_phy_link_speed(struct ixgbe_hw
*hw
,
49 ixgbe_link_speed speed
,
51 bool autoneg_wait_to_complete
);
52 void ixgbe_disable_tx_laser(struct ixgbe_hw
*hw
);
53 void ixgbe_enable_tx_laser(struct ixgbe_hw
*hw
);
54 void ixgbe_flap_tx_laser(struct ixgbe_hw
*hw
);
55 s32
ixgbe_setup_link(struct ixgbe_hw
*hw
, ixgbe_link_speed speed
,
56 bool autoneg
, bool autoneg_wait_to_complete
);
57 s32
ixgbe_check_link(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
58 bool *link_up
, bool link_up_wait_to_complete
);
59 s32
ixgbe_get_link_capabilities(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
61 s32
ixgbe_led_on(struct ixgbe_hw
*hw
, u32 index
);
62 s32
ixgbe_led_off(struct ixgbe_hw
*hw
, u32 index
);
63 s32
ixgbe_blink_led_start(struct ixgbe_hw
*hw
, u32 index
);
64 s32
ixgbe_blink_led_stop(struct ixgbe_hw
*hw
, u32 index
);
66 s32
ixgbe_init_eeprom_params(struct ixgbe_hw
*hw
);
67 s32
ixgbe_write_eeprom(struct ixgbe_hw
*hw
, u16 offset
, u16 data
);
68 s32
ixgbe_write_eeprom_buffer(struct ixgbe_hw
*hw
, u16 offset
,
69 u16 words
, u16
*data
);
70 s32
ixgbe_read_eeprom(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
);
71 s32
ixgbe_read_eeprom_buffer(struct ixgbe_hw
*hw
, u16 offset
,
72 u16 words
, u16
*data
);
74 s32
ixgbe_validate_eeprom_checksum(struct ixgbe_hw
*hw
, u16
*checksum_val
);
75 s32
ixgbe_update_eeprom_checksum(struct ixgbe_hw
*hw
);
77 s32
ixgbe_insert_mac_addr(struct ixgbe_hw
*hw
, u8
*addr
, u32 vmdq
);
78 s32
ixgbe_set_rar(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
80 s32
ixgbe_clear_rar(struct ixgbe_hw
*hw
, u32 index
);
81 s32
ixgbe_set_vmdq(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
);
82 s32
ixgbe_set_vmdq_san_mac(struct ixgbe_hw
*hw
, u32 vmdq
);
83 s32
ixgbe_clear_vmdq(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
);
84 s32
ixgbe_init_rx_addrs(struct ixgbe_hw
*hw
);
85 u32
ixgbe_get_num_rx_addrs(struct ixgbe_hw
*hw
);
86 s32
ixgbe_update_uc_addr_list(struct ixgbe_hw
*hw
, u8
*addr_list
,
87 u32 addr_count
, ixgbe_mc_addr_itr func
);
88 s32
ixgbe_update_mc_addr_list(struct ixgbe_hw
*hw
, u8
*mc_addr_list
,
89 u32 mc_addr_count
, ixgbe_mc_addr_itr func
,
91 void ixgbe_add_uc_addr(struct ixgbe_hw
*hw
, u8
*addr_list
, u32 vmdq
);
92 s32
ixgbe_enable_mc(struct ixgbe_hw
*hw
);
93 s32
ixgbe_disable_mc(struct ixgbe_hw
*hw
);
94 s32
ixgbe_clear_vfta(struct ixgbe_hw
*hw
);
95 s32
ixgbe_set_vfta(struct ixgbe_hw
*hw
, u32 vlan
,
96 u32 vind
, bool vlan_on
);
97 s32
ixgbe_set_vlvf(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
98 bool vlan_on
, bool *vfta_changed
);
99 s32
ixgbe_fc_enable(struct ixgbe_hw
*hw
);
100 s32
ixgbe_set_fw_drv_ver(struct ixgbe_hw
*hw
, u8 maj
, u8 min
, u8 build
,
102 s32
ixgbe_get_thermal_sensor_data(struct ixgbe_hw
*hw
);
103 s32
ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw
*hw
);
104 void ixgbe_set_mta(struct ixgbe_hw
*hw
, u8
*mc_addr
);
105 s32
ixgbe_get_phy_firmware_version(struct ixgbe_hw
*hw
,
106 u16
*firmware_version
);
107 s32
ixgbe_read_analog_reg8(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
);
108 s32
ixgbe_write_analog_reg8(struct ixgbe_hw
*hw
, u32 reg
, u8 val
);
109 s32
ixgbe_init_uta_tables(struct ixgbe_hw
*hw
);
110 s32
ixgbe_read_i2c_eeprom(struct ixgbe_hw
*hw
, u8 byte_offset
, u8
*eeprom_data
);
111 u32
ixgbe_get_supported_physical_layer(struct ixgbe_hw
*hw
);
112 s32
ixgbe_enable_rx_dma(struct ixgbe_hw
*hw
, u32 regval
);
113 s32
ixgbe_disable_sec_rx_path(struct ixgbe_hw
*hw
);
114 s32
ixgbe_enable_sec_rx_path(struct ixgbe_hw
*hw
);
115 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
);
116 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
);
117 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 fdirctrl
);
118 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
119 union ixgbe_atr_hash_dword input
,
120 union ixgbe_atr_hash_dword common
,
122 s32
ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw
*hw
,
123 union ixgbe_atr_input
*input_mask
);
124 s32
ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw
*hw
,
125 union ixgbe_atr_input
*input
,
126 u16 soft_id
, u8 queue
);
127 s32
ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw
*hw
,
128 union ixgbe_atr_input
*input
,
130 s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
131 union ixgbe_atr_input
*input
,
132 union ixgbe_atr_input
*mask
,
135 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input
*input
,
136 union ixgbe_atr_input
*mask
);
137 u32
ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input
,
138 union ixgbe_atr_hash_dword common
);
139 s32
ixgbe_read_i2c_byte(struct ixgbe_hw
*hw
, u8 byte_offset
, u8 dev_addr
,
141 s32
ixgbe_write_i2c_byte(struct ixgbe_hw
*hw
, u8 byte_offset
, u8 dev_addr
,
143 s32
ixgbe_write_i2c_eeprom(struct ixgbe_hw
*hw
, u8 byte_offset
, u8 eeprom_data
);
144 s32
ixgbe_get_san_mac_addr(struct ixgbe_hw
*hw
, u8
*san_mac_addr
);
145 s32
ixgbe_set_san_mac_addr(struct ixgbe_hw
*hw
, u8
*san_mac_addr
);
146 s32
ixgbe_get_device_caps(struct ixgbe_hw
*hw
, u16
*device_caps
);
147 s32
ixgbe_acquire_swfw_semaphore(struct ixgbe_hw
*hw
, u16 mask
);
148 void ixgbe_release_swfw_semaphore(struct ixgbe_hw
*hw
, u16 mask
);
149 s32
ixgbe_get_wwn_prefix(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
151 s32
ixgbe_get_fcoe_boot_status(struct ixgbe_hw
*hw
, u16
*bs
);
153 #endif /* _IXGBE_API_H_ */