ceph/src/seastar/dpdk/lib/librte_eal/common/arch/x86/rte_cpuflags.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include "rte_cpuflags.h"
  35
  36 #include <stdio.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39
  40 enum cpu_register_t {
  41         RTE_REG_EAX = 0,
  42         RTE_REG_EBX,
  43         RTE_REG_ECX,
  44         RTE_REG_EDX,
  45 };
  46
  47 typedef uint32_t cpuid_registers_t[4];
  48
  49 /**
  50  * Struct to hold a processor feature entry
  51  */
  52 struct feature_entry {
  53         uint32_t leaf;                          /**< cpuid leaf */
  54         uint32_t subleaf;                       /**< cpuid subleaf */
  55         uint32_t reg;                           /**< cpuid register */
  56         uint32_t bit;                           /**< cpuid register bit */
  57 #define CPU_FLAG_NAME_MAX_LEN 64
  58         char name[CPU_FLAG_NAME_MAX_LEN];       /**< String for printing */
  59 };
  60
  61 #define FEAT_DEF(name, leaf, subleaf, reg, bit) \
  62         [RTE_CPUFLAG_##name] = {leaf, subleaf, reg, bit, #name },
  63
  64 const struct feature_entry rte_cpu_feature_table[] = {
  65         FEAT_DEF(SSE3, 0x00000001, 0, RTE_REG_ECX,  0)
  66         FEAT_DEF(PCLMULQDQ, 0x00000001, 0, RTE_REG_ECX,  1)
  67         FEAT_DEF(DTES64, 0x00000001, 0, RTE_REG_ECX,  2)
  68         FEAT_DEF(MONITOR, 0x00000001, 0, RTE_REG_ECX,  3)
  69         FEAT_DEF(DS_CPL, 0x00000001, 0, RTE_REG_ECX,  4)
  70         FEAT_DEF(VMX, 0x00000001, 0, RTE_REG_ECX,  5)
  71         FEAT_DEF(SMX, 0x00000001, 0, RTE_REG_ECX,  6)
  72         FEAT_DEF(EIST, 0x00000001, 0, RTE_REG_ECX,  7)
  73         FEAT_DEF(TM2, 0x00000001, 0, RTE_REG_ECX,  8)
  74         FEAT_DEF(SSSE3, 0x00000001, 0, RTE_REG_ECX,  9)
  75         FEAT_DEF(CNXT_ID, 0x00000001, 0, RTE_REG_ECX, 10)
  76         FEAT_DEF(FMA, 0x00000001, 0, RTE_REG_ECX, 12)
  77         FEAT_DEF(CMPXCHG16B, 0x00000001, 0, RTE_REG_ECX, 13)
  78         FEAT_DEF(XTPR, 0x00000001, 0, RTE_REG_ECX, 14)
  79         FEAT_DEF(PDCM, 0x00000001, 0, RTE_REG_ECX, 15)
  80         FEAT_DEF(PCID, 0x00000001, 0, RTE_REG_ECX, 17)
  81         FEAT_DEF(DCA, 0x00000001, 0, RTE_REG_ECX, 18)
  82         FEAT_DEF(SSE4_1, 0x00000001, 0, RTE_REG_ECX, 19)
  83         FEAT_DEF(SSE4_2, 0x00000001, 0, RTE_REG_ECX, 20)
  84         FEAT_DEF(X2APIC, 0x00000001, 0, RTE_REG_ECX, 21)
  85         FEAT_DEF(MOVBE, 0x00000001, 0, RTE_REG_ECX, 22)
  86         FEAT_DEF(POPCNT, 0x00000001, 0, RTE_REG_ECX, 23)
  87         FEAT_DEF(TSC_DEADLINE, 0x00000001, 0, RTE_REG_ECX, 24)
  88         FEAT_DEF(AES, 0x00000001, 0, RTE_REG_ECX, 25)
  89         FEAT_DEF(XSAVE, 0x00000001, 0, RTE_REG_ECX, 26)
  90         FEAT_DEF(OSXSAVE, 0x00000001, 0, RTE_REG_ECX, 27)
  91         FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28)
  92         FEAT_DEF(F16C, 0x00000001, 0, RTE_REG_ECX, 29)
  93         FEAT_DEF(RDRAND, 0x00000001, 0, RTE_REG_ECX, 30)
  94
  95         FEAT_DEF(FPU, 0x00000001, 0, RTE_REG_EDX,  0)
  96         FEAT_DEF(VME, 0x00000001, 0, RTE_REG_EDX,  1)
  97         FEAT_DEF(DE, 0x00000001, 0, RTE_REG_EDX,  2)
  98         FEAT_DEF(PSE, 0x00000001, 0, RTE_REG_EDX,  3)
  99         FEAT_DEF(TSC, 0x00000001, 0, RTE_REG_EDX,  4)
 100         FEAT_DEF(MSR, 0x00000001, 0, RTE_REG_EDX,  5)
 101         FEAT_DEF(PAE, 0x00000001, 0, RTE_REG_EDX,  6)
 102         FEAT_DEF(MCE, 0x00000001, 0, RTE_REG_EDX,  7)
 103         FEAT_DEF(CX8, 0x00000001, 0, RTE_REG_EDX,  8)
 104         FEAT_DEF(APIC, 0x00000001, 0, RTE_REG_EDX,  9)
 105         FEAT_DEF(SEP, 0x00000001, 0, RTE_REG_EDX, 11)
 106         FEAT_DEF(MTRR, 0x00000001, 0, RTE_REG_EDX, 12)
 107         FEAT_DEF(PGE, 0x00000001, 0, RTE_REG_EDX, 13)
 108         FEAT_DEF(MCA, 0x00000001, 0, RTE_REG_EDX, 14)
 109         FEAT_DEF(CMOV, 0x00000001, 0, RTE_REG_EDX, 15)
 110         FEAT_DEF(PAT, 0x00000001, 0, RTE_REG_EDX, 16)
 111         FEAT_DEF(PSE36, 0x00000001, 0, RTE_REG_EDX, 17)
 112         FEAT_DEF(PSN, 0x00000001, 0, RTE_REG_EDX, 18)
 113         FEAT_DEF(CLFSH, 0x00000001, 0, RTE_REG_EDX, 19)
 114         FEAT_DEF(DS, 0x00000001, 0, RTE_REG_EDX, 21)
 115         FEAT_DEF(ACPI, 0x00000001, 0, RTE_REG_EDX, 22)
 116         FEAT_DEF(MMX, 0x00000001, 0, RTE_REG_EDX, 23)
 117         FEAT_DEF(FXSR, 0x00000001, 0, RTE_REG_EDX, 24)
 118         FEAT_DEF(SSE, 0x00000001, 0, RTE_REG_EDX, 25)
 119         FEAT_DEF(SSE2, 0x00000001, 0, RTE_REG_EDX, 26)
 120         FEAT_DEF(SS, 0x00000001, 0, RTE_REG_EDX, 27)
 121         FEAT_DEF(HTT, 0x00000001, 0, RTE_REG_EDX, 28)
 122         FEAT_DEF(TM, 0x00000001, 0, RTE_REG_EDX, 29)
 123         FEAT_DEF(PBE, 0x00000001, 0, RTE_REG_EDX, 31)
 124
 125         FEAT_DEF(DIGTEMP, 0x00000006, 0, RTE_REG_EAX,  0)
 126         FEAT_DEF(TRBOBST, 0x00000006, 0, RTE_REG_EAX,  1)
 127         FEAT_DEF(ARAT, 0x00000006, 0, RTE_REG_EAX,  2)
 128         FEAT_DEF(PLN, 0x00000006, 0, RTE_REG_EAX,  4)
 129         FEAT_DEF(ECMD, 0x00000006, 0, RTE_REG_EAX,  5)
 130         FEAT_DEF(PTM, 0x00000006, 0, RTE_REG_EAX,  6)
 131
 132         FEAT_DEF(MPERF_APERF_MSR, 0x00000006, 0, RTE_REG_ECX,  0)
 133         FEAT_DEF(ACNT2, 0x00000006, 0, RTE_REG_ECX,  1)
 134         FEAT_DEF(ENERGY_EFF, 0x00000006, 0, RTE_REG_ECX,  3)
 135
 136         FEAT_DEF(FSGSBASE, 0x00000007, 0, RTE_REG_EBX,  0)
 137         FEAT_DEF(BMI1, 0x00000007, 0, RTE_REG_EBX,  2)
 138         FEAT_DEF(HLE, 0x00000007, 0, RTE_REG_EBX,  4)
 139         FEAT_DEF(AVX2, 0x00000007, 0, RTE_REG_EBX,  5)
 140         FEAT_DEF(SMEP, 0x00000007, 0, RTE_REG_EBX,  6)
 141         FEAT_DEF(BMI2, 0x00000007, 0, RTE_REG_EBX,  7)
 142         FEAT_DEF(ERMS, 0x00000007, 0, RTE_REG_EBX,  8)
 143         FEAT_DEF(INVPCID, 0x00000007, 0, RTE_REG_EBX, 10)
 144         FEAT_DEF(RTM, 0x00000007, 0, RTE_REG_EBX, 11)
 145         FEAT_DEF(AVX512F, 0x00000007, 0, RTE_REG_EBX, 16)
 146
 147         FEAT_DEF(LAHF_SAHF, 0x80000001, 0, RTE_REG_ECX,  0)
 148         FEAT_DEF(LZCNT, 0x80000001, 0, RTE_REG_ECX,  4)
 149
 150         FEAT_DEF(SYSCALL, 0x80000001, 0, RTE_REG_EDX, 11)
 151         FEAT_DEF(XD, 0x80000001, 0, RTE_REG_EDX, 20)
 152         FEAT_DEF(1GB_PG, 0x80000001, 0, RTE_REG_EDX, 26)
 153         FEAT_DEF(RDTSCP, 0x80000001, 0, RTE_REG_EDX, 27)
 154         FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
 155
 156         FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
 157 };
 158
 159 /*
 160  * Execute CPUID instruction and get contents of a specific register
 161  *
 162  * This function, when compiled with GCC, will generate architecture-neutral
 163  * code, as per GCC manual.
 164  */
 165 static void
 166 rte_cpu_get_features(uint32_t leaf, uint32_t subleaf, cpuid_registers_t out)
 167 {
 168 #if defined(__i386__) && defined(__PIC__)
 169         /* %ebx is a forbidden register if we compile with -fPIC or -fPIE */
 170         asm volatile("movl %%ebx,%0 ; cpuid ; xchgl %%ebx,%0"
 171                  : "=r" (out[RTE_REG_EBX]),
 172                    "=a" (out[RTE_REG_EAX]),
 173                    "=c" (out[RTE_REG_ECX]),
 174                    "=d" (out[RTE_REG_EDX])
 175                  : "a" (leaf), "c" (subleaf));
 176 #else
 177         asm volatile("cpuid"
 178                  : "=a" (out[RTE_REG_EAX]),
 179                    "=b" (out[RTE_REG_EBX]),
 180                    "=c" (out[RTE_REG_ECX]),
 181                    "=d" (out[RTE_REG_EDX])
 182                  : "a" (leaf), "c" (subleaf));
 183 #endif
 184 }
 185
 186 int
 187 rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
 188 {
 189         const struct feature_entry *feat;
 190         cpuid_registers_t regs;
 191
 192         if (feature >= RTE_CPUFLAG_NUMFLAGS)
 193                 /* Flag does not match anything in the feature tables */
 194                 return -ENOENT;
 195
 196         feat = &rte_cpu_feature_table[feature];
 197
 198         if (!feat->leaf)
 199                 /* This entry in the table wasn't filled out! */
 200                 return -EFAULT;
 201
 202         rte_cpu_get_features(feat->leaf & 0xffff0000, 0, regs);
 203         if (((regs[RTE_REG_EAX] ^ feat->leaf) & 0xffff0000) ||
 204               regs[RTE_REG_EAX] < feat->leaf)
 205                 return 0;
 206
 207         /* get the cpuid leaf containing the desired feature */
 208         rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
 209
 210         /* check if the feature is enabled */
 211         return (regs[feat->reg] >> feat->bit) & 1;
 212 }
 213
 214 const char *
 215 rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
 216 {
 217         if (feature >= RTE_CPUFLAG_NUMFLAGS)
 218                 return NULL;
 219         return rte_cpu_feature_table[feature].name;
 220 }