ceph/src/seastar/dpdk/lib/librte_eal/common/eal_common_memory.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdint.h>
  36 #include <stdlib.h>
  37 #include <stdarg.h>
  38 #include <inttypes.h>
  39 #include <sys/queue.h>
  40
  41 #include <rte_memory.h>
  42 #include <rte_memzone.h>
  43 #include <rte_eal.h>
  44 #include <rte_eal_memconfig.h>
  45 #include <rte_log.h>
  46
  47 #include "eal_private.h"
  48 #include "eal_internal_cfg.h"
  49
  50 /*
  51  * Return a pointer to a read-only table of struct rte_physmem_desc
  52  * elements, containing the layout of all addressable physical
  53  * memory. The last element of the table contains a NULL address.
  54  */
  55 const struct rte_memseg *
  56 rte_eal_get_physmem_layout(void)
  57 {
  58         return rte_eal_get_configuration()->mem_config->memseg;
  59 }
  60
  61
  62 /* get the total size of memory */
  63 uint64_t
  64 rte_eal_get_physmem_size(void)
  65 {
  66         const struct rte_mem_config *mcfg;
  67         unsigned i = 0;
  68         uint64_t total_len = 0;
  69
  70         /* get pointer to global configuration */
  71         mcfg = rte_eal_get_configuration()->mem_config;
  72
  73         for (i = 0; i < RTE_MAX_MEMSEG; i++) {
  74                 if (mcfg->memseg[i].addr == NULL)
  75                         break;
  76
  77                 total_len += mcfg->memseg[i].len;
  78         }
  79
  80         return total_len;
  81 }
  82
  83 /* Dump the physical memory layout on console */
  84 void
  85 rte_dump_physmem_layout(FILE *f)
  86 {
  87         const struct rte_mem_config *mcfg;
  88         unsigned i = 0;
  89
  90         /* get pointer to global configuration */
  91         mcfg = rte_eal_get_configuration()->mem_config;
  92
  93         for (i = 0; i < RTE_MAX_MEMSEG; i++) {
  94                 if (mcfg->memseg[i].addr == NULL)
  95                         break;
  96
  97                 fprintf(f, "Segment %u: phys:0x%"PRIx64", len:%zu, "
  98                        "virt:%p, socket_id:%"PRId32", "
  99                        "hugepage_sz:%"PRIu64", nchannel:%"PRIx32", "
 100                        "nrank:%"PRIx32"\n", i,
 101                        mcfg->memseg[i].phys_addr,
 102                        mcfg->memseg[i].len,
 103                        mcfg->memseg[i].addr,
 104                        mcfg->memseg[i].socket_id,
 105                        mcfg->memseg[i].hugepage_sz,
 106                        mcfg->memseg[i].nchannel,
 107                        mcfg->memseg[i].nrank);
 108         }
 109 }
 110
 111 /* return the number of memory channels */
 112 unsigned rte_memory_get_nchannel(void)
 113 {
 114         return rte_eal_get_configuration()->mem_config->nchannel;
 115 }
 116
 117 /* return the number of memory rank */
 118 unsigned rte_memory_get_nrank(void)
 119 {
 120         return rte_eal_get_configuration()->mem_config->nrank;
 121 }
 122
 123 static int
 124 rte_eal_memdevice_init(void)
 125 {
 126         struct rte_config *config;
 127
 128         if (rte_eal_process_type() == RTE_PROC_SECONDARY)
 129                 return 0;
 130
 131         config = rte_eal_get_configuration();
 132         config->mem_config->nchannel = internal_config.force_nchannel;
 133         config->mem_config->nrank = internal_config.force_nrank;
 134
 135         return 0;
 136 }
 137
 138 /* init memory subsystem */
 139 int
 140 rte_eal_memory_init(void)
 141 {
 142         RTE_LOG(DEBUG, EAL, "Setting up physically contiguous memory...\n");
 143
 144         const int retval = rte_eal_process_type() == RTE_PROC_PRIMARY ?
 145                         rte_eal_hugepage_init() :
 146                         rte_eal_hugepage_attach();
 147         if (retval < 0)
 148                 return -1;
 149
 150         if (internal_config.no_shconf == 0 && rte_eal_memdevice_init() < 0)
 151                 return -1;
 152
 153         return 0;
 154 }