ceph/src/seastar/dpdk/lib/librte_eal/common/include/arch/x86/rte_atomic_32.h

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * Inspired from FreeBSD src/sys/i386/include/atomic.h
  36  * Copyright (c) 1998 Doug Rabson
  37  * All rights reserved.
  38  */
  39
  40 #ifndef _RTE_ATOMIC_X86_H_
  41 #error do not include this file directly, use <rte_atomic.h> instead
  42 #endif
  43
  44 #ifndef _RTE_ATOMIC_I686_H_
  45 #define _RTE_ATOMIC_I686_H_
  46
  47 #include <stdint.h>
  48 #include <rte_common.h>
  49 #include <rte_atomic.h>
  50
  51 /*------------------------- 64 bit atomic operations -------------------------*/
  52
  53 #ifndef RTE_FORCE_INTRINSICS
  54 static inline int
  55 rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
  56 {
  57         uint8_t res;
  58         RTE_STD_C11
  59         union {
  60                 struct {
  61                         uint32_t l32;
  62                         uint32_t h32;
  63                 };
  64                 uint64_t u64;
  65         } _exp, _src;
  66
  67         _exp.u64 = exp;
  68         _src.u64 = src;
  69
  70 #ifndef __PIC__
  71     asm volatile (
  72             MPLOCKED
  73             "cmpxchg8b (%[dst]);"
  74             "setz %[res];"
  75             : [res] "=a" (res)      /* result in eax */
  76             : [dst] "S" (dst),      /* esi */
  77              "b" (_src.l32),       /* ebx */
  78              "c" (_src.h32),       /* ecx */
  79              "a" (_exp.l32),       /* eax */
  80              "d" (_exp.h32)        /* edx */
  81                         : "memory" );           /* no-clobber list */
  82 #else
  83         asm volatile (
  84             "xchgl %%ebx, %%edi;\n"
  85                         MPLOCKED
  86                         "cmpxchg8b (%[dst]);"
  87                         "setz %[res];"
  88             "xchgl %%ebx, %%edi;\n"
  89                         : [res] "=a" (res)      /* result in eax */
  90                         : [dst] "S" (dst),      /* esi */
  91                           "D" (_src.l32),       /* ebx */
  92                           "c" (_src.h32),       /* ecx */
  93                           "a" (_exp.l32),       /* eax */
  94                           "d" (_exp.h32)        /* edx */
  95                         : "memory" );           /* no-clobber list */
  96 #endif
  97
  98         return res;
  99 }
 100
 101 static inline uint64_t
 102 rte_atomic64_exchange(volatile uint64_t *dest, uint64_t val)
 103 {
 104         uint64_t old;
 105
 106         do {
 107                 old = *dest;
 108         } while (rte_atomic64_cmpset(dest, old, val) == 0);
 109
 110         return old;
 111 }
 112
 113 static inline void
 114 rte_atomic64_init(rte_atomic64_t *v)
 115 {
 116         int success = 0;
 117         uint64_t tmp;
 118
 119         while (success == 0) {
 120                 tmp = v->cnt;
 121                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 122                                               tmp, 0);
 123         }
 124 }
 125
 126 static inline int64_t
 127 rte_atomic64_read(rte_atomic64_t *v)
 128 {
 129         int success = 0;
 130         uint64_t tmp;
 131
 132         while (success == 0) {
 133                 tmp = v->cnt;
 134                 /* replace the value by itself */
 135                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 136                                               tmp, tmp);
 137         }
 138         return tmp;
 139 }
 140
 141 static inline void
 142 rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
 143 {
 144         int success = 0;
 145         uint64_t tmp;
 146
 147         while (success == 0) {
 148                 tmp = v->cnt;
 149                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 150                                               tmp, new_value);
 151         }
 152 }
 153
 154 static inline void
 155 rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
 156 {
 157         int success = 0;
 158         uint64_t tmp;
 159
 160         while (success == 0) {
 161                 tmp = v->cnt;
 162                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 163                                               tmp, tmp + inc);
 164         }
 165 }
 166
 167 static inline void
 168 rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
 169 {
 170         int success = 0;
 171         uint64_t tmp;
 172
 173         while (success == 0) {
 174                 tmp = v->cnt;
 175                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 176                                               tmp, tmp - dec);
 177         }
 178 }
 179
 180 static inline void
 181 rte_atomic64_inc(rte_atomic64_t *v)
 182 {
 183         rte_atomic64_add(v, 1);
 184 }
 185
 186 static inline void
 187 rte_atomic64_dec(rte_atomic64_t *v)
 188 {
 189         rte_atomic64_sub(v, 1);
 190 }
 191
 192 static inline int64_t
 193 rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
 194 {
 195         int success = 0;
 196         uint64_t tmp;
 197
 198         while (success == 0) {
 199                 tmp = v->cnt;
 200                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 201                                               tmp, tmp + inc);
 202         }
 203
 204         return tmp + inc;
 205 }
 206
 207 static inline int64_t
 208 rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
 209 {
 210         int success = 0;
 211         uint64_t tmp;
 212
 213         while (success == 0) {
 214                 tmp = v->cnt;
 215                 success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
 216                                               tmp, tmp - dec);
 217         }
 218
 219         return tmp - dec;
 220 }
 221
 222 static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
 223 {
 224         return rte_atomic64_add_return(v, 1) == 0;
 225 }
 226
 227 static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
 228 {
 229         return rte_atomic64_sub_return(v, 1) == 0;
 230 }
 231
 232 static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
 233 {
 234         return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
 235 }
 236
 237 static inline void rte_atomic64_clear(rte_atomic64_t *v)
 238 {
 239         rte_atomic64_set(v, 0);
 240 }
 241 #endif
 242
 243 #endif /* _RTE_ATOMIC_I686_H_ */