ceph/src/seastar/dpdk/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _RTE_CPUFLAGS_X86_64_H_
  35 #define _RTE_CPUFLAGS_X86_64_H_
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 enum rte_cpu_flag_t {
  42         /* (EAX 01h) ECX features*/
  43         RTE_CPUFLAG_SSE3 = 0,               /**< SSE3 */
  44         RTE_CPUFLAG_PCLMULQDQ,              /**< PCLMULQDQ */
  45         RTE_CPUFLAG_DTES64,                 /**< DTES64 */
  46         RTE_CPUFLAG_MONITOR,                /**< MONITOR */
  47         RTE_CPUFLAG_DS_CPL,                 /**< DS_CPL */
  48         RTE_CPUFLAG_VMX,                    /**< VMX */
  49         RTE_CPUFLAG_SMX,                    /**< SMX */
  50         RTE_CPUFLAG_EIST,                   /**< EIST */
  51         RTE_CPUFLAG_TM2,                    /**< TM2 */
  52         RTE_CPUFLAG_SSSE3,                  /**< SSSE3 */
  53         RTE_CPUFLAG_CNXT_ID,                /**< CNXT_ID */
  54         RTE_CPUFLAG_FMA,                    /**< FMA */
  55         RTE_CPUFLAG_CMPXCHG16B,             /**< CMPXCHG16B */
  56         RTE_CPUFLAG_XTPR,                   /**< XTPR */
  57         RTE_CPUFLAG_PDCM,                   /**< PDCM */
  58         RTE_CPUFLAG_PCID,                   /**< PCID */
  59         RTE_CPUFLAG_DCA,                    /**< DCA */
  60         RTE_CPUFLAG_SSE4_1,                 /**< SSE4_1 */
  61         RTE_CPUFLAG_SSE4_2,                 /**< SSE4_2 */
  62         RTE_CPUFLAG_X2APIC,                 /**< X2APIC */
  63         RTE_CPUFLAG_MOVBE,                  /**< MOVBE */
  64         RTE_CPUFLAG_POPCNT,                 /**< POPCNT */
  65         RTE_CPUFLAG_TSC_DEADLINE,           /**< TSC_DEADLINE */
  66         RTE_CPUFLAG_AES,                    /**< AES */
  67         RTE_CPUFLAG_XSAVE,                  /**< XSAVE */
  68         RTE_CPUFLAG_OSXSAVE,                /**< OSXSAVE */
  69         RTE_CPUFLAG_AVX,                    /**< AVX */
  70         RTE_CPUFLAG_F16C,                   /**< F16C */
  71         RTE_CPUFLAG_RDRAND,                 /**< RDRAND */
  72
  73         /* (EAX 01h) EDX features */
  74         RTE_CPUFLAG_FPU,                    /**< FPU */
  75         RTE_CPUFLAG_VME,                    /**< VME */
  76         RTE_CPUFLAG_DE,                     /**< DE */
  77         RTE_CPUFLAG_PSE,                    /**< PSE */
  78         RTE_CPUFLAG_TSC,                    /**< TSC */
  79         RTE_CPUFLAG_MSR,                    /**< MSR */
  80         RTE_CPUFLAG_PAE,                    /**< PAE */
  81         RTE_CPUFLAG_MCE,                    /**< MCE */
  82         RTE_CPUFLAG_CX8,                    /**< CX8 */
  83         RTE_CPUFLAG_APIC,                   /**< APIC */
  84         RTE_CPUFLAG_SEP,                    /**< SEP */
  85         RTE_CPUFLAG_MTRR,                   /**< MTRR */
  86         RTE_CPUFLAG_PGE,                    /**< PGE */
  87         RTE_CPUFLAG_MCA,                    /**< MCA */
  88         RTE_CPUFLAG_CMOV,                   /**< CMOV */
  89         RTE_CPUFLAG_PAT,                    /**< PAT */
  90         RTE_CPUFLAG_PSE36,                  /**< PSE36 */
  91         RTE_CPUFLAG_PSN,                    /**< PSN */
  92         RTE_CPUFLAG_CLFSH,                  /**< CLFSH */
  93         RTE_CPUFLAG_DS,                     /**< DS */
  94         RTE_CPUFLAG_ACPI,                   /**< ACPI */
  95         RTE_CPUFLAG_MMX,                    /**< MMX */
  96         RTE_CPUFLAG_FXSR,                   /**< FXSR */
  97         RTE_CPUFLAG_SSE,                    /**< SSE */
  98         RTE_CPUFLAG_SSE2,                   /**< SSE2 */
  99         RTE_CPUFLAG_SS,                     /**< SS */
 100         RTE_CPUFLAG_HTT,                    /**< HTT */
 101         RTE_CPUFLAG_TM,                     /**< TM */
 102         RTE_CPUFLAG_PBE,                    /**< PBE */
 103
 104         /* (EAX 06h) EAX features */
 105         RTE_CPUFLAG_DIGTEMP,                /**< DIGTEMP */
 106         RTE_CPUFLAG_TRBOBST,                /**< TRBOBST */
 107         RTE_CPUFLAG_ARAT,                   /**< ARAT */
 108         RTE_CPUFLAG_PLN,                    /**< PLN */
 109         RTE_CPUFLAG_ECMD,                   /**< ECMD */
 110         RTE_CPUFLAG_PTM,                    /**< PTM */
 111
 112         /* (EAX 06h) ECX features */
 113         RTE_CPUFLAG_MPERF_APERF_MSR,        /**< MPERF_APERF_MSR */
 114         RTE_CPUFLAG_ACNT2,                  /**< ACNT2 */
 115         RTE_CPUFLAG_ENERGY_EFF,             /**< ENERGY_EFF */
 116
 117         /* (EAX 07h, ECX 0h) EBX features */
 118         RTE_CPUFLAG_FSGSBASE,               /**< FSGSBASE */
 119         RTE_CPUFLAG_BMI1,                   /**< BMI1 */
 120         RTE_CPUFLAG_HLE,                    /**< Hardware Lock elision */
 121         RTE_CPUFLAG_AVX2,                   /**< AVX2 */
 122         RTE_CPUFLAG_SMEP,                   /**< SMEP */
 123         RTE_CPUFLAG_BMI2,                   /**< BMI2 */
 124         RTE_CPUFLAG_ERMS,                   /**< ERMS */
 125         RTE_CPUFLAG_INVPCID,                /**< INVPCID */
 126         RTE_CPUFLAG_RTM,                    /**< Transactional memory */
 127         RTE_CPUFLAG_AVX512F,                /**< AVX512F */
 128
 129         /* (EAX 80000001h) ECX features */
 130         RTE_CPUFLAG_LAHF_SAHF,              /**< LAHF_SAHF */
 131         RTE_CPUFLAG_LZCNT,                  /**< LZCNT */
 132
 133         /* (EAX 80000001h) EDX features */
 134         RTE_CPUFLAG_SYSCALL,                /**< SYSCALL */
 135         RTE_CPUFLAG_XD,                     /**< XD */
 136         RTE_CPUFLAG_1GB_PG,                 /**< 1GB_PG */
 137         RTE_CPUFLAG_RDTSCP,                 /**< RDTSCP */
 138         RTE_CPUFLAG_EM64T,                  /**< EM64T */
 139
 140         /* (EAX 80000007h) EDX features */
 141         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
 142
 143         /* The last item */
 144         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
 145 };
 146
 147 #include "generic/rte_cpuflags.h"
 148
 149 #ifdef __cplusplus
 150 }
 151 #endif
 152
 153 #endif /* _RTE_CPUFLAGS_X86_64_H_ */