ceph/src/seastar/dpdk/lib/librte_eal/common/include/generic/rte_io.h

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2016 Cavium networks. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Cavium networks nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #ifndef _RTE_IO_H_
  35 #define _RTE_IO_H_
  36
  37 #include <rte_atomic.h>
  38
  39 /**
  40  * @file
  41  * I/O device memory operations
  42  *
  43  * This file defines the generic API for I/O device memory read/write operations
  44  */
  45
  46 #include <stdint.h>
  47 #include <rte_common.h>
  48 #include <rte_atomic.h>
  49
  50 #ifdef __DOXYGEN__
  51
  52 /**
  53  * Read a 8-bit value from I/O device memory address *addr*.
  54  *
  55  * The relaxed version does not have additional I/O memory barrier, useful in
  56  * accessing the device registers of integrated controllers which implicitly
  57  * strongly ordered with respect to memory access.
  58  *
  59  * @param addr
  60  *  I/O memory address to read the value from
  61  * @return
  62  *  read value
  63  */
  64 static inline uint8_t
  65 rte_read8_relaxed(const volatile void *addr);
  66
  67 /**
  68  * Read a 16-bit value from I/O device memory address *addr*.
  69  *
  70  * The relaxed version does not have additional I/O memory barrier, useful in
  71  * accessing the device registers of integrated controllers which implicitly
  72  * strongly ordered with respect to memory access.
  73  *
  74  * @param addr
  75  *  I/O memory address to read the value from
  76  * @return
  77  *  read value
  78  */
  79 static inline uint16_t
  80 rte_read16_relaxed(const volatile void *addr);
  81
  82 /**
  83  * Read a 32-bit value from I/O device memory address *addr*.
  84  *
  85  * The relaxed version does not have additional I/O memory barrier, useful in
  86  * accessing the device registers of integrated controllers which implicitly
  87  * strongly ordered with respect to memory access.
  88  *
  89  * @param addr
  90  *  I/O memory address to read the value from
  91  * @return
  92  *  read value
  93  */
  94 static inline uint32_t
  95 rte_read32_relaxed(const volatile void *addr);
  96
  97 /**
  98  * Read a 64-bit value from I/O device memory address *addr*.
  99  *
 100  * The relaxed version does not have additional I/O memory barrier, useful in
 101  * accessing the device registers of integrated controllers which implicitly
 102  * strongly ordered with respect to memory access.
 103  *
 104  * @param addr
 105  *  I/O memory address to read the value from
 106  * @return
 107  *  read value
 108  */
 109 static inline uint64_t
 110 rte_read64_relaxed(const volatile void *addr);
 111
 112 /**
 113  * Write a 8-bit value to I/O device memory address *addr*.
 114  *
 115  * The relaxed version does not have additional I/O memory barrier, useful in
 116  * accessing the device registers of integrated controllers which implicitly
 117  * strongly ordered with respect to memory access.
 118  *
 119  * @param value
 120  *  Value to write
 121  * @param addr
 122  *  I/O memory address to write the value to
 123  */
 124
 125 static inline void
 126 rte_write8_relaxed(uint8_t value, volatile void *addr);
 127
 128 /**
 129  * Write a 16-bit value to I/O device memory address *addr*.
 130  *
 131  * The relaxed version does not have additional I/O memory barrier, useful in
 132  * accessing the device registers of integrated controllers which implicitly
 133  * strongly ordered with respect to memory access.
 134  *
 135  * @param value
 136  *  Value to write
 137  * @param addr
 138  *  I/O memory address to write the value to
 139  */
 140 static inline void
 141 rte_write16_relaxed(uint16_t value, volatile void *addr);
 142
 143 /**
 144  * Write a 32-bit value to I/O device memory address *addr*.
 145  *
 146  * The relaxed version does not have additional I/O memory barrier, useful in
 147  * accessing the device registers of integrated controllers which implicitly
 148  * strongly ordered with respect to memory access.
 149  *
 150  * @param value
 151  *  Value to write
 152  * @param addr
 153  *  I/O memory address to write the value to
 154  */
 155 static inline void
 156 rte_write32_relaxed(uint32_t value, volatile void *addr);
 157
 158 /**
 159  * Write a 64-bit value to I/O device memory address *addr*.
 160  *
 161  * The relaxed version does not have additional I/O memory barrier, useful in
 162  * accessing the device registers of integrated controllers which implicitly
 163  * strongly ordered with respect to memory access.
 164  *
 165  * @param value
 166  *  Value to write
 167  * @param addr
 168  *  I/O memory address to write the value to
 169  */
 170 static inline void
 171 rte_write64_relaxed(uint64_t value, volatile void *addr);
 172
 173 /**
 174  * Read a 8-bit value from I/O device memory address *addr*.
 175  *
 176  * @param addr
 177  *  I/O memory address to read the value from
 178  * @return
 179  *  read value
 180  */
 181 static inline uint8_t
 182 rte_read8(const volatile void *addr);
 183
 184 /**
 185  * Read a 16-bit value from I/O device memory address *addr*.
 186  *
 187  *
 188  * @param addr
 189  *  I/O memory address to read the value from
 190  * @return
 191  *  read value
 192  */
 193 static inline uint16_t
 194 rte_read16(const volatile void *addr);
 195
 196 /**
 197  * Read a 32-bit value from I/O device memory address *addr*.
 198  *
 199  * @param addr
 200  *  I/O memory address to read the value from
 201  * @return
 202  *  read value
 203  */
 204 static inline uint32_t
 205 rte_read32(const volatile void *addr);
 206
 207 /**
 208  * Read a 64-bit value from I/O device memory address *addr*.
 209  *
 210  * @param addr
 211  *  I/O memory address to read the value from
 212  * @return
 213  *  read value
 214  */
 215 static inline uint64_t
 216 rte_read64(const volatile void *addr);
 217
 218 /**
 219  * Write a 8-bit value to I/O device memory address *addr*.
 220  *
 221  * @param value
 222  *  Value to write
 223  * @param addr
 224  *  I/O memory address to write the value to
 225  */
 226
 227 static inline void
 228 rte_write8(uint8_t value, volatile void *addr);
 229
 230 /**
 231  * Write a 16-bit value to I/O device memory address *addr*.
 232  *
 233  * @param value
 234  *  Value to write
 235  * @param addr
 236  *  I/O memory address to write the value to
 237  */
 238 static inline void
 239 rte_write16(uint16_t value, volatile void *addr);
 240
 241 /**
 242  * Write a 32-bit value to I/O device memory address *addr*.
 243  *
 244  * @param value
 245  *  Value to write
 246  * @param addr
 247  *  I/O memory address to write the value to
 248  */
 249 static inline void
 250 rte_write32(uint32_t value, volatile void *addr);
 251
 252 /**
 253  * Write a 64-bit value to I/O device memory address *addr*.
 254  *
 255  * @param value
 256  *  Value to write
 257  * @param addr
 258  *  I/O memory address to write the value to
 259  */
 260 static inline void
 261 rte_write64(uint64_t value, volatile void *addr);
 262
 263 #endif /* __DOXYGEN__ */
 264
 265 #ifndef RTE_OVERRIDE_IO_H
 266
 267 static inline uint8_t __attribute__((always_inline))
 268 rte_read8_relaxed(const volatile void *addr)
 269 {
 270         return *(const volatile uint8_t *)addr;
 271 }
 272
 273 static inline uint16_t __attribute__((always_inline))
 274 rte_read16_relaxed(const volatile void *addr)
 275 {
 276         return *(const volatile uint16_t *)addr;
 277 }
 278
 279 static inline uint32_t __attribute__((always_inline))
 280 rte_read32_relaxed(const volatile void *addr)
 281 {
 282         return *(const volatile uint32_t *)addr;
 283 }
 284
 285 static inline uint64_t __attribute__((always_inline))
 286 rte_read64_relaxed(const volatile void *addr)
 287 {
 288         return *(const volatile uint64_t *)addr;
 289 }
 290
 291 static inline void __attribute__((always_inline))
 292 rte_write8_relaxed(uint8_t value, volatile void *addr)
 293 {
 294         *(volatile uint8_t *)addr = value;
 295 }
 296
 297 static inline void __attribute__((always_inline))
 298 rte_write16_relaxed(uint16_t value, volatile void *addr)
 299 {
 300         *(volatile uint16_t *)addr = value;
 301 }
 302
 303 static inline void __attribute__((always_inline))
 304 rte_write32_relaxed(uint32_t value, volatile void *addr)
 305 {
 306         *(volatile uint32_t *)addr = value;
 307 }
 308
 309 static inline void __attribute__((always_inline))
 310 rte_write64_relaxed(uint64_t value, volatile void *addr)
 311 {
 312         *(volatile uint64_t *)addr = value;
 313 }
 314
 315 static inline uint8_t __attribute__((always_inline))
 316 rte_read8(const volatile void *addr)
 317 {
 318         uint8_t val;
 319         val = rte_read8_relaxed(addr);
 320         rte_io_rmb();
 321         return val;
 322 }
 323
 324 static inline uint16_t __attribute__((always_inline))
 325 rte_read16(const volatile void *addr)
 326 {
 327         uint16_t val;
 328         val = rte_read16_relaxed(addr);
 329         rte_io_rmb();
 330         return val;
 331 }
 332
 333 static inline uint32_t  __attribute__((always_inline))
 334 rte_read32(const volatile void *addr)
 335 {
 336         uint32_t val;
 337         val = rte_read32_relaxed(addr);
 338         rte_io_rmb();
 339         return val;
 340 }
 341
 342 static inline uint64_t __attribute__((always_inline))
 343 rte_read64(const volatile void *addr)
 344 {
 345         uint64_t val;
 346         val = rte_read64_relaxed(addr);
 347         rte_io_rmb();
 348         return val;
 349 }
 350
 351 static inline void __attribute__((always_inline))
 352 rte_write8(uint8_t value, volatile void *addr)
 353 {
 354         rte_io_wmb();
 355         rte_write8_relaxed(value, addr);
 356 }
 357
 358 static inline void __attribute__((always_inline))
 359 rte_write16(uint16_t value, volatile void *addr)
 360 {
 361         rte_io_wmb();
 362         rte_write16_relaxed(value, addr);
 363 }
 364
 365 static inline void __attribute__((always_inline))
 366 rte_write32(uint32_t value, volatile void *addr)
 367 {
 368         rte_io_wmb();
 369         rte_write32_relaxed(value, addr);
 370 }
 371
 372 static inline void __attribute__((always_inline))
 373 rte_write64(uint64_t value, volatile void *addr)
 374 {
 375         rte_io_wmb();
 376         rte_write64_relaxed(value, addr);
 377 }
 378
 379 #endif /* RTE_OVERRIDE_IO_H */
 380
 381 #endif /* _RTE_IO_H_ */