ceph/src/seastar/dpdk/lib/librte_eal/linuxapp/kni/ethtool/igb/e1000_manage.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "LICENSE.GPL".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_MANAGE_H_
  29 #define _E1000_MANAGE_H_
  30
  31 bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
  32 bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
  33 s32  e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
  34 s32  e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
  35                                      u16 length, u16 offset, u8 *sum);
  36 s32  e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
  37                                      struct e1000_host_mng_command_header *hdr);
  38 s32  e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
  39                                        u8 *buffer, u16 length);
  40 bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
  41 u8 e1000_calculate_checksum(u8 *buffer, u32 length);
  42 s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);
  43 s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);
  44
  45 enum e1000_mng_mode {
  46         e1000_mng_mode_none = 0,
  47         e1000_mng_mode_asf,
  48         e1000_mng_mode_pt,
  49         e1000_mng_mode_ipmi,
  50         e1000_mng_mode_host_if_only
  51 };
  52
  53 #define E1000_FACTPS_MNGCG                      0x20000000
  54
  55 #define E1000_FWSM_MODE_MASK                    0xE
  56 #define E1000_FWSM_MODE_SHIFT                   1
  57 #define E1000_FWSM_FW_VALID                     0x00008000
  58 #define E1000_FWSM_HI_EN_ONLY_MODE              0x4
  59
  60 #define E1000_MNG_IAMT_MODE                     0x3
  61 #define E1000_MNG_DHCP_COOKIE_LENGTH            0x10
  62 #define E1000_MNG_DHCP_COOKIE_OFFSET            0x6F0
  63 #define E1000_MNG_DHCP_COMMAND_TIMEOUT          10
  64 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD           64
  65 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING    0x1
  66 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN       0x2
  67
  68 #define E1000_VFTA_ENTRY_SHIFT                  5
  69 #define E1000_VFTA_ENTRY_MASK                   0x7F
  70 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK         0x1F
  71
  72 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH          1792 /* Num of bytes in range */
  73 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH         448 /* Num of dwords in range */
  74 #define E1000_HI_COMMAND_TIMEOUT                500 /* Process HI cmd limit */
  75 #define E1000_HI_FW_BASE_ADDRESS                0x10000
  76 #define E1000_HI_FW_MAX_LENGTH                  (64 * 1024) /* Num of bytes */
  77 #define E1000_HI_FW_BLOCK_DWORD_LENGTH          256 /* Num of DWORDs per page */
  78 #define E1000_HICR_MEMORY_BASE_EN               0x200 /* MB Enable bit - RO */
  79 #define E1000_HICR_EN                   0x01  /* Enable bit - RO */
  80 /* Driver sets this bit when done to put command in RAM */
  81 #define E1000_HICR_C                    0x02
  82 #define E1000_HICR_SV                   0x04  /* Status Validity */
  83 #define E1000_HICR_FW_RESET_ENABLE      0x40
  84 #define E1000_HICR_FW_RESET             0x80
  85
  86 /* Intel(R) Active Management Technology signature */
  87 #define E1000_IAMT_SIGNATURE            0x544D4149
  88
  89 #endif