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[ceph.git] / ceph / src / seastar / dpdk / lib / librte_ethdev / rte_ethdev.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
3 */
4
5 #include <sys/types.h>
6 #include <sys/queue.h>
7 #include <ctype.h>
8 #include <stdio.h>
9 #include <stdlib.h>
10 #include <string.h>
11 #include <stdarg.h>
12 #include <errno.h>
13 #include <stdbool.h>
14 #include <stdint.h>
15 #include <inttypes.h>
16 #include <netinet/in.h>
17
18 #include <rte_byteorder.h>
19 #include <rte_log.h>
20 #include <rte_debug.h>
21 #include <rte_interrupts.h>
22 #include <rte_memory.h>
23 #include <rte_memcpy.h>
24 #include <rte_memzone.h>
25 #include <rte_launch.h>
26 #include <rte_eal.h>
27 #include <rte_per_lcore.h>
28 #include <rte_lcore.h>
29 #include <rte_atomic.h>
30 #include <rte_branch_prediction.h>
31 #include <rte_common.h>
32 #include <rte_mempool.h>
33 #include <rte_malloc.h>
34 #include <rte_mbuf.h>
35 #include <rte_errno.h>
36 #include <rte_spinlock.h>
37 #include <rte_string_fns.h>
38 #include <rte_kvargs.h>
39 #include <rte_class.h>
40
41 #include "rte_ether.h"
42 #include "rte_ethdev.h"
43 #include "rte_ethdev_driver.h"
44 #include "ethdev_profile.h"
45 #include "ethdev_private.h"
46
47 int rte_eth_dev_logtype;
48
49 static const char *MZ_RTE_ETH_DEV_DATA = "rte_eth_dev_data";
50 struct rte_eth_dev rte_eth_devices[RTE_MAX_ETHPORTS];
51
52 /* spinlock for eth device callbacks */
53 static rte_spinlock_t rte_eth_dev_cb_lock = RTE_SPINLOCK_INITIALIZER;
54
55 /* spinlock for add/remove rx callbacks */
56 static rte_spinlock_t rte_eth_rx_cb_lock = RTE_SPINLOCK_INITIALIZER;
57
58 /* spinlock for add/remove tx callbacks */
59 static rte_spinlock_t rte_eth_tx_cb_lock = RTE_SPINLOCK_INITIALIZER;
60
61 /* spinlock for shared data allocation */
62 static rte_spinlock_t rte_eth_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
63
64 /* store statistics names and its offset in stats structure */
65 struct rte_eth_xstats_name_off {
66 char name[RTE_ETH_XSTATS_NAME_SIZE];
67 unsigned offset;
68 };
69
70 /* Shared memory between primary and secondary processes. */
71 static struct {
72 uint64_t next_owner_id;
73 rte_spinlock_t ownership_lock;
74 struct rte_eth_dev_data data[RTE_MAX_ETHPORTS];
75 } *rte_eth_dev_shared_data;
76
77 static const struct rte_eth_xstats_name_off rte_stats_strings[] = {
78 {"rx_good_packets", offsetof(struct rte_eth_stats, ipackets)},
79 {"tx_good_packets", offsetof(struct rte_eth_stats, opackets)},
80 {"rx_good_bytes", offsetof(struct rte_eth_stats, ibytes)},
81 {"tx_good_bytes", offsetof(struct rte_eth_stats, obytes)},
82 {"rx_missed_errors", offsetof(struct rte_eth_stats, imissed)},
83 {"rx_errors", offsetof(struct rte_eth_stats, ierrors)},
84 {"tx_errors", offsetof(struct rte_eth_stats, oerrors)},
85 {"rx_mbuf_allocation_errors", offsetof(struct rte_eth_stats,
86 rx_nombuf)},
87 };
88
89 #define RTE_NB_STATS (sizeof(rte_stats_strings) / sizeof(rte_stats_strings[0]))
90
91 static const struct rte_eth_xstats_name_off rte_rxq_stats_strings[] = {
92 {"packets", offsetof(struct rte_eth_stats, q_ipackets)},
93 {"bytes", offsetof(struct rte_eth_stats, q_ibytes)},
94 {"errors", offsetof(struct rte_eth_stats, q_errors)},
95 };
96
97 #define RTE_NB_RXQ_STATS (sizeof(rte_rxq_stats_strings) / \
98 sizeof(rte_rxq_stats_strings[0]))
99
100 static const struct rte_eth_xstats_name_off rte_txq_stats_strings[] = {
101 {"packets", offsetof(struct rte_eth_stats, q_opackets)},
102 {"bytes", offsetof(struct rte_eth_stats, q_obytes)},
103 };
104 #define RTE_NB_TXQ_STATS (sizeof(rte_txq_stats_strings) / \
105 sizeof(rte_txq_stats_strings[0]))
106
107 #define RTE_RX_OFFLOAD_BIT2STR(_name) \
108 { DEV_RX_OFFLOAD_##_name, #_name }
109
110 static const struct {
111 uint64_t offload;
112 const char *name;
113 } rte_rx_offload_names[] = {
114 RTE_RX_OFFLOAD_BIT2STR(VLAN_STRIP),
115 RTE_RX_OFFLOAD_BIT2STR(IPV4_CKSUM),
116 RTE_RX_OFFLOAD_BIT2STR(UDP_CKSUM),
117 RTE_RX_OFFLOAD_BIT2STR(TCP_CKSUM),
118 RTE_RX_OFFLOAD_BIT2STR(TCP_LRO),
119 RTE_RX_OFFLOAD_BIT2STR(QINQ_STRIP),
120 RTE_RX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM),
121 RTE_RX_OFFLOAD_BIT2STR(MACSEC_STRIP),
122 RTE_RX_OFFLOAD_BIT2STR(HEADER_SPLIT),
123 RTE_RX_OFFLOAD_BIT2STR(VLAN_FILTER),
124 RTE_RX_OFFLOAD_BIT2STR(VLAN_EXTEND),
125 RTE_RX_OFFLOAD_BIT2STR(JUMBO_FRAME),
126 RTE_RX_OFFLOAD_BIT2STR(SCATTER),
127 RTE_RX_OFFLOAD_BIT2STR(TIMESTAMP),
128 RTE_RX_OFFLOAD_BIT2STR(SECURITY),
129 RTE_RX_OFFLOAD_BIT2STR(KEEP_CRC),
130 RTE_RX_OFFLOAD_BIT2STR(SCTP_CKSUM),
131 RTE_RX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
132 };
133
134 #undef RTE_RX_OFFLOAD_BIT2STR
135
136 #define RTE_TX_OFFLOAD_BIT2STR(_name) \
137 { DEV_TX_OFFLOAD_##_name, #_name }
138
139 static const struct {
140 uint64_t offload;
141 const char *name;
142 } rte_tx_offload_names[] = {
143 RTE_TX_OFFLOAD_BIT2STR(VLAN_INSERT),
144 RTE_TX_OFFLOAD_BIT2STR(IPV4_CKSUM),
145 RTE_TX_OFFLOAD_BIT2STR(UDP_CKSUM),
146 RTE_TX_OFFLOAD_BIT2STR(TCP_CKSUM),
147 RTE_TX_OFFLOAD_BIT2STR(SCTP_CKSUM),
148 RTE_TX_OFFLOAD_BIT2STR(TCP_TSO),
149 RTE_TX_OFFLOAD_BIT2STR(UDP_TSO),
150 RTE_TX_OFFLOAD_BIT2STR(OUTER_IPV4_CKSUM),
151 RTE_TX_OFFLOAD_BIT2STR(QINQ_INSERT),
152 RTE_TX_OFFLOAD_BIT2STR(VXLAN_TNL_TSO),
153 RTE_TX_OFFLOAD_BIT2STR(GRE_TNL_TSO),
154 RTE_TX_OFFLOAD_BIT2STR(IPIP_TNL_TSO),
155 RTE_TX_OFFLOAD_BIT2STR(GENEVE_TNL_TSO),
156 RTE_TX_OFFLOAD_BIT2STR(MACSEC_INSERT),
157 RTE_TX_OFFLOAD_BIT2STR(MT_LOCKFREE),
158 RTE_TX_OFFLOAD_BIT2STR(MULTI_SEGS),
159 RTE_TX_OFFLOAD_BIT2STR(MBUF_FAST_FREE),
160 RTE_TX_OFFLOAD_BIT2STR(SECURITY),
161 RTE_TX_OFFLOAD_BIT2STR(UDP_TNL_TSO),
162 RTE_TX_OFFLOAD_BIT2STR(IP_TNL_TSO),
163 RTE_TX_OFFLOAD_BIT2STR(OUTER_UDP_CKSUM),
164 RTE_TX_OFFLOAD_BIT2STR(MATCH_METADATA),
165 };
166
167 #undef RTE_TX_OFFLOAD_BIT2STR
168
169 /**
170 * The user application callback description.
171 *
172 * It contains callback address to be registered by user application,
173 * the pointer to the parameters for callback, and the event type.
174 */
175 struct rte_eth_dev_callback {
176 TAILQ_ENTRY(rte_eth_dev_callback) next; /**< Callbacks list */
177 rte_eth_dev_cb_fn cb_fn; /**< Callback address */
178 void *cb_arg; /**< Parameter for callback */
179 void *ret_param; /**< Return parameter */
180 enum rte_eth_event_type event; /**< Interrupt event type */
181 uint32_t active; /**< Callback is executing */
182 };
183
184 enum {
185 STAT_QMAP_TX = 0,
186 STAT_QMAP_RX
187 };
188
189 int
190 rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs_str)
191 {
192 int ret;
193 struct rte_devargs devargs = {.args = NULL};
194 const char *bus_param_key;
195 char *bus_str = NULL;
196 char *cls_str = NULL;
197 int str_size;
198
199 memset(iter, 0, sizeof(*iter));
200
201 /*
202 * The devargs string may use various syntaxes:
203 * - 0000:08:00.0,representor=[1-3]
204 * - pci:0000:06:00.0,representor=[0,5]
205 * - class=eth,mac=00:11:22:33:44:55
206 * A new syntax is in development (not yet supported):
207 * - bus=X,paramX=x/class=Y,paramY=y/driver=Z,paramZ=z
208 */
209
210 /*
211 * Handle pure class filter (i.e. without any bus-level argument),
212 * from future new syntax.
213 * rte_devargs_parse() is not yet supporting the new syntax,
214 * that's why this simple case is temporarily parsed here.
215 */
216 #define iter_anybus_str "class=eth,"
217 if (strncmp(devargs_str, iter_anybus_str,
218 strlen(iter_anybus_str)) == 0) {
219 iter->cls_str = devargs_str + strlen(iter_anybus_str);
220 goto end;
221 }
222
223 /* Split bus, device and parameters. */
224 ret = rte_devargs_parse(&devargs, devargs_str);
225 if (ret != 0)
226 goto error;
227
228 /*
229 * Assume parameters of old syntax can match only at ethdev level.
230 * Extra parameters will be ignored, thanks to "+" prefix.
231 */
232 str_size = strlen(devargs.args) + 2;
233 cls_str = malloc(str_size);
234 if (cls_str == NULL) {
235 ret = -ENOMEM;
236 goto error;
237 }
238 ret = snprintf(cls_str, str_size, "+%s", devargs.args);
239 if (ret != str_size - 1) {
240 ret = -EINVAL;
241 goto error;
242 }
243 iter->cls_str = cls_str;
244 free(devargs.args); /* allocated by rte_devargs_parse() */
245 devargs.args = NULL;
246
247 iter->bus = devargs.bus;
248 if (iter->bus->dev_iterate == NULL) {
249 ret = -ENOTSUP;
250 goto error;
251 }
252
253 /* Convert bus args to new syntax for use with new API dev_iterate. */
254 if (strcmp(iter->bus->name, "vdev") == 0) {
255 bus_param_key = "name";
256 } else if (strcmp(iter->bus->name, "pci") == 0) {
257 bus_param_key = "addr";
258 } else {
259 ret = -ENOTSUP;
260 goto error;
261 }
262 str_size = strlen(bus_param_key) + strlen(devargs.name) + 2;
263 bus_str = malloc(str_size);
264 if (bus_str == NULL) {
265 ret = -ENOMEM;
266 goto error;
267 }
268 ret = snprintf(bus_str, str_size, "%s=%s",
269 bus_param_key, devargs.name);
270 if (ret != str_size - 1) {
271 ret = -EINVAL;
272 goto error;
273 }
274 iter->bus_str = bus_str;
275
276 end:
277 iter->cls = rte_class_find_by_name("eth");
278 return 0;
279
280 error:
281 if (ret == -ENOTSUP)
282 RTE_LOG(ERR, EAL, "Bus %s does not support iterating.\n",
283 iter->bus->name);
284 free(devargs.args);
285 free(bus_str);
286 free(cls_str);
287 return ret;
288 }
289
290 uint16_t
291 rte_eth_iterator_next(struct rte_dev_iterator *iter)
292 {
293 if (iter->cls == NULL) /* invalid ethdev iterator */
294 return RTE_MAX_ETHPORTS;
295
296 do { /* loop to try all matching rte_device */
297 /* If not pure ethdev filter and */
298 if (iter->bus != NULL &&
299 /* not in middle of rte_eth_dev iteration, */
300 iter->class_device == NULL) {
301 /* get next rte_device to try. */
302 iter->device = iter->bus->dev_iterate(
303 iter->device, iter->bus_str, iter);
304 if (iter->device == NULL)
305 break; /* no more rte_device candidate */
306 }
307 /* A device is matching bus part, need to check ethdev part. */
308 iter->class_device = iter->cls->dev_iterate(
309 iter->class_device, iter->cls_str, iter);
310 if (iter->class_device != NULL)
311 return eth_dev_to_id(iter->class_device); /* match */
312 } while (iter->bus != NULL); /* need to try next rte_device */
313
314 /* No more ethdev port to iterate. */
315 rte_eth_iterator_cleanup(iter);
316 return RTE_MAX_ETHPORTS;
317 }
318
319 void
320 rte_eth_iterator_cleanup(struct rte_dev_iterator *iter)
321 {
322 if (iter->bus_str == NULL)
323 return; /* nothing to free in pure class filter */
324 free(RTE_CAST_FIELD(iter, bus_str, char *)); /* workaround const */
325 free(RTE_CAST_FIELD(iter, cls_str, char *)); /* workaround const */
326 memset(iter, 0, sizeof(*iter));
327 }
328
329 uint16_t
330 rte_eth_find_next(uint16_t port_id)
331 {
332 while (port_id < RTE_MAX_ETHPORTS &&
333 rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED)
334 port_id++;
335
336 if (port_id >= RTE_MAX_ETHPORTS)
337 return RTE_MAX_ETHPORTS;
338
339 return port_id;
340 }
341
342 /*
343 * Macro to iterate over all valid ports for internal usage.
344 * Note: RTE_ETH_FOREACH_DEV is different because filtering owned ports.
345 */
346 #define RTE_ETH_FOREACH_VALID_DEV(port_id) \
347 for (port_id = rte_eth_find_next(0); \
348 port_id < RTE_MAX_ETHPORTS; \
349 port_id = rte_eth_find_next(port_id + 1))
350
351 uint16_t
352 rte_eth_find_next_of(uint16_t port_id, const struct rte_device *parent)
353 {
354 port_id = rte_eth_find_next(port_id);
355 while (port_id < RTE_MAX_ETHPORTS &&
356 rte_eth_devices[port_id].device != parent)
357 port_id = rte_eth_find_next(port_id + 1);
358
359 return port_id;
360 }
361
362 uint16_t
363 rte_eth_find_next_sibling(uint16_t port_id, uint16_t ref_port_id)
364 {
365 RTE_ETH_VALID_PORTID_OR_ERR_RET(ref_port_id, RTE_MAX_ETHPORTS);
366 return rte_eth_find_next_of(port_id,
367 rte_eth_devices[ref_port_id].device);
368 }
369
370 static void
371 rte_eth_dev_shared_data_prepare(void)
372 {
373 const unsigned flags = 0;
374 const struct rte_memzone *mz;
375
376 rte_spinlock_lock(&rte_eth_shared_data_lock);
377
378 if (rte_eth_dev_shared_data == NULL) {
379 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
380 /* Allocate port data and ownership shared memory. */
381 mz = rte_memzone_reserve(MZ_RTE_ETH_DEV_DATA,
382 sizeof(*rte_eth_dev_shared_data),
383 rte_socket_id(), flags);
384 } else
385 mz = rte_memzone_lookup(MZ_RTE_ETH_DEV_DATA);
386 if (mz == NULL)
387 rte_panic("Cannot allocate ethdev shared data\n");
388
389 rte_eth_dev_shared_data = mz->addr;
390 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
391 rte_eth_dev_shared_data->next_owner_id =
392 RTE_ETH_DEV_NO_OWNER + 1;
393 rte_spinlock_init(&rte_eth_dev_shared_data->ownership_lock);
394 memset(rte_eth_dev_shared_data->data, 0,
395 sizeof(rte_eth_dev_shared_data->data));
396 }
397 }
398
399 rte_spinlock_unlock(&rte_eth_shared_data_lock);
400 }
401
402 static bool
403 is_allocated(const struct rte_eth_dev *ethdev)
404 {
405 return ethdev->data->name[0] != '\0';
406 }
407
408 static struct rte_eth_dev *
409 _rte_eth_dev_allocated(const char *name)
410 {
411 unsigned i;
412
413 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
414 if (rte_eth_devices[i].data != NULL &&
415 strcmp(rte_eth_devices[i].data->name, name) == 0)
416 return &rte_eth_devices[i];
417 }
418 return NULL;
419 }
420
421 struct rte_eth_dev *
422 rte_eth_dev_allocated(const char *name)
423 {
424 struct rte_eth_dev *ethdev;
425
426 rte_eth_dev_shared_data_prepare();
427
428 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
429
430 ethdev = _rte_eth_dev_allocated(name);
431
432 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
433
434 return ethdev;
435 }
436
437 static uint16_t
438 rte_eth_dev_find_free_port(void)
439 {
440 unsigned i;
441
442 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
443 /* Using shared name field to find a free port. */
444 if (rte_eth_dev_shared_data->data[i].name[0] == '\0') {
445 RTE_ASSERT(rte_eth_devices[i].state ==
446 RTE_ETH_DEV_UNUSED);
447 return i;
448 }
449 }
450 return RTE_MAX_ETHPORTS;
451 }
452
453 static struct rte_eth_dev *
454 eth_dev_get(uint16_t port_id)
455 {
456 struct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];
457
458 eth_dev->data = &rte_eth_dev_shared_data->data[port_id];
459
460 return eth_dev;
461 }
462
463 struct rte_eth_dev *
464 rte_eth_dev_allocate(const char *name)
465 {
466 uint16_t port_id;
467 struct rte_eth_dev *eth_dev = NULL;
468 size_t name_len;
469
470 name_len = strnlen(name, RTE_ETH_NAME_MAX_LEN);
471 if (name_len == 0) {
472 RTE_ETHDEV_LOG(ERR, "Zero length Ethernet device name\n");
473 return NULL;
474 }
475
476 if (name_len >= RTE_ETH_NAME_MAX_LEN) {
477 RTE_ETHDEV_LOG(ERR, "Ethernet device name is too long\n");
478 return NULL;
479 }
480
481 rte_eth_dev_shared_data_prepare();
482
483 /* Synchronize port creation between primary and secondary threads. */
484 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
485
486 if (_rte_eth_dev_allocated(name) != NULL) {
487 RTE_ETHDEV_LOG(ERR,
488 "Ethernet device with name %s already allocated\n",
489 name);
490 goto unlock;
491 }
492
493 port_id = rte_eth_dev_find_free_port();
494 if (port_id == RTE_MAX_ETHPORTS) {
495 RTE_ETHDEV_LOG(ERR,
496 "Reached maximum number of Ethernet ports\n");
497 goto unlock;
498 }
499
500 eth_dev = eth_dev_get(port_id);
501 strlcpy(eth_dev->data->name, name, sizeof(eth_dev->data->name));
502 eth_dev->data->port_id = port_id;
503 eth_dev->data->mtu = ETHER_MTU;
504
505 unlock:
506 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
507
508 return eth_dev;
509 }
510
511 /*
512 * Attach to a port already registered by the primary process, which
513 * makes sure that the same device would have the same port id both
514 * in the primary and secondary process.
515 */
516 struct rte_eth_dev *
517 rte_eth_dev_attach_secondary(const char *name)
518 {
519 uint16_t i;
520 struct rte_eth_dev *eth_dev = NULL;
521
522 rte_eth_dev_shared_data_prepare();
523
524 /* Synchronize port attachment to primary port creation and release. */
525 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
526
527 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
528 if (strcmp(rte_eth_dev_shared_data->data[i].name, name) == 0)
529 break;
530 }
531 if (i == RTE_MAX_ETHPORTS) {
532 RTE_ETHDEV_LOG(ERR,
533 "Device %s is not driven by the primary process\n",
534 name);
535 } else {
536 eth_dev = eth_dev_get(i);
537 RTE_ASSERT(eth_dev->data->port_id == i);
538 }
539
540 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
541 return eth_dev;
542 }
543
544 int
545 rte_eth_dev_release_port(struct rte_eth_dev *eth_dev)
546 {
547 if (eth_dev == NULL)
548 return -EINVAL;
549
550 rte_eth_dev_shared_data_prepare();
551
552 if (eth_dev->state != RTE_ETH_DEV_UNUSED)
553 _rte_eth_dev_callback_process(eth_dev,
554 RTE_ETH_EVENT_DESTROY, NULL);
555
556 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
557
558 eth_dev->state = RTE_ETH_DEV_UNUSED;
559
560 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
561 rte_free(eth_dev->data->rx_queues);
562 rte_free(eth_dev->data->tx_queues);
563 rte_free(eth_dev->data->mac_addrs);
564 rte_free(eth_dev->data->hash_mac_addrs);
565 rte_free(eth_dev->data->dev_private);
566 memset(eth_dev->data, 0, sizeof(struct rte_eth_dev_data));
567 }
568
569 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
570
571 return 0;
572 }
573
574 int
575 rte_eth_dev_is_valid_port(uint16_t port_id)
576 {
577 if (port_id >= RTE_MAX_ETHPORTS ||
578 (rte_eth_devices[port_id].state == RTE_ETH_DEV_UNUSED))
579 return 0;
580 else
581 return 1;
582 }
583
584 static int
585 rte_eth_is_valid_owner_id(uint64_t owner_id)
586 {
587 if (owner_id == RTE_ETH_DEV_NO_OWNER ||
588 rte_eth_dev_shared_data->next_owner_id <= owner_id)
589 return 0;
590 return 1;
591 }
592
593 uint64_t
594 rte_eth_find_next_owned_by(uint16_t port_id, const uint64_t owner_id)
595 {
596 port_id = rte_eth_find_next(port_id);
597 while (port_id < RTE_MAX_ETHPORTS &&
598 rte_eth_devices[port_id].data->owner.id != owner_id)
599 port_id = rte_eth_find_next(port_id + 1);
600
601 return port_id;
602 }
603
604 int __rte_experimental
605 rte_eth_dev_owner_new(uint64_t *owner_id)
606 {
607 rte_eth_dev_shared_data_prepare();
608
609 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
610
611 *owner_id = rte_eth_dev_shared_data->next_owner_id++;
612
613 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
614 return 0;
615 }
616
617 static int
618 _rte_eth_dev_owner_set(const uint16_t port_id, const uint64_t old_owner_id,
619 const struct rte_eth_dev_owner *new_owner)
620 {
621 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id];
622 struct rte_eth_dev_owner *port_owner;
623
624 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) {
625 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n",
626 port_id);
627 return -ENODEV;
628 }
629
630 if (!rte_eth_is_valid_owner_id(new_owner->id) &&
631 !rte_eth_is_valid_owner_id(old_owner_id)) {
632 RTE_ETHDEV_LOG(ERR,
633 "Invalid owner old_id=%016"PRIx64" new_id=%016"PRIx64"\n",
634 old_owner_id, new_owner->id);
635 return -EINVAL;
636 }
637
638 port_owner = &rte_eth_devices[port_id].data->owner;
639 if (port_owner->id != old_owner_id) {
640 RTE_ETHDEV_LOG(ERR,
641 "Cannot set owner to port %u already owned by %s_%016"PRIX64"\n",
642 port_id, port_owner->name, port_owner->id);
643 return -EPERM;
644 }
645
646 /* can not truncate (same structure) */
647 strlcpy(port_owner->name, new_owner->name, RTE_ETH_MAX_OWNER_NAME_LEN);
648
649 port_owner->id = new_owner->id;
650
651 RTE_ETHDEV_LOG(DEBUG, "Port %u owner is %s_%016"PRIx64"\n",
652 port_id, new_owner->name, new_owner->id);
653
654 return 0;
655 }
656
657 int __rte_experimental
658 rte_eth_dev_owner_set(const uint16_t port_id,
659 const struct rte_eth_dev_owner *owner)
660 {
661 int ret;
662
663 rte_eth_dev_shared_data_prepare();
664
665 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
666
667 ret = _rte_eth_dev_owner_set(port_id, RTE_ETH_DEV_NO_OWNER, owner);
668
669 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
670 return ret;
671 }
672
673 int __rte_experimental
674 rte_eth_dev_owner_unset(const uint16_t port_id, const uint64_t owner_id)
675 {
676 const struct rte_eth_dev_owner new_owner = (struct rte_eth_dev_owner)
677 {.id = RTE_ETH_DEV_NO_OWNER, .name = ""};
678 int ret;
679
680 rte_eth_dev_shared_data_prepare();
681
682 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
683
684 ret = _rte_eth_dev_owner_set(port_id, owner_id, &new_owner);
685
686 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
687 return ret;
688 }
689
690 void __rte_experimental
691 rte_eth_dev_owner_delete(const uint64_t owner_id)
692 {
693 uint16_t port_id;
694
695 rte_eth_dev_shared_data_prepare();
696
697 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
698
699 if (rte_eth_is_valid_owner_id(owner_id)) {
700 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++)
701 if (rte_eth_devices[port_id].data->owner.id == owner_id)
702 memset(&rte_eth_devices[port_id].data->owner, 0,
703 sizeof(struct rte_eth_dev_owner));
704 RTE_ETHDEV_LOG(NOTICE,
705 "All port owners owned by %016"PRIx64" identifier have removed\n",
706 owner_id);
707 } else {
708 RTE_ETHDEV_LOG(ERR,
709 "Invalid owner id=%016"PRIx64"\n",
710 owner_id);
711 }
712
713 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
714 }
715
716 int __rte_experimental
717 rte_eth_dev_owner_get(const uint16_t port_id, struct rte_eth_dev_owner *owner)
718 {
719 int ret = 0;
720 struct rte_eth_dev *ethdev = &rte_eth_devices[port_id];
721
722 rte_eth_dev_shared_data_prepare();
723
724 rte_spinlock_lock(&rte_eth_dev_shared_data->ownership_lock);
725
726 if (port_id >= RTE_MAX_ETHPORTS || !is_allocated(ethdev)) {
727 RTE_ETHDEV_LOG(ERR, "Port id %"PRIu16" is not allocated\n",
728 port_id);
729 ret = -ENODEV;
730 } else {
731 rte_memcpy(owner, &ethdev->data->owner, sizeof(*owner));
732 }
733
734 rte_spinlock_unlock(&rte_eth_dev_shared_data->ownership_lock);
735 return ret;
736 }
737
738 int
739 rte_eth_dev_socket_id(uint16_t port_id)
740 {
741 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1);
742 return rte_eth_devices[port_id].data->numa_node;
743 }
744
745 void *
746 rte_eth_dev_get_sec_ctx(uint16_t port_id)
747 {
748 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, NULL);
749 return rte_eth_devices[port_id].security_ctx;
750 }
751
752 uint16_t
753 rte_eth_dev_count(void)
754 {
755 return rte_eth_dev_count_avail();
756 }
757
758 uint16_t
759 rte_eth_dev_count_avail(void)
760 {
761 uint16_t p;
762 uint16_t count;
763
764 count = 0;
765
766 RTE_ETH_FOREACH_DEV(p)
767 count++;
768
769 return count;
770 }
771
772 uint16_t
773 rte_eth_dev_count_total(void)
774 {
775 uint16_t port, count = 0;
776
777 RTE_ETH_FOREACH_VALID_DEV(port)
778 count++;
779
780 return count;
781 }
782
783 int
784 rte_eth_dev_get_name_by_port(uint16_t port_id, char *name)
785 {
786 char *tmp;
787
788 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
789
790 if (name == NULL) {
791 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n");
792 return -EINVAL;
793 }
794
795 /* shouldn't check 'rte_eth_devices[i].data',
796 * because it might be overwritten by VDEV PMD */
797 tmp = rte_eth_dev_shared_data->data[port_id].name;
798 strcpy(name, tmp);
799 return 0;
800 }
801
802 int
803 rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id)
804 {
805 uint32_t pid;
806
807 if (name == NULL) {
808 RTE_ETHDEV_LOG(ERR, "Null pointer is specified\n");
809 return -EINVAL;
810 }
811
812 RTE_ETH_FOREACH_VALID_DEV(pid)
813 if (!strcmp(name, rte_eth_dev_shared_data->data[pid].name)) {
814 *port_id = pid;
815 return 0;
816 }
817
818 return -ENODEV;
819 }
820
821 static int
822 eth_err(uint16_t port_id, int ret)
823 {
824 if (ret == 0)
825 return 0;
826 if (rte_eth_dev_is_removed(port_id))
827 return -EIO;
828 return ret;
829 }
830
831 static int
832 rte_eth_dev_rx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)
833 {
834 uint16_t old_nb_queues = dev->data->nb_rx_queues;
835 void **rxq;
836 unsigned i;
837
838 if (dev->data->rx_queues == NULL && nb_queues != 0) { /* first time configuration */
839 dev->data->rx_queues = rte_zmalloc("ethdev->rx_queues",
840 sizeof(dev->data->rx_queues[0]) * nb_queues,
841 RTE_CACHE_LINE_SIZE);
842 if (dev->data->rx_queues == NULL) {
843 dev->data->nb_rx_queues = 0;
844 return -(ENOMEM);
845 }
846 } else if (dev->data->rx_queues != NULL && nb_queues != 0) { /* re-configure */
847 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP);
848
849 rxq = dev->data->rx_queues;
850
851 for (i = nb_queues; i < old_nb_queues; i++)
852 (*dev->dev_ops->rx_queue_release)(rxq[i]);
853 rxq = rte_realloc(rxq, sizeof(rxq[0]) * nb_queues,
854 RTE_CACHE_LINE_SIZE);
855 if (rxq == NULL)
856 return -(ENOMEM);
857 if (nb_queues > old_nb_queues) {
858 uint16_t new_qs = nb_queues - old_nb_queues;
859
860 memset(rxq + old_nb_queues, 0,
861 sizeof(rxq[0]) * new_qs);
862 }
863
864 dev->data->rx_queues = rxq;
865
866 } else if (dev->data->rx_queues != NULL && nb_queues == 0) {
867 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release, -ENOTSUP);
868
869 rxq = dev->data->rx_queues;
870
871 for (i = nb_queues; i < old_nb_queues; i++)
872 (*dev->dev_ops->rx_queue_release)(rxq[i]);
873
874 rte_free(dev->data->rx_queues);
875 dev->data->rx_queues = NULL;
876 }
877 dev->data->nb_rx_queues = nb_queues;
878 return 0;
879 }
880
881 int
882 rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id)
883 {
884 struct rte_eth_dev *dev;
885
886 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
887
888 dev = &rte_eth_devices[port_id];
889 if (!dev->data->dev_started) {
890 RTE_ETHDEV_LOG(ERR,
891 "Port %u must be started before start any queue\n",
892 port_id);
893 return -EINVAL;
894 }
895
896 if (rx_queue_id >= dev->data->nb_rx_queues) {
897 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
898 return -EINVAL;
899 }
900
901 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_start, -ENOTSUP);
902
903 if (dev->data->rx_queue_state[rx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
904 RTE_ETHDEV_LOG(INFO,
905 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
906 rx_queue_id, port_id);
907 return 0;
908 }
909
910 return eth_err(port_id, dev->dev_ops->rx_queue_start(dev,
911 rx_queue_id));
912
913 }
914
915 int
916 rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id)
917 {
918 struct rte_eth_dev *dev;
919
920 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
921
922 dev = &rte_eth_devices[port_id];
923 if (rx_queue_id >= dev->data->nb_rx_queues) {
924 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
925 return -EINVAL;
926 }
927
928 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_stop, -ENOTSUP);
929
930 if (dev->data->rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
931 RTE_ETHDEV_LOG(INFO,
932 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
933 rx_queue_id, port_id);
934 return 0;
935 }
936
937 return eth_err(port_id, dev->dev_ops->rx_queue_stop(dev, rx_queue_id));
938
939 }
940
941 int
942 rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id)
943 {
944 struct rte_eth_dev *dev;
945
946 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
947
948 dev = &rte_eth_devices[port_id];
949 if (!dev->data->dev_started) {
950 RTE_ETHDEV_LOG(ERR,
951 "Port %u must be started before start any queue\n",
952 port_id);
953 return -EINVAL;
954 }
955
956 if (tx_queue_id >= dev->data->nb_tx_queues) {
957 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
958 return -EINVAL;
959 }
960
961 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_start, -ENOTSUP);
962
963 if (dev->data->tx_queue_state[tx_queue_id] != RTE_ETH_QUEUE_STATE_STOPPED) {
964 RTE_ETHDEV_LOG(INFO,
965 "Queue %"PRIu16" of device with port_id=%"PRIu16" already started\n",
966 tx_queue_id, port_id);
967 return 0;
968 }
969
970 return eth_err(port_id, dev->dev_ops->tx_queue_start(dev, tx_queue_id));
971 }
972
973 int
974 rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id)
975 {
976 struct rte_eth_dev *dev;
977
978 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
979
980 dev = &rte_eth_devices[port_id];
981 if (tx_queue_id >= dev->data->nb_tx_queues) {
982 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
983 return -EINVAL;
984 }
985
986 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_stop, -ENOTSUP);
987
988 if (dev->data->tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STOPPED) {
989 RTE_ETHDEV_LOG(INFO,
990 "Queue %"PRIu16" of device with port_id=%"PRIu16" already stopped\n",
991 tx_queue_id, port_id);
992 return 0;
993 }
994
995 return eth_err(port_id, dev->dev_ops->tx_queue_stop(dev, tx_queue_id));
996
997 }
998
999 static int
1000 rte_eth_dev_tx_queue_config(struct rte_eth_dev *dev, uint16_t nb_queues)
1001 {
1002 uint16_t old_nb_queues = dev->data->nb_tx_queues;
1003 void **txq;
1004 unsigned i;
1005
1006 if (dev->data->tx_queues == NULL && nb_queues != 0) { /* first time configuration */
1007 dev->data->tx_queues = rte_zmalloc("ethdev->tx_queues",
1008 sizeof(dev->data->tx_queues[0]) * nb_queues,
1009 RTE_CACHE_LINE_SIZE);
1010 if (dev->data->tx_queues == NULL) {
1011 dev->data->nb_tx_queues = 0;
1012 return -(ENOMEM);
1013 }
1014 } else if (dev->data->tx_queues != NULL && nb_queues != 0) { /* re-configure */
1015 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP);
1016
1017 txq = dev->data->tx_queues;
1018
1019 for (i = nb_queues; i < old_nb_queues; i++)
1020 (*dev->dev_ops->tx_queue_release)(txq[i]);
1021 txq = rte_realloc(txq, sizeof(txq[0]) * nb_queues,
1022 RTE_CACHE_LINE_SIZE);
1023 if (txq == NULL)
1024 return -ENOMEM;
1025 if (nb_queues > old_nb_queues) {
1026 uint16_t new_qs = nb_queues - old_nb_queues;
1027
1028 memset(txq + old_nb_queues, 0,
1029 sizeof(txq[0]) * new_qs);
1030 }
1031
1032 dev->data->tx_queues = txq;
1033
1034 } else if (dev->data->tx_queues != NULL && nb_queues == 0) {
1035 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release, -ENOTSUP);
1036
1037 txq = dev->data->tx_queues;
1038
1039 for (i = nb_queues; i < old_nb_queues; i++)
1040 (*dev->dev_ops->tx_queue_release)(txq[i]);
1041
1042 rte_free(dev->data->tx_queues);
1043 dev->data->tx_queues = NULL;
1044 }
1045 dev->data->nb_tx_queues = nb_queues;
1046 return 0;
1047 }
1048
1049 uint32_t
1050 rte_eth_speed_bitflag(uint32_t speed, int duplex)
1051 {
1052 switch (speed) {
1053 case ETH_SPEED_NUM_10M:
1054 return duplex ? ETH_LINK_SPEED_10M : ETH_LINK_SPEED_10M_HD;
1055 case ETH_SPEED_NUM_100M:
1056 return duplex ? ETH_LINK_SPEED_100M : ETH_LINK_SPEED_100M_HD;
1057 case ETH_SPEED_NUM_1G:
1058 return ETH_LINK_SPEED_1G;
1059 case ETH_SPEED_NUM_2_5G:
1060 return ETH_LINK_SPEED_2_5G;
1061 case ETH_SPEED_NUM_5G:
1062 return ETH_LINK_SPEED_5G;
1063 case ETH_SPEED_NUM_10G:
1064 return ETH_LINK_SPEED_10G;
1065 case ETH_SPEED_NUM_20G:
1066 return ETH_LINK_SPEED_20G;
1067 case ETH_SPEED_NUM_25G:
1068 return ETH_LINK_SPEED_25G;
1069 case ETH_SPEED_NUM_40G:
1070 return ETH_LINK_SPEED_40G;
1071 case ETH_SPEED_NUM_50G:
1072 return ETH_LINK_SPEED_50G;
1073 case ETH_SPEED_NUM_56G:
1074 return ETH_LINK_SPEED_56G;
1075 case ETH_SPEED_NUM_100G:
1076 return ETH_LINK_SPEED_100G;
1077 default:
1078 return 0;
1079 }
1080 }
1081
1082 const char *
1083 rte_eth_dev_rx_offload_name(uint64_t offload)
1084 {
1085 const char *name = "UNKNOWN";
1086 unsigned int i;
1087
1088 for (i = 0; i < RTE_DIM(rte_rx_offload_names); ++i) {
1089 if (offload == rte_rx_offload_names[i].offload) {
1090 name = rte_rx_offload_names[i].name;
1091 break;
1092 }
1093 }
1094
1095 return name;
1096 }
1097
1098 const char *
1099 rte_eth_dev_tx_offload_name(uint64_t offload)
1100 {
1101 const char *name = "UNKNOWN";
1102 unsigned int i;
1103
1104 for (i = 0; i < RTE_DIM(rte_tx_offload_names); ++i) {
1105 if (offload == rte_tx_offload_names[i].offload) {
1106 name = rte_tx_offload_names[i].name;
1107 break;
1108 }
1109 }
1110
1111 return name;
1112 }
1113
1114 int
1115 rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_q, uint16_t nb_tx_q,
1116 const struct rte_eth_conf *dev_conf)
1117 {
1118 struct rte_eth_dev *dev;
1119 struct rte_eth_dev_info dev_info;
1120 struct rte_eth_conf orig_conf;
1121 int diag;
1122 int ret;
1123
1124 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1125
1126 dev = &rte_eth_devices[port_id];
1127
1128 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);
1129 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_configure, -ENOTSUP);
1130
1131 if (dev->data->dev_started) {
1132 RTE_ETHDEV_LOG(ERR,
1133 "Port %u must be stopped to allow configuration\n",
1134 port_id);
1135 return -EBUSY;
1136 }
1137
1138 /* Store original config, as rollback required on failure */
1139 memcpy(&orig_conf, &dev->data->dev_conf, sizeof(dev->data->dev_conf));
1140
1141 /*
1142 * Copy the dev_conf parameter into the dev structure.
1143 * rte_eth_dev_info_get() requires dev_conf, copy it before dev_info get
1144 */
1145 memcpy(&dev->data->dev_conf, dev_conf, sizeof(dev->data->dev_conf));
1146
1147 rte_eth_dev_info_get(port_id, &dev_info);
1148
1149 /* If number of queues specified by application for both Rx and Tx is
1150 * zero, use driver preferred values. This cannot be done individually
1151 * as it is valid for either Tx or Rx (but not both) to be zero.
1152 * If driver does not provide any preferred valued, fall back on
1153 * EAL defaults.
1154 */
1155 if (nb_rx_q == 0 && nb_tx_q == 0) {
1156 nb_rx_q = dev_info.default_rxportconf.nb_queues;
1157 if (nb_rx_q == 0)
1158 nb_rx_q = RTE_ETH_DEV_FALLBACK_RX_NBQUEUES;
1159 nb_tx_q = dev_info.default_txportconf.nb_queues;
1160 if (nb_tx_q == 0)
1161 nb_tx_q = RTE_ETH_DEV_FALLBACK_TX_NBQUEUES;
1162 }
1163
1164 if (nb_rx_q > RTE_MAX_QUEUES_PER_PORT) {
1165 RTE_ETHDEV_LOG(ERR,
1166 "Number of RX queues requested (%u) is greater than max supported(%d)\n",
1167 nb_rx_q, RTE_MAX_QUEUES_PER_PORT);
1168 ret = -EINVAL;
1169 goto rollback;
1170 }
1171
1172 if (nb_tx_q > RTE_MAX_QUEUES_PER_PORT) {
1173 RTE_ETHDEV_LOG(ERR,
1174 "Number of TX queues requested (%u) is greater than max supported(%d)\n",
1175 nb_tx_q, RTE_MAX_QUEUES_PER_PORT);
1176 ret = -EINVAL;
1177 goto rollback;
1178 }
1179
1180 /*
1181 * Check that the numbers of RX and TX queues are not greater
1182 * than the maximum number of RX and TX queues supported by the
1183 * configured device.
1184 */
1185 if (nb_rx_q > dev_info.max_rx_queues) {
1186 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_rx_queues=%u > %u\n",
1187 port_id, nb_rx_q, dev_info.max_rx_queues);
1188 ret = -EINVAL;
1189 goto rollback;
1190 }
1191
1192 if (nb_tx_q > dev_info.max_tx_queues) {
1193 RTE_ETHDEV_LOG(ERR, "Ethdev port_id=%u nb_tx_queues=%u > %u\n",
1194 port_id, nb_tx_q, dev_info.max_tx_queues);
1195 ret = -EINVAL;
1196 goto rollback;
1197 }
1198
1199 /* Check that the device supports requested interrupts */
1200 if ((dev_conf->intr_conf.lsc == 1) &&
1201 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC))) {
1202 RTE_ETHDEV_LOG(ERR, "Driver %s does not support lsc\n",
1203 dev->device->driver->name);
1204 ret = -EINVAL;
1205 goto rollback;
1206 }
1207 if ((dev_conf->intr_conf.rmv == 1) &&
1208 (!(dev->data->dev_flags & RTE_ETH_DEV_INTR_RMV))) {
1209 RTE_ETHDEV_LOG(ERR, "Driver %s does not support rmv\n",
1210 dev->device->driver->name);
1211 ret = -EINVAL;
1212 goto rollback;
1213 }
1214
1215 /*
1216 * If jumbo frames are enabled, check that the maximum RX packet
1217 * length is supported by the configured device.
1218 */
1219 if (dev_conf->rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
1220 if (dev_conf->rxmode.max_rx_pkt_len > dev_info.max_rx_pktlen) {
1221 RTE_ETHDEV_LOG(ERR,
1222 "Ethdev port_id=%u max_rx_pkt_len %u > max valid value %u\n",
1223 port_id, dev_conf->rxmode.max_rx_pkt_len,
1224 dev_info.max_rx_pktlen);
1225 ret = -EINVAL;
1226 goto rollback;
1227 } else if (dev_conf->rxmode.max_rx_pkt_len < ETHER_MIN_LEN) {
1228 RTE_ETHDEV_LOG(ERR,
1229 "Ethdev port_id=%u max_rx_pkt_len %u < min valid value %u\n",
1230 port_id, dev_conf->rxmode.max_rx_pkt_len,
1231 (unsigned)ETHER_MIN_LEN);
1232 ret = -EINVAL;
1233 goto rollback;
1234 }
1235 } else {
1236 if (dev_conf->rxmode.max_rx_pkt_len < ETHER_MIN_LEN ||
1237 dev_conf->rxmode.max_rx_pkt_len > ETHER_MAX_LEN)
1238 /* Use default value */
1239 dev->data->dev_conf.rxmode.max_rx_pkt_len =
1240 ETHER_MAX_LEN;
1241 }
1242
1243 /* Any requested offloading must be within its device capabilities */
1244 if ((dev_conf->rxmode.offloads & dev_info.rx_offload_capa) !=
1245 dev_conf->rxmode.offloads) {
1246 RTE_ETHDEV_LOG(ERR,
1247 "Ethdev port_id=%u requested Rx offloads 0x%"PRIx64" doesn't match Rx offloads "
1248 "capabilities 0x%"PRIx64" in %s()\n",
1249 port_id, dev_conf->rxmode.offloads,
1250 dev_info.rx_offload_capa,
1251 __func__);
1252 ret = -EINVAL;
1253 goto rollback;
1254 }
1255 if ((dev_conf->txmode.offloads & dev_info.tx_offload_capa) !=
1256 dev_conf->txmode.offloads) {
1257 RTE_ETHDEV_LOG(ERR,
1258 "Ethdev port_id=%u requested Tx offloads 0x%"PRIx64" doesn't match Tx offloads "
1259 "capabilities 0x%"PRIx64" in %s()\n",
1260 port_id, dev_conf->txmode.offloads,
1261 dev_info.tx_offload_capa,
1262 __func__);
1263 ret = -EINVAL;
1264 goto rollback;
1265 }
1266
1267 /* Check that device supports requested rss hash functions. */
1268 if ((dev_info.flow_type_rss_offloads |
1269 dev_conf->rx_adv_conf.rss_conf.rss_hf) !=
1270 dev_info.flow_type_rss_offloads) {
1271 RTE_ETHDEV_LOG(ERR,
1272 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n",
1273 port_id, dev_conf->rx_adv_conf.rss_conf.rss_hf,
1274 dev_info.flow_type_rss_offloads);
1275 ret = -EINVAL;
1276 goto rollback;
1277 }
1278
1279 /*
1280 * Setup new number of RX/TX queues and reconfigure device.
1281 */
1282 diag = rte_eth_dev_rx_queue_config(dev, nb_rx_q);
1283 if (diag != 0) {
1284 RTE_ETHDEV_LOG(ERR,
1285 "Port%u rte_eth_dev_rx_queue_config = %d\n",
1286 port_id, diag);
1287 ret = diag;
1288 goto rollback;
1289 }
1290
1291 diag = rte_eth_dev_tx_queue_config(dev, nb_tx_q);
1292 if (diag != 0) {
1293 RTE_ETHDEV_LOG(ERR,
1294 "Port%u rte_eth_dev_tx_queue_config = %d\n",
1295 port_id, diag);
1296 rte_eth_dev_rx_queue_config(dev, 0);
1297 ret = diag;
1298 goto rollback;
1299 }
1300
1301 diag = (*dev->dev_ops->dev_configure)(dev);
1302 if (diag != 0) {
1303 RTE_ETHDEV_LOG(ERR, "Port%u dev_configure = %d\n",
1304 port_id, diag);
1305 rte_eth_dev_rx_queue_config(dev, 0);
1306 rte_eth_dev_tx_queue_config(dev, 0);
1307 ret = eth_err(port_id, diag);
1308 goto rollback;
1309 }
1310
1311 /* Initialize Rx profiling if enabled at compilation time. */
1312 diag = __rte_eth_dev_profile_init(port_id, dev);
1313 if (diag != 0) {
1314 RTE_ETHDEV_LOG(ERR, "Port%u __rte_eth_dev_profile_init = %d\n",
1315 port_id, diag);
1316 rte_eth_dev_rx_queue_config(dev, 0);
1317 rte_eth_dev_tx_queue_config(dev, 0);
1318 ret = eth_err(port_id, diag);
1319 goto rollback;
1320 }
1321
1322 return 0;
1323
1324 rollback:
1325 memcpy(&dev->data->dev_conf, &orig_conf, sizeof(dev->data->dev_conf));
1326
1327 return ret;
1328 }
1329
1330 void
1331 _rte_eth_dev_reset(struct rte_eth_dev *dev)
1332 {
1333 if (dev->data->dev_started) {
1334 RTE_ETHDEV_LOG(ERR, "Port %u must be stopped to allow reset\n",
1335 dev->data->port_id);
1336 return;
1337 }
1338
1339 rte_eth_dev_rx_queue_config(dev, 0);
1340 rte_eth_dev_tx_queue_config(dev, 0);
1341
1342 memset(&dev->data->dev_conf, 0, sizeof(dev->data->dev_conf));
1343 }
1344
1345 static void
1346 rte_eth_dev_mac_restore(struct rte_eth_dev *dev,
1347 struct rte_eth_dev_info *dev_info)
1348 {
1349 struct ether_addr *addr;
1350 uint16_t i;
1351 uint32_t pool = 0;
1352 uint64_t pool_mask;
1353
1354 /* replay MAC address configuration including default MAC */
1355 addr = &dev->data->mac_addrs[0];
1356 if (*dev->dev_ops->mac_addr_set != NULL)
1357 (*dev->dev_ops->mac_addr_set)(dev, addr);
1358 else if (*dev->dev_ops->mac_addr_add != NULL)
1359 (*dev->dev_ops->mac_addr_add)(dev, addr, 0, pool);
1360
1361 if (*dev->dev_ops->mac_addr_add != NULL) {
1362 for (i = 1; i < dev_info->max_mac_addrs; i++) {
1363 addr = &dev->data->mac_addrs[i];
1364
1365 /* skip zero address */
1366 if (is_zero_ether_addr(addr))
1367 continue;
1368
1369 pool = 0;
1370 pool_mask = dev->data->mac_pool_sel[i];
1371
1372 do {
1373 if (pool_mask & 1ULL)
1374 (*dev->dev_ops->mac_addr_add)(dev,
1375 addr, i, pool);
1376 pool_mask >>= 1;
1377 pool++;
1378 } while (pool_mask);
1379 }
1380 }
1381 }
1382
1383 static void
1384 rte_eth_dev_config_restore(struct rte_eth_dev *dev,
1385 struct rte_eth_dev_info *dev_info, uint16_t port_id)
1386 {
1387 if (!(*dev_info->dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR))
1388 rte_eth_dev_mac_restore(dev, dev_info);
1389
1390 /* replay promiscuous configuration */
1391 if (rte_eth_promiscuous_get(port_id) == 1)
1392 rte_eth_promiscuous_enable(port_id);
1393 else if (rte_eth_promiscuous_get(port_id) == 0)
1394 rte_eth_promiscuous_disable(port_id);
1395
1396 /* replay all multicast configuration */
1397 if (rte_eth_allmulticast_get(port_id) == 1)
1398 rte_eth_allmulticast_enable(port_id);
1399 else if (rte_eth_allmulticast_get(port_id) == 0)
1400 rte_eth_allmulticast_disable(port_id);
1401 }
1402
1403 int
1404 rte_eth_dev_start(uint16_t port_id)
1405 {
1406 struct rte_eth_dev *dev;
1407 struct rte_eth_dev_info dev_info;
1408 int diag;
1409
1410 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1411
1412 dev = &rte_eth_devices[port_id];
1413
1414 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_start, -ENOTSUP);
1415
1416 if (dev->data->dev_started != 0) {
1417 RTE_ETHDEV_LOG(INFO,
1418 "Device with port_id=%"PRIu16" already started\n",
1419 port_id);
1420 return 0;
1421 }
1422
1423 rte_eth_dev_info_get(port_id, &dev_info);
1424
1425 /* Lets restore MAC now if device does not support live change */
1426 if (*dev_info.dev_flags & RTE_ETH_DEV_NOLIVE_MAC_ADDR)
1427 rte_eth_dev_mac_restore(dev, &dev_info);
1428
1429 diag = (*dev->dev_ops->dev_start)(dev);
1430 if (diag == 0)
1431 dev->data->dev_started = 1;
1432 else
1433 return eth_err(port_id, diag);
1434
1435 rte_eth_dev_config_restore(dev, &dev_info, port_id);
1436
1437 if (dev->data->dev_conf.intr_conf.lsc == 0) {
1438 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->link_update, -ENOTSUP);
1439 (*dev->dev_ops->link_update)(dev, 0);
1440 }
1441 return 0;
1442 }
1443
1444 void
1445 rte_eth_dev_stop(uint16_t port_id)
1446 {
1447 struct rte_eth_dev *dev;
1448
1449 RTE_ETH_VALID_PORTID_OR_RET(port_id);
1450 dev = &rte_eth_devices[port_id];
1451
1452 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->dev_stop);
1453
1454 if (dev->data->dev_started == 0) {
1455 RTE_ETHDEV_LOG(INFO,
1456 "Device with port_id=%"PRIu16" already stopped\n",
1457 port_id);
1458 return;
1459 }
1460
1461 dev->data->dev_started = 0;
1462 (*dev->dev_ops->dev_stop)(dev);
1463 }
1464
1465 int
1466 rte_eth_dev_set_link_up(uint16_t port_id)
1467 {
1468 struct rte_eth_dev *dev;
1469
1470 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1471
1472 dev = &rte_eth_devices[port_id];
1473
1474 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_up, -ENOTSUP);
1475 return eth_err(port_id, (*dev->dev_ops->dev_set_link_up)(dev));
1476 }
1477
1478 int
1479 rte_eth_dev_set_link_down(uint16_t port_id)
1480 {
1481 struct rte_eth_dev *dev;
1482
1483 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1484
1485 dev = &rte_eth_devices[port_id];
1486
1487 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_set_link_down, -ENOTSUP);
1488 return eth_err(port_id, (*dev->dev_ops->dev_set_link_down)(dev));
1489 }
1490
1491 void
1492 rte_eth_dev_close(uint16_t port_id)
1493 {
1494 struct rte_eth_dev *dev;
1495
1496 RTE_ETH_VALID_PORTID_OR_RET(port_id);
1497 dev = &rte_eth_devices[port_id];
1498
1499 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->dev_close);
1500 dev->data->dev_started = 0;
1501 (*dev->dev_ops->dev_close)(dev);
1502
1503 /* check behaviour flag - temporary for PMD migration */
1504 if ((dev->data->dev_flags & RTE_ETH_DEV_CLOSE_REMOVE) != 0) {
1505 /* new behaviour: send event + reset state + free all data */
1506 rte_eth_dev_release_port(dev);
1507 return;
1508 }
1509 RTE_ETHDEV_LOG(DEBUG, "Port closing is using an old behaviour.\n"
1510 "The driver %s should migrate to the new behaviour.\n",
1511 dev->device->driver->name);
1512 /* old behaviour: only free queue arrays */
1513 dev->data->nb_rx_queues = 0;
1514 rte_free(dev->data->rx_queues);
1515 dev->data->rx_queues = NULL;
1516 dev->data->nb_tx_queues = 0;
1517 rte_free(dev->data->tx_queues);
1518 dev->data->tx_queues = NULL;
1519 }
1520
1521 int
1522 rte_eth_dev_reset(uint16_t port_id)
1523 {
1524 struct rte_eth_dev *dev;
1525 int ret;
1526
1527 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1528 dev = &rte_eth_devices[port_id];
1529
1530 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_reset, -ENOTSUP);
1531
1532 rte_eth_dev_stop(port_id);
1533 ret = dev->dev_ops->dev_reset(dev);
1534
1535 return eth_err(port_id, ret);
1536 }
1537
1538 int __rte_experimental
1539 rte_eth_dev_is_removed(uint16_t port_id)
1540 {
1541 struct rte_eth_dev *dev;
1542 int ret;
1543
1544 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
1545
1546 dev = &rte_eth_devices[port_id];
1547
1548 if (dev->state == RTE_ETH_DEV_REMOVED)
1549 return 1;
1550
1551 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->is_removed, 0);
1552
1553 ret = dev->dev_ops->is_removed(dev);
1554 if (ret != 0)
1555 /* Device is physically removed. */
1556 dev->state = RTE_ETH_DEV_REMOVED;
1557
1558 return ret;
1559 }
1560
1561 int
1562 rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
1563 uint16_t nb_rx_desc, unsigned int socket_id,
1564 const struct rte_eth_rxconf *rx_conf,
1565 struct rte_mempool *mp)
1566 {
1567 int ret;
1568 uint32_t mbp_buf_size;
1569 struct rte_eth_dev *dev;
1570 struct rte_eth_dev_info dev_info;
1571 struct rte_eth_rxconf local_conf;
1572 void **rxq;
1573
1574 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1575
1576 dev = &rte_eth_devices[port_id];
1577 if (rx_queue_id >= dev->data->nb_rx_queues) {
1578 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", rx_queue_id);
1579 return -EINVAL;
1580 }
1581
1582 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);
1583 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_setup, -ENOTSUP);
1584
1585 /*
1586 * Check the size of the mbuf data buffer.
1587 * This value must be provided in the private data of the memory pool.
1588 * First check that the memory pool has a valid private data.
1589 */
1590 rte_eth_dev_info_get(port_id, &dev_info);
1591 if (mp->private_data_size < sizeof(struct rte_pktmbuf_pool_private)) {
1592 RTE_ETHDEV_LOG(ERR, "%s private_data_size %d < %d\n",
1593 mp->name, (int)mp->private_data_size,
1594 (int)sizeof(struct rte_pktmbuf_pool_private));
1595 return -ENOSPC;
1596 }
1597 mbp_buf_size = rte_pktmbuf_data_room_size(mp);
1598
1599 if ((mbp_buf_size - RTE_PKTMBUF_HEADROOM) < dev_info.min_rx_bufsize) {
1600 RTE_ETHDEV_LOG(ERR,
1601 "%s mbuf_data_room_size %d < %d (RTE_PKTMBUF_HEADROOM=%d + min_rx_bufsize(dev)=%d)\n",
1602 mp->name, (int)mbp_buf_size,
1603 (int)(RTE_PKTMBUF_HEADROOM + dev_info.min_rx_bufsize),
1604 (int)RTE_PKTMBUF_HEADROOM,
1605 (int)dev_info.min_rx_bufsize);
1606 return -EINVAL;
1607 }
1608
1609 /* Use default specified by driver, if nb_rx_desc is zero */
1610 if (nb_rx_desc == 0) {
1611 nb_rx_desc = dev_info.default_rxportconf.ring_size;
1612 /* If driver default is also zero, fall back on EAL default */
1613 if (nb_rx_desc == 0)
1614 nb_rx_desc = RTE_ETH_DEV_FALLBACK_RX_RINGSIZE;
1615 }
1616
1617 if (nb_rx_desc > dev_info.rx_desc_lim.nb_max ||
1618 nb_rx_desc < dev_info.rx_desc_lim.nb_min ||
1619 nb_rx_desc % dev_info.rx_desc_lim.nb_align != 0) {
1620
1621 RTE_ETHDEV_LOG(ERR,
1622 "Invalid value for nb_rx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n",
1623 nb_rx_desc, dev_info.rx_desc_lim.nb_max,
1624 dev_info.rx_desc_lim.nb_min,
1625 dev_info.rx_desc_lim.nb_align);
1626 return -EINVAL;
1627 }
1628
1629 if (dev->data->dev_started &&
1630 !(dev_info.dev_capa &
1631 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP))
1632 return -EBUSY;
1633
1634 if (dev->data->dev_started &&
1635 (dev->data->rx_queue_state[rx_queue_id] !=
1636 RTE_ETH_QUEUE_STATE_STOPPED))
1637 return -EBUSY;
1638
1639 rxq = dev->data->rx_queues;
1640 if (rxq[rx_queue_id]) {
1641 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_release,
1642 -ENOTSUP);
1643 (*dev->dev_ops->rx_queue_release)(rxq[rx_queue_id]);
1644 rxq[rx_queue_id] = NULL;
1645 }
1646
1647 if (rx_conf == NULL)
1648 rx_conf = &dev_info.default_rxconf;
1649
1650 local_conf = *rx_conf;
1651
1652 /*
1653 * If an offloading has already been enabled in
1654 * rte_eth_dev_configure(), it has been enabled on all queues,
1655 * so there is no need to enable it in this queue again.
1656 * The local_conf.offloads input to underlying PMD only carries
1657 * those offloadings which are only enabled on this queue and
1658 * not enabled on all queues.
1659 */
1660 local_conf.offloads &= ~dev->data->dev_conf.rxmode.offloads;
1661
1662 /*
1663 * New added offloadings for this queue are those not enabled in
1664 * rte_eth_dev_configure() and they must be per-queue type.
1665 * A pure per-port offloading can't be enabled on a queue while
1666 * disabled on another queue. A pure per-port offloading can't
1667 * be enabled for any queue as new added one if it hasn't been
1668 * enabled in rte_eth_dev_configure().
1669 */
1670 if ((local_conf.offloads & dev_info.rx_queue_offload_capa) !=
1671 local_conf.offloads) {
1672 RTE_ETHDEV_LOG(ERR,
1673 "Ethdev port_id=%d rx_queue_id=%d, new added offloads 0x%"PRIx64" must be "
1674 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n",
1675 port_id, rx_queue_id, local_conf.offloads,
1676 dev_info.rx_queue_offload_capa,
1677 __func__);
1678 return -EINVAL;
1679 }
1680
1681 ret = (*dev->dev_ops->rx_queue_setup)(dev, rx_queue_id, nb_rx_desc,
1682 socket_id, &local_conf, mp);
1683 if (!ret) {
1684 if (!dev->data->min_rx_buf_size ||
1685 dev->data->min_rx_buf_size > mbp_buf_size)
1686 dev->data->min_rx_buf_size = mbp_buf_size;
1687 }
1688
1689 return eth_err(port_id, ret);
1690 }
1691
1692 int
1693 rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
1694 uint16_t nb_tx_desc, unsigned int socket_id,
1695 const struct rte_eth_txconf *tx_conf)
1696 {
1697 struct rte_eth_dev *dev;
1698 struct rte_eth_dev_info dev_info;
1699 struct rte_eth_txconf local_conf;
1700 void **txq;
1701
1702 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1703
1704 dev = &rte_eth_devices[port_id];
1705 if (tx_queue_id >= dev->data->nb_tx_queues) {
1706 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", tx_queue_id);
1707 return -EINVAL;
1708 }
1709
1710 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);
1711 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_setup, -ENOTSUP);
1712
1713 rte_eth_dev_info_get(port_id, &dev_info);
1714
1715 /* Use default specified by driver, if nb_tx_desc is zero */
1716 if (nb_tx_desc == 0) {
1717 nb_tx_desc = dev_info.default_txportconf.ring_size;
1718 /* If driver default is zero, fall back on EAL default */
1719 if (nb_tx_desc == 0)
1720 nb_tx_desc = RTE_ETH_DEV_FALLBACK_TX_RINGSIZE;
1721 }
1722 if (nb_tx_desc > dev_info.tx_desc_lim.nb_max ||
1723 nb_tx_desc < dev_info.tx_desc_lim.nb_min ||
1724 nb_tx_desc % dev_info.tx_desc_lim.nb_align != 0) {
1725 RTE_ETHDEV_LOG(ERR,
1726 "Invalid value for nb_tx_desc(=%hu), should be: <= %hu, >= %hu, and a product of %hu\n",
1727 nb_tx_desc, dev_info.tx_desc_lim.nb_max,
1728 dev_info.tx_desc_lim.nb_min,
1729 dev_info.tx_desc_lim.nb_align);
1730 return -EINVAL;
1731 }
1732
1733 if (dev->data->dev_started &&
1734 !(dev_info.dev_capa &
1735 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP))
1736 return -EBUSY;
1737
1738 if (dev->data->dev_started &&
1739 (dev->data->tx_queue_state[tx_queue_id] !=
1740 RTE_ETH_QUEUE_STATE_STOPPED))
1741 return -EBUSY;
1742
1743 txq = dev->data->tx_queues;
1744 if (txq[tx_queue_id]) {
1745 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_queue_release,
1746 -ENOTSUP);
1747 (*dev->dev_ops->tx_queue_release)(txq[tx_queue_id]);
1748 txq[tx_queue_id] = NULL;
1749 }
1750
1751 if (tx_conf == NULL)
1752 tx_conf = &dev_info.default_txconf;
1753
1754 local_conf = *tx_conf;
1755
1756 /*
1757 * If an offloading has already been enabled in
1758 * rte_eth_dev_configure(), it has been enabled on all queues,
1759 * so there is no need to enable it in this queue again.
1760 * The local_conf.offloads input to underlying PMD only carries
1761 * those offloadings which are only enabled on this queue and
1762 * not enabled on all queues.
1763 */
1764 local_conf.offloads &= ~dev->data->dev_conf.txmode.offloads;
1765
1766 /*
1767 * New added offloadings for this queue are those not enabled in
1768 * rte_eth_dev_configure() and they must be per-queue type.
1769 * A pure per-port offloading can't be enabled on a queue while
1770 * disabled on another queue. A pure per-port offloading can't
1771 * be enabled for any queue as new added one if it hasn't been
1772 * enabled in rte_eth_dev_configure().
1773 */
1774 if ((local_conf.offloads & dev_info.tx_queue_offload_capa) !=
1775 local_conf.offloads) {
1776 RTE_ETHDEV_LOG(ERR,
1777 "Ethdev port_id=%d tx_queue_id=%d, new added offloads 0x%"PRIx64" must be "
1778 "within per-queue offload capabilities 0x%"PRIx64" in %s()\n",
1779 port_id, tx_queue_id, local_conf.offloads,
1780 dev_info.tx_queue_offload_capa,
1781 __func__);
1782 return -EINVAL;
1783 }
1784
1785 return eth_err(port_id, (*dev->dev_ops->tx_queue_setup)(dev,
1786 tx_queue_id, nb_tx_desc, socket_id, &local_conf));
1787 }
1788
1789 void
1790 rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent,
1791 void *userdata __rte_unused)
1792 {
1793 unsigned i;
1794
1795 for (i = 0; i < unsent; i++)
1796 rte_pktmbuf_free(pkts[i]);
1797 }
1798
1799 void
1800 rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent,
1801 void *userdata)
1802 {
1803 uint64_t *count = userdata;
1804 unsigned i;
1805
1806 for (i = 0; i < unsent; i++)
1807 rte_pktmbuf_free(pkts[i]);
1808
1809 *count += unsent;
1810 }
1811
1812 int
1813 rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer,
1814 buffer_tx_error_fn cbfn, void *userdata)
1815 {
1816 buffer->error_callback = cbfn;
1817 buffer->error_userdata = userdata;
1818 return 0;
1819 }
1820
1821 int
1822 rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size)
1823 {
1824 int ret = 0;
1825
1826 if (buffer == NULL)
1827 return -EINVAL;
1828
1829 buffer->size = size;
1830 if (buffer->error_callback == NULL) {
1831 ret = rte_eth_tx_buffer_set_err_callback(
1832 buffer, rte_eth_tx_buffer_drop_callback, NULL);
1833 }
1834
1835 return ret;
1836 }
1837
1838 int
1839 rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt)
1840 {
1841 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1842 int ret;
1843
1844 /* Validate Input Data. Bail if not valid or not supported. */
1845 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1846 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_done_cleanup, -ENOTSUP);
1847
1848 /* Call driver to free pending mbufs. */
1849 ret = (*dev->dev_ops->tx_done_cleanup)(dev->data->tx_queues[queue_id],
1850 free_cnt);
1851 return eth_err(port_id, ret);
1852 }
1853
1854 void
1855 rte_eth_promiscuous_enable(uint16_t port_id)
1856 {
1857 struct rte_eth_dev *dev;
1858
1859 RTE_ETH_VALID_PORTID_OR_RET(port_id);
1860 dev = &rte_eth_devices[port_id];
1861
1862 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->promiscuous_enable);
1863 (*dev->dev_ops->promiscuous_enable)(dev);
1864 dev->data->promiscuous = 1;
1865 }
1866
1867 void
1868 rte_eth_promiscuous_disable(uint16_t port_id)
1869 {
1870 struct rte_eth_dev *dev;
1871
1872 RTE_ETH_VALID_PORTID_OR_RET(port_id);
1873 dev = &rte_eth_devices[port_id];
1874
1875 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->promiscuous_disable);
1876 dev->data->promiscuous = 0;
1877 (*dev->dev_ops->promiscuous_disable)(dev);
1878 }
1879
1880 int
1881 rte_eth_promiscuous_get(uint16_t port_id)
1882 {
1883 struct rte_eth_dev *dev;
1884
1885 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1886
1887 dev = &rte_eth_devices[port_id];
1888 return dev->data->promiscuous;
1889 }
1890
1891 void
1892 rte_eth_allmulticast_enable(uint16_t port_id)
1893 {
1894 struct rte_eth_dev *dev;
1895
1896 RTE_ETH_VALID_PORTID_OR_RET(port_id);
1897 dev = &rte_eth_devices[port_id];
1898
1899 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->allmulticast_enable);
1900 (*dev->dev_ops->allmulticast_enable)(dev);
1901 dev->data->all_multicast = 1;
1902 }
1903
1904 void
1905 rte_eth_allmulticast_disable(uint16_t port_id)
1906 {
1907 struct rte_eth_dev *dev;
1908
1909 RTE_ETH_VALID_PORTID_OR_RET(port_id);
1910 dev = &rte_eth_devices[port_id];
1911
1912 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->allmulticast_disable);
1913 dev->data->all_multicast = 0;
1914 (*dev->dev_ops->allmulticast_disable)(dev);
1915 }
1916
1917 int
1918 rte_eth_allmulticast_get(uint16_t port_id)
1919 {
1920 struct rte_eth_dev *dev;
1921
1922 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1923
1924 dev = &rte_eth_devices[port_id];
1925 return dev->data->all_multicast;
1926 }
1927
1928 void
1929 rte_eth_link_get(uint16_t port_id, struct rte_eth_link *eth_link)
1930 {
1931 struct rte_eth_dev *dev;
1932
1933 RTE_ETH_VALID_PORTID_OR_RET(port_id);
1934 dev = &rte_eth_devices[port_id];
1935
1936 if (dev->data->dev_conf.intr_conf.lsc &&
1937 dev->data->dev_started)
1938 rte_eth_linkstatus_get(dev, eth_link);
1939 else {
1940 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->link_update);
1941 (*dev->dev_ops->link_update)(dev, 1);
1942 *eth_link = dev->data->dev_link;
1943 }
1944 }
1945
1946 void
1947 rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *eth_link)
1948 {
1949 struct rte_eth_dev *dev;
1950
1951 RTE_ETH_VALID_PORTID_OR_RET(port_id);
1952 dev = &rte_eth_devices[port_id];
1953
1954 if (dev->data->dev_conf.intr_conf.lsc &&
1955 dev->data->dev_started)
1956 rte_eth_linkstatus_get(dev, eth_link);
1957 else {
1958 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->link_update);
1959 (*dev->dev_ops->link_update)(dev, 0);
1960 *eth_link = dev->data->dev_link;
1961 }
1962 }
1963
1964 int
1965 rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats)
1966 {
1967 struct rte_eth_dev *dev;
1968
1969 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
1970
1971 dev = &rte_eth_devices[port_id];
1972 memset(stats, 0, sizeof(*stats));
1973
1974 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_get, -ENOTSUP);
1975 stats->rx_nombuf = dev->data->rx_mbuf_alloc_failed;
1976 return eth_err(port_id, (*dev->dev_ops->stats_get)(dev, stats));
1977 }
1978
1979 int
1980 rte_eth_stats_reset(uint16_t port_id)
1981 {
1982 struct rte_eth_dev *dev;
1983
1984 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
1985 dev = &rte_eth_devices[port_id];
1986
1987 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->stats_reset, -ENOTSUP);
1988 (*dev->dev_ops->stats_reset)(dev);
1989 dev->data->rx_mbuf_alloc_failed = 0;
1990
1991 return 0;
1992 }
1993
1994 static inline int
1995 get_xstats_basic_count(struct rte_eth_dev *dev)
1996 {
1997 uint16_t nb_rxqs, nb_txqs;
1998 int count;
1999
2000 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2001 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2002
2003 count = RTE_NB_STATS;
2004 count += nb_rxqs * RTE_NB_RXQ_STATS;
2005 count += nb_txqs * RTE_NB_TXQ_STATS;
2006
2007 return count;
2008 }
2009
2010 static int
2011 get_xstats_count(uint16_t port_id)
2012 {
2013 struct rte_eth_dev *dev;
2014 int count;
2015
2016 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2017 dev = &rte_eth_devices[port_id];
2018 if (dev->dev_ops->xstats_get_names_by_id != NULL) {
2019 count = (*dev->dev_ops->xstats_get_names_by_id)(dev, NULL,
2020 NULL, 0);
2021 if (count < 0)
2022 return eth_err(port_id, count);
2023 }
2024 if (dev->dev_ops->xstats_get_names != NULL) {
2025 count = (*dev->dev_ops->xstats_get_names)(dev, NULL, 0);
2026 if (count < 0)
2027 return eth_err(port_id, count);
2028 } else
2029 count = 0;
2030
2031
2032 count += get_xstats_basic_count(dev);
2033
2034 return count;
2035 }
2036
2037 int
2038 rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name,
2039 uint64_t *id)
2040 {
2041 int cnt_xstats, idx_xstat;
2042
2043 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2044
2045 if (!id) {
2046 RTE_ETHDEV_LOG(ERR, "Id pointer is NULL\n");
2047 return -ENOMEM;
2048 }
2049
2050 if (!xstat_name) {
2051 RTE_ETHDEV_LOG(ERR, "xstat_name pointer is NULL\n");
2052 return -ENOMEM;
2053 }
2054
2055 /* Get count */
2056 cnt_xstats = rte_eth_xstats_get_names_by_id(port_id, NULL, 0, NULL);
2057 if (cnt_xstats < 0) {
2058 RTE_ETHDEV_LOG(ERR, "Cannot get count of xstats\n");
2059 return -ENODEV;
2060 }
2061
2062 /* Get id-name lookup table */
2063 struct rte_eth_xstat_name xstats_names[cnt_xstats];
2064
2065 if (cnt_xstats != rte_eth_xstats_get_names_by_id(
2066 port_id, xstats_names, cnt_xstats, NULL)) {
2067 RTE_ETHDEV_LOG(ERR, "Cannot get xstats lookup\n");
2068 return -1;
2069 }
2070
2071 for (idx_xstat = 0; idx_xstat < cnt_xstats; idx_xstat++) {
2072 if (!strcmp(xstats_names[idx_xstat].name, xstat_name)) {
2073 *id = idx_xstat;
2074 return 0;
2075 };
2076 }
2077
2078 return -EINVAL;
2079 }
2080
2081 /* retrieve basic stats names */
2082 static int
2083 rte_eth_basic_stats_get_names(struct rte_eth_dev *dev,
2084 struct rte_eth_xstat_name *xstats_names)
2085 {
2086 int cnt_used_entries = 0;
2087 uint32_t idx, id_queue;
2088 uint16_t num_q;
2089
2090 for (idx = 0; idx < RTE_NB_STATS; idx++) {
2091 strlcpy(xstats_names[cnt_used_entries].name,
2092 rte_stats_strings[idx].name,
2093 sizeof(xstats_names[0].name));
2094 cnt_used_entries++;
2095 }
2096 num_q = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2097 for (id_queue = 0; id_queue < num_q; id_queue++) {
2098 for (idx = 0; idx < RTE_NB_RXQ_STATS; idx++) {
2099 snprintf(xstats_names[cnt_used_entries].name,
2100 sizeof(xstats_names[0].name),
2101 "rx_q%u%s",
2102 id_queue, rte_rxq_stats_strings[idx].name);
2103 cnt_used_entries++;
2104 }
2105
2106 }
2107 num_q = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2108 for (id_queue = 0; id_queue < num_q; id_queue++) {
2109 for (idx = 0; idx < RTE_NB_TXQ_STATS; idx++) {
2110 snprintf(xstats_names[cnt_used_entries].name,
2111 sizeof(xstats_names[0].name),
2112 "tx_q%u%s",
2113 id_queue, rte_txq_stats_strings[idx].name);
2114 cnt_used_entries++;
2115 }
2116 }
2117 return cnt_used_entries;
2118 }
2119
2120 /* retrieve ethdev extended statistics names */
2121 int
2122 rte_eth_xstats_get_names_by_id(uint16_t port_id,
2123 struct rte_eth_xstat_name *xstats_names, unsigned int size,
2124 uint64_t *ids)
2125 {
2126 struct rte_eth_xstat_name *xstats_names_copy;
2127 unsigned int no_basic_stat_requested = 1;
2128 unsigned int no_ext_stat_requested = 1;
2129 unsigned int expected_entries;
2130 unsigned int basic_count;
2131 struct rte_eth_dev *dev;
2132 unsigned int i;
2133 int ret;
2134
2135 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2136 dev = &rte_eth_devices[port_id];
2137
2138 basic_count = get_xstats_basic_count(dev);
2139 ret = get_xstats_count(port_id);
2140 if (ret < 0)
2141 return ret;
2142 expected_entries = (unsigned int)ret;
2143
2144 /* Return max number of stats if no ids given */
2145 if (!ids) {
2146 if (!xstats_names)
2147 return expected_entries;
2148 else if (xstats_names && size < expected_entries)
2149 return expected_entries;
2150 }
2151
2152 if (ids && !xstats_names)
2153 return -EINVAL;
2154
2155 if (ids && dev->dev_ops->xstats_get_names_by_id != NULL && size > 0) {
2156 uint64_t ids_copy[size];
2157
2158 for (i = 0; i < size; i++) {
2159 if (ids[i] < basic_count) {
2160 no_basic_stat_requested = 0;
2161 break;
2162 }
2163
2164 /*
2165 * Convert ids to xstats ids that PMD knows.
2166 * ids known by user are basic + extended stats.
2167 */
2168 ids_copy[i] = ids[i] - basic_count;
2169 }
2170
2171 if (no_basic_stat_requested)
2172 return (*dev->dev_ops->xstats_get_names_by_id)(dev,
2173 xstats_names, ids_copy, size);
2174 }
2175
2176 /* Retrieve all stats */
2177 if (!ids) {
2178 int num_stats = rte_eth_xstats_get_names(port_id, xstats_names,
2179 expected_entries);
2180 if (num_stats < 0 || num_stats > (int)expected_entries)
2181 return num_stats;
2182 else
2183 return expected_entries;
2184 }
2185
2186 xstats_names_copy = calloc(expected_entries,
2187 sizeof(struct rte_eth_xstat_name));
2188
2189 if (!xstats_names_copy) {
2190 RTE_ETHDEV_LOG(ERR, "Can't allocate memory\n");
2191 return -ENOMEM;
2192 }
2193
2194 if (ids) {
2195 for (i = 0; i < size; i++) {
2196 if (ids[i] >= basic_count) {
2197 no_ext_stat_requested = 0;
2198 break;
2199 }
2200 }
2201 }
2202
2203 /* Fill xstats_names_copy structure */
2204 if (ids && no_ext_stat_requested) {
2205 rte_eth_basic_stats_get_names(dev, xstats_names_copy);
2206 } else {
2207 ret = rte_eth_xstats_get_names(port_id, xstats_names_copy,
2208 expected_entries);
2209 if (ret < 0) {
2210 free(xstats_names_copy);
2211 return ret;
2212 }
2213 }
2214
2215 /* Filter stats */
2216 for (i = 0; i < size; i++) {
2217 if (ids[i] >= expected_entries) {
2218 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n");
2219 free(xstats_names_copy);
2220 return -1;
2221 }
2222 xstats_names[i] = xstats_names_copy[ids[i]];
2223 }
2224
2225 free(xstats_names_copy);
2226 return size;
2227 }
2228
2229 int
2230 rte_eth_xstats_get_names(uint16_t port_id,
2231 struct rte_eth_xstat_name *xstats_names,
2232 unsigned int size)
2233 {
2234 struct rte_eth_dev *dev;
2235 int cnt_used_entries;
2236 int cnt_expected_entries;
2237 int cnt_driver_entries;
2238
2239 cnt_expected_entries = get_xstats_count(port_id);
2240 if (xstats_names == NULL || cnt_expected_entries < 0 ||
2241 (int)size < cnt_expected_entries)
2242 return cnt_expected_entries;
2243
2244 /* port_id checked in get_xstats_count() */
2245 dev = &rte_eth_devices[port_id];
2246
2247 cnt_used_entries = rte_eth_basic_stats_get_names(
2248 dev, xstats_names);
2249
2250 if (dev->dev_ops->xstats_get_names != NULL) {
2251 /* If there are any driver-specific xstats, append them
2252 * to end of list.
2253 */
2254 cnt_driver_entries = (*dev->dev_ops->xstats_get_names)(
2255 dev,
2256 xstats_names + cnt_used_entries,
2257 size - cnt_used_entries);
2258 if (cnt_driver_entries < 0)
2259 return eth_err(port_id, cnt_driver_entries);
2260 cnt_used_entries += cnt_driver_entries;
2261 }
2262
2263 return cnt_used_entries;
2264 }
2265
2266
2267 static int
2268 rte_eth_basic_stats_get(uint16_t port_id, struct rte_eth_xstat *xstats)
2269 {
2270 struct rte_eth_dev *dev;
2271 struct rte_eth_stats eth_stats;
2272 unsigned int count = 0, i, q;
2273 uint64_t val, *stats_ptr;
2274 uint16_t nb_rxqs, nb_txqs;
2275 int ret;
2276
2277 ret = rte_eth_stats_get(port_id, &eth_stats);
2278 if (ret < 0)
2279 return ret;
2280
2281 dev = &rte_eth_devices[port_id];
2282
2283 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2284 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2285
2286 /* global stats */
2287 for (i = 0; i < RTE_NB_STATS; i++) {
2288 stats_ptr = RTE_PTR_ADD(&eth_stats,
2289 rte_stats_strings[i].offset);
2290 val = *stats_ptr;
2291 xstats[count++].value = val;
2292 }
2293
2294 /* per-rxq stats */
2295 for (q = 0; q < nb_rxqs; q++) {
2296 for (i = 0; i < RTE_NB_RXQ_STATS; i++) {
2297 stats_ptr = RTE_PTR_ADD(&eth_stats,
2298 rte_rxq_stats_strings[i].offset +
2299 q * sizeof(uint64_t));
2300 val = *stats_ptr;
2301 xstats[count++].value = val;
2302 }
2303 }
2304
2305 /* per-txq stats */
2306 for (q = 0; q < nb_txqs; q++) {
2307 for (i = 0; i < RTE_NB_TXQ_STATS; i++) {
2308 stats_ptr = RTE_PTR_ADD(&eth_stats,
2309 rte_txq_stats_strings[i].offset +
2310 q * sizeof(uint64_t));
2311 val = *stats_ptr;
2312 xstats[count++].value = val;
2313 }
2314 }
2315 return count;
2316 }
2317
2318 /* retrieve ethdev extended statistics */
2319 int
2320 rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids,
2321 uint64_t *values, unsigned int size)
2322 {
2323 unsigned int no_basic_stat_requested = 1;
2324 unsigned int no_ext_stat_requested = 1;
2325 unsigned int num_xstats_filled;
2326 unsigned int basic_count;
2327 uint16_t expected_entries;
2328 struct rte_eth_dev *dev;
2329 unsigned int i;
2330 int ret;
2331
2332 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2333 ret = get_xstats_count(port_id);
2334 if (ret < 0)
2335 return ret;
2336 expected_entries = (uint16_t)ret;
2337 struct rte_eth_xstat xstats[expected_entries];
2338 dev = &rte_eth_devices[port_id];
2339 basic_count = get_xstats_basic_count(dev);
2340
2341 /* Return max number of stats if no ids given */
2342 if (!ids) {
2343 if (!values)
2344 return expected_entries;
2345 else if (values && size < expected_entries)
2346 return expected_entries;
2347 }
2348
2349 if (ids && !values)
2350 return -EINVAL;
2351
2352 if (ids && dev->dev_ops->xstats_get_by_id != NULL && size) {
2353 unsigned int basic_count = get_xstats_basic_count(dev);
2354 uint64_t ids_copy[size];
2355
2356 for (i = 0; i < size; i++) {
2357 if (ids[i] < basic_count) {
2358 no_basic_stat_requested = 0;
2359 break;
2360 }
2361
2362 /*
2363 * Convert ids to xstats ids that PMD knows.
2364 * ids known by user are basic + extended stats.
2365 */
2366 ids_copy[i] = ids[i] - basic_count;
2367 }
2368
2369 if (no_basic_stat_requested)
2370 return (*dev->dev_ops->xstats_get_by_id)(dev, ids_copy,
2371 values, size);
2372 }
2373
2374 if (ids) {
2375 for (i = 0; i < size; i++) {
2376 if (ids[i] >= basic_count) {
2377 no_ext_stat_requested = 0;
2378 break;
2379 }
2380 }
2381 }
2382
2383 /* Fill the xstats structure */
2384 if (ids && no_ext_stat_requested)
2385 ret = rte_eth_basic_stats_get(port_id, xstats);
2386 else
2387 ret = rte_eth_xstats_get(port_id, xstats, expected_entries);
2388
2389 if (ret < 0)
2390 return ret;
2391 num_xstats_filled = (unsigned int)ret;
2392
2393 /* Return all stats */
2394 if (!ids) {
2395 for (i = 0; i < num_xstats_filled; i++)
2396 values[i] = xstats[i].value;
2397 return expected_entries;
2398 }
2399
2400 /* Filter stats */
2401 for (i = 0; i < size; i++) {
2402 if (ids[i] >= expected_entries) {
2403 RTE_ETHDEV_LOG(ERR, "Id value isn't valid\n");
2404 return -1;
2405 }
2406 values[i] = xstats[ids[i]].value;
2407 }
2408 return size;
2409 }
2410
2411 int
2412 rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats,
2413 unsigned int n)
2414 {
2415 struct rte_eth_dev *dev;
2416 unsigned int count = 0, i;
2417 signed int xcount = 0;
2418 uint16_t nb_rxqs, nb_txqs;
2419 int ret;
2420
2421 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
2422
2423 dev = &rte_eth_devices[port_id];
2424
2425 nb_rxqs = RTE_MIN(dev->data->nb_rx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2426 nb_txqs = RTE_MIN(dev->data->nb_tx_queues, RTE_ETHDEV_QUEUE_STAT_CNTRS);
2427
2428 /* Return generic statistics */
2429 count = RTE_NB_STATS + (nb_rxqs * RTE_NB_RXQ_STATS) +
2430 (nb_txqs * RTE_NB_TXQ_STATS);
2431
2432 /* implemented by the driver */
2433 if (dev->dev_ops->xstats_get != NULL) {
2434 /* Retrieve the xstats from the driver at the end of the
2435 * xstats struct.
2436 */
2437 xcount = (*dev->dev_ops->xstats_get)(dev,
2438 xstats ? xstats + count : NULL,
2439 (n > count) ? n - count : 0);
2440
2441 if (xcount < 0)
2442 return eth_err(port_id, xcount);
2443 }
2444
2445 if (n < count + xcount || xstats == NULL)
2446 return count + xcount;
2447
2448 /* now fill the xstats structure */
2449 ret = rte_eth_basic_stats_get(port_id, xstats);
2450 if (ret < 0)
2451 return ret;
2452 count = ret;
2453
2454 for (i = 0; i < count; i++)
2455 xstats[i].id = i;
2456 /* add an offset to driver-specific stats */
2457 for ( ; i < count + xcount; i++)
2458 xstats[i].id += count;
2459
2460 return count + xcount;
2461 }
2462
2463 /* reset ethdev extended statistics */
2464 void
2465 rte_eth_xstats_reset(uint16_t port_id)
2466 {
2467 struct rte_eth_dev *dev;
2468
2469 RTE_ETH_VALID_PORTID_OR_RET(port_id);
2470 dev = &rte_eth_devices[port_id];
2471
2472 /* implemented by the driver */
2473 if (dev->dev_ops->xstats_reset != NULL) {
2474 (*dev->dev_ops->xstats_reset)(dev);
2475 return;
2476 }
2477
2478 /* fallback to default */
2479 rte_eth_stats_reset(port_id);
2480 }
2481
2482 static int
2483 set_queue_stats_mapping(uint16_t port_id, uint16_t queue_id, uint8_t stat_idx,
2484 uint8_t is_rx)
2485 {
2486 struct rte_eth_dev *dev;
2487
2488 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2489
2490 dev = &rte_eth_devices[port_id];
2491
2492 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->queue_stats_mapping_set, -ENOTSUP);
2493
2494 if (is_rx && (queue_id >= dev->data->nb_rx_queues))
2495 return -EINVAL;
2496
2497 if (!is_rx && (queue_id >= dev->data->nb_tx_queues))
2498 return -EINVAL;
2499
2500 if (stat_idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
2501 return -EINVAL;
2502
2503 return (*dev->dev_ops->queue_stats_mapping_set)
2504 (dev, queue_id, stat_idx, is_rx);
2505 }
2506
2507
2508 int
2509 rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id, uint16_t tx_queue_id,
2510 uint8_t stat_idx)
2511 {
2512 return eth_err(port_id, set_queue_stats_mapping(port_id, tx_queue_id,
2513 stat_idx, STAT_QMAP_TX));
2514 }
2515
2516
2517 int
2518 rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id, uint16_t rx_queue_id,
2519 uint8_t stat_idx)
2520 {
2521 return eth_err(port_id, set_queue_stats_mapping(port_id, rx_queue_id,
2522 stat_idx, STAT_QMAP_RX));
2523 }
2524
2525 int
2526 rte_eth_dev_fw_version_get(uint16_t port_id, char *fw_version, size_t fw_size)
2527 {
2528 struct rte_eth_dev *dev;
2529
2530 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2531 dev = &rte_eth_devices[port_id];
2532
2533 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->fw_version_get, -ENOTSUP);
2534 return eth_err(port_id, (*dev->dev_ops->fw_version_get)(dev,
2535 fw_version, fw_size));
2536 }
2537
2538 void
2539 rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info)
2540 {
2541 struct rte_eth_dev *dev;
2542 const struct rte_eth_desc_lim lim = {
2543 .nb_max = UINT16_MAX,
2544 .nb_min = 0,
2545 .nb_align = 1,
2546 };
2547
2548 RTE_ETH_VALID_PORTID_OR_RET(port_id);
2549 dev = &rte_eth_devices[port_id];
2550
2551 memset(dev_info, 0, sizeof(struct rte_eth_dev_info));
2552 dev_info->rx_desc_lim = lim;
2553 dev_info->tx_desc_lim = lim;
2554 dev_info->device = dev->device;
2555 dev_info->min_mtu = ETHER_MIN_MTU;
2556 dev_info->max_mtu = UINT16_MAX;
2557
2558 RTE_FUNC_PTR_OR_RET(*dev->dev_ops->dev_infos_get);
2559 (*dev->dev_ops->dev_infos_get)(dev, dev_info);
2560 dev_info->driver_name = dev->device->driver->name;
2561 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2562 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2563
2564 dev_info->dev_flags = &dev->data->dev_flags;
2565 }
2566
2567 int
2568 rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask,
2569 uint32_t *ptypes, int num)
2570 {
2571 int i, j;
2572 struct rte_eth_dev *dev;
2573 const uint32_t *all_ptypes;
2574
2575 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2576 dev = &rte_eth_devices[port_id];
2577 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_supported_ptypes_get, 0);
2578 all_ptypes = (*dev->dev_ops->dev_supported_ptypes_get)(dev);
2579
2580 if (!all_ptypes)
2581 return 0;
2582
2583 for (i = 0, j = 0; all_ptypes[i] != RTE_PTYPE_UNKNOWN; ++i)
2584 if (all_ptypes[i] & ptype_mask) {
2585 if (j < num)
2586 ptypes[j] = all_ptypes[i];
2587 j++;
2588 }
2589
2590 return j;
2591 }
2592
2593 void
2594 rte_eth_macaddr_get(uint16_t port_id, struct ether_addr *mac_addr)
2595 {
2596 struct rte_eth_dev *dev;
2597
2598 RTE_ETH_VALID_PORTID_OR_RET(port_id);
2599 dev = &rte_eth_devices[port_id];
2600 ether_addr_copy(&dev->data->mac_addrs[0], mac_addr);
2601 }
2602
2603
2604 int
2605 rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu)
2606 {
2607 struct rte_eth_dev *dev;
2608
2609 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2610
2611 dev = &rte_eth_devices[port_id];
2612 *mtu = dev->data->mtu;
2613 return 0;
2614 }
2615
2616 int
2617 rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu)
2618 {
2619 int ret;
2620 struct rte_eth_dev_info dev_info;
2621 struct rte_eth_dev *dev;
2622
2623 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2624 dev = &rte_eth_devices[port_id];
2625 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mtu_set, -ENOTSUP);
2626
2627 /*
2628 * Check if the device supports dev_infos_get, if it does not
2629 * skip min_mtu/max_mtu validation here as this requires values
2630 * that are populated within the call to rte_eth_dev_info_get()
2631 * which relies on dev->dev_ops->dev_infos_get.
2632 */
2633 if (*dev->dev_ops->dev_infos_get != NULL) {
2634 rte_eth_dev_info_get(port_id, &dev_info);
2635 if (mtu < dev_info.min_mtu || mtu > dev_info.max_mtu)
2636 return -EINVAL;
2637 }
2638
2639 ret = (*dev->dev_ops->mtu_set)(dev, mtu);
2640 if (!ret)
2641 dev->data->mtu = mtu;
2642
2643 return eth_err(port_id, ret);
2644 }
2645
2646 int
2647 rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on)
2648 {
2649 struct rte_eth_dev *dev;
2650 int ret;
2651
2652 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2653 dev = &rte_eth_devices[port_id];
2654 if (!(dev->data->dev_conf.rxmode.offloads &
2655 DEV_RX_OFFLOAD_VLAN_FILTER)) {
2656 RTE_ETHDEV_LOG(ERR, "Port %u: vlan-filtering disabled\n",
2657 port_id);
2658 return -ENOSYS;
2659 }
2660
2661 if (vlan_id > 4095) {
2662 RTE_ETHDEV_LOG(ERR, "Port_id=%u invalid vlan_id=%u > 4095\n",
2663 port_id, vlan_id);
2664 return -EINVAL;
2665 }
2666 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_filter_set, -ENOTSUP);
2667
2668 ret = (*dev->dev_ops->vlan_filter_set)(dev, vlan_id, on);
2669 if (ret == 0) {
2670 struct rte_vlan_filter_conf *vfc;
2671 int vidx;
2672 int vbit;
2673
2674 vfc = &dev->data->vlan_filter_conf;
2675 vidx = vlan_id / 64;
2676 vbit = vlan_id % 64;
2677
2678 if (on)
2679 vfc->ids[vidx] |= UINT64_C(1) << vbit;
2680 else
2681 vfc->ids[vidx] &= ~(UINT64_C(1) << vbit);
2682 }
2683
2684 return eth_err(port_id, ret);
2685 }
2686
2687 int
2688 rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id,
2689 int on)
2690 {
2691 struct rte_eth_dev *dev;
2692
2693 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2694 dev = &rte_eth_devices[port_id];
2695 if (rx_queue_id >= dev->data->nb_rx_queues) {
2696 RTE_ETHDEV_LOG(ERR, "Invalid rx_queue_id=%u\n", rx_queue_id);
2697 return -EINVAL;
2698 }
2699
2700 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
2701 (*dev->dev_ops->vlan_strip_queue_set)(dev, rx_queue_id, on);
2702
2703 return 0;
2704 }
2705
2706 int
2707 rte_eth_dev_set_vlan_ether_type(uint16_t port_id,
2708 enum rte_vlan_type vlan_type,
2709 uint16_t tpid)
2710 {
2711 struct rte_eth_dev *dev;
2712
2713 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2714 dev = &rte_eth_devices[port_id];
2715 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_tpid_set, -ENOTSUP);
2716
2717 return eth_err(port_id, (*dev->dev_ops->vlan_tpid_set)(dev, vlan_type,
2718 tpid));
2719 }
2720
2721 int
2722 rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask)
2723 {
2724 struct rte_eth_dev *dev;
2725 int ret = 0;
2726 int mask = 0;
2727 int cur, org = 0;
2728 uint64_t orig_offloads;
2729
2730 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2731 dev = &rte_eth_devices[port_id];
2732
2733 /* save original values in case of failure */
2734 orig_offloads = dev->data->dev_conf.rxmode.offloads;
2735
2736 /*check which option changed by application*/
2737 cur = !!(offload_mask & ETH_VLAN_STRIP_OFFLOAD);
2738 org = !!(dev->data->dev_conf.rxmode.offloads &
2739 DEV_RX_OFFLOAD_VLAN_STRIP);
2740 if (cur != org) {
2741 if (cur)
2742 dev->data->dev_conf.rxmode.offloads |=
2743 DEV_RX_OFFLOAD_VLAN_STRIP;
2744 else
2745 dev->data->dev_conf.rxmode.offloads &=
2746 ~DEV_RX_OFFLOAD_VLAN_STRIP;
2747 mask |= ETH_VLAN_STRIP_MASK;
2748 }
2749
2750 cur = !!(offload_mask & ETH_VLAN_FILTER_OFFLOAD);
2751 org = !!(dev->data->dev_conf.rxmode.offloads &
2752 DEV_RX_OFFLOAD_VLAN_FILTER);
2753 if (cur != org) {
2754 if (cur)
2755 dev->data->dev_conf.rxmode.offloads |=
2756 DEV_RX_OFFLOAD_VLAN_FILTER;
2757 else
2758 dev->data->dev_conf.rxmode.offloads &=
2759 ~DEV_RX_OFFLOAD_VLAN_FILTER;
2760 mask |= ETH_VLAN_FILTER_MASK;
2761 }
2762
2763 cur = !!(offload_mask & ETH_VLAN_EXTEND_OFFLOAD);
2764 org = !!(dev->data->dev_conf.rxmode.offloads &
2765 DEV_RX_OFFLOAD_VLAN_EXTEND);
2766 if (cur != org) {
2767 if (cur)
2768 dev->data->dev_conf.rxmode.offloads |=
2769 DEV_RX_OFFLOAD_VLAN_EXTEND;
2770 else
2771 dev->data->dev_conf.rxmode.offloads &=
2772 ~DEV_RX_OFFLOAD_VLAN_EXTEND;
2773 mask |= ETH_VLAN_EXTEND_MASK;
2774 }
2775
2776 /*no change*/
2777 if (mask == 0)
2778 return ret;
2779
2780 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_offload_set, -ENOTSUP);
2781 ret = (*dev->dev_ops->vlan_offload_set)(dev, mask);
2782 if (ret) {
2783 /* hit an error restore original values */
2784 dev->data->dev_conf.rxmode.offloads = orig_offloads;
2785 }
2786
2787 return eth_err(port_id, ret);
2788 }
2789
2790 int
2791 rte_eth_dev_get_vlan_offload(uint16_t port_id)
2792 {
2793 struct rte_eth_dev *dev;
2794 int ret = 0;
2795
2796 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2797 dev = &rte_eth_devices[port_id];
2798
2799 if (dev->data->dev_conf.rxmode.offloads &
2800 DEV_RX_OFFLOAD_VLAN_STRIP)
2801 ret |= ETH_VLAN_STRIP_OFFLOAD;
2802
2803 if (dev->data->dev_conf.rxmode.offloads &
2804 DEV_RX_OFFLOAD_VLAN_FILTER)
2805 ret |= ETH_VLAN_FILTER_OFFLOAD;
2806
2807 if (dev->data->dev_conf.rxmode.offloads &
2808 DEV_RX_OFFLOAD_VLAN_EXTEND)
2809 ret |= ETH_VLAN_EXTEND_OFFLOAD;
2810
2811 return ret;
2812 }
2813
2814 int
2815 rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on)
2816 {
2817 struct rte_eth_dev *dev;
2818
2819 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2820 dev = &rte_eth_devices[port_id];
2821 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_pvid_set, -ENOTSUP);
2822
2823 return eth_err(port_id, (*dev->dev_ops->vlan_pvid_set)(dev, pvid, on));
2824 }
2825
2826 int
2827 rte_eth_dev_flow_ctrl_get(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
2828 {
2829 struct rte_eth_dev *dev;
2830
2831 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2832 dev = &rte_eth_devices[port_id];
2833 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_get, -ENOTSUP);
2834 memset(fc_conf, 0, sizeof(*fc_conf));
2835 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_get)(dev, fc_conf));
2836 }
2837
2838 int
2839 rte_eth_dev_flow_ctrl_set(uint16_t port_id, struct rte_eth_fc_conf *fc_conf)
2840 {
2841 struct rte_eth_dev *dev;
2842
2843 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2844 if ((fc_conf->send_xon != 0) && (fc_conf->send_xon != 1)) {
2845 RTE_ETHDEV_LOG(ERR, "Invalid send_xon, only 0/1 allowed\n");
2846 return -EINVAL;
2847 }
2848
2849 dev = &rte_eth_devices[port_id];
2850 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->flow_ctrl_set, -ENOTSUP);
2851 return eth_err(port_id, (*dev->dev_ops->flow_ctrl_set)(dev, fc_conf));
2852 }
2853
2854 int
2855 rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,
2856 struct rte_eth_pfc_conf *pfc_conf)
2857 {
2858 struct rte_eth_dev *dev;
2859
2860 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2861 if (pfc_conf->priority > (ETH_DCB_NUM_USER_PRIORITIES - 1)) {
2862 RTE_ETHDEV_LOG(ERR, "Invalid priority, only 0-7 allowed\n");
2863 return -EINVAL;
2864 }
2865
2866 dev = &rte_eth_devices[port_id];
2867 /* High water, low water validation are device specific */
2868 if (*dev->dev_ops->priority_flow_ctrl_set)
2869 return eth_err(port_id, (*dev->dev_ops->priority_flow_ctrl_set)
2870 (dev, pfc_conf));
2871 return -ENOTSUP;
2872 }
2873
2874 static int
2875 rte_eth_check_reta_mask(struct rte_eth_rss_reta_entry64 *reta_conf,
2876 uint16_t reta_size)
2877 {
2878 uint16_t i, num;
2879
2880 if (!reta_conf)
2881 return -EINVAL;
2882
2883 num = (reta_size + RTE_RETA_GROUP_SIZE - 1) / RTE_RETA_GROUP_SIZE;
2884 for (i = 0; i < num; i++) {
2885 if (reta_conf[i].mask)
2886 return 0;
2887 }
2888
2889 return -EINVAL;
2890 }
2891
2892 static int
2893 rte_eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf,
2894 uint16_t reta_size,
2895 uint16_t max_rxq)
2896 {
2897 uint16_t i, idx, shift;
2898
2899 if (!reta_conf)
2900 return -EINVAL;
2901
2902 if (max_rxq == 0) {
2903 RTE_ETHDEV_LOG(ERR, "No receive queue is available\n");
2904 return -EINVAL;
2905 }
2906
2907 for (i = 0; i < reta_size; i++) {
2908 idx = i / RTE_RETA_GROUP_SIZE;
2909 shift = i % RTE_RETA_GROUP_SIZE;
2910 if ((reta_conf[idx].mask & (1ULL << shift)) &&
2911 (reta_conf[idx].reta[shift] >= max_rxq)) {
2912 RTE_ETHDEV_LOG(ERR,
2913 "reta_conf[%u]->reta[%u]: %u exceeds the maximum rxq index: %u\n",
2914 idx, shift,
2915 reta_conf[idx].reta[shift], max_rxq);
2916 return -EINVAL;
2917 }
2918 }
2919
2920 return 0;
2921 }
2922
2923 int
2924 rte_eth_dev_rss_reta_update(uint16_t port_id,
2925 struct rte_eth_rss_reta_entry64 *reta_conf,
2926 uint16_t reta_size)
2927 {
2928 struct rte_eth_dev *dev;
2929 int ret;
2930
2931 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2932 /* Check mask bits */
2933 ret = rte_eth_check_reta_mask(reta_conf, reta_size);
2934 if (ret < 0)
2935 return ret;
2936
2937 dev = &rte_eth_devices[port_id];
2938
2939 /* Check entry value */
2940 ret = rte_eth_check_reta_entry(reta_conf, reta_size,
2941 dev->data->nb_rx_queues);
2942 if (ret < 0)
2943 return ret;
2944
2945 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_update, -ENOTSUP);
2946 return eth_err(port_id, (*dev->dev_ops->reta_update)(dev, reta_conf,
2947 reta_size));
2948 }
2949
2950 int
2951 rte_eth_dev_rss_reta_query(uint16_t port_id,
2952 struct rte_eth_rss_reta_entry64 *reta_conf,
2953 uint16_t reta_size)
2954 {
2955 struct rte_eth_dev *dev;
2956 int ret;
2957
2958 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2959
2960 /* Check mask bits */
2961 ret = rte_eth_check_reta_mask(reta_conf, reta_size);
2962 if (ret < 0)
2963 return ret;
2964
2965 dev = &rte_eth_devices[port_id];
2966 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->reta_query, -ENOTSUP);
2967 return eth_err(port_id, (*dev->dev_ops->reta_query)(dev, reta_conf,
2968 reta_size));
2969 }
2970
2971 int
2972 rte_eth_dev_rss_hash_update(uint16_t port_id,
2973 struct rte_eth_rss_conf *rss_conf)
2974 {
2975 struct rte_eth_dev *dev;
2976 struct rte_eth_dev_info dev_info = { .flow_type_rss_offloads = 0, };
2977
2978 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
2979 dev = &rte_eth_devices[port_id];
2980 rte_eth_dev_info_get(port_id, &dev_info);
2981 if ((dev_info.flow_type_rss_offloads | rss_conf->rss_hf) !=
2982 dev_info.flow_type_rss_offloads) {
2983 RTE_ETHDEV_LOG(ERR,
2984 "Ethdev port_id=%u invalid rss_hf: 0x%"PRIx64", valid value: 0x%"PRIx64"\n",
2985 port_id, rss_conf->rss_hf,
2986 dev_info.flow_type_rss_offloads);
2987 return -EINVAL;
2988 }
2989 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_update, -ENOTSUP);
2990 return eth_err(port_id, (*dev->dev_ops->rss_hash_update)(dev,
2991 rss_conf));
2992 }
2993
2994 int
2995 rte_eth_dev_rss_hash_conf_get(uint16_t port_id,
2996 struct rte_eth_rss_conf *rss_conf)
2997 {
2998 struct rte_eth_dev *dev;
2999
3000 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3001 dev = &rte_eth_devices[port_id];
3002 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rss_hash_conf_get, -ENOTSUP);
3003 return eth_err(port_id, (*dev->dev_ops->rss_hash_conf_get)(dev,
3004 rss_conf));
3005 }
3006
3007 int
3008 rte_eth_dev_udp_tunnel_port_add(uint16_t port_id,
3009 struct rte_eth_udp_tunnel *udp_tunnel)
3010 {
3011 struct rte_eth_dev *dev;
3012
3013 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3014 if (udp_tunnel == NULL) {
3015 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n");
3016 return -EINVAL;
3017 }
3018
3019 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {
3020 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
3021 return -EINVAL;
3022 }
3023
3024 dev = &rte_eth_devices[port_id];
3025 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_add, -ENOTSUP);
3026 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_add)(dev,
3027 udp_tunnel));
3028 }
3029
3030 int
3031 rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id,
3032 struct rte_eth_udp_tunnel *udp_tunnel)
3033 {
3034 struct rte_eth_dev *dev;
3035
3036 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3037 dev = &rte_eth_devices[port_id];
3038
3039 if (udp_tunnel == NULL) {
3040 RTE_ETHDEV_LOG(ERR, "Invalid udp_tunnel parameter\n");
3041 return -EINVAL;
3042 }
3043
3044 if (udp_tunnel->prot_type >= RTE_TUNNEL_TYPE_MAX) {
3045 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
3046 return -EINVAL;
3047 }
3048
3049 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->udp_tunnel_port_del, -ENOTSUP);
3050 return eth_err(port_id, (*dev->dev_ops->udp_tunnel_port_del)(dev,
3051 udp_tunnel));
3052 }
3053
3054 int
3055 rte_eth_led_on(uint16_t port_id)
3056 {
3057 struct rte_eth_dev *dev;
3058
3059 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3060 dev = &rte_eth_devices[port_id];
3061 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_on, -ENOTSUP);
3062 return eth_err(port_id, (*dev->dev_ops->dev_led_on)(dev));
3063 }
3064
3065 int
3066 rte_eth_led_off(uint16_t port_id)
3067 {
3068 struct rte_eth_dev *dev;
3069
3070 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3071 dev = &rte_eth_devices[port_id];
3072 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_led_off, -ENOTSUP);
3073 return eth_err(port_id, (*dev->dev_ops->dev_led_off)(dev));
3074 }
3075
3076 /*
3077 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find
3078 * an empty spot.
3079 */
3080 static int
3081 get_mac_addr_index(uint16_t port_id, const struct ether_addr *addr)
3082 {
3083 struct rte_eth_dev_info dev_info;
3084 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3085 unsigned i;
3086
3087 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3088 rte_eth_dev_info_get(port_id, &dev_info);
3089
3090 for (i = 0; i < dev_info.max_mac_addrs; i++)
3091 if (memcmp(addr, &dev->data->mac_addrs[i], ETHER_ADDR_LEN) == 0)
3092 return i;
3093
3094 return -1;
3095 }
3096
3097 static const struct ether_addr null_mac_addr;
3098
3099 int
3100 rte_eth_dev_mac_addr_add(uint16_t port_id, struct ether_addr *addr,
3101 uint32_t pool)
3102 {
3103 struct rte_eth_dev *dev;
3104 int index;
3105 uint64_t pool_mask;
3106 int ret;
3107
3108 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3109 dev = &rte_eth_devices[port_id];
3110 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_add, -ENOTSUP);
3111
3112 if (is_zero_ether_addr(addr)) {
3113 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n",
3114 port_id);
3115 return -EINVAL;
3116 }
3117 if (pool >= ETH_64_POOLS) {
3118 RTE_ETHDEV_LOG(ERR, "Pool id must be 0-%d\n", ETH_64_POOLS - 1);
3119 return -EINVAL;
3120 }
3121
3122 index = get_mac_addr_index(port_id, addr);
3123 if (index < 0) {
3124 index = get_mac_addr_index(port_id, &null_mac_addr);
3125 if (index < 0) {
3126 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n",
3127 port_id);
3128 return -ENOSPC;
3129 }
3130 } else {
3131 pool_mask = dev->data->mac_pool_sel[index];
3132
3133 /* Check if both MAC address and pool is already there, and do nothing */
3134 if (pool_mask & (1ULL << pool))
3135 return 0;
3136 }
3137
3138 /* Update NIC */
3139 ret = (*dev->dev_ops->mac_addr_add)(dev, addr, index, pool);
3140
3141 if (ret == 0) {
3142 /* Update address in NIC data structure */
3143 ether_addr_copy(addr, &dev->data->mac_addrs[index]);
3144
3145 /* Update pool bitmap in NIC data structure */
3146 dev->data->mac_pool_sel[index] |= (1ULL << pool);
3147 }
3148
3149 return eth_err(port_id, ret);
3150 }
3151
3152 int
3153 rte_eth_dev_mac_addr_remove(uint16_t port_id, struct ether_addr *addr)
3154 {
3155 struct rte_eth_dev *dev;
3156 int index;
3157
3158 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3159 dev = &rte_eth_devices[port_id];
3160 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_remove, -ENOTSUP);
3161
3162 index = get_mac_addr_index(port_id, addr);
3163 if (index == 0) {
3164 RTE_ETHDEV_LOG(ERR,
3165 "Port %u: Cannot remove default MAC address\n",
3166 port_id);
3167 return -EADDRINUSE;
3168 } else if (index < 0)
3169 return 0; /* Do nothing if address wasn't found */
3170
3171 /* Update NIC */
3172 (*dev->dev_ops->mac_addr_remove)(dev, index);
3173
3174 /* Update address in NIC data structure */
3175 ether_addr_copy(&null_mac_addr, &dev->data->mac_addrs[index]);
3176
3177 /* reset pool bitmap */
3178 dev->data->mac_pool_sel[index] = 0;
3179
3180 return 0;
3181 }
3182
3183 int
3184 rte_eth_dev_default_mac_addr_set(uint16_t port_id, struct ether_addr *addr)
3185 {
3186 struct rte_eth_dev *dev;
3187 int ret;
3188
3189 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3190
3191 if (!is_valid_assigned_ether_addr(addr))
3192 return -EINVAL;
3193
3194 dev = &rte_eth_devices[port_id];
3195 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mac_addr_set, -ENOTSUP);
3196
3197 ret = (*dev->dev_ops->mac_addr_set)(dev, addr);
3198 if (ret < 0)
3199 return ret;
3200
3201 /* Update default address in NIC data structure */
3202 ether_addr_copy(addr, &dev->data->mac_addrs[0]);
3203
3204 return 0;
3205 }
3206
3207
3208 /*
3209 * Returns index into MAC address array of addr. Use 00:00:00:00:00:00 to find
3210 * an empty spot.
3211 */
3212 static int
3213 get_hash_mac_addr_index(uint16_t port_id, const struct ether_addr *addr)
3214 {
3215 struct rte_eth_dev_info dev_info;
3216 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3217 unsigned i;
3218
3219 rte_eth_dev_info_get(port_id, &dev_info);
3220 if (!dev->data->hash_mac_addrs)
3221 return -1;
3222
3223 for (i = 0; i < dev_info.max_hash_mac_addrs; i++)
3224 if (memcmp(addr, &dev->data->hash_mac_addrs[i],
3225 ETHER_ADDR_LEN) == 0)
3226 return i;
3227
3228 return -1;
3229 }
3230
3231 int
3232 rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct ether_addr *addr,
3233 uint8_t on)
3234 {
3235 int index;
3236 int ret;
3237 struct rte_eth_dev *dev;
3238
3239 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3240
3241 dev = &rte_eth_devices[port_id];
3242 if (is_zero_ether_addr(addr)) {
3243 RTE_ETHDEV_LOG(ERR, "Port %u: Cannot add NULL MAC address\n",
3244 port_id);
3245 return -EINVAL;
3246 }
3247
3248 index = get_hash_mac_addr_index(port_id, addr);
3249 /* Check if it's already there, and do nothing */
3250 if ((index >= 0) && on)
3251 return 0;
3252
3253 if (index < 0) {
3254 if (!on) {
3255 RTE_ETHDEV_LOG(ERR,
3256 "Port %u: the MAC address was not set in UTA\n",
3257 port_id);
3258 return -EINVAL;
3259 }
3260
3261 index = get_hash_mac_addr_index(port_id, &null_mac_addr);
3262 if (index < 0) {
3263 RTE_ETHDEV_LOG(ERR, "Port %u: MAC address array full\n",
3264 port_id);
3265 return -ENOSPC;
3266 }
3267 }
3268
3269 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_hash_table_set, -ENOTSUP);
3270 ret = (*dev->dev_ops->uc_hash_table_set)(dev, addr, on);
3271 if (ret == 0) {
3272 /* Update address in NIC data structure */
3273 if (on)
3274 ether_addr_copy(addr,
3275 &dev->data->hash_mac_addrs[index]);
3276 else
3277 ether_addr_copy(&null_mac_addr,
3278 &dev->data->hash_mac_addrs[index]);
3279 }
3280
3281 return eth_err(port_id, ret);
3282 }
3283
3284 int
3285 rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on)
3286 {
3287 struct rte_eth_dev *dev;
3288
3289 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3290
3291 dev = &rte_eth_devices[port_id];
3292
3293 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->uc_all_hash_table_set, -ENOTSUP);
3294 return eth_err(port_id, (*dev->dev_ops->uc_all_hash_table_set)(dev,
3295 on));
3296 }
3297
3298 int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx,
3299 uint16_t tx_rate)
3300 {
3301 struct rte_eth_dev *dev;
3302 struct rte_eth_dev_info dev_info;
3303 struct rte_eth_link link;
3304
3305 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3306
3307 dev = &rte_eth_devices[port_id];
3308 rte_eth_dev_info_get(port_id, &dev_info);
3309 link = dev->data->dev_link;
3310
3311 if (queue_idx > dev_info.max_tx_queues) {
3312 RTE_ETHDEV_LOG(ERR,
3313 "Set queue rate limit:port %u: invalid queue id=%u\n",
3314 port_id, queue_idx);
3315 return -EINVAL;
3316 }
3317
3318 if (tx_rate > link.link_speed) {
3319 RTE_ETHDEV_LOG(ERR,
3320 "Set queue rate limit:invalid tx_rate=%u, bigger than link speed= %d\n",
3321 tx_rate, link.link_speed);
3322 return -EINVAL;
3323 }
3324
3325 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_queue_rate_limit, -ENOTSUP);
3326 return eth_err(port_id, (*dev->dev_ops->set_queue_rate_limit)(dev,
3327 queue_idx, tx_rate));
3328 }
3329
3330 int
3331 rte_eth_mirror_rule_set(uint16_t port_id,
3332 struct rte_eth_mirror_conf *mirror_conf,
3333 uint8_t rule_id, uint8_t on)
3334 {
3335 struct rte_eth_dev *dev;
3336
3337 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3338 if (mirror_conf->rule_type == 0) {
3339 RTE_ETHDEV_LOG(ERR, "Mirror rule type can not be 0\n");
3340 return -EINVAL;
3341 }
3342
3343 if (mirror_conf->dst_pool >= ETH_64_POOLS) {
3344 RTE_ETHDEV_LOG(ERR, "Invalid dst pool, pool id must be 0-%d\n",
3345 ETH_64_POOLS - 1);
3346 return -EINVAL;
3347 }
3348
3349 if ((mirror_conf->rule_type & (ETH_MIRROR_VIRTUAL_POOL_UP |
3350 ETH_MIRROR_VIRTUAL_POOL_DOWN)) &&
3351 (mirror_conf->pool_mask == 0)) {
3352 RTE_ETHDEV_LOG(ERR,
3353 "Invalid mirror pool, pool mask can not be 0\n");
3354 return -EINVAL;
3355 }
3356
3357 if ((mirror_conf->rule_type & ETH_MIRROR_VLAN) &&
3358 mirror_conf->vlan.vlan_mask == 0) {
3359 RTE_ETHDEV_LOG(ERR,
3360 "Invalid vlan mask, vlan mask can not be 0\n");
3361 return -EINVAL;
3362 }
3363
3364 dev = &rte_eth_devices[port_id];
3365 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_set, -ENOTSUP);
3366
3367 return eth_err(port_id, (*dev->dev_ops->mirror_rule_set)(dev,
3368 mirror_conf, rule_id, on));
3369 }
3370
3371 int
3372 rte_eth_mirror_rule_reset(uint16_t port_id, uint8_t rule_id)
3373 {
3374 struct rte_eth_dev *dev;
3375
3376 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3377
3378 dev = &rte_eth_devices[port_id];
3379 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->mirror_rule_reset, -ENOTSUP);
3380
3381 return eth_err(port_id, (*dev->dev_ops->mirror_rule_reset)(dev,
3382 rule_id));
3383 }
3384
3385 RTE_INIT(eth_dev_init_cb_lists)
3386 {
3387 int i;
3388
3389 for (i = 0; i < RTE_MAX_ETHPORTS; i++)
3390 TAILQ_INIT(&rte_eth_devices[i].link_intr_cbs);
3391 }
3392
3393 int
3394 rte_eth_dev_callback_register(uint16_t port_id,
3395 enum rte_eth_event_type event,
3396 rte_eth_dev_cb_fn cb_fn, void *cb_arg)
3397 {
3398 struct rte_eth_dev *dev;
3399 struct rte_eth_dev_callback *user_cb;
3400 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */
3401 uint16_t last_port;
3402
3403 if (!cb_fn)
3404 return -EINVAL;
3405
3406 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) {
3407 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id);
3408 return -EINVAL;
3409 }
3410
3411 if (port_id == RTE_ETH_ALL) {
3412 next_port = 0;
3413 last_port = RTE_MAX_ETHPORTS - 1;
3414 } else {
3415 next_port = last_port = port_id;
3416 }
3417
3418 rte_spinlock_lock(&rte_eth_dev_cb_lock);
3419
3420 do {
3421 dev = &rte_eth_devices[next_port];
3422
3423 TAILQ_FOREACH(user_cb, &(dev->link_intr_cbs), next) {
3424 if (user_cb->cb_fn == cb_fn &&
3425 user_cb->cb_arg == cb_arg &&
3426 user_cb->event == event) {
3427 break;
3428 }
3429 }
3430
3431 /* create a new callback. */
3432 if (user_cb == NULL) {
3433 user_cb = rte_zmalloc("INTR_USER_CALLBACK",
3434 sizeof(struct rte_eth_dev_callback), 0);
3435 if (user_cb != NULL) {
3436 user_cb->cb_fn = cb_fn;
3437 user_cb->cb_arg = cb_arg;
3438 user_cb->event = event;
3439 TAILQ_INSERT_TAIL(&(dev->link_intr_cbs),
3440 user_cb, next);
3441 } else {
3442 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
3443 rte_eth_dev_callback_unregister(port_id, event,
3444 cb_fn, cb_arg);
3445 return -ENOMEM;
3446 }
3447
3448 }
3449 } while (++next_port <= last_port);
3450
3451 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
3452 return 0;
3453 }
3454
3455 int
3456 rte_eth_dev_callback_unregister(uint16_t port_id,
3457 enum rte_eth_event_type event,
3458 rte_eth_dev_cb_fn cb_fn, void *cb_arg)
3459 {
3460 int ret;
3461 struct rte_eth_dev *dev;
3462 struct rte_eth_dev_callback *cb, *next;
3463 uint32_t next_port; /* size is 32-bit to prevent loop wrap-around */
3464 uint16_t last_port;
3465
3466 if (!cb_fn)
3467 return -EINVAL;
3468
3469 if (!rte_eth_dev_is_valid_port(port_id) && port_id != RTE_ETH_ALL) {
3470 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%d\n", port_id);
3471 return -EINVAL;
3472 }
3473
3474 if (port_id == RTE_ETH_ALL) {
3475 next_port = 0;
3476 last_port = RTE_MAX_ETHPORTS - 1;
3477 } else {
3478 next_port = last_port = port_id;
3479 }
3480
3481 rte_spinlock_lock(&rte_eth_dev_cb_lock);
3482
3483 do {
3484 dev = &rte_eth_devices[next_port];
3485 ret = 0;
3486 for (cb = TAILQ_FIRST(&dev->link_intr_cbs); cb != NULL;
3487 cb = next) {
3488
3489 next = TAILQ_NEXT(cb, next);
3490
3491 if (cb->cb_fn != cb_fn || cb->event != event ||
3492 (cb->cb_arg != (void *)-1 && cb->cb_arg != cb_arg))
3493 continue;
3494
3495 /*
3496 * if this callback is not executing right now,
3497 * then remove it.
3498 */
3499 if (cb->active == 0) {
3500 TAILQ_REMOVE(&(dev->link_intr_cbs), cb, next);
3501 rte_free(cb);
3502 } else {
3503 ret = -EAGAIN;
3504 }
3505 }
3506 } while (++next_port <= last_port);
3507
3508 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
3509 return ret;
3510 }
3511
3512 int
3513 _rte_eth_dev_callback_process(struct rte_eth_dev *dev,
3514 enum rte_eth_event_type event, void *ret_param)
3515 {
3516 struct rte_eth_dev_callback *cb_lst;
3517 struct rte_eth_dev_callback dev_cb;
3518 int rc = 0;
3519
3520 rte_spinlock_lock(&rte_eth_dev_cb_lock);
3521 TAILQ_FOREACH(cb_lst, &(dev->link_intr_cbs), next) {
3522 if (cb_lst->cb_fn == NULL || cb_lst->event != event)
3523 continue;
3524 dev_cb = *cb_lst;
3525 cb_lst->active = 1;
3526 if (ret_param != NULL)
3527 dev_cb.ret_param = ret_param;
3528
3529 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
3530 rc = dev_cb.cb_fn(dev->data->port_id, dev_cb.event,
3531 dev_cb.cb_arg, dev_cb.ret_param);
3532 rte_spinlock_lock(&rte_eth_dev_cb_lock);
3533 cb_lst->active = 0;
3534 }
3535 rte_spinlock_unlock(&rte_eth_dev_cb_lock);
3536 return rc;
3537 }
3538
3539 void
3540 rte_eth_dev_probing_finish(struct rte_eth_dev *dev)
3541 {
3542 if (dev == NULL)
3543 return;
3544
3545 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_NEW, NULL);
3546
3547 dev->state = RTE_ETH_DEV_ATTACHED;
3548 }
3549
3550 int
3551 rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data)
3552 {
3553 uint32_t vec;
3554 struct rte_eth_dev *dev;
3555 struct rte_intr_handle *intr_handle;
3556 uint16_t qid;
3557 int rc;
3558
3559 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3560
3561 dev = &rte_eth_devices[port_id];
3562
3563 if (!dev->intr_handle) {
3564 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
3565 return -ENOTSUP;
3566 }
3567
3568 intr_handle = dev->intr_handle;
3569 if (!intr_handle->intr_vec) {
3570 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
3571 return -EPERM;
3572 }
3573
3574 for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
3575 vec = intr_handle->intr_vec[qid];
3576 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);
3577 if (rc && rc != -EEXIST) {
3578 RTE_ETHDEV_LOG(ERR,
3579 "p %u q %u rx ctl error op %d epfd %d vec %u\n",
3580 port_id, qid, op, epfd, vec);
3581 }
3582 }
3583
3584 return 0;
3585 }
3586
3587 int __rte_experimental
3588 rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id)
3589 {
3590 struct rte_intr_handle *intr_handle;
3591 struct rte_eth_dev *dev;
3592 unsigned int efd_idx;
3593 uint32_t vec;
3594 int fd;
3595
3596 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -1);
3597
3598 dev = &rte_eth_devices[port_id];
3599
3600 if (queue_id >= dev->data->nb_rx_queues) {
3601 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
3602 return -1;
3603 }
3604
3605 if (!dev->intr_handle) {
3606 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
3607 return -1;
3608 }
3609
3610 intr_handle = dev->intr_handle;
3611 if (!intr_handle->intr_vec) {
3612 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
3613 return -1;
3614 }
3615
3616 vec = intr_handle->intr_vec[queue_id];
3617 efd_idx = (vec >= RTE_INTR_VEC_RXTX_OFFSET) ?
3618 (vec - RTE_INTR_VEC_RXTX_OFFSET) : vec;
3619 fd = intr_handle->efds[efd_idx];
3620
3621 return fd;
3622 }
3623
3624 const struct rte_memzone *
3625 rte_eth_dma_zone_reserve(const struct rte_eth_dev *dev, const char *ring_name,
3626 uint16_t queue_id, size_t size, unsigned align,
3627 int socket_id)
3628 {
3629 char z_name[RTE_MEMZONE_NAMESIZE];
3630 const struct rte_memzone *mz;
3631 int rc;
3632
3633 rc = snprintf(z_name, sizeof(z_name), "eth_p%d_q%d_%s",
3634 dev->data->port_id, queue_id, ring_name);
3635 if (rc >= RTE_MEMZONE_NAMESIZE) {
3636 RTE_ETHDEV_LOG(ERR, "ring name too long\n");
3637 rte_errno = ENAMETOOLONG;
3638 return NULL;
3639 }
3640
3641 mz = rte_memzone_lookup(z_name);
3642 if (mz)
3643 return mz;
3644
3645 return rte_memzone_reserve_aligned(z_name, size, socket_id,
3646 RTE_MEMZONE_IOVA_CONTIG, align);
3647 }
3648
3649 int __rte_experimental
3650 rte_eth_dev_create(struct rte_device *device, const char *name,
3651 size_t priv_data_size,
3652 ethdev_bus_specific_init ethdev_bus_specific_init,
3653 void *bus_init_params,
3654 ethdev_init_t ethdev_init, void *init_params)
3655 {
3656 struct rte_eth_dev *ethdev;
3657 int retval;
3658
3659 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_init, -EINVAL);
3660
3661 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3662 ethdev = rte_eth_dev_allocate(name);
3663 if (!ethdev)
3664 return -ENODEV;
3665
3666 if (priv_data_size) {
3667 ethdev->data->dev_private = rte_zmalloc_socket(
3668 name, priv_data_size, RTE_CACHE_LINE_SIZE,
3669 device->numa_node);
3670
3671 if (!ethdev->data->dev_private) {
3672 RTE_LOG(ERR, EAL, "failed to allocate private data");
3673 retval = -ENOMEM;
3674 goto probe_failed;
3675 }
3676 }
3677 } else {
3678 ethdev = rte_eth_dev_attach_secondary(name);
3679 if (!ethdev) {
3680 RTE_LOG(ERR, EAL, "secondary process attach failed, "
3681 "ethdev doesn't exist");
3682 return -ENODEV;
3683 }
3684 }
3685
3686 ethdev->device = device;
3687
3688 if (ethdev_bus_specific_init) {
3689 retval = ethdev_bus_specific_init(ethdev, bus_init_params);
3690 if (retval) {
3691 RTE_LOG(ERR, EAL,
3692 "ethdev bus specific initialisation failed");
3693 goto probe_failed;
3694 }
3695 }
3696
3697 retval = ethdev_init(ethdev, init_params);
3698 if (retval) {
3699 RTE_LOG(ERR, EAL, "ethdev initialisation failed");
3700 goto probe_failed;
3701 }
3702
3703 rte_eth_dev_probing_finish(ethdev);
3704
3705 return retval;
3706
3707 probe_failed:
3708 rte_eth_dev_release_port(ethdev);
3709 return retval;
3710 }
3711
3712 int __rte_experimental
3713 rte_eth_dev_destroy(struct rte_eth_dev *ethdev,
3714 ethdev_uninit_t ethdev_uninit)
3715 {
3716 int ret;
3717
3718 ethdev = rte_eth_dev_allocated(ethdev->data->name);
3719 if (!ethdev)
3720 return -ENODEV;
3721
3722 RTE_FUNC_PTR_OR_ERR_RET(*ethdev_uninit, -EINVAL);
3723
3724 ret = ethdev_uninit(ethdev);
3725 if (ret)
3726 return ret;
3727
3728 return rte_eth_dev_release_port(ethdev);
3729 }
3730
3731 int
3732 rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id,
3733 int epfd, int op, void *data)
3734 {
3735 uint32_t vec;
3736 struct rte_eth_dev *dev;
3737 struct rte_intr_handle *intr_handle;
3738 int rc;
3739
3740 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3741
3742 dev = &rte_eth_devices[port_id];
3743 if (queue_id >= dev->data->nb_rx_queues) {
3744 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
3745 return -EINVAL;
3746 }
3747
3748 if (!dev->intr_handle) {
3749 RTE_ETHDEV_LOG(ERR, "RX Intr handle unset\n");
3750 return -ENOTSUP;
3751 }
3752
3753 intr_handle = dev->intr_handle;
3754 if (!intr_handle->intr_vec) {
3755 RTE_ETHDEV_LOG(ERR, "RX Intr vector unset\n");
3756 return -EPERM;
3757 }
3758
3759 vec = intr_handle->intr_vec[queue_id];
3760 rc = rte_intr_rx_ctl(intr_handle, epfd, op, vec, data);
3761 if (rc && rc != -EEXIST) {
3762 RTE_ETHDEV_LOG(ERR,
3763 "p %u q %u rx ctl error op %d epfd %d vec %u\n",
3764 port_id, queue_id, op, epfd, vec);
3765 return rc;
3766 }
3767
3768 return 0;
3769 }
3770
3771 int
3772 rte_eth_dev_rx_intr_enable(uint16_t port_id,
3773 uint16_t queue_id)
3774 {
3775 struct rte_eth_dev *dev;
3776
3777 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3778
3779 dev = &rte_eth_devices[port_id];
3780
3781 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_enable, -ENOTSUP);
3782 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_enable)(dev,
3783 queue_id));
3784 }
3785
3786 int
3787 rte_eth_dev_rx_intr_disable(uint16_t port_id,
3788 uint16_t queue_id)
3789 {
3790 struct rte_eth_dev *dev;
3791
3792 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3793
3794 dev = &rte_eth_devices[port_id];
3795
3796 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_intr_disable, -ENOTSUP);
3797 return eth_err(port_id, (*dev->dev_ops->rx_queue_intr_disable)(dev,
3798 queue_id));
3799 }
3800
3801
3802 int
3803 rte_eth_dev_filter_supported(uint16_t port_id,
3804 enum rte_filter_type filter_type)
3805 {
3806 struct rte_eth_dev *dev;
3807
3808 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3809
3810 dev = &rte_eth_devices[port_id];
3811 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP);
3812 return (*dev->dev_ops->filter_ctrl)(dev, filter_type,
3813 RTE_ETH_FILTER_NOP, NULL);
3814 }
3815
3816 int
3817 rte_eth_dev_filter_ctrl(uint16_t port_id, enum rte_filter_type filter_type,
3818 enum rte_filter_op filter_op, void *arg)
3819 {
3820 struct rte_eth_dev *dev;
3821
3822 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3823
3824 dev = &rte_eth_devices[port_id];
3825 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->filter_ctrl, -ENOTSUP);
3826 return eth_err(port_id, (*dev->dev_ops->filter_ctrl)(dev, filter_type,
3827 filter_op, arg));
3828 }
3829
3830 const struct rte_eth_rxtx_callback *
3831 rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id,
3832 rte_rx_callback_fn fn, void *user_param)
3833 {
3834 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
3835 rte_errno = ENOTSUP;
3836 return NULL;
3837 #endif
3838 /* check input parameters */
3839 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
3840 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {
3841 rte_errno = EINVAL;
3842 return NULL;
3843 }
3844 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
3845
3846 if (cb == NULL) {
3847 rte_errno = ENOMEM;
3848 return NULL;
3849 }
3850
3851 cb->fn.rx = fn;
3852 cb->param = user_param;
3853
3854 rte_spinlock_lock(&rte_eth_rx_cb_lock);
3855 /* Add the callbacks in fifo order. */
3856 struct rte_eth_rxtx_callback *tail =
3857 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id];
3858
3859 if (!tail) {
3860 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id] = cb;
3861
3862 } else {
3863 while (tail->next)
3864 tail = tail->next;
3865 tail->next = cb;
3866 }
3867 rte_spinlock_unlock(&rte_eth_rx_cb_lock);
3868
3869 return cb;
3870 }
3871
3872 const struct rte_eth_rxtx_callback *
3873 rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id,
3874 rte_rx_callback_fn fn, void *user_param)
3875 {
3876 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
3877 rte_errno = ENOTSUP;
3878 return NULL;
3879 #endif
3880 /* check input parameters */
3881 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
3882 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues) {
3883 rte_errno = EINVAL;
3884 return NULL;
3885 }
3886
3887 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
3888
3889 if (cb == NULL) {
3890 rte_errno = ENOMEM;
3891 return NULL;
3892 }
3893
3894 cb->fn.rx = fn;
3895 cb->param = user_param;
3896
3897 rte_spinlock_lock(&rte_eth_rx_cb_lock);
3898 /* Add the callbacks at fisrt position*/
3899 cb->next = rte_eth_devices[port_id].post_rx_burst_cbs[queue_id];
3900 rte_smp_wmb();
3901 rte_eth_devices[port_id].post_rx_burst_cbs[queue_id] = cb;
3902 rte_spinlock_unlock(&rte_eth_rx_cb_lock);
3903
3904 return cb;
3905 }
3906
3907 const struct rte_eth_rxtx_callback *
3908 rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id,
3909 rte_tx_callback_fn fn, void *user_param)
3910 {
3911 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
3912 rte_errno = ENOTSUP;
3913 return NULL;
3914 #endif
3915 /* check input parameters */
3916 if (!rte_eth_dev_is_valid_port(port_id) || fn == NULL ||
3917 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues) {
3918 rte_errno = EINVAL;
3919 return NULL;
3920 }
3921
3922 struct rte_eth_rxtx_callback *cb = rte_zmalloc(NULL, sizeof(*cb), 0);
3923
3924 if (cb == NULL) {
3925 rte_errno = ENOMEM;
3926 return NULL;
3927 }
3928
3929 cb->fn.tx = fn;
3930 cb->param = user_param;
3931
3932 rte_spinlock_lock(&rte_eth_tx_cb_lock);
3933 /* Add the callbacks in fifo order. */
3934 struct rte_eth_rxtx_callback *tail =
3935 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id];
3936
3937 if (!tail) {
3938 rte_eth_devices[port_id].pre_tx_burst_cbs[queue_id] = cb;
3939
3940 } else {
3941 while (tail->next)
3942 tail = tail->next;
3943 tail->next = cb;
3944 }
3945 rte_spinlock_unlock(&rte_eth_tx_cb_lock);
3946
3947 return cb;
3948 }
3949
3950 int
3951 rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id,
3952 const struct rte_eth_rxtx_callback *user_cb)
3953 {
3954 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
3955 return -ENOTSUP;
3956 #endif
3957 /* Check input parameters. */
3958 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
3959 if (user_cb == NULL ||
3960 queue_id >= rte_eth_devices[port_id].data->nb_rx_queues)
3961 return -EINVAL;
3962
3963 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3964 struct rte_eth_rxtx_callback *cb;
3965 struct rte_eth_rxtx_callback **prev_cb;
3966 int ret = -EINVAL;
3967
3968 rte_spinlock_lock(&rte_eth_rx_cb_lock);
3969 prev_cb = &dev->post_rx_burst_cbs[queue_id];
3970 for (; *prev_cb != NULL; prev_cb = &cb->next) {
3971 cb = *prev_cb;
3972 if (cb == user_cb) {
3973 /* Remove the user cb from the callback list. */
3974 *prev_cb = cb->next;
3975 ret = 0;
3976 break;
3977 }
3978 }
3979 rte_spinlock_unlock(&rte_eth_rx_cb_lock);
3980
3981 return ret;
3982 }
3983
3984 int
3985 rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id,
3986 const struct rte_eth_rxtx_callback *user_cb)
3987 {
3988 #ifndef RTE_ETHDEV_RXTX_CALLBACKS
3989 return -ENOTSUP;
3990 #endif
3991 /* Check input parameters. */
3992 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
3993 if (user_cb == NULL ||
3994 queue_id >= rte_eth_devices[port_id].data->nb_tx_queues)
3995 return -EINVAL;
3996
3997 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3998 int ret = -EINVAL;
3999 struct rte_eth_rxtx_callback *cb;
4000 struct rte_eth_rxtx_callback **prev_cb;
4001
4002 rte_spinlock_lock(&rte_eth_tx_cb_lock);
4003 prev_cb = &dev->pre_tx_burst_cbs[queue_id];
4004 for (; *prev_cb != NULL; prev_cb = &cb->next) {
4005 cb = *prev_cb;
4006 if (cb == user_cb) {
4007 /* Remove the user cb from the callback list. */
4008 *prev_cb = cb->next;
4009 ret = 0;
4010 break;
4011 }
4012 }
4013 rte_spinlock_unlock(&rte_eth_tx_cb_lock);
4014
4015 return ret;
4016 }
4017
4018 int
4019 rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id,
4020 struct rte_eth_rxq_info *qinfo)
4021 {
4022 struct rte_eth_dev *dev;
4023
4024 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4025
4026 if (qinfo == NULL)
4027 return -EINVAL;
4028
4029 dev = &rte_eth_devices[port_id];
4030 if (queue_id >= dev->data->nb_rx_queues) {
4031 RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
4032 return -EINVAL;
4033 }
4034
4035 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rxq_info_get, -ENOTSUP);
4036
4037 memset(qinfo, 0, sizeof(*qinfo));
4038 dev->dev_ops->rxq_info_get(dev, queue_id, qinfo);
4039 return 0;
4040 }
4041
4042 int
4043 rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id,
4044 struct rte_eth_txq_info *qinfo)
4045 {
4046 struct rte_eth_dev *dev;
4047
4048 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4049
4050 if (qinfo == NULL)
4051 return -EINVAL;
4052
4053 dev = &rte_eth_devices[port_id];
4054 if (queue_id >= dev->data->nb_tx_queues) {
4055 RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id);
4056 return -EINVAL;
4057 }
4058
4059 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->txq_info_get, -ENOTSUP);
4060
4061 memset(qinfo, 0, sizeof(*qinfo));
4062 dev->dev_ops->txq_info_get(dev, queue_id, qinfo);
4063
4064 return 0;
4065 }
4066
4067 int
4068 rte_eth_dev_set_mc_addr_list(uint16_t port_id,
4069 struct ether_addr *mc_addr_set,
4070 uint32_t nb_mc_addr)
4071 {
4072 struct rte_eth_dev *dev;
4073
4074 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4075
4076 dev = &rte_eth_devices[port_id];
4077 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_mc_addr_list, -ENOTSUP);
4078 return eth_err(port_id, dev->dev_ops->set_mc_addr_list(dev,
4079 mc_addr_set, nb_mc_addr));
4080 }
4081
4082 int
4083 rte_eth_timesync_enable(uint16_t port_id)
4084 {
4085 struct rte_eth_dev *dev;
4086
4087 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4088 dev = &rte_eth_devices[port_id];
4089
4090 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_enable, -ENOTSUP);
4091 return eth_err(port_id, (*dev->dev_ops->timesync_enable)(dev));
4092 }
4093
4094 int
4095 rte_eth_timesync_disable(uint16_t port_id)
4096 {
4097 struct rte_eth_dev *dev;
4098
4099 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4100 dev = &rte_eth_devices[port_id];
4101
4102 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_disable, -ENOTSUP);
4103 return eth_err(port_id, (*dev->dev_ops->timesync_disable)(dev));
4104 }
4105
4106 int
4107 rte_eth_timesync_read_rx_timestamp(uint16_t port_id, struct timespec *timestamp,
4108 uint32_t flags)
4109 {
4110 struct rte_eth_dev *dev;
4111
4112 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4113 dev = &rte_eth_devices[port_id];
4114
4115 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_rx_timestamp, -ENOTSUP);
4116 return eth_err(port_id, (*dev->dev_ops->timesync_read_rx_timestamp)
4117 (dev, timestamp, flags));
4118 }
4119
4120 int
4121 rte_eth_timesync_read_tx_timestamp(uint16_t port_id,
4122 struct timespec *timestamp)
4123 {
4124 struct rte_eth_dev *dev;
4125
4126 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4127 dev = &rte_eth_devices[port_id];
4128
4129 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_tx_timestamp, -ENOTSUP);
4130 return eth_err(port_id, (*dev->dev_ops->timesync_read_tx_timestamp)
4131 (dev, timestamp));
4132 }
4133
4134 int
4135 rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta)
4136 {
4137 struct rte_eth_dev *dev;
4138
4139 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4140 dev = &rte_eth_devices[port_id];
4141
4142 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_adjust_time, -ENOTSUP);
4143 return eth_err(port_id, (*dev->dev_ops->timesync_adjust_time)(dev,
4144 delta));
4145 }
4146
4147 int
4148 rte_eth_timesync_read_time(uint16_t port_id, struct timespec *timestamp)
4149 {
4150 struct rte_eth_dev *dev;
4151
4152 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4153 dev = &rte_eth_devices[port_id];
4154
4155 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_read_time, -ENOTSUP);
4156 return eth_err(port_id, (*dev->dev_ops->timesync_read_time)(dev,
4157 timestamp));
4158 }
4159
4160 int
4161 rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *timestamp)
4162 {
4163 struct rte_eth_dev *dev;
4164
4165 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4166 dev = &rte_eth_devices[port_id];
4167
4168 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->timesync_write_time, -ENOTSUP);
4169 return eth_err(port_id, (*dev->dev_ops->timesync_write_time)(dev,
4170 timestamp));
4171 }
4172
4173 int
4174 rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info)
4175 {
4176 struct rte_eth_dev *dev;
4177
4178 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4179
4180 dev = &rte_eth_devices[port_id];
4181 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_reg, -ENOTSUP);
4182 return eth_err(port_id, (*dev->dev_ops->get_reg)(dev, info));
4183 }
4184
4185 int
4186 rte_eth_dev_get_eeprom_length(uint16_t port_id)
4187 {
4188 struct rte_eth_dev *dev;
4189
4190 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4191
4192 dev = &rte_eth_devices[port_id];
4193 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom_length, -ENOTSUP);
4194 return eth_err(port_id, (*dev->dev_ops->get_eeprom_length)(dev));
4195 }
4196
4197 int
4198 rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
4199 {
4200 struct rte_eth_dev *dev;
4201
4202 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4203
4204 dev = &rte_eth_devices[port_id];
4205 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_eeprom, -ENOTSUP);
4206 return eth_err(port_id, (*dev->dev_ops->get_eeprom)(dev, info));
4207 }
4208
4209 int
4210 rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info)
4211 {
4212 struct rte_eth_dev *dev;
4213
4214 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4215
4216 dev = &rte_eth_devices[port_id];
4217 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->set_eeprom, -ENOTSUP);
4218 return eth_err(port_id, (*dev->dev_ops->set_eeprom)(dev, info));
4219 }
4220
4221 int __rte_experimental
4222 rte_eth_dev_get_module_info(uint16_t port_id,
4223 struct rte_eth_dev_module_info *modinfo)
4224 {
4225 struct rte_eth_dev *dev;
4226
4227 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4228
4229 dev = &rte_eth_devices[port_id];
4230 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_info, -ENOTSUP);
4231 return (*dev->dev_ops->get_module_info)(dev, modinfo);
4232 }
4233
4234 int __rte_experimental
4235 rte_eth_dev_get_module_eeprom(uint16_t port_id,
4236 struct rte_dev_eeprom_info *info)
4237 {
4238 struct rte_eth_dev *dev;
4239
4240 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4241
4242 dev = &rte_eth_devices[port_id];
4243 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_module_eeprom, -ENOTSUP);
4244 return (*dev->dev_ops->get_module_eeprom)(dev, info);
4245 }
4246
4247 int
4248 rte_eth_dev_get_dcb_info(uint16_t port_id,
4249 struct rte_eth_dcb_info *dcb_info)
4250 {
4251 struct rte_eth_dev *dev;
4252
4253 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4254
4255 dev = &rte_eth_devices[port_id];
4256 memset(dcb_info, 0, sizeof(struct rte_eth_dcb_info));
4257
4258 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->get_dcb_info, -ENOTSUP);
4259 return eth_err(port_id, (*dev->dev_ops->get_dcb_info)(dev, dcb_info));
4260 }
4261
4262 int
4263 rte_eth_dev_l2_tunnel_eth_type_conf(uint16_t port_id,
4264 struct rte_eth_l2_tunnel_conf *l2_tunnel)
4265 {
4266 struct rte_eth_dev *dev;
4267
4268 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4269 if (l2_tunnel == NULL) {
4270 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n");
4271 return -EINVAL;
4272 }
4273
4274 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) {
4275 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
4276 return -EINVAL;
4277 }
4278
4279 dev = &rte_eth_devices[port_id];
4280 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_eth_type_conf,
4281 -ENOTSUP);
4282 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_eth_type_conf)(dev,
4283 l2_tunnel));
4284 }
4285
4286 int
4287 rte_eth_dev_l2_tunnel_offload_set(uint16_t port_id,
4288 struct rte_eth_l2_tunnel_conf *l2_tunnel,
4289 uint32_t mask,
4290 uint8_t en)
4291 {
4292 struct rte_eth_dev *dev;
4293
4294 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4295
4296 if (l2_tunnel == NULL) {
4297 RTE_ETHDEV_LOG(ERR, "Invalid l2_tunnel parameter\n");
4298 return -EINVAL;
4299 }
4300
4301 if (l2_tunnel->l2_tunnel_type >= RTE_TUNNEL_TYPE_MAX) {
4302 RTE_ETHDEV_LOG(ERR, "Invalid tunnel type\n");
4303 return -EINVAL;
4304 }
4305
4306 if (mask == 0) {
4307 RTE_ETHDEV_LOG(ERR, "Mask should have a value\n");
4308 return -EINVAL;
4309 }
4310
4311 dev = &rte_eth_devices[port_id];
4312 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->l2_tunnel_offload_set,
4313 -ENOTSUP);
4314 return eth_err(port_id, (*dev->dev_ops->l2_tunnel_offload_set)(dev,
4315 l2_tunnel, mask, en));
4316 }
4317
4318 static void
4319 rte_eth_dev_adjust_nb_desc(uint16_t *nb_desc,
4320 const struct rte_eth_desc_lim *desc_lim)
4321 {
4322 if (desc_lim->nb_align != 0)
4323 *nb_desc = RTE_ALIGN_CEIL(*nb_desc, desc_lim->nb_align);
4324
4325 if (desc_lim->nb_max != 0)
4326 *nb_desc = RTE_MIN(*nb_desc, desc_lim->nb_max);
4327
4328 *nb_desc = RTE_MAX(*nb_desc, desc_lim->nb_min);
4329 }
4330
4331 int
4332 rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id,
4333 uint16_t *nb_rx_desc,
4334 uint16_t *nb_tx_desc)
4335 {
4336 struct rte_eth_dev *dev;
4337 struct rte_eth_dev_info dev_info;
4338
4339 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4340
4341 dev = &rte_eth_devices[port_id];
4342 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->dev_infos_get, -ENOTSUP);
4343
4344 rte_eth_dev_info_get(port_id, &dev_info);
4345
4346 if (nb_rx_desc != NULL)
4347 rte_eth_dev_adjust_nb_desc(nb_rx_desc, &dev_info.rx_desc_lim);
4348
4349 if (nb_tx_desc != NULL)
4350 rte_eth_dev_adjust_nb_desc(nb_tx_desc, &dev_info.tx_desc_lim);
4351
4352 return 0;
4353 }
4354
4355 int
4356 rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool)
4357 {
4358 struct rte_eth_dev *dev;
4359
4360 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4361
4362 if (pool == NULL)
4363 return -EINVAL;
4364
4365 dev = &rte_eth_devices[port_id];
4366
4367 if (*dev->dev_ops->pool_ops_supported == NULL)
4368 return 1; /* all pools are supported */
4369
4370 return (*dev->dev_ops->pool_ops_supported)(dev, pool);
4371 }
4372
4373 /**
4374 * A set of values to describe the possible states of a switch domain.
4375 */
4376 enum rte_eth_switch_domain_state {
4377 RTE_ETH_SWITCH_DOMAIN_UNUSED = 0,
4378 RTE_ETH_SWITCH_DOMAIN_ALLOCATED
4379 };
4380
4381 /**
4382 * Array of switch domains available for allocation. Array is sized to
4383 * RTE_MAX_ETHPORTS elements as there cannot be more active switch domains than
4384 * ethdev ports in a single process.
4385 */
4386 static struct rte_eth_dev_switch {
4387 enum rte_eth_switch_domain_state state;
4388 } rte_eth_switch_domains[RTE_MAX_ETHPORTS];
4389
4390 int __rte_experimental
4391 rte_eth_switch_domain_alloc(uint16_t *domain_id)
4392 {
4393 unsigned int i;
4394
4395 *domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
4396
4397 for (i = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID + 1;
4398 i < RTE_MAX_ETHPORTS; i++) {
4399 if (rte_eth_switch_domains[i].state ==
4400 RTE_ETH_SWITCH_DOMAIN_UNUSED) {
4401 rte_eth_switch_domains[i].state =
4402 RTE_ETH_SWITCH_DOMAIN_ALLOCATED;
4403 *domain_id = i;
4404 return 0;
4405 }
4406 }
4407
4408 return -ENOSPC;
4409 }
4410
4411 int __rte_experimental
4412 rte_eth_switch_domain_free(uint16_t domain_id)
4413 {
4414 if (domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID ||
4415 domain_id >= RTE_MAX_ETHPORTS)
4416 return -EINVAL;
4417
4418 if (rte_eth_switch_domains[domain_id].state !=
4419 RTE_ETH_SWITCH_DOMAIN_ALLOCATED)
4420 return -EINVAL;
4421
4422 rte_eth_switch_domains[domain_id].state = RTE_ETH_SWITCH_DOMAIN_UNUSED;
4423
4424 return 0;
4425 }
4426
4427 static int
4428 rte_eth_devargs_tokenise(struct rte_kvargs *arglist, const char *str_in)
4429 {
4430 int state;
4431 struct rte_kvargs_pair *pair;
4432 char *letter;
4433
4434 arglist->str = strdup(str_in);
4435 if (arglist->str == NULL)
4436 return -ENOMEM;
4437
4438 letter = arglist->str;
4439 state = 0;
4440 arglist->count = 0;
4441 pair = &arglist->pairs[0];
4442 while (1) {
4443 switch (state) {
4444 case 0: /* Initial */
4445 if (*letter == '=')
4446 return -EINVAL;
4447 else if (*letter == '\0')
4448 return 0;
4449
4450 state = 1;
4451 pair->key = letter;
4452 /* fall-thru */
4453
4454 case 1: /* Parsing key */
4455 if (*letter == '=') {
4456 *letter = '\0';
4457 pair->value = letter + 1;
4458 state = 2;
4459 } else if (*letter == ',' || *letter == '\0')
4460 return -EINVAL;
4461 break;
4462
4463
4464 case 2: /* Parsing value */
4465 if (*letter == '[')
4466 state = 3;
4467 else if (*letter == ',') {
4468 *letter = '\0';
4469 arglist->count++;
4470 pair = &arglist->pairs[arglist->count];
4471 state = 0;
4472 } else if (*letter == '\0') {
4473 letter--;
4474 arglist->count++;
4475 pair = &arglist->pairs[arglist->count];
4476 state = 0;
4477 }
4478 break;
4479
4480 case 3: /* Parsing list */
4481 if (*letter == ']')
4482 state = 2;
4483 else if (*letter == '\0')
4484 return -EINVAL;
4485 break;
4486 }
4487 letter++;
4488 }
4489 }
4490
4491 int __rte_experimental
4492 rte_eth_devargs_parse(const char *dargs, struct rte_eth_devargs *eth_da)
4493 {
4494 struct rte_kvargs args;
4495 struct rte_kvargs_pair *pair;
4496 unsigned int i;
4497 int result = 0;
4498
4499 memset(eth_da, 0, sizeof(*eth_da));
4500
4501 result = rte_eth_devargs_tokenise(&args, dargs);
4502 if (result < 0)
4503 goto parse_cleanup;
4504
4505 for (i = 0; i < args.count; i++) {
4506 pair = &args.pairs[i];
4507 if (strcmp("representor", pair->key) == 0) {
4508 result = rte_eth_devargs_parse_list(pair->value,
4509 rte_eth_devargs_parse_representor_ports,
4510 eth_da);
4511 if (result < 0)
4512 goto parse_cleanup;
4513 }
4514 }
4515
4516 parse_cleanup:
4517 if (args.str)
4518 free(args.str);
4519
4520 return result;
4521 }
4522
4523 RTE_INIT(ethdev_init_log)
4524 {
4525 rte_eth_dev_logtype = rte_log_register("lib.ethdev");
4526 if (rte_eth_dev_logtype >= 0)
4527 rte_log_set_level(rte_eth_dev_logtype, RTE_LOG_INFO);
4528 }
Ceph