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1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
3 */
4
5 #include <stdbool.h>
6
7 #include <rte_crypto.h>
8 #include <rte_cryptodev.h>
9 #include <rte_cycles.h>
10 #include <rte_malloc.h>
11
12 #include "cperf_ops.h"
13 #include "cperf_test_pmd_cyclecount.h"
14 #include "cperf_test_common.h"
15
16 #define PRETTY_HDR_FMT "%12s%12s%12s%12s%12s%12s%12s%12s%12s%12s\n\n"
17 #define PRETTY_LINE_FMT "%12u%12u%12u%12u%12u%12u%12u%12.0f%12.0f%12.0f\n"
18 #define CSV_HDR_FMT "%s,%s,%s,%s,%s,%s,%s,%s,%s,%s\n"
19 #define CSV_LINE_FMT "%10u;%10u;%u;%u;%u;%u;%u;%.f3;%.f3;%.f3\n"
20
21 struct cperf_pmd_cyclecount_ctx {
22 uint8_t dev_id;
23 uint16_t qp_id;
24 uint8_t lcore_id;
25
26 struct rte_mempool *pool;
27 struct rte_crypto_op **ops;
28 struct rte_crypto_op **ops_processed;
29
30 struct rte_cryptodev_sym_session *sess;
31
32 cperf_populate_ops_t populate_ops;
33
34 uint32_t src_buf_offset;
35 uint32_t dst_buf_offset;
36
37 const struct cperf_options *options;
38 const struct cperf_test_vector *test_vector;
39 };
40
41 struct pmd_cyclecount_state {
42 struct cperf_pmd_cyclecount_ctx *ctx;
43 const struct cperf_options *opts;
44 uint32_t lcore;
45 uint64_t delay;
46 int linearize;
47 uint32_t ops_enqd;
48 uint32_t ops_deqd;
49 uint32_t ops_enq_retries;
50 uint32_t ops_deq_retries;
51 double cycles_per_build;
52 double cycles_per_enq;
53 double cycles_per_deq;
54 };
55
56 static const uint16_t iv_offset =
57 sizeof(struct rte_crypto_op) + sizeof(struct rte_crypto_sym_op);
58
59 static void
60 cperf_pmd_cyclecount_test_free(struct cperf_pmd_cyclecount_ctx *ctx)
61 {
62 if (ctx) {
63 if (ctx->sess) {
64 rte_cryptodev_sym_session_clear(ctx->dev_id, ctx->sess);
65 rte_cryptodev_sym_session_free(ctx->sess);
66 }
67
68 if (ctx->pool)
69 rte_mempool_free(ctx->pool);
70
71 if (ctx->ops)
72 rte_free(ctx->ops);
73
74 if (ctx->ops_processed)
75 rte_free(ctx->ops_processed);
76
77 rte_free(ctx);
78 }
79 }
80
81 void *
82 cperf_pmd_cyclecount_test_constructor(struct rte_mempool *sess_mp,
83 uint8_t dev_id, uint16_t qp_id,
84 const struct cperf_options *options,
85 const struct cperf_test_vector *test_vector,
86 const struct cperf_op_fns *op_fns)
87 {
88 struct cperf_pmd_cyclecount_ctx *ctx = NULL;
89
90 /* preallocate buffers for crypto ops as they can get quite big */
91 size_t alloc_sz = sizeof(struct rte_crypto_op *) *
92 options->nb_descriptors;
93
94 ctx = rte_malloc(NULL, sizeof(struct cperf_pmd_cyclecount_ctx), 0);
95 if (ctx == NULL)
96 goto err;
97
98 ctx->dev_id = dev_id;
99 ctx->qp_id = qp_id;
100
101 ctx->populate_ops = op_fns->populate_ops;
102 ctx->options = options;
103 ctx->test_vector = test_vector;
104
105 /* IV goes at the end of the crypto operation */
106 uint16_t iv_offset = sizeof(struct rte_crypto_op) +
107 sizeof(struct rte_crypto_sym_op);
108
109 ctx->sess = op_fns->sess_create(
110 sess_mp, dev_id, options, test_vector, iv_offset);
111 if (ctx->sess == NULL)
112 goto err;
113
114 if (cperf_alloc_common_memory(options, test_vector, dev_id, qp_id, 0,
115 &ctx->src_buf_offset, &ctx->dst_buf_offset,
116 &ctx->pool) < 0)
117 goto err;
118
119 ctx->ops = rte_malloc("ops", alloc_sz, 0);
120 if (!ctx->ops)
121 goto err;
122
123 ctx->ops_processed = rte_malloc("ops_processed", alloc_sz, 0);
124 if (!ctx->ops_processed)
125 goto err;
126
127 return ctx;
128
129 err:
130 cperf_pmd_cyclecount_test_free(ctx);
131
132 return NULL;
133 }
134
135 /* benchmark alloc-build-free of ops */
136 static inline int
137 pmd_cyclecount_bench_ops(struct pmd_cyclecount_state *state, uint32_t cur_op,
138 uint16_t test_burst_size)
139 {
140 uint32_t iter_ops_left = state->opts->total_ops - cur_op;
141 uint32_t iter_ops_needed =
142 RTE_MIN(state->opts->nb_descriptors, iter_ops_left);
143 uint32_t cur_iter_op;
144 uint32_t imix_idx = 0;
145
146 for (cur_iter_op = 0; cur_iter_op < iter_ops_needed;
147 cur_iter_op += test_burst_size) {
148 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op,
149 test_burst_size);
150 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op];
151
152 /* Allocate objects containing crypto operations and mbufs */
153 if (rte_mempool_get_bulk(state->ctx->pool, (void **)ops,
154 burst_size) != 0) {
155 RTE_LOG(ERR, USER1,
156 "Failed to allocate more crypto operations "
157 "from the crypto operation pool.\n"
158 "Consider increasing the pool size "
159 "with --pool-sz\n");
160 return -1;
161 }
162
163 /* Setup crypto op, attach mbuf etc */
164 (state->ctx->populate_ops)(ops,
165 state->ctx->src_buf_offset,
166 state->ctx->dst_buf_offset,
167 burst_size,
168 state->ctx->sess, state->opts,
169 state->ctx->test_vector, iv_offset,
170 &imix_idx);
171
172 #ifdef CPERF_LINEARIZATION_ENABLE
173 /* Check if source mbufs require coalescing */
174 if (state->linearize) {
175 uint8_t i;
176 for (i = 0; i < burst_size; i++) {
177 struct rte_mbuf *src = ops[i]->sym->m_src;
178 rte_pktmbuf_linearize(src);
179 }
180 }
181 #endif /* CPERF_LINEARIZATION_ENABLE */
182 rte_mempool_put_bulk(state->ctx->pool, (void **)ops,
183 burst_size);
184 }
185
186 return 0;
187 }
188
189 /* allocate and build ops (no free) */
190 static int
191 pmd_cyclecount_build_ops(struct pmd_cyclecount_state *state,
192 uint32_t iter_ops_needed, uint16_t test_burst_size)
193 {
194 uint32_t cur_iter_op;
195 uint32_t imix_idx = 0;
196
197 for (cur_iter_op = 0; cur_iter_op < iter_ops_needed;
198 cur_iter_op += test_burst_size) {
199 uint32_t burst_size = RTE_MIN(
200 iter_ops_needed - cur_iter_op, test_burst_size);
201 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op];
202
203 /* Allocate objects containing crypto operations and mbufs */
204 if (rte_mempool_get_bulk(state->ctx->pool, (void **)ops,
205 burst_size) != 0) {
206 RTE_LOG(ERR, USER1,
207 "Failed to allocate more crypto operations "
208 "from the crypto operation pool.\n"
209 "Consider increasing the pool size "
210 "with --pool-sz\n");
211 return -1;
212 }
213
214 /* Setup crypto op, attach mbuf etc */
215 (state->ctx->populate_ops)(ops,
216 state->ctx->src_buf_offset,
217 state->ctx->dst_buf_offset,
218 burst_size,
219 state->ctx->sess, state->opts,
220 state->ctx->test_vector, iv_offset,
221 &imix_idx);
222 }
223 return 0;
224 }
225
226 /* benchmark enqueue, returns number of ops enqueued */
227 static uint32_t
228 pmd_cyclecount_bench_enq(struct pmd_cyclecount_state *state,
229 uint32_t iter_ops_needed, uint16_t test_burst_size)
230 {
231 /* Enqueue full descriptor ring of ops on crypto device */
232 uint32_t cur_iter_op = 0;
233 while (cur_iter_op < iter_ops_needed) {
234 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op,
235 test_burst_size);
236 struct rte_crypto_op **ops = &state->ctx->ops[cur_iter_op];
237 uint32_t burst_enqd;
238
239 burst_enqd = rte_cryptodev_enqueue_burst(state->ctx->dev_id,
240 state->ctx->qp_id, ops, burst_size);
241
242 /* if we couldn't enqueue anything, the queue is full */
243 if (!burst_enqd) {
244 /* don't try to dequeue anything we didn't enqueue */
245 return cur_iter_op;
246 }
247
248 if (burst_enqd < burst_size)
249 state->ops_enq_retries++;
250 state->ops_enqd += burst_enqd;
251 cur_iter_op += burst_enqd;
252 }
253 return iter_ops_needed;
254 }
255
256 /* benchmark dequeue */
257 static void
258 pmd_cyclecount_bench_deq(struct pmd_cyclecount_state *state,
259 uint32_t iter_ops_needed, uint16_t test_burst_size)
260 {
261 /* Dequeue full descriptor ring of ops on crypto device */
262 uint32_t cur_iter_op = 0;
263 while (cur_iter_op < iter_ops_needed) {
264 uint32_t burst_size = RTE_MIN(iter_ops_needed - cur_iter_op,
265 test_burst_size);
266 struct rte_crypto_op **ops_processed =
267 &state->ctx->ops[cur_iter_op];
268 uint32_t burst_deqd;
269
270 burst_deqd = rte_cryptodev_dequeue_burst(state->ctx->dev_id,
271 state->ctx->qp_id, ops_processed, burst_size);
272
273 if (burst_deqd < burst_size)
274 state->ops_deq_retries++;
275 state->ops_deqd += burst_deqd;
276 cur_iter_op += burst_deqd;
277 }
278 }
279
280 /* run benchmark per burst size */
281 static inline int
282 pmd_cyclecount_bench_burst_sz(
283 struct pmd_cyclecount_state *state, uint16_t test_burst_size)
284 {
285 uint64_t tsc_start;
286 uint64_t tsc_end;
287 uint64_t tsc_op;
288 uint64_t tsc_enq;
289 uint64_t tsc_deq;
290 uint32_t cur_op;
291
292 /* reset all counters */
293 tsc_enq = 0;
294 tsc_deq = 0;
295 state->ops_enqd = 0;
296 state->ops_enq_retries = 0;
297 state->ops_deqd = 0;
298 state->ops_deq_retries = 0;
299
300 /*
301 * Benchmark crypto op alloc-build-free separately.
302 */
303 tsc_start = rte_rdtsc_precise();
304
305 for (cur_op = 0; cur_op < state->opts->total_ops;
306 cur_op += state->opts->nb_descriptors) {
307 if (unlikely(pmd_cyclecount_bench_ops(
308 state, cur_op, test_burst_size)))
309 return -1;
310 }
311
312 tsc_end = rte_rdtsc_precise();
313 tsc_op = tsc_end - tsc_start;
314
315
316 /*
317 * Hardware acceleration cyclecount benchmarking loop.
318 *
319 * We're benchmarking raw enq/deq performance by filling up the device
320 * queue, so we never get any failed enqs unless the driver won't accept
321 * the exact number of descriptors we requested, or the driver won't
322 * wrap around the end of the TX ring. However, since we're only
323 * dequeueing once we've filled up the queue, we have to benchmark it
324 * piecemeal and then average out the results.
325 */
326 cur_op = 0;
327 while (cur_op < state->opts->total_ops) {
328 uint32_t iter_ops_left = state->opts->total_ops - cur_op;
329 uint32_t iter_ops_needed = RTE_MIN(
330 state->opts->nb_descriptors, iter_ops_left);
331 uint32_t iter_ops_allocd = iter_ops_needed;
332
333 /* allocate and build ops */
334 if (unlikely(pmd_cyclecount_build_ops(state, iter_ops_needed,
335 test_burst_size)))
336 return -1;
337
338 tsc_start = rte_rdtsc_precise();
339
340 /* fill up TX ring */
341 iter_ops_needed = pmd_cyclecount_bench_enq(state,
342 iter_ops_needed, test_burst_size);
343
344 tsc_end = rte_rdtsc_precise();
345
346 tsc_enq += tsc_end - tsc_start;
347
348 /* allow for HW to catch up */
349 if (state->delay)
350 rte_delay_us_block(state->delay);
351
352 tsc_start = rte_rdtsc_precise();
353
354 /* drain RX ring */
355 pmd_cyclecount_bench_deq(state, iter_ops_needed,
356 test_burst_size);
357
358 tsc_end = rte_rdtsc_precise();
359
360 tsc_deq += tsc_end - tsc_start;
361
362 cur_op += iter_ops_needed;
363
364 /*
365 * we may not have processed all ops that we allocated, so
366 * free everything we've allocated.
367 */
368 rte_mempool_put_bulk(state->ctx->pool,
369 (void **)state->ctx->ops, iter_ops_allocd);
370 }
371
372 state->cycles_per_build = (double)tsc_op / state->opts->total_ops;
373 state->cycles_per_enq = (double)tsc_enq / state->ops_enqd;
374 state->cycles_per_deq = (double)tsc_deq / state->ops_deqd;
375
376 return 0;
377 }
378
379 int
380 cperf_pmd_cyclecount_test_runner(void *test_ctx)
381 {
382 struct pmd_cyclecount_state state = {0};
383 const struct cperf_options *opts;
384 uint16_t test_burst_size;
385 uint8_t burst_size_idx = 0;
386
387 state.ctx = test_ctx;
388 opts = state.ctx->options;
389 state.opts = opts;
390 state.lcore = rte_lcore_id();
391 state.linearize = 0;
392
393 static int only_once;
394 static bool warmup = true;
395
396 /*
397 * We need a small delay to allow for hardware to process all the crypto
398 * operations. We can't automatically figure out what the delay should
399 * be, so we leave it up to the user (by default it's 0).
400 */
401 state.delay = 1000 * opts->pmdcc_delay;
402
403 #ifdef CPERF_LINEARIZATION_ENABLE
404 struct rte_cryptodev_info dev_info;
405
406 /* Check if source mbufs require coalescing */
407 if (opts->segments_sz < ctx->options->max_buffer_size) {
408 rte_cryptodev_info_get(state.ctx->dev_id, &dev_info);
409 if ((dev_info.feature_flags &
410 RTE_CRYPTODEV_FF_MBUF_SCATTER_GATHER) ==
411 0) {
412 state.linearize = 1;
413 }
414 }
415 #endif /* CPERF_LINEARIZATION_ENABLE */
416
417 state.ctx->lcore_id = state.lcore;
418
419 /* Get first size from range or list */
420 if (opts->inc_burst_size != 0)
421 test_burst_size = opts->min_burst_size;
422 else
423 test_burst_size = opts->burst_size_list[0];
424
425 while (test_burst_size <= opts->max_burst_size) {
426 /* do a benchmark run */
427 if (pmd_cyclecount_bench_burst_sz(&state, test_burst_size))
428 return -1;
429
430 /*
431 * First run is always a warm up run.
432 */
433 if (warmup) {
434 warmup = false;
435 continue;
436 }
437
438 if (!opts->csv) {
439 if (!only_once)
440 printf(PRETTY_HDR_FMT, "lcore id", "Buf Size",
441 "Burst Size", "Enqueued",
442 "Dequeued", "Enq Retries",
443 "Deq Retries", "Cycles/Op",
444 "Cycles/Enq", "Cycles/Deq");
445 only_once = 1;
446
447 printf(PRETTY_LINE_FMT, state.ctx->lcore_id,
448 opts->test_buffer_size, test_burst_size,
449 state.ops_enqd, state.ops_deqd,
450 state.ops_enq_retries,
451 state.ops_deq_retries,
452 state.cycles_per_build,
453 state.cycles_per_enq,
454 state.cycles_per_deq);
455 } else {
456 if (!only_once)
457 printf(CSV_HDR_FMT, "# lcore id", "Buf Size",
458 "Burst Size", "Enqueued",
459 "Dequeued", "Enq Retries",
460 "Deq Retries", "Cycles/Op",
461 "Cycles/Enq", "Cycles/Deq");
462 only_once = 1;
463
464 printf(CSV_LINE_FMT, state.ctx->lcore_id,
465 opts->test_buffer_size, test_burst_size,
466 state.ops_enqd, state.ops_deqd,
467 state.ops_enq_retries,
468 state.ops_deq_retries,
469 state.cycles_per_build,
470 state.cycles_per_enq,
471 state.cycles_per_deq);
472 }
473
474 /* Get next size from range or list */
475 if (opts->inc_burst_size != 0)
476 test_burst_size += opts->inc_burst_size;
477 else {
478 if (++burst_size_idx == opts->burst_size_count)
479 break;
480 test_burst_size = opts->burst_size_list[burst_size_idx];
481 }
482 }
483
484 return 0;
485 }
486
487 void
488 cperf_pmd_cyclecount_test_destructor(void *arg)
489 {
490 struct cperf_pmd_cyclecount_ctx *ctx = arg;
491
492 if (ctx == NULL)
493 return;
494
495 cperf_pmd_cyclecount_test_free(ctx);
496 }