ceph/src/spdk/dpdk/doc/guides/cryptodevs/qat.rst

   1 ..  SPDX-License-Identifier: BSD-3-Clause
   2     Copyright(c) 2015-2019 Intel Corporation.
   3
   4 Intel(R) QuickAssist (QAT) Crypto Poll Mode Driver
   5 ==================================================
   6
   7 QAT documentation consists of three parts:
   8
   9 * Details of the symmetric and asymmetric crypto services below.
  10 * Details of the :doc:`compression service <../compressdevs/qat_comp>`
  11   in the compressdev drivers section.
  12 * Details of building the common QAT infrastructure and the PMDs to support the
  13   above services. See :ref:`building_qat` below.
  14
  15
  16 Symmetric Crypto Service on QAT
  17 -------------------------------
  18
  19 The QAT symmetric crypto PMD (hereafter referred to as `QAT SYM [PMD]`) provides
  20 poll mode crypto driver support for the following hardware accelerator devices:
  21
  22 * ``Intel QuickAssist Technology DH895xCC``
  23 * ``Intel QuickAssist Technology C62x``
  24 * ``Intel QuickAssist Technology C3xxx``
  25 * ``Intel QuickAssist Technology D15xx``
  26 * ``Intel QuickAssist Technology P5xxx``
  27
  28
  29 Features
  30 ~~~~~~~~
  31
  32 The QAT SYM PMD has support for:
  33
  34 Cipher algorithms:
  35
  36 * ``RTE_CRYPTO_CIPHER_3DES_CBC``
  37 * ``RTE_CRYPTO_CIPHER_3DES_CTR``
  38 * ``RTE_CRYPTO_CIPHER_AES128_CBC``
  39 * ``RTE_CRYPTO_CIPHER_AES192_CBC``
  40 * ``RTE_CRYPTO_CIPHER_AES256_CBC``
  41 * ``RTE_CRYPTO_CIPHER_AES128_CTR``
  42 * ``RTE_CRYPTO_CIPHER_AES192_CTR``
  43 * ``RTE_CRYPTO_CIPHER_AES256_CTR``
  44 * ``RTE_CRYPTO_CIPHER_AES_XTS``
  45 * ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``
  46 * ``RTE_CRYPTO_CIPHER_NULL``
  47 * ``RTE_CRYPTO_CIPHER_KASUMI_F8``
  48 * ``RTE_CRYPTO_CIPHER_DES_CBC``
  49 * ``RTE_CRYPTO_CIPHER_AES_DOCSISBPI``
  50 * ``RTE_CRYPTO_CIPHER_DES_DOCSISBPI``
  51 * ``RTE_CRYPTO_CIPHER_ZUC_EEA3``
  52
  53 Hash algorithms:
  54
  55 * ``RTE_CRYPTO_AUTH_SHA1``
  56 * ``RTE_CRYPTO_AUTH_SHA1_HMAC``
  57 * ``RTE_CRYPTO_AUTH_SHA224``
  58 * ``RTE_CRYPTO_AUTH_SHA224_HMAC``
  59 * ``RTE_CRYPTO_AUTH_SHA256``
  60 * ``RTE_CRYPTO_AUTH_SHA256_HMAC``
  61 * ``RTE_CRYPTO_AUTH_SHA384``
  62 * ``RTE_CRYPTO_AUTH_SHA384_HMAC``
  63 * ``RTE_CRYPTO_AUTH_SHA512``
  64 * ``RTE_CRYPTO_AUTH_SHA512_HMAC``
  65 * ``RTE_CRYPTO_AUTH_AES_XCBC_MAC``
  66 * ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``
  67 * ``RTE_CRYPTO_AUTH_MD5_HMAC``
  68 * ``RTE_CRYPTO_AUTH_NULL``
  69 * ``RTE_CRYPTO_AUTH_KASUMI_F9``
  70 * ``RTE_CRYPTO_AUTH_AES_GMAC``
  71 * ``RTE_CRYPTO_AUTH_ZUC_EIA3``
  72 * ``RTE_CRYPTO_AUTH_AES_CMAC``
  73
  74 Supported AEAD algorithms:
  75
  76 * ``RTE_CRYPTO_AEAD_AES_GCM``
  77 * ``RTE_CRYPTO_AEAD_AES_CCM``
  78
  79
  80 Supported Chains
  81 ~~~~~~~~~~~~~~~~
  82
  83 All the usual chains are supported and also some mixed chains:
  84
  85 .. table:: Supported hash-cipher chains for wireless digest-encrypted cases
  86
  87    +------------------+-----------+-------------+----------+----------+
  88    | Cipher algorithm | NULL AUTH | SNOW3G UIA2 | ZUC EIA3 | AES CMAC |
  89    +==================+===========+=============+==========+==========+
  90    | NULL CIPHER      | Y         | 2&3         | 2&3      | Y        |
  91    +------------------+-----------+-------------+----------+----------+
  92    | SNOW3G UEA2      | 2&3       | Y           | 2&3      | 2&3      |
  93    +------------------+-----------+-------------+----------+----------+
  94    | ZUC EEA3         | 2&3       | 2&3         | 2&3      | 2&3      |
  95    +------------------+-----------+-------------+----------+----------+
  96    | AES CTR          | Y         | 2&3         | 2&3      | Y        |
  97    +------------------+-----------+-------------+----------+----------+
  98
  99 * The combinations marked as "Y" are supported on all QAT hardware versions.
 100 * The combinations marked as "2&3" are supported on GEN2/GEN3 QAT hardware only.
 101
 102
 103 Limitations
 104 ~~~~~~~~~~~
 105
 106 * Only supports the session-oriented API implementation (session-less APIs are not supported).
 107 * SNOW 3G (UEA2), KASUMI (F8) and ZUC (EEA3) supported only if cipher length and offset fields are byte-multiple.
 108 * SNOW 3G (UIA2) and ZUC (EIA3) supported only if hash length and offset fields are byte-multiple.
 109 * No BSD support as BSD QAT kernel driver not available.
 110 * ZUC EEA3/EIA3 is not supported by dh895xcc devices
 111 * Maximum additional authenticated data (AAD) for GCM is 240 bytes long and must be passed to the device in a buffer rounded up to the nearest block-size multiple (x16) and padded with zeros.
 112 * Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single
 113   queue-pair all enqueues to the TX queue must be done from one thread and all dequeues
 114   from the RX queue must be done from one thread, but enqueues and dequeues may be done
 115   in different threads.)
 116 * A GCM limitation exists, but only in the case where there are multiple
 117   generations of QAT devices on a single platform.
 118   To optimise performance, the GCM crypto session should be initialised for the
 119   device generation to which the ops will be enqueued. Specifically if a GCM
 120   session is initialised on a GEN2 device, but then attached to an op enqueued
 121   to a GEN3 device, it will work but cannot take advantage of hardware
 122   optimisations in the GEN3 device. And if a GCM session is initialised on a
 123   GEN3 device, then attached to an op sent to a GEN1/GEN2 device, it will not be
 124   enqueued to the device and will be marked as failed. The simplest way to
 125   mitigate this is to use the bdf whitelist to avoid mixing devices of different
 126   generations in the same process if planning to use for GCM.
 127 * The mixed algo feature on GEN2 is not supported by all kernel drivers. Check
 128   the notes under the Available Kernel Drivers table below for specific details.
 129
 130 Extra notes on KASUMI F9
 131 ~~~~~~~~~~~~~~~~~~~~~~~~
 132
 133 When using KASUMI F9 authentication algorithm, the input buffer must be
 134 constructed according to the
 135 `3GPP KASUMI specification <http://cryptome.org/3gpp/35201-900.pdf>`_
 136 (section 4.4, page 13). The input buffer has to have COUNT (4 bytes),
 137 FRESH (4 bytes), MESSAGE and DIRECTION (1 bit) concatenated. After the DIRECTION
 138 bit, a single '1' bit is appended, followed by between 0 and 7 '0' bits, so that
 139 the total length of the buffer is multiple of 8 bits. Note that the actual
 140 message can be any length, specified in bits.
 141
 142 Once this buffer is passed this way, when creating the crypto operation,
 143 length of data to authenticate "op.sym.auth.data.length" must be the length
 144 of all the items described above, including the padding at the end.
 145 Also, offset of data to authenticate "op.sym.auth.data.offset"
 146 must be such that points at the start of the COUNT bytes.
 147
 148 Asymmetric Crypto Service on QAT
 149 --------------------------------
 150
 151 The QAT asymmetric crypto PMD (hereafter referred to as `QAT ASYM [PMD]`) provides
 152 poll mode crypto driver support for the following hardware accelerator devices:
 153
 154 * ``Intel QuickAssist Technology DH895xCC``
 155 * ``Intel QuickAssist Technology C62x``
 156 * ``Intel QuickAssist Technology C3xxx``
 157 * ``Intel QuickAssist Technology D15xx``
 158 * ``Intel QuickAssist Technology P5xxx``
 159
 160 The QAT ASYM PMD has support for:
 161
 162 * ``RTE_CRYPTO_ASYM_XFORM_MODEX``
 163 * ``RTE_CRYPTO_ASYM_XFORM_MODINV``
 164
 165 Limitations
 166 ~~~~~~~~~~~
 167
 168 * Big integers longer than 4096 bits are not supported.
 169 * Queue-pairs are thread-safe on Intel CPUs but Queues are not (that is, within a single
 170   queue-pair all enqueues to the TX queue must be done from one thread and all dequeues
 171   from the RX queue must be done from one thread, but enqueues and dequeues may be done
 172   in different threads.)
 173 * RSA-2560, RSA-3584 are not supported
 174
 175 .. _building_qat:
 176
 177 Building PMDs on QAT
 178 --------------------
 179
 180 A QAT device can host multiple acceleration services:
 181
 182 * symmetric cryptography
 183 * data compression
 184 * asymmetric cryptography
 185
 186 These services are provided to DPDK applications via PMDs which register to
 187 implement the corresponding cryptodev and compressdev APIs. The PMDs use
 188 common QAT driver code which manages the QAT PCI device. They also depend on a
 189 QAT kernel driver being installed on the platform, see :ref:`qat_kernel` below.
 190
 191
 192 Configuring and Building the DPDK QAT PMDs
 193 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 194
 195
 196 Further information on configuring, building and installing DPDK is described
 197 :doc:`here <../linux_gsg/build_dpdk>`.
 198
 199
 200 Quick instructions for QAT cryptodev PMD are as follows:
 201
 202 .. code-block:: console
 203
 204         cd to the top-level DPDK directory
 205         make defconfig
 206         sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_SYM\)=n,\1=y,' build/.config
 207         or/and
 208         sed -i 's,\(CONFIG_RTE_LIBRTE_PMD_QAT_ASYM\)=n,\1=y,' build/.config
 209         make
 210
 211 Quick instructions for QAT compressdev PMD are as follows:
 212
 213 .. code-block:: console
 214
 215         cd to the top-level DPDK directory
 216         make defconfig
 217         make
 218
 219
 220 .. _building_qat_config:
 221
 222 Build Configuration
 223 ~~~~~~~~~~~~~~~~~~~
 224
 225 These are the build configuration options affecting QAT, and their default values:
 226
 227 .. code-block:: console
 228
 229         CONFIG_RTE_LIBRTE_PMD_QAT=y
 230         CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n
 231         CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n
 232         CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48
 233         CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536
 234
 235 CONFIG_RTE_LIBRTE_PMD_QAT must be enabled for any QAT PMD to be built.
 236
 237 Both QAT SYM PMD and QAT ASYM PMD have an external dependency on libcrypto, so are not
 238 built by default. CONFIG_RTE_LIBRTE_PMD_QAT_SYM/ASYM should be enabled to build them.
 239
 240 The QAT compressdev PMD has no external dependencies, so needs no configuration
 241 options and is built by default.
 242
 243 The number of VFs per PF varies - see table below. If multiple QAT packages are
 244 installed on a platform then CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES should be
 245 adjusted to the number of VFs which the QAT common code will need to handle.
 246
 247 .. Note::
 248
 249         There are separate config items (not QAT-specific) for max cryptodevs
 250         CONFIG_RTE_CRYPTO_MAX_DEVS and max compressdevs CONFIG_RTE_COMPRESS_MAX_DEVS,
 251         if necessary these should be adjusted to handle the total of QAT and other
 252         devices which the process will use. In particular for crypto, where each
 253         QAT VF may expose two crypto devices, sym and asym, it may happen that the
 254         number of devices will be bigger than MAX_DEVS and the process will show an error
 255         during PMD initialisation. To avoid this problem CONFIG_RTE_CRYPTO_MAX_DEVS may be
 256         increased or -w, pci-whitelist domain:bus:devid:func option may be used.
 257
 258
 259 QAT compression PMD needs intermediate buffers to support Deflate compression
 260 with Dynamic Huffman encoding. CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE
 261 specifies the size of a single buffer, the PMD will allocate a multiple of these,
 262 plus some extra space for associated meta-data. For GEN2 devices, 20 buffers are
 263 allocated while for GEN1 devices, 12 buffers are allocated, plus 1472 bytes overhead.
 264
 265 .. Note::
 266
 267         If the compressed output of a Deflate operation using Dynamic Huffman
 268         Encoding is too big to fit in an intermediate buffer, then the
 269         operation will be split into smaller operations and their results will
 270         be merged afterwards.
 271         This is not possible if any checksum calculation was requested - in such
 272         case the code falls back to fixed compression.
 273         To avoid this less performant case, applications should configure
 274         the intermediate buffer size to be larger than the expected input data size
 275         (compressed output size is usually unknown, so the only option is to make
 276         larger than the input size).
 277
 278
 279 Running QAT PMD with minimum threshold for burst size
 280 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 281
 282 If only a small number or packets can be enqueued. Each enqueue causes an expensive MMIO write.
 283 These MMIO write occurrences can be optimised by setting any of the following parameters:
 284
 285 - qat_sym_enq_threshold
 286 - qat_asym_enq_threshold
 287 - qat_comp_enq_threshold
 288
 289 When any of these parameters is set rte_cryptodev_enqueue_burst function will
 290 return 0 (thereby avoiding an MMIO) if the device is congested and number of packets
 291 possible to enqueue is smaller.
 292 To use this feature the user must set the parameter on process start as a device additional parameter::
 293
 294   -w 03:01.1,qat_sym_enq_threshold=32,qat_comp_enq_threshold=16
 295
 296 All parameters can be used with the same device regardless of order. Parameters are separated
 297 by comma. When the same parameter is used more than once first occurrence of the parameter
 298 is used.
 299 Maximum threshold that can be set is 32.
 300
 301
 302 Device and driver naming
 303 ~~~~~~~~~~~~~~~~~~~~~~~~
 304
 305 * The qat cryptodev symmetric crypto driver name is "crypto_qat".
 306 * The qat cryptodev asymmetric crypto driver name is "crypto_qat_asym".
 307
 308 The "rte_cryptodev_devices_get()" returns the devices exposed by either of these drivers.
 309
 310 * Each qat sym crypto device has a unique name, in format
 311   "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_sym".
 312 * Each qat asym crypto device has a unique name, in format
 313   "<pci bdf>_<service>", e.g. "0000:41:01.0_qat_asym".
 314   This name can be passed to "rte_cryptodev_get_dev_id()" to get the device_id.
 315
 316 .. Note::
 317
 318         The cryptodev driver name is passed to the dpdk-test-crypto-perf tool in the "-devtype" parameter.
 319
 320         The qat crypto device name is in the format of the slave parameter passed to the crypto scheduler.
 321
 322 * The qat compressdev driver name is "compress_qat".
 323   The rte_compressdev_devices_get() returns the devices exposed by this driver.
 324
 325 * Each qat compression device has a unique name, in format
 326   <pci bdf>_<service>, e.g. "0000:41:01.0_qat_comp".
 327   This name can be passed to rte_compressdev_get_dev_id() to get the device_id.
 328
 329 .. _qat_kernel:
 330
 331 Dependency on the QAT kernel driver
 332 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 333
 334 To use QAT an SRIOV-enabled QAT kernel driver is required. The VF
 335 devices created and initialised by this driver will be used by the QAT PMDs.
 336
 337 Instructions for installation are below, but first an explanation of the
 338 relationships between the PF/VF devices and the PMDs visible to
 339 DPDK applications.
 340
 341 Each QuickAssist PF device exposes a number of VF devices. Each VF device can
 342 enable one symmetric cryptodev PMD and/or one asymmetric cryptodev PMD and/or
 343 one compressdev PMD.
 344 These QAT PMDs share the same underlying device and pci-mgmt code, but are
 345 enumerated independently on their respective APIs and appear as independent
 346 devices to applications.
 347
 348 .. Note::
 349
 350    Each VF can only be used by one DPDK process. It is not possible to share
 351    the same VF across multiple processes, even if these processes are using
 352    different acceleration services.
 353
 354    Conversely one DPDK process can use one or more QAT VFs and can expose both
 355    cryptodev and compressdev instances on each of those VFs.
 356
 357
 358 Available kernel drivers
 359 ~~~~~~~~~~~~~~~~~~~~~~~~
 360
 361 Kernel drivers for each device for each service are listed in the following table. (Scroll right
 362 to see the full table)
 363
 364
 365 .. _table_qat_pmds_drivers:
 366
 367 .. table:: QAT device generations, devices and drivers
 368
 369    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 370    | S   | A   | C   | Gen | Device   | Driver/ver    | Kernel Module | Pci Driver | PF Did | #PFs | VF Did | VFs/PF |
 371    +=====+=====+=====+=====+==========+===============+===============+============+========+======+========+========+
 372    | Yes | No  | No  | 1   | DH895xCC | linux/4.4+    | qat_dh895xcc  | dh895xcc   | 435    | 1    | 443    | 32     |
 373    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 374    | Yes | Yes | No  | "   | "        | 01.org/4.2.0+ | "             | "          | "      | "    | "      | "      |
 375    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 376    | Yes | Yes | Yes | "   | "        | 01.org/4.3.0+ | "             | "          | "      | "    | "      | "      |
 377    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 378    | Yes | No  | No  | 2   | C62x     | linux/4.5+    | qat_c62x      | c6xx       | 37c8   | 3    | 37c9   | 16     |
 379    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 380    | Yes | Yes | Yes | "   | "        | 01.org/4.2.0+ | "             | "          | "      | "    | "      | "      |
 381    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 382    | Yes | No  | No  | 2   | C3xxx    | linux/4.5+    | qat_c3xxx     | c3xxx      | 19e2   | 1    | 19e3   | 16     |
 383    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 384    | Yes | Yes | Yes | "   | "        | 01.org/4.2.0+ | "             | "          | "      | "    | "      | "      |
 385    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 386    | Yes | No  | No  | 2   | D15xx    | p             | qat_d15xx     | d15xx      | 6f54   | 1    | 6f55   | 16     |
 387    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 388    | Yes | No  | No  | 3   | P5xxx    | p             | qat_p5xxx     | p5xxx      | 18a0   | 1    | 18a1   | 128    |
 389    +-----+-----+-----+-----+----------+---------------+---------------+------------+--------+------+--------+--------+
 390
 391 * Note: Symmetric mixed crypto algorithms feature on Gen 2 works only with 01.org driver version 4.9.0+
 392
 393 The first 3 columns indicate the service:
 394
 395 * S = Symmetric crypto service (via cryptodev API)
 396 * A = Asymmetric crypto service  (via cryptodev API)
 397 * C = Compression service (via compressdev API)
 398
 399 The ``Driver`` column indicates either the Linux kernel version in which
 400 support for this device was introduced or a driver available on Intel's 01.org
 401 website. There are both linux in-tree and 01.org kernel drivers available for some
 402 devices. p = release pending.
 403
 404 If you are running on a kernel which includes a driver for your device, see
 405 `Installation using kernel.org driver`_ below. Otherwise see
 406 `Installation using 01.org QAT driver`_.
 407
 408
 409 Installation using kernel.org driver
 410 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 411
 412 The examples below are based on the C62x device, if you have a different device
 413 use the corresponding values in the above table.
 414
 415 In BIOS ensure that SRIOV is enabled and either:
 416
 417 * Disable VT-d or
 418 * Enable VT-d and set ``"intel_iommu=on iommu=pt"`` in the grub file.
 419
 420 Check that the QAT driver is loaded on your system, by executing::
 421
 422     lsmod | grep qa
 423
 424 You should see the kernel module for your device listed, e.g.::
 425
 426     qat_c62x               5626  0
 427     intel_qat              82336  1 qat_c62x
 428
 429 Next, you need to expose the Virtual Functions (VFs) using the sysfs file system.
 430
 431 First find the BDFs (Bus-Device-Function) of the physical functions (PFs) of
 432 your device, e.g.::
 433
 434     lspci -d:37c8
 435
 436 You should see output similar to::
 437
 438     1a:00.0 Co-processor: Intel Corporation Device 37c8
 439     3d:00.0 Co-processor: Intel Corporation Device 37c8
 440     3f:00.0 Co-processor: Intel Corporation Device 37c8
 441
 442 Enable the VFs for each PF by echoing the number of VFs per PF to the pci driver::
 443
 444      echo 16 > /sys/bus/pci/drivers/c6xx/0000:1a:00.0/sriov_numvfs
 445      echo 16 > /sys/bus/pci/drivers/c6xx/0000:3d:00.0/sriov_numvfs
 446      echo 16 > /sys/bus/pci/drivers/c6xx/0000:3f:00.0/sriov_numvfs
 447
 448 Check that the VFs are available for use. For example ``lspci -d:37c9`` should
 449 list 48 VF devices available for a ``C62x`` device.
 450
 451 To complete the installation follow the instructions in
 452 `Binding the available VFs to the DPDK UIO driver`_.
 453
 454 .. Note::
 455
 456    If the QAT kernel modules are not loaded and you see an error like ``Failed
 457    to load MMP firmware qat_895xcc_mmp.bin`` in kernel logs, this may be as a
 458    result of not using a distribution, but just updating the kernel directly.
 459
 460    Download firmware from the `kernel firmware repo
 461    <http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tree/>`_.
 462
 463    Copy qat binaries to ``/lib/firmware``::
 464
 465       cp qat_895xcc.bin /lib/firmware
 466       cp qat_895xcc_mmp.bin /lib/firmware
 467
 468    Change to your linux source root directory and start the qat kernel modules::
 469
 470       insmod ./drivers/crypto/qat/qat_common/intel_qat.ko
 471       insmod ./drivers/crypto/qat/qat_dh895xcc/qat_dh895xcc.ko
 472
 473
 474 .. Note::
 475
 476    If you see the following warning in ``/var/log/messages`` it can be ignored:
 477    ``IOMMU should be enabled for SR-IOV to work correctly``.
 478
 479
 480 Installation using 01.org QAT driver
 481 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 482
 483 Download the latest QuickAssist Technology Driver from `01.org
 484 <https://01.org/packet-processing/intel%C2%AE-quickassist-technology-drivers-and-patches>`_.
 485 Consult the *Getting Started Guide* at the same URL for further information.
 486
 487 The steps below assume you are:
 488
 489 * Building on a platform with one ``C62x`` device.
 490 * Using package ``qat1.7.l.4.2.0-000xx.tar.gz``.
 491 * On Fedora26 kernel ``4.11.11-300.fc26.x86_64``.
 492
 493 In the BIOS ensure that SRIOV is enabled and VT-d is disabled.
 494
 495 Uninstall any existing QAT driver, for example by running:
 496
 497 * ``./installer.sh uninstall`` in the directory where originally installed.
 498
 499
 500 Build and install the SRIOV-enabled QAT driver::
 501
 502     mkdir /QAT
 503     cd /QAT
 504
 505     # Copy the package to this location and unpack
 506     tar zxof qat1.7.l.4.2.0-000xx.tar.gz
 507
 508     ./configure --enable-icp-sriov=host
 509     make install
 510
 511 You can use ``cat /sys/kernel/debug/qat<your device type and bdf>/version/fw`` to confirm the driver is correctly installed and is using firmware version 4.2.0.
 512 You can use ``lspci -d:37c9`` to confirm the presence of the 16 VF devices available per ``C62x`` PF.
 513
 514 Confirm the driver is correctly installed and is using firmware version 4.2.0::
 515
 516     cat /sys/kernel/debug/qat<your device type and bdf>/version/fw
 517
 518
 519 Confirm the presence of 48 VF devices - 16 per PF::
 520
 521     lspci -d:37c9
 522
 523
 524 To complete the installation - follow instructions in `Binding the available VFs to the DPDK UIO driver`_.
 525
 526 .. Note::
 527
 528    If using a later kernel and the build fails with an error relating to
 529    ``strict_stroul`` not being available apply the following patch:
 530
 531    .. code-block:: diff
 532
 533       /QAT/QAT1.6/quickassist/utilities/downloader/Target_CoreLibs/uclo/include/linux/uclo_platform.h
 534       + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,5)
 535       + #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (kstrtoul((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
 536       + #else
 537       #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)
 538       #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; if (strict_strtoull((str), (base), (num))) printk("Error strtoull convert %s\n", str); }
 539       #else
 540       #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,25)
 541       #define STR_TO_64(str, base, num, endPtr) {endPtr=NULL; strict_strtoll((str), (base), (num));}
 542       #else
 543       #define STR_TO_64(str, base, num, endPtr)                                 \
 544            do {                                                               \
 545                  if (str[0] == '-')                                           \
 546                  {                                                            \
 547                       *(num) = -(simple_strtoull((str+1), &(endPtr), (base))); \
 548                  }else {                                                      \
 549                       *(num) = simple_strtoull((str), &(endPtr), (base));      \
 550                  }                                                            \
 551            } while(0)
 552       + #endif
 553       #endif
 554       #endif
 555
 556
 557 .. Note::
 558
 559    If the build fails due to missing header files you may need to do following::
 560
 561       sudo yum install zlib-devel
 562       sudo yum install openssl-devel
 563       sudo yum install libudev-devel
 564
 565 .. Note::
 566
 567    If the build or install fails due to mismatching kernel sources you may need to do the following::
 568
 569       sudo yum install kernel-headers-`uname -r`
 570       sudo yum install kernel-src-`uname -r`
 571       sudo yum install kernel-devel-`uname -r`
 572
 573
 574 Binding the available VFs to the DPDK UIO driver
 575 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 576
 577 Unbind the VFs from the stock driver so they can be bound to the uio driver.
 578
 579 For an Intel(R) QuickAssist Technology DH895xCC device
 580 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 581
 582 The unbind command below assumes ``BDFs`` of ``03:01.00-03:04.07``, if your
 583 VFs are different adjust the unbind command below::
 584
 585     for device in $(seq 1 4); do \
 586         for fn in $(seq 0 7); do \
 587             echo -n 0000:03:0${device}.${fn} > \
 588             /sys/bus/pci/devices/0000\:03\:0${device}.${fn}/driver/unbind; \
 589         done; \
 590     done
 591
 592 For an Intel(R) QuickAssist Technology C62x device
 593 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 594
 595 The unbind command below assumes ``BDFs`` of ``1a:01.00-1a:02.07``,
 596 ``3d:01.00-3d:02.07`` and ``3f:01.00-3f:02.07``, if your VFs are different
 597 adjust the unbind command below::
 598
 599     for device in $(seq 1 2); do \
 600         for fn in $(seq 0 7); do \
 601             echo -n 0000:1a:0${device}.${fn} > \
 602             /sys/bus/pci/devices/0000\:1a\:0${device}.${fn}/driver/unbind; \
 603
 604             echo -n 0000:3d:0${device}.${fn} > \
 605             /sys/bus/pci/devices/0000\:3d\:0${device}.${fn}/driver/unbind; \
 606
 607             echo -n 0000:3f:0${device}.${fn} > \
 608             /sys/bus/pci/devices/0000\:3f\:0${device}.${fn}/driver/unbind; \
 609         done; \
 610     done
 611
 612 For Intel(R) QuickAssist Technology C3xxx or D15xx device
 613 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 614
 615 The unbind command below assumes ``BDFs`` of ``01:01.00-01:02.07``, if your
 616 VFs are different adjust the unbind command below::
 617
 618     for device in $(seq 1 2); do \
 619         for fn in $(seq 0 7); do \
 620             echo -n 0000:01:0${device}.${fn} > \
 621             /sys/bus/pci/devices/0000\:01\:0${device}.${fn}/driver/unbind; \
 622         done; \
 623     done
 624
 625 Bind to the DPDK uio driver
 626 ^^^^^^^^^^^^^^^^^^^^^^^^^^^
 627
 628 Install the DPDK igb_uio driver, bind the VF PCI Device id to it and use lspci
 629 to confirm the VF devices are now in use by igb_uio kernel driver,
 630 e.g. for the C62x device::
 631
 632     cd to the top-level DPDK directory
 633     modprobe uio
 634     insmod ./build/kmod/igb_uio.ko
 635     echo "8086 37c9" > /sys/bus/pci/drivers/igb_uio/new_id
 636     lspci -vvd:37c9
 637
 638
 639 Another way to bind the VFs to the DPDK UIO driver is by using the
 640 ``dpdk-devbind.py`` script::
 641
 642     cd to the top-level DPDK directory
 643     ./usertools/dpdk-devbind.py -b igb_uio 0000:03:01.1
 644
 645 Testing
 646 ~~~~~~~
 647
 648 QAT SYM crypto PMD can be tested by running the test application::
 649
 650     make defconfig
 651     make -j
 652     cd ./build/app
 653     ./test -l1 -n1 -w <your qat bdf>
 654     RTE>>cryptodev_qat_autotest
 655
 656 QAT ASYM crypto PMD can be tested by running the test application::
 657
 658     make defconfig
 659     make -j
 660     cd ./build/app
 661     ./test -l1 -n1 -w <your qat bdf>
 662     RTE>>cryptodev_qat_asym_autotest
 663
 664 QAT compression PMD can be tested by running the test application::
 665
 666     make defconfig
 667     sed -i 's,\(CONFIG_RTE_COMPRESSDEV_TEST\)=n,\1=y,' build/.config
 668     make -j
 669     cd ./build/app
 670     ./test -l1 -n1 -w <your qat bdf>
 671     RTE>>compressdev_autotest
 672
 673
 674 Debugging
 675 ~~~~~~~~~
 676
 677 There are 2 sets of trace available via the dynamic logging feature:
 678
 679 * pmd.qat_dp exposes trace on the data-path.
 680 * pmd.qat_general exposes all other trace.
 681
 682 pmd.qat exposes both sets of traces.
 683 They can be enabled using the log-level option (where 8=maximum log level) on
 684 the process cmdline, e.g. using any of the following::
 685
 686     --log-level="pmd.qat_general,8"
 687     --log-level="pmd.qat_dp,8"
 688     --log-level="pmd.qat,8"
 689
 690 .. Note::
 691
 692     The global RTE_LOG_DP_LEVEL overrides data-path trace so must be set to
 693     RTE_LOG_DEBUG to see all the trace. This variable is in config/rte_config.h
 694     for meson build and config/common_base for gnu make.
 695     Also the dynamic global log level overrides both sets of trace, so e.g. no
 696     QAT trace would display in this case::
 697
 698         --log-level="7" --log-level="pmd.qat_general,8"