ceph/src/spdk/dpdk/drivers/bus/dpaa/include/fman.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  *
   3  * Copyright 2010-2012 Freescale Semiconductor, Inc.
   4  * All rights reserved.
   5  *
   6  */
   7
   8 #ifndef __FMAN_H
   9 #define __FMAN_H
  10
  11 #include <stdbool.h>
  12 #include <net/if.h>
  13
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_ether.h>
  16
  17 #include <compat.h>
  18
  19 #ifndef FMAN_DEVICE_PATH
  20 #define FMAN_DEVICE_PATH "/dev/mem"
  21 #endif
  22
  23 #define MEMAC_NUM_OF_PADDRS 7 /* Num of additional exact match MAC adr regs */
  24
  25 /* Control and Configuration Register (COMMAND_CONFIG) for MEMAC */
  26 #define CMD_CFG_LOOPBACK_EN     0x00000400
  27 /**< 21 XGMII/GMII loopback enable */
  28 #define CMD_CFG_PROMIS_EN       0x00000010
  29 /**< 27 Promiscuous operation enable */
  30 #define CMD_CFG_PAUSE_IGNORE    0x00000100
  31 /**< 23 Ignore Pause frame quanta */
  32
  33 /* Statistics Configuration Register (STATN_CONFIG) */
  34 #define STATS_CFG_CLR           0x00000004
  35 /**< 29 Reset all counters */
  36 #define STATS_CFG_CLR_ON_RD     0x00000002
  37 /**< 30 Clear on read */
  38 #define STATS_CFG_SATURATE      0x00000001
  39 /**< 31 Saturate at the maximum val */
  40
  41 /**< Max receive frame length mask */
  42 #define MAXFRM_SIZE_MEMAC       0x00007fe0
  43 #define MAXFRM_RX_MASK          0x0000ffff
  44
  45 /**< Interface Mode Register Register for MEMAC */
  46 #define IF_MODE_RLP 0x00000820
  47
  48 /**< Pool Limits */
  49 #define FMAN_PORT_MAX_EXT_POOLS_NUM     8
  50 #define FMAN_PORT_OBS_EXT_POOLS_NUM     2
  51
  52 #define FMAN_PORT_CG_MAP_NUM            8
  53 #define FMAN_PORT_PRS_RESULT_WORDS_NUM  8
  54 #define FMAN_PORT_BMI_FIFO_UNITS        0x100
  55 #define FMAN_PORT_IC_OFFSET_UNITS       0x10
  56
  57 #define FMAN_ENABLE_BPOOL_DEPLETION     0xF00000F0
  58
  59 #define HASH_CTRL_MCAST_EN      0x00000100
  60 #define GROUP_ADDRESS           0x0000010000000000LL
  61 #define HASH_CTRL_ADDR_MASK     0x0000003F
  62
  63 /* Pre definitions of FMAN interface and Bpool structures */
  64 struct __fman_if;
  65 struct fman_if_bpool;
  66 /* Lists of fman interfaces and bpools */
  67 TAILQ_HEAD(rte_fman_if_list, __fman_if);
  68
  69 /* Represents the different flavour of network interface */
  70 enum fman_mac_type {
  71         fman_offline = 0,
  72         fman_mac_1g,
  73         fman_mac_10g,
  74 };
  75
  76 struct mac_addr {
  77         uint32_t   mac_addr_l;  /**< Lower 32 bits of 48-bit MAC address */
  78         uint32_t   mac_addr_u;  /**< Upper 16 bits of 48-bit MAC address */
  79 };
  80
  81 struct memac_regs {
  82         /* General Control and Status */
  83         uint32_t res0000[2];
  84         uint32_t command_config;        /**< 0x008 Ctrl and cfg */
  85         struct mac_addr mac_addr0;      /**< 0x00C-0x010 MAC_ADDR_0...1 */
  86         uint32_t maxfrm;                /**< 0x014 Max frame length */
  87         uint32_t res0018[5];
  88         uint32_t hashtable_ctrl;        /**< 0x02C Hash table control */
  89         uint32_t res0030[4];
  90         uint32_t ievent;                /**< 0x040 Interrupt event */
  91         uint32_t tx_ipg_length;
  92         /**< 0x044 Transmitter inter-packet-gap */
  93         uint32_t res0048;
  94         uint32_t imask;                 /**< 0x04C Interrupt mask */
  95         uint32_t res0050;
  96         uint32_t pause_quanta[4];       /**< 0x054 Pause quanta */
  97         uint32_t pause_thresh[4];       /**< 0x064 Pause quanta threshold */
  98         uint32_t rx_pause_status;       /**< 0x074 Receive pause status */
  99         uint32_t res0078[2];
 100         struct mac_addr mac_addr[MEMAC_NUM_OF_PADDRS];
 101         /**< 0x80-0x0B4 mac padr */
 102         uint32_t lpwake_timer;
 103         /**< 0x0B8 Low Power Wakeup Timer */
 104         uint32_t sleep_timer;
 105         /**< 0x0BC Transmit EEE Low Power Timer */
 106         uint32_t res00c0[8];
 107         uint32_t statn_config;
 108         /**< 0x0E0 Statistics configuration */
 109         uint32_t res00e4[7];
 110         /* Rx Statistics Counter */
 111         uint32_t reoct_l;               /**<Rx Eth Octets Counter */
 112         uint32_t reoct_u;
 113         uint32_t roct_l;                /**<Rx Octet Counters */
 114         uint32_t roct_u;
 115         uint32_t raln_l;                /**<Rx Alignment Error Counter */
 116         uint32_t raln_u;
 117         uint32_t rxpf_l;                /**<Rx valid Pause Frame */
 118         uint32_t rxpf_u;
 119         uint32_t rfrm_l;                /**<Rx Frame counter */
 120         uint32_t rfrm_u;
 121         uint32_t rfcs_l;                /**<Rx frame check seq error */
 122         uint32_t rfcs_u;
 123         uint32_t rvlan_l;               /**<Rx Vlan Frame Counter */
 124         uint32_t rvlan_u;
 125         uint32_t rerr_l;                /**<Rx Frame error */
 126         uint32_t rerr_u;
 127         uint32_t ruca_l;                /**<Rx Unicast */
 128         uint32_t ruca_u;
 129         uint32_t rmca_l;                /**<Rx Multicast */
 130         uint32_t rmca_u;
 131         uint32_t rbca_l;                /**<Rx Broadcast */
 132         uint32_t rbca_u;
 133         uint32_t rdrp_l;                /**<Rx Dropper Packet */
 134         uint32_t rdrp_u;
 135         uint32_t rpkt_l;                /**<Rx packet */
 136         uint32_t rpkt_u;
 137         uint32_t rund_l;                /**<Rx undersized packets */
 138         uint32_t rund_u;
 139         uint32_t r64_l;                 /**<Rx 64 byte */
 140         uint32_t r64_u;
 141         uint32_t r127_l;
 142         uint32_t r127_u;
 143         uint32_t r255_l;
 144         uint32_t r255_u;
 145         uint32_t r511_l;
 146         uint32_t r511_u;
 147         uint32_t r1023_l;
 148         uint32_t r1023_u;
 149         uint32_t r1518_l;
 150         uint32_t r1518_u;
 151         uint32_t r1519x_l;
 152         uint32_t r1519x_u;
 153         uint32_t rovr_l;                /**<Rx oversized but good */
 154         uint32_t rovr_u;
 155         uint32_t rjbr_l;                /**<Rx oversized with bad csum */
 156         uint32_t rjbr_u;
 157         uint32_t rfrg_l;                /**<Rx fragment Packet */
 158         uint32_t rfrg_u;
 159         uint32_t rcnp_l;                /**<Rx control packets (0x8808 */
 160         uint32_t rcnp_u;
 161         uint32_t rdrntp_l;              /**<Rx dropped due to FIFO overflow */
 162         uint32_t rdrntp_u;
 163         uint32_t res01d0[12];
 164         /* Tx Statistics Counter */
 165         uint32_t teoct_l;               /**<Tx eth octets */
 166         uint32_t teoct_u;
 167         uint32_t toct_l;                /**<Tx Octets */
 168         uint32_t toct_u;
 169         uint32_t res0210[2];
 170         uint32_t txpf_l;                /**<Tx valid pause frame */
 171         uint32_t txpf_u;
 172         uint32_t tfrm_l;                /**<Tx frame counter */
 173         uint32_t tfrm_u;
 174         uint32_t tfcs_l;                /**<Tx FCS error */
 175         uint32_t tfcs_u;
 176         uint32_t tvlan_l;               /**<Tx Vlan Frame */
 177         uint32_t tvlan_u;
 178         uint32_t terr_l;                /**<Tx frame error */
 179         uint32_t terr_u;
 180         uint32_t tuca_l;                /**<Tx Unicast */
 181         uint32_t tuca_u;
 182         uint32_t tmca_l;                /**<Tx Multicast */
 183         uint32_t tmca_u;
 184         uint32_t tbca_l;                /**<Tx Broadcast */
 185         uint32_t tbca_u;
 186         uint32_t res0258[2];
 187         uint32_t tpkt_l;                /**<Tx Packet */
 188         uint32_t tpkt_u;
 189         uint32_t tund_l;                /**<Tx Undersized */
 190         uint32_t tund_u;
 191         uint32_t t64_l;
 192         uint32_t t64_u;
 193         uint32_t t127_l;
 194         uint32_t t127_u;
 195         uint32_t t255_l;
 196         uint32_t t255_u;
 197         uint32_t t511_l;
 198         uint32_t t511_u;
 199         uint32_t t1023_l;
 200         uint32_t t1023_u;
 201         uint32_t t1518_l;
 202         uint32_t t1518_u;
 203         uint32_t t1519x_l;
 204         uint32_t t1519x_u;
 205         uint32_t res02a8[6];
 206         uint32_t tcnp_l;                /**<Tx Control Packet type - 0x8808 */
 207         uint32_t tcnp_u;
 208         uint32_t res02c8[14];
 209         /* Line Interface Control */
 210         uint32_t if_mode;               /**< 0x300 Interface Mode Control */
 211         uint32_t if_status;             /**< 0x304 Interface Status */
 212         uint32_t res0308[14];
 213         /* HiGig/2 */
 214         uint32_t hg_config;             /**< 0x340 Control and cfg */
 215         uint32_t res0344[3];
 216         uint32_t hg_pause_quanta;       /**< 0x350 Pause quanta */
 217         uint32_t res0354[3];
 218         uint32_t hg_pause_thresh;       /**< 0x360 Pause quanta threshold */
 219         uint32_t res0364[3];
 220         uint32_t hgrx_pause_status;     /**< 0x370 Receive pause status */
 221         uint32_t hg_fifos_status;       /**< 0x374 fifos status */
 222         uint32_t rhm;                   /**< 0x378 rx messages counter */
 223         uint32_t thm;                   /**< 0x37C tx messages counter */
 224 };
 225
 226 struct rx_bmi_regs {
 227         uint32_t fmbm_rcfg;             /**< Rx Configuration */
 228         uint32_t fmbm_rst;              /**< Rx Status */
 229         uint32_t fmbm_rda;              /**< Rx DMA attributes*/
 230         uint32_t fmbm_rfp;              /**< Rx FIFO Parameters*/
 231         uint32_t fmbm_rfed;             /**< Rx Frame End Data*/
 232         uint32_t fmbm_ricp;             /**< Rx Internal Context Parameters*/
 233         uint32_t fmbm_rim;              /**< Rx Internal Buffer Margins*/
 234         uint32_t fmbm_rebm;             /**< Rx External Buffer Margins*/
 235         uint32_t fmbm_rfne;             /**< Rx Frame Next Engine*/
 236         uint32_t fmbm_rfca;             /**< Rx Frame Command Attributes.*/
 237         uint32_t fmbm_rfpne;            /**< Rx Frame Parser Next Engine*/
 238         uint32_t fmbm_rpso;             /**< Rx Parse Start Offset*/
 239         uint32_t fmbm_rpp;              /**< Rx Policer Profile  */
 240         uint32_t fmbm_rccb;             /**< Rx Coarse Classification Base */
 241         uint32_t fmbm_reth;             /**< Rx Excessive Threshold */
 242         uint32_t reserved003c[1];       /**< (0x03C 0x03F) */
 243         uint32_t fmbm_rprai[FMAN_PORT_PRS_RESULT_WORDS_NUM];
 244                                         /**< Rx Parse Results Array Init*/
 245         uint32_t fmbm_rfqid;            /**< Rx Frame Queue ID*/
 246         uint32_t fmbm_refqid;           /**< Rx Error Frame Queue ID*/
 247         uint32_t fmbm_rfsdm;            /**< Rx Frame Status Discard Mask*/
 248         uint32_t fmbm_rfsem;            /**< Rx Frame Status Error Mask*/
 249         uint32_t fmbm_rfene;            /**< Rx Frame Enqueue Next Engine */
 250         uint32_t reserved0074[0x2];     /**< (0x074-0x07C)  */
 251         uint32_t fmbm_rcmne;
 252         /**< Rx Frame Continuous Mode Next Engine */
 253         uint32_t reserved0080[0x20];/**< (0x080 0x0FF)  */
 254         uint32_t fmbm_ebmpi[FMAN_PORT_MAX_EXT_POOLS_NUM];
 255                                         /**< Buffer Manager pool Information-*/
 256         uint32_t fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM];
 257                                         /**< Allocate Counter-*/
 258         uint32_t reserved0130[8];
 259                                         /**< 0x130/0x140 - 0x15F reserved -*/
 260         uint32_t fmbm_rcgm[FMAN_PORT_CG_MAP_NUM];
 261                                         /**< Congestion Group Map*/
 262         uint32_t fmbm_mpd;              /**< BM Pool Depletion  */
 263         uint32_t reserved0184[0x1F];    /**< (0x184 0x1FF) */
 264         uint32_t fmbm_rstc;             /**< Rx Statistics Counters*/
 265         uint32_t fmbm_rfrc;             /**< Rx Frame Counter*/
 266         uint32_t fmbm_rfbc;             /**< Rx Bad Frames Counter*/
 267         uint32_t fmbm_rlfc;             /**< Rx Large Frames Counter*/
 268         uint32_t fmbm_rffc;             /**< Rx Filter Frames Counter*/
 269         uint32_t fmbm_rfdc;             /**< Rx Frame Discard Counter*/
 270         uint32_t fmbm_rfldec;           /**< Rx Frames List DMA Error Counter*/
 271         uint32_t fmbm_rodc;             /**< Rx Out of Buffers Discard nntr*/
 272         uint32_t fmbm_rbdc;             /**< Rx Buffers Deallocate Counter*/
 273         uint32_t reserved0224[0x17];    /**< (0x224 0x27F) */
 274         uint32_t fmbm_rpc;              /**< Rx Performance Counters*/
 275         uint32_t fmbm_rpcp;             /**< Rx Performance Count Parameters*/
 276         uint32_t fmbm_rccn;             /**< Rx Cycle Counter*/
 277         uint32_t fmbm_rtuc;             /**< Rx Tasks Utilization Counter*/
 278         uint32_t fmbm_rrquc;
 279         /**< Rx Receive Queue Utilization cntr*/
 280         uint32_t fmbm_rduc;             /**< Rx DMA Utilization Counter*/
 281         uint32_t fmbm_rfuc;             /**< Rx FIFO Utilization Counter*/
 282         uint32_t fmbm_rpac;             /**< Rx Pause Activation Counter*/
 283         uint32_t reserved02a0[0x18];    /**< (0x2A0 0x2FF) */
 284         uint32_t fmbm_rdbg;             /**< Rx Debug-*/
 285 };
 286
 287 struct fman_port_qmi_regs {
 288         uint32_t fmqm_pnc;              /**< PortID n Configuration Register */
 289         uint32_t fmqm_pns;              /**< PortID n Status Register */
 290         uint32_t fmqm_pnts;             /**< PortID n Task Status Register */
 291         uint32_t reserved00c[4];        /**< 0xn00C - 0xn01B */
 292         uint32_t fmqm_pnen;             /**< PortID n Enqueue NIA Register */
 293         uint32_t fmqm_pnetfc;           /**< PortID n Enq Total Frame Counter */
 294         uint32_t reserved024[2];        /**< 0xn024 - 0x02B */
 295         uint32_t fmqm_pndn;             /**< PortID n Dequeue NIA Register */
 296         uint32_t fmqm_pndc;             /**< PortID n Dequeue Config Register */
 297         uint32_t fmqm_pndtfc;           /**< PortID n Dequeue tot Frame cntr */
 298         uint32_t fmqm_pndfdc;           /**< PortID n Dequeue FQID Dflt Cntr */
 299         uint32_t fmqm_pndcc;            /**< PortID n Dequeue Confirm Counter */
 300 };
 301
 302 /* This struct exports parameters about an Fman network interface, determined
 303  * from the device-tree.
 304  */
 305 struct fman_if {
 306         /* Which Fman this interface belongs to */
 307         uint8_t fman_idx;
 308         /* The type/speed of the interface */
 309         enum fman_mac_type mac_type;
 310         /* Boolean, set when mac type is memac */
 311         uint8_t is_memac;
 312         /* Boolean, set when PHY is RGMII */
 313         uint8_t is_rgmii;
 314         /* The index of this MAC (within the Fman it belongs to) */
 315         uint8_t mac_idx;
 316         /* The MAC address */
 317         struct ether_addr mac_addr;
 318         /* The Qman channel to schedule Tx FQs to */
 319         u16 tx_channel_id;
 320         /* The hard-coded FQIDs for this interface. Note: this doesn't cover
 321          * the PCD nor the "Rx default" FQIDs, which are configured via FMC
 322          * and its XML-based configuration.
 323          */
 324         uint32_t fqid_rx_def;
 325         uint32_t fqid_rx_err;
 326         uint32_t fqid_tx_err;
 327         uint32_t fqid_tx_confirm;
 328
 329         struct list_head bpool_list;
 330         /* The node for linking this interface into "fman_if_list" */
 331         struct list_head node;
 332 };
 333
 334 /* This struct exposes parameters for buffer pools, extracted from the network
 335  * interface settings in the device tree.
 336  */
 337 struct fman_if_bpool {
 338         uint32_t bpid;
 339         uint64_t count;
 340         uint64_t size;
 341         uint64_t addr;
 342         /* The node for linking this bpool into fman_if::bpool_list */
 343         struct list_head node;
 344 };
 345
 346 /* Internal Context transfer params - FMBM_RICP*/
 347 struct fman_if_ic_params {
 348         /*IC offset in the packet buffer */
 349         uint16_t iceof;
 350         /*IC internal offset */
 351         uint16_t iciof;
 352         /*IC size to copy */
 353         uint16_t icsz;
 354 };
 355
 356 /* The exported "struct fman_if" type contains the subset of fields we want
 357  * exposed. This struct is embedded in a larger "struct __fman_if" which
 358  * contains the extra bits we *don't* want exposed.
 359  */
 360 struct __fman_if {
 361         struct fman_if __if;
 362         char node_path[PATH_MAX];
 363         uint64_t regs_size;
 364         void *ccsr_map;
 365         void *bmi_map;
 366         void *qmi_map;
 367         struct list_head node;
 368 };
 369
 370 /* And this is the base list node that the interfaces are added to. (See
 371  * fman_if_enable_all_rx() below for an example of its use.)
 372  */
 373 extern const struct list_head *fman_if_list;
 374
 375 extern int fman_ccsr_map_fd;
 376
 377 /* To iterate the "bpool_list" for an interface. Eg;
 378  *        struct fman_if *p = get_ptr_to_some_interface();
 379  *        struct fman_if_bpool *bp;
 380  *        printf("Interface uses following BPIDs;\n");
 381  *        fman_if_for_each_bpool(bp, p) {
 382  *            printf("    %d\n", bp->bpid);
 383  *            [...]
 384  *        }
 385  */
 386 #define fman_if_for_each_bpool(bp, __if) \
 387         list_for_each_entry(bp, &(__if)->bpool_list, node)
 388
 389 #define FMAN_ERR(rc, fmt, args...) \
 390         do { \
 391                 _errno = (rc); \
 392                 DPAA_BUS_LOG(ERR, fmt "(%d)", ##args, errno); \
 393         } while (0)
 394
 395 #define FMAN_IP_REV_1   0xC30C4
 396 #define FMAN_IP_REV_1_MAJOR_MASK 0x0000FF00
 397 #define FMAN_IP_REV_1_MAJOR_SHIFT 8
 398 #define FMAN_V3 0x06
 399 #define FMAN_V3_CONTEXTA_EN_A2V 0x10000000
 400 #define FMAN_V3_CONTEXTA_EN_OVOM        0x02000000
 401 #define FMAN_V3_CONTEXTA_EN_EBD 0x80000000
 402 #define FMAN_CONTEXTA_DIS_CHECKSUM      0x7ull
 403 #define FMAN_CONTEXTA_SET_OPCODE11 0x2000000b00000000
 404 extern u16 fman_ip_rev;
 405 extern u32 fman_dealloc_bufs_mask_hi;
 406 extern u32 fman_dealloc_bufs_mask_lo;
 407
 408 /**
 409  * Initialize the FMAN driver
 410  *
 411  * @args void
 412  * @return
 413  *      0 for success; error OTHERWISE
 414  */
 415 int fman_init(void);
 416
 417 /**
 418  * Teardown the FMAN driver
 419  *
 420  * @args void
 421  * @return void
 422  */
 423 void fman_finish(void);
 424
 425 #endif  /* __FMAN_H */