ceph/src/spdk/dpdk/drivers/bus/fslmc/mc/fsl_dpci_cmd.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  *
   3  * Copyright 2013-2016 Freescale Semiconductor Inc.
   4  *
   5  */
   6 #ifndef _FSL_DPCI_CMD_H
   7 #define _FSL_DPCI_CMD_H
   8
   9 /* DPCI Version */
  10 #define DPCI_VER_MAJOR                  3
  11 #define DPCI_VER_MINOR                  4
  12
  13 #define DPCI_CMD_BASE_VERSION           1
  14 #define DPCI_CMD_BASE_VERSION_V2        2
  15 #define DPCI_CMD_ID_OFFSET              4
  16
  17 #define DPCI_CMD_V1(id) ((id << DPCI_CMD_ID_OFFSET) | DPCI_CMD_BASE_VERSION)
  18 #define DPCI_CMD_V2(id) ((id << DPCI_CMD_ID_OFFSET) | DPCI_CMD_BASE_VERSION_V2)
  19
  20 /* Command IDs */
  21 #define DPCI_CMDID_CLOSE                DPCI_CMD_V1(0x800)
  22 #define DPCI_CMDID_OPEN                 DPCI_CMD_V1(0x807)
  23 #define DPCI_CMDID_CREATE               DPCI_CMD_V2(0x907)
  24 #define DPCI_CMDID_DESTROY              DPCI_CMD_V1(0x987)
  25 #define DPCI_CMDID_GET_API_VERSION      DPCI_CMD_V1(0xa07)
  26
  27 #define DPCI_CMDID_ENABLE               DPCI_CMD_V1(0x002)
  28 #define DPCI_CMDID_DISABLE              DPCI_CMD_V1(0x003)
  29 #define DPCI_CMDID_GET_ATTR             DPCI_CMD_V1(0x004)
  30 #define DPCI_CMDID_RESET                DPCI_CMD_V1(0x005)
  31 #define DPCI_CMDID_IS_ENABLED           DPCI_CMD_V1(0x006)
  32
  33 #define DPCI_CMDID_SET_RX_QUEUE         DPCI_CMD_V1(0x0e0)
  34 #define DPCI_CMDID_GET_LINK_STATE       DPCI_CMD_V1(0x0e1)
  35 #define DPCI_CMDID_GET_PEER_ATTR        DPCI_CMD_V1(0x0e2)
  36 #define DPCI_CMDID_GET_RX_QUEUE         DPCI_CMD_V1(0x0e3)
  37 #define DPCI_CMDID_GET_TX_QUEUE         DPCI_CMD_V1(0x0e4)
  38 #define DPCI_CMDID_SET_OPR              DPCI_CMD_V1(0x0e5)
  39 #define DPCI_CMDID_GET_OPR              DPCI_CMD_V1(0x0e6)
  40
  41 /* Macros for accessing command fields smaller than 1byte */
  42 #define DPCI_MASK(field)        \
  43         GENMASK(DPCI_##field##_SHIFT + DPCI_##field##_SIZE - 1, \
  44                 DPCI_##field##_SHIFT)
  45 #define dpci_set_field(var, field, val) \
  46         ((var) |= (((val) << DPCI_##field##_SHIFT) & DPCI_MASK(field)))
  47 #define dpci_get_field(var, field)      \
  48         (((var) & DPCI_MASK(field)) >> DPCI_##field##_SHIFT)
  49
  50 #pragma pack(push, 1)
  51 struct dpci_cmd_open {
  52         uint32_t dpci_id;
  53 };
  54
  55 struct dpci_cmd_create {
  56         uint8_t num_of_priorities;
  57         uint8_t pad[15];
  58         uint32_t options;
  59 };
  60
  61 struct dpci_cmd_destroy {
  62         uint32_t dpci_id;
  63 };
  64
  65 #define DPCI_ENABLE_SHIFT       0
  66 #define DPCI_ENABLE_SIZE        1
  67
  68 struct dpci_rsp_is_enabled {
  69         /* only the LSB bit */
  70         uint8_t en;
  71 };
  72
  73 struct dpci_rsp_get_attr {
  74         uint32_t id;
  75         uint16_t pad;
  76         uint8_t num_of_priorities;
  77 };
  78
  79 struct dpci_rsp_get_peer_attr {
  80         uint32_t id;
  81         uint32_t pad;
  82         uint8_t num_of_priorities;
  83 };
  84
  85 #define DPCI_UP_SHIFT   0
  86 #define DPCI_UP_SIZE    1
  87
  88 struct dpci_rsp_get_link_state {
  89         /* only the LSB bit */
  90         uint8_t up;
  91 };
  92
  93 #define DPCI_DEST_TYPE_SHIFT    0
  94 #define DPCI_DEST_TYPE_SIZE     4
  95 #define DPCI_ORDER_PRESERVATION_SHIFT   4
  96 #define DPCI_ORDER_PRESERVATION_SIZE    1
  97
  98 struct dpci_cmd_set_rx_queue {
  99         uint32_t dest_id;
 100         uint8_t dest_priority;
 101         uint8_t priority;
 102         /* from LSB: dest_type:4 */
 103         uint8_t dest_type;
 104         uint8_t pad;
 105         uint64_t user_ctx;
 106         uint32_t options;
 107 };
 108
 109 struct dpci_cmd_get_queue {
 110         uint8_t pad[5];
 111         uint8_t priority;
 112 };
 113
 114 struct dpci_rsp_get_rx_queue {
 115         uint32_t dest_id;
 116         uint8_t dest_priority;
 117         uint8_t pad;
 118         /* from LSB: dest_type:4 */
 119         uint8_t dest_type;
 120         uint8_t pad1;
 121         uint64_t user_ctx;
 122         uint32_t fqid;
 123 };
 124
 125 struct dpci_rsp_get_tx_queue {
 126         uint32_t pad;
 127         uint32_t fqid;
 128 };
 129
 130 struct dpci_rsp_get_api_version {
 131         uint16_t major;
 132         uint16_t minor;
 133 };
 134
 135 struct dpci_cmd_set_opr {
 136         uint16_t pad0;
 137         uint8_t index;
 138         uint8_t options;
 139         uint8_t pad1[7];
 140         uint8_t oloe;
 141         uint8_t oeane;
 142         uint8_t olws;
 143         uint8_t oa;
 144         uint8_t oprrws;
 145 };
 146
 147 struct dpci_cmd_get_opr {
 148         uint16_t pad;
 149         uint8_t index;
 150 };
 151
 152 #define DPCI_RIP_SHIFT          0
 153 #define DPCI_RIP_SIZE           1
 154 #define DPCI_OPR_ENABLE_SHIFT   1
 155 #define DPCI_OPR_ENABLE_SIZE    1
 156 #define DPCI_TSEQ_NLIS_SHIFT    0
 157 #define DPCI_TSEQ_NLIS_SIZE     1
 158 #define DPCI_HSEQ_NLIS_SHIFT    0
 159 #define DPCI_HSEQ_NLIS_SIZE     1
 160
 161 struct dpci_rsp_get_opr {
 162         uint64_t pad0;
 163         /* from LSB: rip:1 enable:1 */
 164         uint8_t flags;
 165         uint16_t pad1;
 166         uint8_t oloe;
 167         uint8_t oeane;
 168         uint8_t olws;
 169         uint8_t oa;
 170         uint8_t oprrws;
 171         uint16_t nesn;
 172         uint16_t pad8;
 173         uint16_t ndsn;
 174         uint16_t pad2;
 175         uint16_t ea_tseq;
 176         /* only the LSB */
 177         uint8_t tseq_nlis;
 178         uint8_t pad3;
 179         uint16_t ea_hseq;
 180         /* only the LSB */
 181         uint8_t hseq_nlis;
 182         uint8_t pad4;
 183         uint16_t ea_hptr;
 184         uint16_t pad5;
 185         uint16_t ea_tptr;
 186         uint16_t pad6;
 187         uint16_t opr_vid;
 188         uint16_t pad7;
 189         uint16_t opr_id;
 190 };
 191 #pragma pack(pop)
 192 #endif /* _FSL_DPCI_CMD_H */