ceph/src/spdk/dpdk/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2019 NXP
   5  *
   6  */
   7 #include <unistd.h>
   8 #include <stdio.h>
   9 #include <string.h>
  10 #include <stdlib.h>
  11 #include <fcntl.h>
  12 #include <errno.h>
  13 #include <stdarg.h>
  14 #include <inttypes.h>
  15 #include <signal.h>
  16 #include <pthread.h>
  17 #include <sys/types.h>
  18 #include <sys/queue.h>
  19 #include <sys/ioctl.h>
  20 #include <sys/stat.h>
  21 #include <sys/mman.h>
  22 #include <sys/syscall.h>
  23 #include <sys/epoll.h>
  24 #include<sys/eventfd.h>
  25
  26 #include <rte_mbuf.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_malloc.h>
  29 #include <rte_memcpy.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_cycles.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_dev.h>
  34
  35 #include <fslmc_logs.h>
  36 #include <rte_fslmc.h>
  37 #include "dpaa2_hw_pvt.h"
  38 #include "dpaa2_hw_dpio.h"
  39 #include <mc/fsl_dpmng.h>
  40
  41 #define NUM_HOST_CPUS RTE_MAX_LCORE
  42
  43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
  44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
  45
  46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
  47
  48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
  49 static struct dpio_dev_list dpio_dev_list
  50         = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
  51 static uint32_t io_space_count;
  52
  53 /* Variable to store DPAA2 platform type */
  54 uint32_t dpaa2_svr_family;
  55
  56 /* Physical core id for lcores running on dpaa2. */
  57 /* DPAA2 only support 1 lcore to 1 phy cpu mapping */
  58 static unsigned int dpaa2_cpu[RTE_MAX_LCORE];
  59
  60 /* Variable to store DPAA2 DQRR size */
  61 uint8_t dpaa2_dqrr_size;
  62 /* Variable to store DPAA2 EQCR size */
  63 uint8_t dpaa2_eqcr_size;
  64
  65 /*Stashing Macros default for LS208x*/
  66 static int dpaa2_core_cluster_base = 0x04;
  67 static int dpaa2_cluster_sz = 2;
  68
  69 /* For LS208X platform There are four clusters with following mapping:
  70  * Cluster 1 (ID = x04) : CPU0, CPU1;
  71  * Cluster 2 (ID = x05) : CPU2, CPU3;
  72  * Cluster 3 (ID = x06) : CPU4, CPU5;
  73  * Cluster 4 (ID = x07) : CPU6, CPU7;
  74  */
  75 /* For LS108X platform There are two clusters with following mapping:
  76  * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
  77  * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
  78  */
  79 /* For LX2160 platform There are four clusters with following mapping:
  80  * Cluster 1 (ID = x00) : CPU0, CPU1;
  81  * Cluster 2 (ID = x01) : CPU2, CPU3;
  82  * Cluster 3 (ID = x02) : CPU4, CPU5;
  83  * Cluster 4 (ID = x03) : CPU6, CPU7;
  84  * Cluster 1 (ID = x04) : CPU8, CPU9;
  85  * Cluster 2 (ID = x05) : CPU10, CP11;
  86  * Cluster 3 (ID = x06) : CPU12, CPU13;
  87  * Cluster 4 (ID = x07) : CPU14, CPU15;
  88  */
  89
  90 static int
  91 dpaa2_core_cluster_sdest(int cpu_id)
  92 {
  93         int x = cpu_id / dpaa2_cluster_sz;
  94
  95         return dpaa2_core_cluster_base + x;
  96 }
  97
  98 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
  99 static void
 100 dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id, int lcoreid)
 101 {
 102 #define STRING_LEN      28
 103 #define COMMAND_LEN     50
 104         uint32_t cpu_mask = 1;
 105         int ret;
 106         size_t len = 0;
 107         char *temp = NULL, *token = NULL;
 108         char string[STRING_LEN], command[COMMAND_LEN];
 109         FILE *file;
 110
 111         snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
 112         file = fopen("/proc/interrupts", "r");
 113         if (!file) {
 114                 DPAA2_BUS_WARN("Failed to open /proc/interrupts file");
 115                 return;
 116         }
 117         while (getline(&temp, &len, file) != -1) {
 118                 if ((strstr(temp, string)) != NULL) {
 119                         token = strtok(temp, ":");
 120                         break;
 121                 }
 122         }
 123
 124         if (!token) {
 125                 DPAA2_BUS_WARN("Failed to get interrupt id for dpio.%d",
 126                                dpio_id);
 127                 if (temp)
 128                         free(temp);
 129                 fclose(file);
 130                 return;
 131         }
 132
 133         cpu_mask = cpu_mask << dpaa2_cpu[lcoreid];
 134         snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
 135                  cpu_mask, token);
 136         ret = system(command);
 137         if (ret < 0)
 138                 DPAA2_BUS_DEBUG(
 139                         "Failed to affine interrupts on respective core");
 140         else
 141                 DPAA2_BUS_DEBUG(" %s command is executed", command);
 142
 143         free(temp);
 144         fclose(file);
 145 }
 146
 147 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev, int lcoreid)
 148 {
 149         struct epoll_event epoll_ev;
 150         int eventfd, dpio_epoll_fd, ret;
 151         int threshold = 0x3, timeout = 0xFF;
 152
 153         dpio_epoll_fd = epoll_create(1);
 154         ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
 155         if (ret) {
 156                 DPAA2_BUS_ERR("Interrupt registeration failed");
 157                 return -1;
 158         }
 159
 160         if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
 161                 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
 162
 163         if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
 164                 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
 165
 166         qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
 167                                         QBMAN_SWP_INTERRUPT_DQRI);
 168         qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
 169         qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
 170         qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
 171         qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
 172
 173         eventfd = dpio_dev->intr_handle.fd;
 174         epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
 175         epoll_ev.data.fd = eventfd;
 176
 177         ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
 178         if (ret < 0) {
 179                 DPAA2_BUS_ERR("epoll_ctl failed");
 180                 return -1;
 181         }
 182         dpio_dev->epoll_fd = dpio_epoll_fd;
 183
 184         dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id, lcoreid);
 185
 186         return 0;
 187 }
 188 #endif
 189
 190 static int
 191 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int lcoreid)
 192 {
 193         int sdest, ret;
 194         int cpu_id;
 195
 196         /* Set the Stashing Destination */
 197         if (lcoreid < 0) {
 198                 lcoreid = rte_get_master_lcore();
 199                 if (lcoreid < 0) {
 200                         DPAA2_BUS_ERR("Getting CPU Index failed");
 201                         return -1;
 202                 }
 203         }
 204
 205         cpu_id = dpaa2_cpu[lcoreid];
 206
 207         /* Set the STASH Destination depending on Current CPU ID.
 208          * Valid values of SDEST are 4,5,6,7. Where,
 209          */
 210
 211         sdest = dpaa2_core_cluster_sdest(cpu_id);
 212         DPAA2_BUS_DEBUG("Portal= %d  CPU= %u lcore id =%u SDEST= %d",
 213                         dpio_dev->index, cpu_id, lcoreid, sdest);
 214
 215         ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
 216                                             dpio_dev->token, sdest);
 217         if (ret) {
 218                 DPAA2_BUS_ERR("%d ERROR in SDEST",  ret);
 219                 return -1;
 220         }
 221
 222 #ifdef RTE_LIBRTE_PMD_DPAA2_EVENTDEV
 223         if (dpaa2_dpio_intr_init(dpio_dev, lcoreid)) {
 224                 DPAA2_BUS_ERR("Interrupt registration failed for dpio");
 225                 return -1;
 226         }
 227 #endif
 228
 229         return 0;
 230 }
 231
 232 static struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int lcoreid)
 233 {
 234         struct dpaa2_dpio_dev *dpio_dev = NULL;
 235         int ret;
 236
 237         /* Get DPIO dev handle from list using index */
 238         TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
 239                 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
 240                         break;
 241         }
 242         if (!dpio_dev)
 243                 return NULL;
 244
 245         DPAA2_BUS_DEBUG("New Portal %p (%d) affined thread - %lu",
 246                         dpio_dev, dpio_dev->index, syscall(SYS_gettid));
 247
 248         ret = dpaa2_configure_stashing(dpio_dev, lcoreid);
 249         if (ret)
 250                 DPAA2_BUS_ERR("dpaa2_configure_stashing failed");
 251
 252         return dpio_dev;
 253 }
 254
 255 int
 256 dpaa2_affine_qbman_swp(void)
 257 {
 258         unsigned int lcore_id = rte_lcore_id();
 259         uint64_t tid = syscall(SYS_gettid);
 260
 261         if (lcore_id == LCORE_ID_ANY)
 262                 lcore_id = rte_get_master_lcore();
 263         /* if the core id is not supported */
 264         else if (lcore_id >= RTE_MAX_LCORE)
 265                 return -1;
 266
 267         if (dpaa2_io_portal[lcore_id].dpio_dev) {
 268                 DPAA2_BUS_DP_INFO("DPAA Portal=%p (%d) is being shared"
 269                             " between thread %" PRIu64 " and current "
 270                             "%" PRIu64 "\n",
 271                             dpaa2_io_portal[lcore_id].dpio_dev,
 272                             dpaa2_io_portal[lcore_id].dpio_dev->index,
 273                             dpaa2_io_portal[lcore_id].net_tid,
 274                             tid);
 275                 RTE_PER_LCORE(_dpaa2_io).dpio_dev
 276                         = dpaa2_io_portal[lcore_id].dpio_dev;
 277                 rte_atomic16_inc(&dpaa2_io_portal
 278                                  [lcore_id].dpio_dev->ref_count);
 279                 dpaa2_io_portal[lcore_id].net_tid = tid;
 280
 281                 DPAA2_BUS_DP_DEBUG("Old Portal=%p (%d) affined thread - "
 282                                    "%" PRIu64 "\n",
 283                             dpaa2_io_portal[lcore_id].dpio_dev,
 284                             dpaa2_io_portal[lcore_id].dpio_dev->index,
 285                             tid);
 286                 return 0;
 287         }
 288
 289         /* Populate the dpaa2_io_portal structure */
 290         dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
 291
 292         if (dpaa2_io_portal[lcore_id].dpio_dev) {
 293                 RTE_PER_LCORE(_dpaa2_io).dpio_dev
 294                         = dpaa2_io_portal[lcore_id].dpio_dev;
 295                 dpaa2_io_portal[lcore_id].net_tid = tid;
 296
 297                 return 0;
 298         } else {
 299                 return -1;
 300         }
 301 }
 302
 303 int
 304 dpaa2_affine_qbman_ethrx_swp(void)
 305 {
 306         unsigned int lcore_id = rte_lcore_id();
 307         uint64_t tid = syscall(SYS_gettid);
 308
 309         if (lcore_id == LCORE_ID_ANY)
 310                 lcore_id = rte_get_master_lcore();
 311         /* if the core id is not supported */
 312         else if (lcore_id >= RTE_MAX_LCORE)
 313                 return -1;
 314
 315         if (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) {
 316                 DPAA2_BUS_DP_INFO(
 317                         "DPAA Portal=%p (%d) is being shared between thread"
 318                         " %" PRIu64 " and current %" PRIu64 "\n",
 319                         dpaa2_io_portal[lcore_id].ethrx_dpio_dev,
 320                         dpaa2_io_portal[lcore_id].ethrx_dpio_dev->index,
 321                         dpaa2_io_portal[lcore_id].sec_tid,
 322                         tid);
 323                 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev
 324                         = dpaa2_io_portal[lcore_id].ethrx_dpio_dev;
 325                 rte_atomic16_inc(&dpaa2_io_portal
 326                                  [lcore_id].ethrx_dpio_dev->ref_count);
 327                 dpaa2_io_portal[lcore_id].sec_tid = tid;
 328
 329                 DPAA2_BUS_DP_DEBUG(
 330                         "Old Portal=%p (%d) affined thread"
 331                         " - %" PRIu64 "\n",
 332                         dpaa2_io_portal[lcore_id].ethrx_dpio_dev,
 333                         dpaa2_io_portal[lcore_id].ethrx_dpio_dev->index,
 334                         tid);
 335                 return 0;
 336         }
 337
 338         /* Populate the dpaa2_io_portal structure */
 339         dpaa2_io_portal[lcore_id].ethrx_dpio_dev =
 340                 dpaa2_get_qbman_swp(lcore_id);
 341
 342         if (dpaa2_io_portal[lcore_id].ethrx_dpio_dev) {
 343                 RTE_PER_LCORE(_dpaa2_io).ethrx_dpio_dev
 344                         = dpaa2_io_portal[lcore_id].ethrx_dpio_dev;
 345                 dpaa2_io_portal[lcore_id].sec_tid = tid;
 346                 return 0;
 347         } else {
 348                 return -1;
 349         }
 350 }
 351
 352 /*
 353  * This checks for not supported lcore mappings as well as get the physical
 354  * cpuid for the lcore.
 355  * one lcore can only map to 1 cpu i.e. 1@10-14 not supported.
 356  * one cpu can be mapped to more than one lcores.
 357  */
 358 static int
 359 dpaa2_check_lcore_cpuset(void)
 360 {
 361         unsigned int lcore_id, i;
 362         int ret = 0;
 363
 364         for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++)
 365                 dpaa2_cpu[lcore_id] = 0xffffffff;
 366
 367         for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
 368                 rte_cpuset_t cpuset = rte_lcore_cpuset(lcore_id);
 369
 370                 for (i = 0; i < CPU_SETSIZE; i++) {
 371                         if (!CPU_ISSET(i, &cpuset))
 372                                 continue;
 373                         if (i >= RTE_MAX_LCORE) {
 374                                 DPAA2_BUS_ERR("ERR:lcore map to core %u (>= %u) not supported",
 375                                         i, RTE_MAX_LCORE);
 376                                 ret = -1;
 377                                 continue;
 378                         }
 379                         RTE_LOG(DEBUG, EAL, "lcore id = %u cpu=%u\n",
 380                                 lcore_id, i);
 381                         if (dpaa2_cpu[lcore_id] != 0xffffffff) {
 382                                 DPAA2_BUS_ERR("ERR:lcore map to multi-cpu not supported");
 383                                 ret = -1;
 384                                 continue;
 385                         }
 386                         dpaa2_cpu[lcore_id] = i;
 387                 }
 388         }
 389         return ret;
 390 }
 391
 392 static int
 393 dpaa2_create_dpio_device(int vdev_fd,
 394                          struct vfio_device_info *obj_info,
 395                          int object_id)
 396 {
 397         struct dpaa2_dpio_dev *dpio_dev = NULL;
 398         struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
 399         struct qbman_swp_desc p_des;
 400         struct dpio_attr attr;
 401         static int check_lcore_cpuset;
 402
 403         if (obj_info->num_regions < NUM_DPIO_REGIONS) {
 404                 DPAA2_BUS_ERR("Not sufficient number of DPIO regions");
 405                 return -1;
 406         }
 407
 408         dpio_dev = rte_zmalloc(NULL, sizeof(struct dpaa2_dpio_dev),
 409                               RTE_CACHE_LINE_SIZE);
 410         if (!dpio_dev) {
 411                 DPAA2_BUS_ERR("Memory allocation failed for DPIO Device");
 412                 return -1;
 413         }
 414
 415         dpio_dev->dpio = NULL;
 416         dpio_dev->hw_id = object_id;
 417         rte_atomic16_init(&dpio_dev->ref_count);
 418         /* Using single portal  for all devices */
 419         dpio_dev->mc_portal = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
 420
 421         if (!check_lcore_cpuset) {
 422                 check_lcore_cpuset = 1;
 423
 424                 if (dpaa2_check_lcore_cpuset() < 0)
 425                         goto err;
 426         }
 427
 428         dpio_dev->dpio = rte_zmalloc(NULL, sizeof(struct fsl_mc_io),
 429                                      RTE_CACHE_LINE_SIZE);
 430         if (!dpio_dev->dpio) {
 431                 DPAA2_BUS_ERR("Memory allocation failure");
 432                 goto err;
 433         }
 434
 435         dpio_dev->dpio->regs = dpio_dev->mc_portal;
 436         if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
 437                       &dpio_dev->token)) {
 438                 DPAA2_BUS_ERR("Failed to allocate IO space");
 439                 goto err;
 440         }
 441
 442         if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
 443                 DPAA2_BUS_ERR("Failed to reset dpio");
 444                 goto err;
 445         }
 446
 447         if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
 448                 DPAA2_BUS_ERR("Failed to Enable dpio");
 449                 goto err;
 450         }
 451
 452         if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
 453                                 dpio_dev->token, &attr)) {
 454                 DPAA2_BUS_ERR("DPIO Get attribute failed");
 455                 goto err;
 456         }
 457
 458         /* find the SoC type for the first time */
 459         if (!dpaa2_svr_family) {
 460                 struct mc_soc_version mc_plat_info = {0};
 461
 462                 if (mc_get_soc_version(dpio_dev->dpio,
 463                                        CMD_PRI_LOW, &mc_plat_info)) {
 464                         DPAA2_BUS_ERR("Unable to get SoC version information");
 465                 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
 466                         dpaa2_core_cluster_base = 0x02;
 467                         dpaa2_cluster_sz = 4;
 468                         DPAA2_BUS_DEBUG("LS108x (A53) Platform Detected");
 469                 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
 470                         dpaa2_core_cluster_base = 0x00;
 471                         dpaa2_cluster_sz = 2;
 472                         DPAA2_BUS_DEBUG("LX2160 Platform Detected");
 473                 }
 474                 dpaa2_svr_family = (mc_plat_info.svr & 0xffff0000);
 475
 476                 if (dpaa2_svr_family == SVR_LX2160A) {
 477                         dpaa2_dqrr_size = DPAA2_LX2_DQRR_RING_SIZE;
 478                         dpaa2_eqcr_size = DPAA2_LX2_EQCR_RING_SIZE;
 479                 } else {
 480                         dpaa2_dqrr_size = DPAA2_DQRR_RING_SIZE;
 481                         dpaa2_eqcr_size = DPAA2_EQCR_RING_SIZE;
 482                 }
 483         }
 484
 485         if (dpaa2_svr_family == SVR_LX2160A)
 486                 reg_info.index = DPAA2_SWP_CENA_MEM_REGION;
 487         else
 488                 reg_info.index = DPAA2_SWP_CENA_REGION;
 489
 490         if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info)) {
 491                 DPAA2_BUS_ERR("vfio: error getting region info");
 492                 goto err;
 493         }
 494
 495         dpio_dev->ce_size = reg_info.size;
 496         dpio_dev->qbman_portal_ce_paddr = (size_t)mmap(NULL, reg_info.size,
 497                                 PROT_WRITE | PROT_READ, MAP_SHARED,
 498                                 vdev_fd, reg_info.offset);
 499
 500         reg_info.index = DPAA2_SWP_CINH_REGION;
 501         if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, &reg_info)) {
 502                 DPAA2_BUS_ERR("vfio: error getting region info");
 503                 goto err;
 504         }
 505
 506         dpio_dev->ci_size = reg_info.size;
 507         dpio_dev->qbman_portal_ci_paddr = (size_t)mmap(NULL, reg_info.size,
 508                                 PROT_WRITE | PROT_READ, MAP_SHARED,
 509                                 vdev_fd, reg_info.offset);
 510
 511         /* Configure & setup SW portal */
 512         p_des.block = NULL;
 513         p_des.idx = attr.qbman_portal_id;
 514         p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
 515         p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
 516         p_des.irq = -1;
 517         p_des.qman_version = attr.qbman_version;
 518         p_des.eqcr_mode = qman_eqcr_vb_ring;
 519         p_des.cena_access_mode = qman_cena_fastest_access;
 520
 521         dpio_dev->sw_portal = qbman_swp_init(&p_des);
 522         if (dpio_dev->sw_portal == NULL) {
 523                 DPAA2_BUS_ERR("QBMan SW Portal Init failed");
 524                 goto err;
 525         }
 526
 527         io_space_count++;
 528         dpio_dev->index = io_space_count;
 529
 530         if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
 531                 DPAA2_BUS_ERR("Fail to setup interrupt for %d",
 532                               dpio_dev->hw_id);
 533                 goto err;
 534         }
 535
 536         dpio_dev->eqresp = rte_zmalloc(NULL, MAX_EQ_RESP_ENTRIES *
 537                                      (sizeof(struct qbman_result) +
 538                                      sizeof(struct eqresp_metadata)),
 539                                      RTE_CACHE_LINE_SIZE);
 540         if (!dpio_dev->eqresp) {
 541                 DPAA2_BUS_ERR("Memory allocation failed for eqresp");
 542                 goto err;
 543         }
 544         dpio_dev->eqresp_meta = (struct eqresp_metadata *)(dpio_dev->eqresp +
 545                                 MAX_EQ_RESP_ENTRIES);
 546
 547
 548         TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
 549
 550         return 0;
 551
 552 err:
 553         if (dpio_dev->dpio) {
 554                 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
 555                 dpio_close(dpio_dev->dpio, CMD_PRI_LOW,  dpio_dev->token);
 556                 rte_free(dpio_dev->dpio);
 557         }
 558
 559         rte_free(dpio_dev);
 560
 561         /* For each element in the list, cleanup */
 562         TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
 563                 if (dpio_dev->dpio) {
 564                         dpio_disable(dpio_dev->dpio, CMD_PRI_LOW,
 565                                 dpio_dev->token);
 566                         dpio_close(dpio_dev->dpio, CMD_PRI_LOW,
 567                                 dpio_dev->token);
 568                         rte_free(dpio_dev->dpio);
 569                 }
 570                 rte_free(dpio_dev);
 571         }
 572
 573         /* Preventing re-use of the list with old entries */
 574         TAILQ_INIT(&dpio_dev_list);
 575
 576         return -1;
 577 }
 578
 579 void
 580 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
 581 {
 582         int i = 0;
 583
 584         for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
 585                 if (q_storage->dq_storage[i])
 586                         rte_free(q_storage->dq_storage[i]);
 587         }
 588 }
 589
 590 int
 591 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
 592 {
 593         int i = 0;
 594
 595         for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
 596                 q_storage->dq_storage[i] = rte_malloc(NULL,
 597                         dpaa2_dqrr_size * sizeof(struct qbman_result),
 598                         RTE_CACHE_LINE_SIZE);
 599                 if (!q_storage->dq_storage[i])
 600                         goto fail;
 601         }
 602         return 0;
 603 fail:
 604         while (--i >= 0)
 605                 rte_free(q_storage->dq_storage[i]);
 606
 607         return -1;
 608 }
 609
 610 uint32_t
 611 dpaa2_free_eq_descriptors(void)
 612 {
 613         struct dpaa2_dpio_dev *dpio_dev = DPAA2_PER_LCORE_DPIO;
 614         struct qbman_result *eqresp;
 615         struct eqresp_metadata *eqresp_meta;
 616         struct dpaa2_queue *txq;
 617
 618         while (dpio_dev->eqresp_ci != dpio_dev->eqresp_pi) {
 619                 eqresp = &dpio_dev->eqresp[dpio_dev->eqresp_ci];
 620                 eqresp_meta = &dpio_dev->eqresp_meta[dpio_dev->eqresp_ci];
 621
 622                 if (!qbman_result_eqresp_rspid(eqresp))
 623                         break;
 624
 625                 if (qbman_result_eqresp_rc(eqresp)) {
 626                         txq = eqresp_meta->dpaa2_q;
 627                         txq->cb_eqresp_free(dpio_dev->eqresp_ci);
 628                 }
 629                 qbman_result_eqresp_set_rspid(eqresp, 0);
 630
 631                 dpio_dev->eqresp_ci + 1 < MAX_EQ_RESP_ENTRIES ?
 632                         dpio_dev->eqresp_ci++ : (dpio_dev->eqresp_ci = 0);
 633         }
 634
 635         /* Return 1 less entry so that PI and CI are never same in a
 636          * case there all the EQ responses are in use.
 637          */
 638         if (dpio_dev->eqresp_ci > dpio_dev->eqresp_pi)
 639                 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi - 1;
 640         else
 641                 return dpio_dev->eqresp_ci - dpio_dev->eqresp_pi +
 642                         MAX_EQ_RESP_ENTRIES - 1;
 643 }
 644
 645 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
 646         .dev_type = DPAA2_IO,
 647         .create = dpaa2_create_dpio_device,
 648 };
 649
 650 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);