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1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP
5 *
6 */
7 #ifndef _FSL_QBMAN_BASE_H
8 #define _FSL_QBMAN_BASE_H
9
10 /**
11 * DOC: QBMan basic structures
12 *
13 * The QBMan block descriptor, software portal descriptor and Frame descriptor
14 * are defined here.
15 *
16 */
17
18 /**
19 * struct qbman_block_desc - qbman block descriptor structure
20 * @ccsr_reg_bar: CCSR register map.
21 * @irq_rerr: Recoverable error interrupt line.
22 * @irq_nrerr: Non-recoverable error interrupt line
23 *
24 * Descriptor for a QBMan instance on the SoC. On partitions/targets that do not
25 * control this QBMan instance, these values may simply be place-holders. The
26 * idea is simply that we be able to distinguish between them, eg. so that SWP
27 * descriptors can identify which QBMan instance they belong to.
28 */
29 struct qbman_block_desc {
30 void *ccsr_reg_bar;
31 int irq_rerr;
32 int irq_nrerr;
33 };
34
35 enum qbman_eqcr_mode {
36 qman_eqcr_vb_ring = 2, /* Valid bit, with eqcr in ring mode */
37 qman_eqcr_vb_array, /* Valid bit, with eqcr in array mode */
38 };
39
40 enum qbman_cena_access_mode {
41 qman_cena_fastest_access = 0, /* Use memory backed node if available */
42 qman_cena_direct_access, /* Use direct access to the CENA region */
43 };
44
45 /**
46 * struct qbman_swp_desc - qbman software portal descriptor structure
47 * @block: The QBMan instance.
48 * @cena_bar: Cache-enabled portal register map.
49 * @cinh_bar: Cache-inhibited portal register map.
50 * @irq: -1 if unused (or unassigned)
51 * @idx: SWPs within a QBMan are indexed. -1 if opaque to the user.
52 * @qman_version: the qman version.
53 * @eqcr_mode: Select the eqcr mode, currently only valid bit ring mode and
54 * valid bit array mode are supported.
55 * @cena_access_mode: Mode used to access the CENA region, direct
56 * or memory backed.
57 *
58 * Descriptor for a QBMan software portal, expressed in terms that make sense to
59 * the user context. Ie. on MC, this information is likely to be true-physical,
60 * and instantiated statically at compile-time. On GPP, this information is
61 * likely to be obtained via "discovery" over a partition's "MC bus"
62 * (ie. in response to a MC portal command), and would take into account any
63 * virtualisation of the GPP user's address space and/or interrupt numbering.
64 */
65 struct qbman_swp_desc {
66 const struct qbman_block_desc *block;
67 uint8_t *cena_bar;
68 uint8_t *cinh_bar;
69 int irq;
70 int idx;
71 uint32_t qman_version;
72 enum qbman_eqcr_mode eqcr_mode;
73 enum qbman_cena_access_mode cena_access_mode;
74 };
75
76 /* Driver object for managing a QBMan portal */
77 struct qbman_swp;
78
79 /**
80 * struct qbman_fd - basci structure for qbman frame descriptor
81 * @words: for easier/faster copying the whole FD structure.
82 * @addr_lo: the lower 32 bits of the address in FD.
83 * @addr_hi: the upper 32 bits of the address in FD.
84 * @len: the length field in FD.
85 * @bpid_offset: represent the bpid and offset fields in FD. offset in
86 * the MS 16 bits, BPID in the LS 16 bits.
87 * @frc: frame context
88 * @ctrl: the 32bit control bits including dd, sc,... va, err.
89 * @flc_lo: the lower 32bit of flow context.
90 * @flc_hi: the upper 32bits of flow context.
91 *
92 * Place-holder for FDs, we represent it via the simplest form that we need for
93 * now. Different overlays may be needed to support different options, etc. (It
94 * is impractical to define One True Struct, because the resulting encoding
95 * routines (lots of read-modify-writes) would be worst-case performance whether
96 * or not circumstances required them.)
97 *
98 * Note, as with all data-structures exchanged between software and hardware (be
99 * they located in the portal register map or DMA'd to and from main-memory),
100 * the driver ensures that the caller of the driver API sees the data-structures
101 * in host-endianness. "struct qbman_fd" is no exception. The 32-bit words
102 * contained within this structure are represented in host-endianness, even if
103 * hardware always treats them as little-endian. As such, if any of these fields
104 * are interpreted in a binary (rather than numerical) fashion by hardware
105 * blocks (eg. accelerators), then the user should be careful. We illustrate
106 * with an example;
107 *
108 * Suppose the desired behaviour of an accelerator is controlled by the "frc"
109 * field of the FDs that are sent to it. Suppose also that the behaviour desired
110 * by the user corresponds to an "frc" value which is expressed as the literal
111 * sequence of bytes 0xfe, 0xed, 0xab, and 0xba. So "frc" should be the 32-bit
112 * value in which 0xfe is the first byte and 0xba is the last byte, and as
113 * hardware is little-endian, this amounts to a 32-bit "value" of 0xbaabedfe. If
114 * the software is little-endian also, this can simply be achieved by setting
115 * frc=0xbaabedfe. On the other hand, if software is big-endian, it should set
116 * frc=0xfeedabba! The best away of avoiding trouble with this sort of thing is
117 * to treat the 32-bit words as numerical values, in which the offset of a field
118 * from the beginning of the first byte (as required or generated by hardware)
119 * is numerically encoded by a left-shift (ie. by raising the field to a
120 * corresponding power of 2). Ie. in the current example, software could set
121 * "frc" in the following way, and it would work correctly on both little-endian
122 * and big-endian operation;
123 * fd.frc = (0xfe << 0) | (0xed << 8) | (0xab << 16) | (0xba << 24);
124 */
125 struct qbman_fd {
126 union {
127 uint32_t words[8];
128 struct qbman_fd_simple {
129 uint32_t addr_lo;
130 uint32_t addr_hi;
131 uint32_t len;
132 uint32_t bpid_offset;
133 uint32_t frc;
134 uint32_t ctrl;
135 uint32_t flc_lo;
136 uint32_t flc_hi;
137 } simple;
138 };
139 };
140
141 #endif /* !_FSL_QBMAN_BASE_H */