ceph/src/spdk/dpdk/drivers/common/cpt/cpt_hw_types.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Cavium, Inc
   3  */
   4
   5 #ifndef _CPT_HW_TYPES_H_
   6 #define _CPT_HW_TYPES_H_
   7
   8 #include <rte_byteorder.h>
   9
  10 /*
  11  * This file defines HRM specific structs.
  12  *
  13  */
  14
  15 #define CPT_VF_INTR_MBOX_MASK   (1<<0)
  16 #define CPT_VF_INTR_DOVF_MASK   (1<<1)
  17 #define CPT_VF_INTR_IRDE_MASK   (1<<2)
  18 #define CPT_VF_INTR_NWRP_MASK   (1<<3)
  19 #define CPT_VF_INTR_SWERR_MASK  (1<<4)
  20 #define CPT_VF_INTR_HWERR_MASK  (1<<5)
  21 #define CPT_VF_INTR_FAULT_MASK  (1<<6)
  22
  23 #define CPT_INST_SIZE           (64)
  24 #define CPT_NEXT_CHUNK_PTR_SIZE (8)
  25
  26 /*
  27  * CPT_INST_S software command definitions
  28  * Words EI (0-3)
  29  */
  30 typedef union {
  31         uint64_t u64;
  32         struct {
  33 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
  34                 uint16_t opcode;
  35                 uint16_t param1;
  36                 uint16_t param2;
  37                 uint16_t dlen;
  38 #else
  39                 uint16_t dlen;
  40                 uint16_t param2;
  41                 uint16_t param1;
  42                 uint16_t opcode;
  43 #endif
  44         } s;
  45 } vq_cmd_word0_t;
  46
  47 typedef union {
  48         uint64_t u64;
  49         struct {
  50 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
  51                 uint64_t grp    : 3;
  52                 uint64_t cptr   : 61;
  53 #else
  54                 uint64_t cptr   : 61;
  55                 uint64_t grp    : 3;
  56 #endif
  57         } s;
  58 } vq_cmd_word3_t;
  59
  60 typedef struct cpt_vq_command {
  61         vq_cmd_word0_t cmd;
  62         uint64_t dptr;
  63         uint64_t rptr;
  64         vq_cmd_word3_t cptr;
  65 } cpt_vq_cmd_t;
  66
  67 /**
  68  * Structure cpt_inst_s
  69  *
  70  * CPT Instruction Structure
  71  * This structure specifies the instruction layout.
  72  * Instructions are stored in memory as little-endian unless
  73  * CPT()_PF_Q()_CTL[INST_BE] is set.
  74  */
  75 typedef union cpt_inst_s {
  76         uint64_t u[8];
  77         struct cpt_inst_s_8s {
  78 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
  79                 uint64_t reserved_17_63        : 47;
  80                 /* [ 16: 16] Done interrupt.
  81                  * 0 = No interrupts related to this instruction.
  82                  * 1 = When the instruction completes,CPT()_VQ()_DONE[DONE]
  83                  * will be incremented, and based on the rules described
  84                  * there an interrupt may occur.
  85                  */
  86                 uint64_t doneint               : 1;
  87                 uint64_t reserved_0_15         : 16;
  88 #else /* Word 0 - Little Endian */
  89                 uint64_t reserved_0_15         : 16;
  90                 uint64_t doneint               : 1;
  91                 uint64_t reserved_17_63        : 47;
  92 #endif /* Word 0 - End */
  93 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
  94                 /* [127: 64] Result IOVA.
  95                  * If nonzero, specifies where to write CPT_RES_S.
  96                  * If zero, no result structure will be written.
  97                  * Address must be 16-byte aligned.
  98                  *
  99                  * Bits <63:49> are ignored by hardware; software should
 100                  * use a sign-extended bit <48> for forward compatibility.
 101                  */
 102                 uint64_t res_addr              : 64;
 103 #else /* Word 1 - Little Endian */
 104                 uint64_t res_addr              : 64;
 105 #endif /* Word 1 - End */
 106 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
 107                 uint64_t reserved_172_191      : 20;
 108                 /* [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to
 109                  * use when CPT submits work to SSO.
 110                  * For the SSO to not discard the add-work request, FPA_PF_MAP()
 111                  * must map [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
 112                  */
 113                 uint64_t grp                   : 10;
 114                 /* [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use
 115                  * when CPT submits work to SSO.
 116                  */
 117                 uint64_t tt                    : 2;
 118                 /* [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when
 119                  * CPT submits work to SSO.
 120                  */
 121                 uint64_t tag                   : 32;
 122 #else /* Word 2 - Little Endian */
 123                 uint64_t tag                   : 32;
 124                 uint64_t tt                    : 2;
 125                 uint64_t grp                   : 10;
 126                 uint64_t reserved_172_191      : 20;
 127 #endif /* Word 2 - End */
 128 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
 129                 /** [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
 130                  * work-queue entry that CPT submits work to SSO after all
 131                  * context, output data, and result write operations are
 132                  * visible to other CNXXXX units and the cores.
 133                  * Bits <2:0> must be zero.
 134                  * Bits <63:49> are ignored by hardware; software should use a
 135                  * sign-extended bit <48> for forward compatibility.
 136                  * Internal:Bits <63:49>, <2:0> are ignored by hardware,
 137                  * treated as always 0x0.
 138                  **/
 139                 uint64_t wq_ptr                : 64;
 140 #else /* Word 3 - Little Endian */
 141                 uint64_t wq_ptr                : 64;
 142 #endif /* Word 3 - End */
 143 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 4 - Big Endian */
 144                 union {
 145                         /** [319:256] Engine instruction word 0. Passed to the
 146                          * AE/SE.
 147                          **/
 148                         uint64_t ei0                   : 64;
 149                         vq_cmd_word0_t vq_cmd_w0;
 150                 };
 151 #else /* Word 4 - Little Endian */
 152                 union {
 153                         uint64_t ei0                   : 64;
 154                         vq_cmd_word0_t vq_cmd_w0;
 155                 };
 156 #endif /* Word 4 - End */
 157 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 5 - Big Endian */
 158                 union {
 159                         /** [383:320] Engine instruction word 1. Passed to the
 160                          * AE/SE.
 161                          **/
 162                         uint64_t ei1                   : 64;
 163                         uint64_t dptr;
 164                 };
 165 #else /* Word 5 - Little Endian */
 166                 union {
 167                         uint64_t ei1                   : 64;
 168                         uint64_t dptr;
 169                 };
 170 #endif /* Word 5 - End */
 171 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 6 - Big Endian */
 172                 union {
 173                         /** [447:384] Engine instruction word 2. Passed to the
 174                          * AE/SE.
 175                          **/
 176                         uint64_t ei2                   : 64;
 177                         uint64_t rptr;
 178                 };
 179 #else /* Word 6 - Little Endian */
 180                 union {
 181                         uint64_t ei2                   : 64;
 182                         uint64_t rptr;
 183                 };
 184 #endif /* Word 6 - End */
 185 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 7 - Big Endian */
 186                 union {
 187                         /** [511:448] Engine instruction word 3. Passed to the
 188                          * AE/SE.
 189                          **/
 190                         uint64_t ei3                   : 64;
 191                         vq_cmd_word3_t vq_cmd_w3;
 192                 };
 193 #else /* Word 7 - Little Endian */
 194                 union {
 195                         uint64_t ei3                   : 64;
 196                         vq_cmd_word3_t vq_cmd_w3;
 197                 };
 198 #endif /* Word 7 - End */
 199         } s8x;
 200         struct cpt_inst_s_9s {
 201 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 202                 uint64_t nixtx_addr            : 60;
 203                 uint64_t doneint               : 1;
 204                 uint64_t nixtxl                : 3;
 205 #else /* Word 0 - Little Endian */
 206                 uint64_t nixtxl                : 3;
 207                 uint64_t doneint               : 1;
 208                 uint64_t nixtx_addr            : 60;
 209 #endif /* Word 0 - End */
 210                 uint64_t res_addr;
 211 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
 212                 uint64_t rvu_pf_func           : 16;
 213                 uint64_t reserved_172_175      : 4;
 214                 uint64_t grp                   : 10;
 215                 uint64_t tt                    : 2;
 216                 uint64_t tag                   : 32;
 217 #else /* Word 2 - Little Endian */
 218                 uint64_t tag                   : 32;
 219                 uint64_t tt                    : 2;
 220                 uint64_t grp                   : 10;
 221                 uint64_t reserved_172_175      : 4;
 222                 uint64_t rvu_pf_func           : 16;
 223 #endif /* Word 2 - End */
 224 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
 225                 uint64_t wq_ptr                : 61;
 226                 uint64_t reserved_194_193      : 2;
 227                 uint64_t qord                  : 1;
 228 #else /* Word 3 - Little Endian */
 229                 uint64_t qord                  : 1;
 230                 uint64_t reserved_194_193      : 2;
 231                 uint64_t wq_ptr                : 61;
 232 #endif /* Word 3 - End */
 233                 uint64_t ei0;
 234                 uint64_t ei1;
 235                 uint64_t ei2;
 236                 uint64_t ei3;
 237         } s9x;
 238 } cpt_inst_s_t;
 239
 240 /**
 241  * Structure cpt_res_s
 242  *
 243  * CPT Result Structure
 244  * The CPT coprocessor writes the result structure after it completes a
 245  * CPT_INST_S instruction. The result structure is exactly 16 bytes, and each
 246  * instruction completion produces exactly one result structure.
 247  *
 248  * This structure is stored in memory as little-endian unless
 249  * CPT()_PF_Q()_CTL[INST_BE] is set.
 250  */
 251 typedef union cpt_res_s {
 252         uint64_t u[2];
 253         struct cpt_res_s_8s {
 254 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 255                 uint64_t reserved_17_63        : 47;
 256                 /** [ 16: 16] Done interrupt. This bit is copied from the
 257                  * corresponding instruction's CPT_INST_S[DONEINT].
 258                  **/
 259                 uint64_t doneint               : 1;
 260                 uint64_t reserved_8_15         : 8;
 261                 /** [  7:  0] Indicates completion/error status of the CPT
 262                  * coprocessor for the associated instruction, as enumerated by
 263                  * CPT_COMP_E. Core software may write the memory location
 264                  * containing [COMPCODE] to 0x0 before ringing the doorbell, and
 265                  * then poll for completion by checking for a nonzero value.
 266                  *
 267                  * Once the core observes a nonzero [COMPCODE] value in this
 268                  * case, the CPT coprocessor will have also completed L2/DRAM
 269                  * write operations.
 270                  **/
 271                 uint64_t compcode              : 8;
 272 #else /* Word 0 - Little Endian */
 273                 uint64_t compcode              : 8;
 274                 uint64_t reserved_8_15         : 8;
 275                 uint64_t doneint               : 1;
 276                 uint64_t reserved_17_63        : 47;
 277 #endif /* Word 0 - End */
 278 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 1 - Big Endian */
 279                 uint64_t reserved_64_127       : 64;
 280 #else /* Word 1 - Little Endian */
 281                 uint64_t reserved_64_127       : 64;
 282 #endif /* Word 1 - End */
 283         } s8x;
 284         struct cpt_res_s_9s {
 285 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 286                 uint64_t reserved_17_63:47;
 287                 uint64_t doneint:1;
 288                 uint64_t uc_compcode:8;
 289                 uint64_t compcode:8;
 290 #else /* Word 0 - Little Endian */
 291                 uint64_t compcode:8;
 292                 uint64_t uc_compcode:8;
 293                 uint64_t doneint:1;
 294                 uint64_t reserved_17_63:47;
 295 #endif /* Word 0 - End */
 296                 uint64_t reserved_64_127;
 297         } s9x;
 298 } cpt_res_s_t;
 299
 300 /**
 301  * Register (NCB) cpt#_vq#_ctl
 302  *
 303  * CPT VF Queue Control Registers
 304  * This register configures queues. This register should be changed (other than
 305  * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
 306  */
 307 typedef union {
 308         uint64_t u;
 309         struct cptx_vqx_ctl_s {
 310 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 311                 uint64_t reserved_1_63         : 63;
 312                 /** [  0:  0](R/W/H) Enables the logical instruction queue.
 313                  * See also CPT()_PF_Q()_CTL[CONT_ERR] and
 314                  * CPT()_VQ()_INPROG[INFLIGHT].
 315                  * 1 = Queue is enabled.
 316                  * 0 = Queue is disabled.
 317                  **/
 318                 uint64_t ena                   : 1;
 319 #else /* Word 0 - Little Endian */
 320                 uint64_t ena                   : 1;
 321                 uint64_t reserved_1_63         : 63;
 322 #endif /* Word 0 - End */
 323         } s;
 324 } cptx_vqx_ctl_t;
 325
 326 /**
 327  * Register (NCB) cpt#_vq#_done
 328  *
 329  * CPT Queue Done Count Registers
 330  * These registers contain the per-queue instruction done count.
 331  */
 332 typedef union {
 333         uint64_t u;
 334         struct cptx_vqx_done_s {
 335 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 336                 uint64_t reserved_20_63        : 44;
 337                 /** [ 19:  0](R/W/H) Done count. When CPT_INST_S[DONEINT] set
 338                  * and that instruction completes,CPT()_VQ()_DONE[DONE] is
 339                  * incremented when the instruction finishes. Write to this
 340                  * field are for diagnostic use only; instead software writes
 341                  * CPT()_VQ()_DONE_ACK with the number of decrements for this
 342                  * field.
 343                  *
 344                  * Interrupts are sent as follows:
 345                  *
 346                  * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending,
 347                  * the interrupt coalescing timer is held to zero, and an
 348                  * interrupt is not sent.
 349                  *
 350                  * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt
 351                  * coalescing timer counts. If the counter is >= CPT()_VQ()_DONE
 352                  * _WAIT[TIME_WAIT]*1024, or CPT()_VQ()_DONE[DONE] >= CPT()_VQ()
 353                  * _DONE_WAIT[NUM_WAIT], i.e. enough time has passed or enough
 354                  * results have arrived, then the interrupt is sent.  Otherwise,
 355                  * it is not sent due to coalescing.
 356                  *
 357                  * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is
 358                  * written but this is not typical), the interrupt coalescing
 359                  * timer restarts.  Note after decrementing this interrupt
 360                  * equation is recomputed, for example if CPT()_VQ()_DONE[DONE]
 361                  * >= CPT()_VQ()_DONE_WAIT[NUM_WAIT] and because the timer is
 362                  * zero, the interrupt will be resent immediately.  (This covers
 363                  * the race case between software acknowledging an interrupt and
 364                  * a result returning.)
 365                  *
 366                  * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not
 367                  * sent, but the counting described above still occurs.
 368                  *
 369                  * Since CPT instructions complete out-of-order, if software is
 370                  * using completion interrupts the suggested scheme is to
 371                  * request a DONEINT on each request, and when an interrupt
 372                  * arrives perform a "greedy" scan for completions; even if a
 373                  * later command is acknowledged first this will not result in
 374                  * missing a completion.
 375                  *
 376                  * Software is responsible for making sure [DONE] does not
 377                  * overflow; for example by insuring there are not more than
 378                  * 2^20-1 instructions in flight that may request interrupts.
 379                  **/
 380                 uint64_t done                  : 20;
 381 #else /* Word 0 - Little Endian */
 382                 uint64_t done                  : 20;
 383                 uint64_t reserved_20_63        : 44;
 384 #endif /* Word 0 - End */
 385         } s;
 386 } cptx_vqx_done_t;
 387
 388 /**
 389  * Register (NCB) cpt#_vq#_done_ack
 390  *
 391  * CPT Queue Done Count Ack Registers
 392  * This register is written by software to acknowledge interrupts.
 393  */
 394 typedef union {
 395         uint64_t u;
 396         struct cptx_vqx_done_ack_s {
 397 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 398                 uint64_t reserved_20_63        : 44;
 399                 /** [ 19:  0](R/W/H) Number of decrements to CPT()_VQ()_DONE
 400                  * [DONE]. Reads CPT()_VQ()_DONE[DONE].
 401                  *
 402                  * Written by software to acknowledge interrupts. If CPT()_VQ()_
 403                  * DONE[DONE] is still nonzero the interrupt will be re-sent if
 404                  * the conditions described in CPT()_VQ()_DONE[DONE] are
 405                  * satisfied.
 406                  **/
 407                 uint64_t done_ack              : 20;
 408 #else /* Word 0 - Little Endian */
 409                 uint64_t done_ack              : 20;
 410                 uint64_t reserved_20_63        : 44;
 411 #endif /* Word 0 - End */
 412         } s;
 413 } cptx_vqx_done_ack_t;
 414
 415 /**
 416  * Register (NCB) cpt#_vq#_done_wait
 417  *
 418  * CPT Queue Done Interrupt Coalescing Wait Registers
 419  * Specifies the per queue interrupt coalescing settings.
 420  */
 421 typedef union {
 422         uint64_t u;
 423         struct cptx_vqx_done_wait_s {
 424 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 425                 uint64_t reserved_48_63        : 16;
 426                 /** [ 47: 32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] =
 427                  * 0, or CPT()_VQ()_DONE_ACK is written a timer is cleared. When
 428                  * the timer reaches [TIME_WAIT]*1024 then interrupt coalescing
 429                  * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is
 430                  * disabled.
 431                  **/
 432                 uint64_t time_wait             : 16;
 433                 uint64_t reserved_20_31        : 12;
 434                 /** [ 19:  0](R/W) Number of messages hold-off. When
 435                  * CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing
 436                  * ends; see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as
 437                  * 0x1.
 438                  **/
 439                 uint64_t num_wait              : 20;
 440 #else /* Word 0 - Little Endian */
 441                 uint64_t num_wait              : 20;
 442                 uint64_t reserved_20_31        : 12;
 443                 uint64_t time_wait             : 16;
 444                 uint64_t reserved_48_63        : 16;
 445 #endif /* Word 0 - End */
 446         } s;
 447 } cptx_vqx_done_wait_t;
 448
 449 /**
 450  * Register (NCB) cpt#_vq#_doorbell
 451  *
 452  * CPT Queue Doorbell Registers
 453  * Doorbells for the CPT instruction queues.
 454  */
 455 typedef union {
 456         uint64_t u;
 457         struct cptx_vqx_doorbell_s {
 458 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 459                 uint64_t reserved_20_63        : 44;
 460                 uint64_t dbell_cnt             : 20;
 461                 /** [ 19:  0](R/W/H) Number of instruction queue 64-bit words
 462                  * to add to the CPT instruction doorbell count. Readback value
 463                  * is the the current number of pending doorbell requests.
 464                  *
 465                  * If counter overflows CPT()_VQ()_MISC_INT[DBELL_DOVF] is set.
 466                  *
 467                  * To reset the count back to zero, write one to clear
 468                  * CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF], then write a value
 469                  * of 2^20 minus the read [DBELL_CNT], then write one to
 470                  * CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
 471                  * CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF].
 472                  *
 473                  * Must be a multiple of 8.  All CPT instructions are 8 words
 474                  * and require a doorbell count of multiple of 8.
 475                  **/
 476 #else /* Word 0 - Little Endian */
 477                 uint64_t dbell_cnt             : 20;
 478                 uint64_t reserved_20_63        : 44;
 479 #endif /* Word 0 - End */
 480         } s;
 481 } cptx_vqx_doorbell_t;
 482
 483 /**
 484  * Register (NCB) cpt#_vq#_inprog
 485  *
 486  * CPT Queue In Progress Count Registers
 487  * These registers contain the per-queue instruction in flight registers.
 488  */
 489 typedef union {
 490         uint64_t u;
 491         struct cptx_vqx_inprog_s {
 492 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 493                 uint64_t reserved_8_63         : 56;
 494                 /** [  7:  0](RO/H) Inflight count. Counts the number of
 495                  * instructions for the VF for which CPT is fetching, executing
 496                  * or responding to instructions. However this does not include
 497                  * any interrupts that are awaiting software handling
 498                  * (CPT()_VQ()_DONE[DONE] != 0x0).
 499                  *
 500                  * A queue may not be reconfigured until:
 501                  *  1. CPT()_VQ()_CTL[ENA] is cleared by software.
 502                  *  2. [INFLIGHT] is polled until equals to zero.
 503                  **/
 504                 uint64_t inflight              : 8;
 505 #else /* Word 0 - Little Endian */
 506                 uint64_t inflight              : 8;
 507                 uint64_t reserved_8_63         : 56;
 508 #endif /* Word 0 - End */
 509         } s;
 510 } cptx_vqx_inprog_t;
 511
 512 /**
 513  * Register (NCB) cpt#_vq#_misc_int
 514  *
 515  * CPT Queue Misc Interrupt Register
 516  * These registers contain the per-queue miscellaneous interrupts.
 517  */
 518 typedef union {
 519         uint64_t u;
 520         struct cptx_vqx_misc_int_s {
 521 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 522                 uint64_t reserved_7_63         : 57;
 523                 /** [  6:  6](R/W1C/H) Translation fault detected. */
 524                 uint64_t fault                 : 1;
 525                 /** [  5:  5](R/W1C/H) Hardware error from engines. */
 526                 uint64_t hwerr                 : 1;
 527                 /** [  4:  4](R/W1C/H) Software error from engines. */
 528                 uint64_t swerr                 : 1;
 529                 /** [  3:  3](R/W1C/H) NCB result write response error. */
 530                 uint64_t nwrp                  : 1;
 531                 /** [  2:  2](R/W1C/H) Instruction NCB read response error. */
 532                 uint64_t irde                  : 1;
 533                 /** [  1:  1](R/W1C/H) Doorbell overflow. */
 534                 uint64_t dovf                  : 1;
 535                 /** [  0:  0](R/W1C/H) PF to VF mailbox interrupt. Set when
 536                  * CPT()_VF()_PF_MBOX(0) is written.
 537                  **/
 538                 uint64_t mbox                  : 1;
 539 #else /* Word 0 - Little Endian */
 540                 uint64_t mbox                  : 1;
 541                 uint64_t dovf                  : 1;
 542                 uint64_t irde                  : 1;
 543                 uint64_t nwrp                  : 1;
 544                 uint64_t swerr                 : 1;
 545                 uint64_t hwerr                 : 1;
 546                 uint64_t fault                 : 1;
 547                 uint64_t reserved_5_63         : 59;
 548 #endif /* Word 0 - End */
 549         } s;
 550 } cptx_vqx_misc_int_t;
 551
 552 /**
 553  * Register (NCB) cpt#_vq#_saddr
 554  *
 555  * CPT Queue Starting Buffer Address Registers
 556  * These registers set the instruction buffer starting address.
 557  */
 558 typedef union {
 559         uint64_t u;
 560         struct cptx_vqx_saddr_s {
 561 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
 562                 uint64_t reserved_49_63        : 15;
 563                 /** [ 48:  6](R/W/H) Instruction buffer IOVA <48:6>
 564                  * (64-byte aligned). When written, it is the initial buffer
 565                  * starting address; when read, it is the next read pointer to
 566                  * be requested from L2C. The PTR field is overwritten with the
 567                  * next pointer each time that the command buffer segment is
 568                  * exhausted. New commands will then be read from the newly
 569                  * specified command buffer pointer.
 570                  **/
 571                 uint64_t ptr                   : 43;
 572                 uint64_t reserved_0_5          : 6;
 573 #else /* Word 0 - Little Endian */
 574                 uint64_t reserved_0_5          : 6;
 575                 uint64_t ptr                   : 43;
 576                 uint64_t reserved_49_63        : 15;
 577 #endif /* Word 0 - End */
 578         } s;
 579 } cptx_vqx_saddr_t;
 580
 581 #endif /*_CPT_HW_TYPES_H_ */