ceph/src/spdk/dpdk/drivers/common/qat/qat_adf/icp_qat_fw_la.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4 #ifndef _ICP_QAT_FW_LA_H_
   5 #define _ICP_QAT_FW_LA_H_
   6 #include "icp_qat_fw.h"
   7
   8 enum icp_qat_fw_la_cmd_id {
   9         ICP_QAT_FW_LA_CMD_CIPHER = 0,
  10         ICP_QAT_FW_LA_CMD_AUTH = 1,
  11         ICP_QAT_FW_LA_CMD_CIPHER_HASH = 2,
  12         ICP_QAT_FW_LA_CMD_HASH_CIPHER = 3,
  13         ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM = 4,
  14         ICP_QAT_FW_LA_CMD_TRNG_TEST = 5,
  15         ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE = 6,
  16         ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE = 7,
  17         ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE = 8,
  18         ICP_QAT_FW_LA_CMD_MGF1 = 9,
  19         ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10,
  20         ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11,
  21         ICP_QAT_FW_LA_CMD_DELIMITER = 12
  22 };
  23
  24 #define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
  25 #define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
  26 #define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
  27 #define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
  28
  29 struct icp_qat_fw_la_bulk_req {
  30         struct icp_qat_fw_comn_req_hdr comn_hdr;
  31         struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
  32         struct icp_qat_fw_comn_req_mid comn_mid;
  33         struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
  34         struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
  35 };
  36
  37 #define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1
  38 #define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0
  39 #define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12
  40 #define ICP_QAT_FW_LA_ZUC_3G_PROTO 1
  41 #define QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK 0x1
  42 #define QAT_LA_GCM_IV_LEN_FLAG_BITPOS 11
  43 #define QAT_LA_GCM_IV_LEN_FLAG_MASK 0x1
  44 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER 1
  45 #define ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER 0
  46 #define QAT_LA_DIGEST_IN_BUFFER_BITPOS  10
  47 #define QAT_LA_DIGEST_IN_BUFFER_MASK 0x1
  48 #define ICP_QAT_FW_LA_SNOW_3G_PROTO 4
  49 #define ICP_QAT_FW_LA_GCM_PROTO 2
  50 #define ICP_QAT_FW_LA_CCM_PROTO 1
  51 #define ICP_QAT_FW_LA_NO_PROTO 0
  52 #define QAT_LA_PROTO_BITPOS 7
  53 #define QAT_LA_PROTO_MASK 0x7
  54 #define ICP_QAT_FW_LA_CMP_AUTH_RES 1
  55 #define ICP_QAT_FW_LA_NO_CMP_AUTH_RES 0
  56 #define QAT_LA_CMP_AUTH_RES_BITPOS 6
  57 #define QAT_LA_CMP_AUTH_RES_MASK 0x1
  58 #define ICP_QAT_FW_LA_RET_AUTH_RES 1
  59 #define ICP_QAT_FW_LA_NO_RET_AUTH_RES 0
  60 #define QAT_LA_RET_AUTH_RES_BITPOS 5
  61 #define QAT_LA_RET_AUTH_RES_MASK 0x1
  62 #define ICP_QAT_FW_LA_UPDATE_STATE 1
  63 #define ICP_QAT_FW_LA_NO_UPDATE_STATE 0
  64 #define QAT_LA_UPDATE_STATE_BITPOS 4
  65 #define QAT_LA_UPDATE_STATE_MASK 0x1
  66 #define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP 0
  67 #define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP 1
  68 #define QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS 3
  69 #define QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK 0x1
  70 #define ICP_QAT_FW_CIPH_IV_64BIT_PTR 0
  71 #define ICP_QAT_FW_CIPH_IV_16BYTE_DATA 1
  72 #define QAT_LA_CIPH_IV_FLD_BITPOS 2
  73 #define QAT_LA_CIPH_IV_FLD_MASK   0x1
  74 #define ICP_QAT_FW_LA_PARTIAL_NONE 0
  75 #define ICP_QAT_FW_LA_PARTIAL_START 1
  76 #define ICP_QAT_FW_LA_PARTIAL_MID 3
  77 #define ICP_QAT_FW_LA_PARTIAL_END 2
  78 #define QAT_LA_PARTIAL_BITPOS 0
  79 #define QAT_LA_PARTIAL_MASK 0x3
  80 #define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \
  81         cmp_auth, ret_auth, update_state, \
  82         ciph_iv, ciphcfg, partial) \
  83         (((zuc_proto & QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) << \
  84         QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS) | \
  85         ((gcm_iv_len & QAT_LA_GCM_IV_LEN_FLAG_MASK) << \
  86         QAT_LA_GCM_IV_LEN_FLAG_BITPOS) | \
  87         ((auth_rslt & QAT_LA_DIGEST_IN_BUFFER_MASK) << \
  88         QAT_LA_DIGEST_IN_BUFFER_BITPOS) | \
  89         ((proto & QAT_LA_PROTO_MASK) << \
  90         QAT_LA_PROTO_BITPOS)    | \
  91         ((cmp_auth & QAT_LA_CMP_AUTH_RES_MASK) << \
  92         QAT_LA_CMP_AUTH_RES_BITPOS) | \
  93         ((ret_auth & QAT_LA_RET_AUTH_RES_MASK) << \
  94         QAT_LA_RET_AUTH_RES_BITPOS) | \
  95         ((update_state & QAT_LA_UPDATE_STATE_MASK) << \
  96         QAT_LA_UPDATE_STATE_BITPOS) | \
  97         ((ciph_iv & QAT_LA_CIPH_IV_FLD_MASK) << \
  98         QAT_LA_CIPH_IV_FLD_BITPOS) | \
  99         ((ciphcfg & QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) << \
 100         QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS) | \
 101         ((partial & QAT_LA_PARTIAL_MASK) << \
 102         QAT_LA_PARTIAL_BITPOS))
 103
 104 #define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET(flags) \
 105         QAT_FIELD_GET(flags, QAT_LA_CIPH_IV_FLD_BITPOS, \
 106         QAT_LA_CIPH_IV_FLD_MASK)
 107
 108 #define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags) \
 109         QAT_FIELD_GET(flags, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
 110         QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
 111
 112 #define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET(flags) \
 113         QAT_FIELD_GET(flags, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
 114         QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
 115
 116 #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET(flags) \
 117         QAT_FIELD_GET(flags, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
 118         QAT_LA_GCM_IV_LEN_FLAG_MASK)
 119
 120 #define ICP_QAT_FW_LA_PROTO_GET(flags) \
 121         QAT_FIELD_GET(flags, QAT_LA_PROTO_BITPOS, QAT_LA_PROTO_MASK)
 122
 123 #define ICP_QAT_FW_LA_CMP_AUTH_GET(flags) \
 124         QAT_FIELD_GET(flags, QAT_LA_CMP_AUTH_RES_BITPOS, \
 125         QAT_LA_CMP_AUTH_RES_MASK)
 126
 127 #define ICP_QAT_FW_LA_RET_AUTH_GET(flags) \
 128         QAT_FIELD_GET(flags, QAT_LA_RET_AUTH_RES_BITPOS, \
 129         QAT_LA_RET_AUTH_RES_MASK)
 130
 131 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET(flags) \
 132         QAT_FIELD_GET(flags, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
 133         QAT_LA_DIGEST_IN_BUFFER_MASK)
 134
 135 #define ICP_QAT_FW_LA_UPDATE_STATE_GET(flags) \
 136         QAT_FIELD_GET(flags, QAT_LA_UPDATE_STATE_BITPOS, \
 137         QAT_LA_UPDATE_STATE_MASK)
 138
 139 #define ICP_QAT_FW_LA_PARTIAL_GET(flags) \
 140         QAT_FIELD_GET(flags, QAT_LA_PARTIAL_BITPOS, \
 141         QAT_LA_PARTIAL_MASK)
 142
 143 #define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \
 144         QAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \
 145         QAT_LA_CIPH_IV_FLD_MASK)
 146
 147 #define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \
 148         QAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
 149         QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
 150
 151 #define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \
 152         QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
 153         QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
 154
 155 #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \
 156         QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
 157         QAT_LA_GCM_IV_LEN_FLAG_MASK)
 158
 159 #define ICP_QAT_FW_LA_PROTO_SET(flags, val) \
 160         QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \
 161         QAT_LA_PROTO_MASK)
 162
 163 #define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \
 164         QAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \
 165         QAT_LA_CMP_AUTH_RES_MASK)
 166
 167 #define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \
 168         QAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \
 169         QAT_LA_RET_AUTH_RES_MASK)
 170
 171 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \
 172         QAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
 173         QAT_LA_DIGEST_IN_BUFFER_MASK)
 174
 175 #define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \
 176         QAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \
 177         QAT_LA_UPDATE_STATE_MASK)
 178
 179 #define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \
 180         QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
 181         QAT_LA_PARTIAL_MASK)
 182
 183 struct icp_qat_fw_cipher_req_hdr_cd_pars {
 184         union {
 185                 struct {
 186                         uint64_t content_desc_addr;
 187                         uint16_t content_desc_resrvd1;
 188                         uint8_t content_desc_params_sz;
 189                         uint8_t content_desc_hdr_resrvd2;
 190                         uint32_t content_desc_resrvd3;
 191                 } s;
 192                 struct {
 193                         uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
 194                 } s1;
 195         } u;
 196 };
 197
 198 struct icp_qat_fw_cipher_auth_req_hdr_cd_pars {
 199         union {
 200                 struct {
 201                         uint64_t content_desc_addr;
 202                         uint16_t content_desc_resrvd1;
 203                         uint8_t content_desc_params_sz;
 204                         uint8_t content_desc_hdr_resrvd2;
 205                         uint32_t content_desc_resrvd3;
 206                 } s;
 207                 struct {
 208                         uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
 209                 } sl;
 210         } u;
 211 };
 212
 213 struct icp_qat_fw_cipher_cd_ctrl_hdr {
 214         uint8_t cipher_state_sz;
 215         uint8_t cipher_key_sz;
 216         uint8_t cipher_cfg_offset;
 217         uint8_t next_curr_id;
 218         uint8_t cipher_padding_sz;
 219         uint8_t resrvd1;
 220         uint16_t resrvd2;
 221         uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];
 222 };
 223
 224 struct icp_qat_fw_auth_cd_ctrl_hdr {
 225         uint32_t resrvd1;
 226         uint8_t resrvd2;
 227         uint8_t hash_flags;
 228         uint8_t hash_cfg_offset;
 229         uint8_t next_curr_id;
 230         uint8_t resrvd3;
 231         uint8_t outer_prefix_sz;
 232         uint8_t final_sz;
 233         uint8_t inner_res_sz;
 234         uint8_t resrvd4;
 235         uint8_t inner_state1_sz;
 236         uint8_t inner_state2_offset;
 237         uint8_t inner_state2_sz;
 238         uint8_t outer_config_offset;
 239         uint8_t outer_state1_sz;
 240         uint8_t outer_res_sz;
 241         uint8_t outer_prefix_offset;
 242 };
 243
 244 struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {
 245         uint8_t cipher_state_sz;
 246         uint8_t cipher_key_sz;
 247         uint8_t cipher_cfg_offset;
 248         uint8_t next_curr_id_cipher;
 249         uint8_t cipher_padding_sz;
 250         uint8_t hash_flags;
 251         uint8_t hash_cfg_offset;
 252         uint8_t next_curr_id_auth;
 253         uint8_t resrvd1;
 254         uint8_t outer_prefix_sz;
 255         uint8_t final_sz;
 256         uint8_t inner_res_sz;
 257         uint8_t resrvd2;
 258         uint8_t inner_state1_sz;
 259         uint8_t inner_state2_offset;
 260         uint8_t inner_state2_sz;
 261         uint8_t outer_config_offset;
 262         uint8_t outer_state1_sz;
 263         uint8_t outer_res_sz;
 264         uint8_t outer_prefix_offset;
 265 };
 266
 267 #define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1
 268 #define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0
 269 #define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX   240
 270 #define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET \
 271         (sizeof(struct icp_qat_fw_la_cipher_req_params_t))
 272 #define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)
 273
 274 struct icp_qat_fw_la_cipher_req_params {
 275         uint32_t cipher_offset;
 276         uint32_t cipher_length;
 277         union {
 278                 uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
 279                 struct {
 280                         uint64_t cipher_IV_ptr;
 281                         uint64_t resrvd1;
 282                 } s;
 283         } u;
 284 };
 285
 286 struct icp_qat_fw_la_auth_req_params {
 287         uint32_t auth_off;
 288         uint32_t auth_len;
 289         union {
 290                 uint64_t auth_partial_st_prefix;
 291                 uint64_t aad_adr;
 292         } u1;
 293         uint64_t auth_res_addr;
 294         union {
 295                 uint8_t inner_prefix_sz;
 296                 uint8_t aad_sz;
 297         } u2;
 298         uint8_t resrvd1;
 299         uint8_t hash_state_sz;
 300         uint8_t auth_res_sz;
 301 } __rte_packed;
 302
 303 struct icp_qat_fw_la_auth_req_params_resrvd_flds {
 304         uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];
 305         union {
 306                 uint8_t inner_prefix_sz;
 307                 uint8_t aad_sz;
 308         } u2;
 309         uint8_t resrvd1;
 310         uint16_t resrvd2;
 311 };
 312
 313 struct icp_qat_fw_la_resp {
 314         struct icp_qat_fw_comn_resp_hdr comn_resp;
 315         uint64_t opaque_data;
 316         uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
 317 };
 318
 319 #define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \
 320         ((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \
 321           ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
 322
 323 #define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
 324 { (cd_ctrl_hdr_t)->next_curr_id_cipher = \
 325         ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
 326         & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
 327         ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
 328         & ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
 329
 330 #define ICP_QAT_FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t) \
 331         (((cd_ctrl_hdr_t)->next_curr_id_cipher) \
 332         & ICP_QAT_FW_COMN_CURR_ID_MASK)
 333
 334 #define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \
 335 { (cd_ctrl_hdr_t)->next_curr_id_cipher = \
 336         ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
 337         & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
 338         ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
 339
 340 #define ICP_QAT_FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t) \
 341         ((((cd_ctrl_hdr_t)->next_curr_id_auth) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
 342         >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
 343
 344 #define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
 345 { (cd_ctrl_hdr_t)->next_curr_id_auth = \
 346         ((((cd_ctrl_hdr_t)->next_curr_id_auth) \
 347         & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
 348         ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
 349         & ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
 350
 351 #define ICP_QAT_FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t) \
 352         (((cd_ctrl_hdr_t)->next_curr_id_auth) \
 353         & ICP_QAT_FW_COMN_CURR_ID_MASK)
 354
 355 #define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \
 356 { (cd_ctrl_hdr_t)->next_curr_id_auth = \
 357         ((((cd_ctrl_hdr_t)->next_curr_id_auth) \
 358         & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
 359         ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
 360
 361 #endif