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1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */
2 /* Copyright (C) 2014-2017 aQuantia Corporation. */
3
4 /* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
5 * abstraction layer.
6 */
7
8 #ifndef HW_ATL_UTILS_H
9 #define HW_ATL_UTILS_H
10
11 #define BIT(x) (1UL << (x))
12 #define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
13
14 /* Hardware tx descriptor */
15 struct hw_atl_txd_s {
16 u64 buf_addr;
17
18 union {
19 struct {
20 u32 type:3;
21 u32:1;
22 u32 len:16;
23 u32 dd:1;
24 u32 eop:1;
25 u32 cmd:8;
26 u32:14;
27 u32 ct_idx:1;
28 u32 ct_en:1;
29 u32 pay_len:18;
30 } __attribute__((__packed__));
31 u64 flags;
32 };
33 } __attribute__((__packed__));
34
35 /* Hardware tx context descriptor */
36 union hw_atl_txc_s {
37 struct {
38 u64 flags1;
39 u64 flags2;
40 };
41
42 struct {
43 u64:40;
44 u32 tun_len:8;
45 u32 out_len:16;
46 u32 type:3;
47 u32 idx:1;
48 u32 vlan_tag:16;
49 u32 cmd:4;
50 u32 l2_len:7;
51 u32 l3_len:9;
52 u32 l4_len:8;
53 u32 mss_len:16;
54 } __attribute__((__packed__));
55 } __attribute__((__packed__));
56
57 enum aq_tx_desc_type {
58 tx_desc_type_desc = 1,
59 tx_desc_type_ctx = 2,
60 };
61
62 enum aq_tx_desc_cmd {
63 tx_desc_cmd_vlan = 1,
64 tx_desc_cmd_fcs = 2,
65 tx_desc_cmd_ipv4 = 4,
66 tx_desc_cmd_l4cs = 8,
67 tx_desc_cmd_lso = 0x10,
68 tx_desc_cmd_wb = 0x20,
69 };
70
71
72 /* Hardware rx descriptor */
73 struct hw_atl_rxd_s {
74 u64 buf_addr;
75 u64 hdr_addr;
76 } __attribute__((__packed__));
77
78 /* Hardware rx descriptor writeback */
79 struct hw_atl_rxd_wb_s {
80 u32 rss_type:4;
81 u32 pkt_type:8;
82 u32 type:20;
83 u32 rss_hash;
84 u16 dd:1;
85 u16 eop:1;
86 u16 rx_stat:4;
87 u16 rx_estat:6;
88 u16 rsc_cnt:4;
89 u16 pkt_len;
90 u16 next_desc_ptr;
91 u16 vlan;
92 } __attribute__((__packed__));
93
94 struct hw_atl_stats_s {
95 u32 uprc;
96 u32 mprc;
97 u32 bprc;
98 u32 erpt;
99 u32 uptc;
100 u32 mptc;
101 u32 bptc;
102 u32 erpr;
103 u32 mbtc;
104 u32 bbtc;
105 u32 mbrc;
106 u32 bbrc;
107 u32 ubrc;
108 u32 ubtc;
109 u32 dpc;
110 } __attribute__((__packed__));
111
112 union ip_addr {
113 struct {
114 u8 addr[16];
115 } v6;
116 struct {
117 u8 padding[12];
118 u8 addr[4];
119 } v4;
120 } __attribute__((__packed__));
121
122 struct hw_aq_atl_utils_fw_rpc {
123 u32 msg_id;
124
125 union {
126 struct {
127 u32 pong;
128 } msg_ping;
129
130 struct {
131 u8 mac_addr[6];
132 u32 ip_addr_cnt;
133
134 struct {
135 union ip_addr addr;
136 union ip_addr mask;
137 } ip[1];
138 } msg_arp;
139
140 struct {
141 u32 len;
142 u8 packet[1514U];
143 } msg_inject;
144
145 struct {
146 u32 priority;
147 u32 wol_packet_type;
148 u32 pattern_id;
149 u32 next_wol_pattern_offset;
150 union {
151 struct {
152 u32 flags;
153 u8 ipv4_source_address[4];
154 u8 ipv4_dest_address[4];
155 u16 tcp_source_port_number;
156 u16 tcp_dest_port_number;
157 } ipv4_tcp_syn_parameters;
158
159 struct {
160 u32 flags;
161 u8 ipv6_source_address[16];
162 u8 ipv6_dest_address[16];
163 u16 tcp_source_port_number;
164 u16 tcp_dest_port_number;
165 } ipv6_tcp_syn_parameters;
166
167 struct {
168 u32 flags;
169 } eapol_request_id_message_parameters;
170
171 struct {
172 u32 flags;
173 u32 mask_offset;
174 u32 mask_size;
175 u32 pattern_offset;
176 u32 pattern_size;
177 } wol_bit_map_pattern;
178 struct {
179 u8 mac_addr[6];
180 } wol_magic_packet_pattern;
181
182 } wol_pattern;
183 } msg_wol;
184
185 struct {
186 u16 tc_quanta[8];
187 u16 tc_threshold[8];
188 } msg_msm_pfc_quantas;
189
190 struct {
191 union {
192 u32 pattern_mask;
193 struct {
194 u32 aq_pm_wol_reason_arp_v4_pkt : 1;
195 u32 aq_pm_wol_reason_ipv4_ping_pkt : 1;
196 u32 aq_pm_wol_reason_ipv6_ns_pkt : 1;
197 u32 aq_pm_wol_reason_ipv6_ping_pkt : 1;
198 u32 aq_pm_wol_reason_link_up : 1;
199 u32 aq_pm_wol_reason_link_down : 1;
200 u32 aq_pm_wol_reason_maximum : 1;
201 };
202 };
203 union {
204 u32 offload_mask;
205 };
206 } msg_enable_wakeup;
207
208 struct {
209 u32 priority;
210 u32 protocol_offload_type;
211 u32 protocol_offload_id;
212 u32 next_protocol_offload_offset;
213
214 union {
215 struct {
216 u32 flags;
217 u8 remote_ipv4_addr[4];
218 u8 host_ipv4_addr[4];
219 u8 mac_addr[6];
220 } ipv4_arp_params;
221 };
222 } msg_offload;
223
224 struct {
225 u32 id;
226 } msg_del_id;
227
228 };
229 } __attribute__((__packed__));
230
231 struct hw_aq_atl_utils_mbox_header {
232 u32 version;
233 u32 transaction_id;
234 u32 error;
235 } __attribute__((__packed__));
236
237 struct hw_aq_info {
238 u8 reserved[6];
239 u16 phy_fault_code;
240 u16 phy_temperature;
241 u8 cable_len;
242 u8 reserved1;
243 u32 cable_diag_data[4];
244 u8 reserved2[32];
245 u32 caps_lo;
246 u32 caps_hi;
247 } __attribute__((__packed__));
248
249 struct hw_aq_atl_utils_mbox {
250 struct hw_aq_atl_utils_mbox_header header;
251 struct hw_atl_stats_s stats;
252 struct hw_aq_info info;
253 } __attribute__((__packed__));
254
255 /* fw2x */
256 typedef u16 in_port_t;
257 typedef u32 ip4_addr_t;
258 typedef int int32_t;
259 typedef short int16_t;
260 typedef u32 fw_offset_t;
261
262 struct ip6_addr {
263 u32 addr[4];
264 } __attribute__((__packed__));
265
266 struct offload_ka_v4 {
267 u32 timeout;
268 in_port_t local_port;
269 in_port_t remote_port;
270 u8 remote_mac_addr[6];
271 u16 win_size;
272 u32 seq_num;
273 u32 ack_num;
274 ip4_addr_t local_ip;
275 ip4_addr_t remote_ip;
276 } __attribute__((__packed__));
277
278 struct offload_ka_v6 {
279 u32 timeout;
280 in_port_t local_port;
281 in_port_t remote_port;
282 u8 remote_mac_addr[6];
283 u16 win_size;
284 u32 seq_num;
285 u32 ack_num;
286 struct ip6_addr local_ip;
287 struct ip6_addr remote_ip;
288 } __attribute__((__packed__));
289
290 struct offload_ip_info {
291 u8 v4_local_addr_count;
292 u8 v4_addr_count;
293 u8 v6_local_addr_count;
294 u8 v6_addr_count;
295 fw_offset_t v4_addr;
296 fw_offset_t v4_prefix;
297 fw_offset_t v6_addr;
298 fw_offset_t v6_prefix;
299 } __attribute__((__packed__));
300
301 struct offload_port_info {
302 u16 udp_port_count;
303 u16 tcp_port_count;
304 fw_offset_t udp_port;
305 fw_offset_t tcp_port;
306 } __attribute__((__packed__));
307
308 struct offload_ka_info {
309 u16 v4_ka_count;
310 u16 v6_ka_count;
311 u32 retry_count;
312 u32 retry_interval;
313 fw_offset_t v4_ka;
314 fw_offset_t v6_ka;
315 } __attribute__((__packed__));
316
317 struct offload_rr_info {
318 u32 rr_count;
319 u32 rr_buf_len;
320 fw_offset_t rr_id_x;
321 fw_offset_t rr_buf;
322 } __attribute__((__packed__));
323
324 struct offload_info {
325 u32 version; // current version is 0x00000000
326 u32 len; // The whole structure length
327 // including the variable-size buf
328 u8 mac_addr[6]; // 8 bytes to keep alignment. Only
329 // first 6 meaningful.
330
331 u8 reserved[2];
332
333 struct offload_ip_info ips;
334 struct offload_port_info ports;
335 struct offload_ka_info kas;
336 struct offload_rr_info rrs;
337 u8 buf[0];
338 } __attribute__((__packed__));
339
340 struct smbus_request {
341 u32 msg_id; /* not used */
342 u32 device_id;
343 u32 address;
344 u32 length;
345 } __attribute__((__packed__));
346
347 enum macsec_msg_type {
348 macsec_cfg_msg = 0,
349 macsec_add_rx_sc_msg,
350 macsec_add_tx_sc_msg,
351 macsec_add_rx_sa_msg,
352 macsec_add_tx_sa_msg,
353 macsec_get_stats_msg,
354 };
355
356 struct macsec_cfg {
357 uint32_t enabled;
358 uint32_t egress_threshold;
359 uint32_t ingress_threshold;
360 uint32_t interrupts_enabled;
361 } __attribute__((__packed__));
362
363 struct add_rx_sc {
364 uint32_t index;
365 uint32_t pi; /* Port identifier */
366 uint32_t sci[2]; /* Secure Channel identifier */
367 uint32_t sci_mask; /* 1: enable comparison of SCI, 0: don't care */
368 uint32_t tci;
369 uint32_t tci_mask;
370 uint32_t mac_sa[2];
371 uint32_t sa_mask; /* 0: ignore mac_sa */
372 uint32_t mac_da[2];
373 uint32_t da_mask; /* 0: ignore mac_da */
374 uint32_t validate_frames; /* 0: strict, 1:check, 2:disabled */
375 uint32_t replay_protect; /* 1: enabled, 0:disabled */
376 uint32_t anti_replay_window; /* default 0 */
377 /* 1: auto_rollover enabled (when SA next_pn is saturated */
378 uint32_t an_rol;
379 } __attribute__((__packed__));
380
381 struct add_tx_sc {
382 uint32_t index;
383 uint32_t pi; /* Port identifier */
384 uint32_t sci[2]; /* Secure Channel identifier */
385 uint32_t sci_mask; /* 1: enable comparison of SCI, 0: don't care */
386 uint32_t tci; /* TCI value, used if packet is not explicitly tagged */
387 uint32_t tci_mask;
388 uint32_t mac_sa[2];
389 uint32_t sa_mask; /* 0: ignore mac_sa */
390 uint32_t mac_da[2];
391 uint32_t da_mask; /* 0: ignore mac_da */
392 uint32_t protect;
393 uint32_t curr_an; /* SA index which currently used */
394 } __attribute__((__packed__));
395
396 struct add_rx_sa {
397 uint32_t index;
398 uint32_t next_pn;
399 uint32_t key[4]; /* 128 bit key */
400 } __attribute__((__packed__));
401
402 struct add_tx_sa {
403 uint32_t index;
404 uint32_t next_pn;
405 uint32_t key[4]; /* 128 bit key */
406 } __attribute__((__packed__));
407
408 struct get_stats {
409 uint32_t version_only;
410 uint32_t ingress_sa_index;
411 uint32_t egress_sa_index;
412 uint32_t egress_sc_index;
413 } __attribute__((__packed__));
414
415 struct macsec_stats {
416 uint32_t api_version;
417 /* Ingress Common Counters */
418 uint64_t in_ctl_pkts;
419 uint64_t in_tagged_miss_pkts;
420 uint64_t in_untagged_miss_pkts;
421 uint64_t in_notag_pkts;
422 uint64_t in_untagged_pkts;
423 uint64_t in_bad_tag_pkts;
424 uint64_t in_no_sci_pkts;
425 uint64_t in_unknown_sci_pkts;
426 uint64_t in_ctrl_prt_pass_pkts;
427 uint64_t in_unctrl_prt_pass_pkts;
428 uint64_t in_ctrl_prt_fail_pkts;
429 uint64_t in_unctrl_prt_fail_pkts;
430 uint64_t in_too_long_pkts;
431 uint64_t in_igpoc_ctl_pkts;
432 uint64_t in_ecc_error_pkts;
433 uint64_t in_unctrl_hit_drop_redir;
434
435 /* Egress Common Counters */
436 uint64_t out_ctl_pkts;
437 uint64_t out_unknown_sa_pkts;
438 uint64_t out_untagged_pkts;
439 uint64_t out_too_long;
440 uint64_t out_ecc_error_pkts;
441 uint64_t out_unctrl_hit_drop_redir;
442
443 /* Ingress SA Counters */
444 uint64_t in_untagged_hit_pkts;
445 uint64_t in_ctrl_hit_drop_redir_pkts;
446 uint64_t in_not_using_sa;
447 uint64_t in_unused_sa;
448 uint64_t in_not_valid_pkts;
449 uint64_t in_invalid_pkts;
450 uint64_t in_ok_pkts;
451 uint64_t in_late_pkts;
452 uint64_t in_delayed_pkts;
453 uint64_t in_unchecked_pkts;
454 uint64_t in_validated_octets;
455 uint64_t in_decrypted_octets;
456
457 /* Egress SA Counters */
458 uint64_t out_sa_hit_drop_redirect;
459 uint64_t out_sa_protected2_pkts;
460 uint64_t out_sa_protected_pkts;
461 uint64_t out_sa_encrypted_pkts;
462
463 /* Egress SC Counters */
464 uint64_t out_sc_protected_pkts;
465 uint64_t out_sc_encrypted_pkts;
466 uint64_t out_sc_protected_octets;
467 uint64_t out_sc_encrypted_octets;
468
469 /* SA Counters expiration info */
470 uint32_t egress_threshold_expired;
471 uint32_t ingress_threshold_expired;
472 uint32_t egress_expired;
473 uint32_t ingress_expired;
474 } __attribute__((__packed__));
475
476 struct macsec_msg_fw_request {
477 uint32_t offset; /* not used */
478 uint32_t msg_type;
479
480 union {
481 struct macsec_cfg cfg;
482 struct add_rx_sc rxsc;
483 struct add_tx_sc txsc;
484 struct add_rx_sa rxsa;
485 struct add_tx_sa txsa;
486 struct get_stats stats;
487 };
488 } __attribute__((__packed__));
489
490 struct macsec_msg_fw_response {
491 uint32_t result;
492 struct macsec_stats stats;
493 } __attribute__((__packed__));
494
495 #define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U
496 #define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U
497 #define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U
498 #define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U
499 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U
500 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U
501 #define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 0x04000000U
502
503
504 #define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
505 self->chip_features)
506
507 enum hal_atl_utils_fw_state_e {
508 MPI_DEINIT = 0,
509 MPI_RESET = 1,
510 MPI_INIT = 2,
511 MPI_POWER = 4,
512 };
513
514 #define HAL_ATLANTIC_RATE_10G BIT(0)
515 #define HAL_ATLANTIC_RATE_5G BIT(1)
516 #define HAL_ATLANTIC_RATE_5GSR BIT(2)
517 #define HAL_ATLANTIC_RATE_2GS BIT(3)
518 #define HAL_ATLANTIC_RATE_1G BIT(4)
519 #define HAL_ATLANTIC_RATE_100M BIT(5)
520 #define HAL_ATLANTIC_RATE_INVALID BIT(6)
521
522 #define HAL_ATLANTIC_UTILS_FW_MSG_PING 1U
523 #define HAL_ATLANTIC_UTILS_FW_MSG_ARP 2U
524 #define HAL_ATLANTIC_UTILS_FW_MSG_INJECT 3U
525 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 4U
526 #define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 5U
527 #define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 6U
528 #define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC 7U
529 #define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 8U
530 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD 9U
531 #define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL 10U
532 #define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG 13U // 0xd
533
534 #define SMBUS_DEVICE_ID 0x50
535
536 enum hw_atl_fw2x_caps_lo {
537 CAPS_LO_10BASET_HD = 0x00,
538 CAPS_LO_10BASET_FD,
539 CAPS_LO_100BASETX_HD,
540 CAPS_LO_100BASET4_HD,
541 CAPS_LO_100BASET2_HD,
542 CAPS_LO_100BASETX_FD,
543 CAPS_LO_100BASET2_FD,
544 CAPS_LO_1000BASET_HD,
545 CAPS_LO_1000BASET_FD,
546 CAPS_LO_2P5GBASET_FD,
547 CAPS_LO_5GBASET_FD,
548 CAPS_LO_10GBASET_FD,
549 CAPS_LO_AUTONEG,
550 CAPS_LO_SMBUS_READ,
551 CAPS_LO_SMBUS_WRITE,
552 CAPS_LO_MACSEC
553 };
554
555 enum hw_atl_fw2x_caps_hi {
556 CAPS_HI_RESERVED1 = 0x00,
557 CAPS_HI_10BASET_EEE,
558 CAPS_HI_RESERVED2,
559 CAPS_HI_PAUSE,
560 CAPS_HI_ASYMMETRIC_PAUSE,
561 CAPS_HI_100BASETX_EEE,
562 CAPS_HI_RESERVED3,
563 CAPS_HI_RESERVED4,
564 CAPS_HI_1000BASET_FD_EEE,
565 CAPS_HI_2P5GBASET_FD_EEE,
566 CAPS_HI_5GBASET_FD_EEE,
567 CAPS_HI_10GBASET_FD_EEE,
568 CAPS_HI_RESERVED5,
569 CAPS_HI_RESERVED6,
570 CAPS_HI_RESERVED7,
571 CAPS_HI_RESERVED8,
572 CAPS_HI_RESERVED9,
573 CAPS_HI_CABLE_DIAG,
574 CAPS_HI_TEMPERATURE,
575 CAPS_HI_DOWNSHIFT,
576 CAPS_HI_PTP_AVB_EN,
577 CAPS_HI_MEDIA_DETECT,
578 CAPS_HI_LINK_DROP,
579 CAPS_HI_SLEEP_PROXY,
580 CAPS_HI_WOL,
581 CAPS_HI_MAC_STOP,
582 CAPS_HI_EXT_LOOPBACK,
583 CAPS_HI_INT_LOOPBACK,
584 CAPS_HI_EFUSE_AGENT,
585 CAPS_HI_WOL_TIMER,
586 CAPS_HI_STATISTICS,
587 CAPS_HI_TRANSACTION_ID,
588 };
589
590 enum hw_atl_fw2x_rate {
591 FW2X_RATE_100M = BIT(CAPS_LO_100BASETX_FD),
592 FW2X_RATE_1G = BIT(CAPS_LO_1000BASET_FD),
593 FW2X_RATE_2G5 = BIT(CAPS_LO_2P5GBASET_FD),
594 FW2X_RATE_5G = BIT(CAPS_LO_5GBASET_FD),
595 FW2X_RATE_10G = BIT(CAPS_LO_10GBASET_FD),
596 };
597
598 struct aq_hw_s;
599 struct aq_fw_ops;
600 struct aq_hw_link_status_s;
601
602 int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
603
604 int hw_atl_utils_soft_reset(struct aq_hw_s *self);
605
606 void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
607
608 int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
609 struct hw_aq_atl_utils_mbox_header *pmbox);
610
611 void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
612 struct hw_aq_atl_utils_mbox *pmbox);
613
614 void hw_atl_utils_mpi_set(struct aq_hw_s *self,
615 enum hal_atl_utils_fw_state_e state,
616 u32 speed);
617
618 int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
619
620 unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
621
622 unsigned int hw_atl_utils_hw_get_reg_length(void);
623
624 int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
625 u32 *regs_buff);
626
627 int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
628 unsigned int power_state);
629
630 int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
631
632 int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
633
634 int hw_atl_utils_update_stats(struct aq_hw_s *self);
635
636 struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
637
638 int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
639 u32 *p, u32 cnt);
640
641 int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
642 u32 cnt);
643
644 int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac);
645
646 int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
647
648 int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
649 struct hw_aq_atl_utils_fw_rpc **rpc);
650
651 extern const struct aq_fw_ops aq_fw_1x_ops;
652 extern const struct aq_fw_ops aq_fw_2x_ops;
653
654 #endif /* HW_ATL_UTILS_H */