ceph/src/spdk/dpdk/drivers/net/bnx2x/ecore_fw_defs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2007-2013 Broadcom Corporation.
   3  *
   4  * Eric Davis        <edavis@broadcom.com>
   5  * David Christensen <davidch@broadcom.com>
   6  * Gary Zambrano     <zambrano@broadcom.com>
   7  *
   8  * Copyright (c) 2014-2018 Cavium Inc.
   9  * All rights reserved.
  10  * www.cavium.com
  11  */
  12
  13 #ifndef ECORE_FW_DEFS_H
  14 #define ECORE_FW_DEFS_H
  15
  16 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
  17 #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
  18         (IRO[151].base + ((assertListEntry) * IRO[151].m1))
  19 #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
  20         (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
  21         IRO[157].m2))
  22 #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
  23         (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
  24         IRO[158].m2))
  25 #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
  26         (IRO[163].base + ((funcId) * IRO[163].m1))
  27 #define CSTORM_FUNC_EN_OFFSET(funcId) \
  28         (IRO[153].base + ((funcId) * IRO[153].m1))
  29 #define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
  30         (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
  31 #define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
  32         (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
  33         * IRO[142].m2) + ((sbId) * IRO[142].m3))
  34 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
  35 #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
  36         (IRO[323].base + ((pfId) * IRO[323].m1))
  37 #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
  38         (IRO[324].base + ((pfId) * IRO[324].m1))
  39 #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
  40         (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
  41 #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
  42         (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
  43 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
  44         (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
  45 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
  46         (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
  47 #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
  48         (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
  49 #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
  50         (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
  51 #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
  52         (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
  53 #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
  54         (IRO[322].base + ((pfId) * IRO[322].m1))
  55 #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
  56         (IRO[314].base + ((pfId) * IRO[314].m1))
  57 #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
  58         (IRO[313].base + ((pfId) * IRO[313].m1))
  59 #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
  60         (IRO[312].base + ((pfId) * IRO[312].m1))
  61 #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
  62         (IRO[155].base + ((funcId) * IRO[155].m1))
  63 #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
  64         (IRO[146].base + ((pfId) * IRO[146].m1))
  65 #define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
  66         (IRO[147].base + ((pfId) * IRO[147].m1))
  67 #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
  68         (IRO[145].base + ((pfId) * IRO[145].m1))
  69 #define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)
  70 #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
  71         (IRO[148].base + ((pfId) * IRO[148].m1))
  72 #define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)
  73 #define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
  74         (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
  75 #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
  76         (IRO[137].base + ((sbId) * IRO[137].m1))
  77 #define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
  78         (IRO[138].base + ((sbId) * IRO[138].m1))
  79 #define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
  80         (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
  81 #define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
  82         (IRO[136].base + ((sbId) * IRO[136].m1))
  83 #define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)
  84 #define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
  85         (IRO[141].base + ((sbId) * IRO[141].m1))
  86 #define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)
  87 #define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
  88         (IRO[159].base + ((vfId) * IRO[159].m1))
  89 #define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
  90         (IRO[160].base + ((vfId) * IRO[160].m1))
  91 #define CSTORM_VF_TO_PF_OFFSET(funcId) \
  92         (IRO[154].base + ((funcId) * IRO[154].m1))
  93 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
  94         (IRO[207].base + ((pfId) * IRO[207].m1))
  95 #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
  96 #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
  97         (IRO[101].base + ((assertListEntry) * IRO[101].m1))
  98 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
  99         (IRO[205].base + ((pfId) * IRO[205].m1))
 100 #define TSTORM_FUNC_EN_OFFSET(funcId) \
 101         (IRO[107].base + ((funcId) * IRO[107].m1))
 102 #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
 103         (IRO[278].base + ((pfId) * IRO[278].m1))
 104 #define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
 105         (IRO[279].base + ((pfId) * IRO[279].m1))
 106 #define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
 107         (IRO[280].base + ((pfId) * IRO[280].m1))
 108 #define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
 109         (IRO[281].base + ((pfId) * IRO[281].m1))
 110 #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
 111         (IRO[277].base + ((pfId) * IRO[277].m1))
 112 #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
 113         (IRO[276].base + ((pfId) * IRO[276].m1))
 114 #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
 115         (IRO[275].base + ((pfId) * IRO[275].m1))
 116 #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
 117         (IRO[274].base + ((pfId) * IRO[274].m1))
 118 #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
 119         (IRO[284].base + ((pfId) * IRO[284].m1))
 120 #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
 121         (IRO[270].base + ((pfId) * IRO[270].m1))
 122 #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
 123         (IRO[271].base + ((pfId) * IRO[271].m1))
 124 #define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
 125         (IRO[272].base + ((pfId) * IRO[272].m1))
 126 #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
 127         (IRO[273].base + ((pfId) * IRO[273].m1))
 128 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
 129         (IRO[206].base + ((pfId) * IRO[206].m1))
 130 #define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
 131         (IRO[109].base + ((funcId) * IRO[109].m1))
 132 #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
 133         (IRO[223].base + ((pfId) * IRO[223].m1))
 134 #define TSTORM_VF_TO_PF_OFFSET(funcId) \
 135         (IRO[108].base + ((funcId) * IRO[108].m1))
 136 #define USTORM_AGG_DATA_OFFSET (IRO[212].base)
 137 #define USTORM_AGG_DATA_SIZE (IRO[212].size)
 138 #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
 139 #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
 140         (IRO[180].base + ((assertListEntry) * IRO[180].m1))
 141 #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
 142         (IRO[187].base + ((portId) * IRO[187].m1))
 143 #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
 144         (IRO[325].base + ((pfId) * IRO[325].m1))
 145 #define USTORM_FUNC_EN_OFFSET(funcId) \
 146         (IRO[182].base + ((funcId) * IRO[182].m1))
 147 #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
 148         (IRO[289].base + ((pfId) * IRO[289].m1))
 149 #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
 150         (IRO[290].base + ((pfId) * IRO[290].m1))
 151 #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
 152         (IRO[294].base + ((pfId) * IRO[294].m1))
 153 #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
 154         (IRO[291].base + ((pfId) * IRO[291].m1))
 155 #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
 156         (IRO[287].base + ((pfId) * IRO[287].m1))
 157 #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
 158         (IRO[286].base + ((pfId) * IRO[286].m1))
 159 #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
 160         (IRO[285].base + ((pfId) * IRO[285].m1))
 161 #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
 162         (IRO[288].base + ((pfId) * IRO[288].m1))
 163 #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
 164         (IRO[292].base + ((pfId) * IRO[292].m1))
 165 #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
 166         (IRO[293].base + ((pfId) * IRO[293].m1))
 167 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
 168         (IRO[186].base + ((pfId) * IRO[186].m1))
 169 #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
 170         (IRO[184].base + ((funcId) * IRO[184].m1))
 171 #define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
 172         (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \
 173         IRO[215].m2))
 174 #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
 175         (IRO[216].base + ((qzoneId) * IRO[216].m1))
 176 #define USTORM_TPA_BTR_OFFSET (IRO[213].base)
 177 #define USTORM_TPA_BTR_SIZE (IRO[213].size)
 178 #define USTORM_VF_TO_PF_OFFSET(funcId) \
 179         (IRO[183].base + ((funcId) * IRO[183].m1))
 180 #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
 181 #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
 182 #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
 183 #define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
 184         (IRO[50].base + ((assertListEntry) * IRO[50].m1))
 185 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \
 186         (IRO[43].base + ((portId) * IRO[43].m1))
 187 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \
 188         (IRO[45].base + ((pfId) * IRO[45].m1))
 189 #define XSTORM_FUNC_EN_OFFSET(funcId) \
 190         (IRO[47].base + ((funcId) * IRO[47].m1))
 191 #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
 192         (IRO[302].base + ((pfId) * IRO[302].m1))
 193 #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
 194         (IRO[305].base + ((pfId) * IRO[305].m1))
 195 #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
 196         (IRO[306].base + ((pfId) * IRO[306].m1))
 197 #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
 198         (IRO[307].base + ((pfId) * IRO[307].m1))
 199 #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
 200         (IRO[308].base + ((pfId) * IRO[308].m1))
 201 #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
 202         (IRO[309].base + ((pfId) * IRO[309].m1))
 203 #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
 204         (IRO[310].base + ((pfId) * IRO[310].m1))
 205 #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
 206         (IRO[311].base + ((pfId) * IRO[311].m1))
 207 #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
 208         (IRO[301].base + ((pfId) * IRO[301].m1))
 209 #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
 210         (IRO[300].base + ((pfId) * IRO[300].m1))
 211 #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
 212         (IRO[299].base + ((pfId) * IRO[299].m1))
 213 #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
 214         (IRO[304].base + ((pfId) * IRO[304].m1))
 215 #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
 216         (IRO[303].base + ((pfId) * IRO[303].m1))
 217 #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
 218         (IRO[298].base + ((pfId) * IRO[298].m1))
 219 #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
 220         (IRO[297].base + ((pfId) * IRO[297].m1))
 221 #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
 222         (IRO[296].base + ((pfId) * IRO[296].m1))
 223 #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
 224         (IRO[295].base + ((pfId) * IRO[295].m1))
 225 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
 226         (IRO[44].base + ((pfId) * IRO[44].m1))
 227 #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
 228         (IRO[49].base + ((funcId) * IRO[49].m1))
 229 #define XSTORM_SPQ_DATA_OFFSET(funcId) \
 230         (IRO[32].base + ((funcId) * IRO[32].m1))
 231 #define XSTORM_SPQ_DATA_SIZE (IRO[32].size)
 232 #define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \
 233         (IRO[30].base + ((funcId) * IRO[30].m1))
 234 #define XSTORM_SPQ_PROD_OFFSET(funcId) \
 235         (IRO[31].base + ((funcId) * IRO[31].m1))
 236 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
 237         (IRO[217].base + ((portId) * IRO[217].m1))
 238 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
 239         (IRO[218].base + ((portId) * IRO[218].m1))
 240 #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
 241         (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
 242         IRO[220].m2))
 243 #define XSTORM_VF_TO_PF_OFFSET(funcId) \
 244         (IRO[48].base + ((funcId) * IRO[48].m1))
 245 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
 246
 247 /* eth hsi version */
 248 #define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2)
 249
 250
 251 /* Ethernet Ring parameters */
 252 #define X_ETH_LOCAL_RING_SIZE 13
 253 #define FIRST_BD_IN_PKT 0
 254 #define PARSE_BD_INDEX 1
 255 #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
 256 #define U_ETH_NUM_OF_SGES_TO_FETCH 8
 257 #define U_ETH_MAX_SGES_FOR_PACKET 3
 258
 259 /* Rx ring params */
 260 #define U_ETH_LOCAL_BD_RING_SIZE 8
 261 #define U_ETH_LOCAL_SGE_RING_SIZE 10
 262 #define U_ETH_SGL_SIZE 8
 263         /* The fw will padd the buffer with this value, so the IP header \
 264         will be align to 4 Byte */
 265 #define IP_HEADER_ALIGNMENT_PADDING 2
 266
 267 #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
 268         (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
 269
 270 #define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
 271 #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
 272 #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
 273
 274 #define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
 275 #define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
 276 #define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
 277
 278 #define U_ETH_UNDEFINED_Q 0xFF
 279
 280 #define T_ETH_INDIRECTION_TABLE_SIZE 128
 281 #define T_ETH_RSS_KEY 10
 282 #define ETH_NUM_OF_RSS_ENGINES_E2 72
 283
 284 #define FILTER_RULES_COUNT 16
 285 #define MULTICAST_RULES_COUNT 16
 286 #define CLASSIFY_RULES_COUNT 16
 287
 288 /*The CRC32 seed, that is used for the hash(reduction) multicast address */
 289 #define ETH_CRC32_HASH_SEED 0x00000000
 290
 291 #define ETH_CRC32_HASH_BIT_SIZE (8)
 292 #define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)
 293
 294 /* Maximal L2 clients supported */
 295 #define ETH_MAX_RX_CLIENTS_E1 18
 296 #define ETH_MAX_RX_CLIENTS_E1H 28
 297 #define ETH_MAX_RX_CLIENTS_E2 152
 298
 299 /* Maximal statistics client Ids */
 300 #define MAX_STAT_COUNTER_ID_E1 36
 301 #define MAX_STAT_COUNTER_ID_E1H 56
 302 #define MAX_STAT_COUNTER_ID_E2 140
 303
 304 #define MAX_MAC_CREDIT_E1 192 /* Per Chip */
 305 #define MAX_MAC_CREDIT_E1H 256 /* Per Chip */
 306 #define MAX_MAC_CREDIT_E2 272 /* Per Path */
 307 #define MAX_VLAN_CREDIT_E1 0 /* Per Chip */
 308 #define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
 309 #define MAX_VLAN_CREDIT_E2 272 /* Per Path */
 310
 311
 312 /* Maximal aggregation queues supported */
 313 #define ETH_MAX_AGGREGATION_QUEUES_E1 32
 314 #define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
 315
 316
 317 #define ETH_NUM_OF_MCAST_BINS 256
 318 #define ETH_NUM_OF_MCAST_ENGINES_E2 72
 319
 320 #define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)
 321 #define ETH_MIN_RX_CQES_WITH_TPA_E1 \
 322         (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA)
 323 #define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \
 324         (ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)
 325
 326 #define DISABLE_STATISTIC_COUNTER_ID_VALUE 0
 327
 328
 329 /* This file defines HSI constants common to all microcode flows */
 330
 331 /* offset in bits of protocol in the state context parameter */
 332 #define PROTOCOL_STATE_BIT_OFFSET 6
 333
 334 #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 335 #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 336 #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
 337
 338 /* microcode fixed page page size 4K (chains and ring segments) */
 339 #define MC_PAGE_SIZE 4096
 340
 341 /* Number of indices per slow-path SB */
 342 #define HC_SP_SB_MAX_INDICES 16 /* The Maximum of all */
 343
 344 /* Number of indices per SB */
 345 #define HC_SB_MAX_INDICES_E1X 8 /* Multiple of 4 */
 346 #define HC_SB_MAX_INDICES_E2 8 /* Multiple of 4 */
 347
 348 /* Number of SB */
 349 #define HC_SB_MAX_SB_E1X 32
 350 #define HC_SB_MAX_SB_E2 136 /* include PF */
 351
 352 /* ID of slow path status block */
 353 #define HC_SP_SB_ID 0xde
 354
 355 /* Num of State machines */
 356 #define HC_SB_MAX_SM 2 /* Fixed */
 357
 358 /* Num of dynamic indices */
 359 #define HC_SB_MAX_DYNAMIC_INDICES 4 /* 0..3 fixed */
 360
 361 /* max number of slow path commands per port */
 362 #define MAX_RAMRODS_PER_PORT 8
 363
 364
 365 /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
 366
 367 /* chip timers frequency constants */
 368 #define TIMERS_TICK_SIZE_CHIP (1e-3)
 369
 370 /* used in toe: TsRecentAge, MaxRt, and temporarily RTT */
 371 #define TSEMI_CLK1_RESUL_CHIP (1e-3)
 372
 373 /* temporarily used for RTT */
 374 #define XSEMI_CLK1_RESUL_CHIP (1e-3)
 375
 376 /* used for Host Coallescing */
 377 #define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
 378 #define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
 379
 380 /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
 381
 382 #define XSTORM_IP_ID_ROLL_HALF 0x8000
 383 #define XSTORM_IP_ID_ROLL_ALL 0
 384
 385 /* assert list: number of entries */
 386 #define FW_LOG_LIST_SIZE 50
 387
 388 #define NUM_OF_SAFC_BITS 16
 389 #define MAX_COS_NUMBER 4
 390 #define MAX_TRAFFIC_TYPES 8
 391 #define MAX_PFC_PRIORITIES 8
 392 #define MAX_VLAN_PRIORITIES 8
 393         /* used by array traffic_type_to_priority[] to mark traffic type \
 394         that is not mapped to priority*/
 395 #define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
 396
 397 /* Event Ring definitions */
 398 #define C_ERES_PER_PAGE \
 399         (PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem)))
 400 #define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1)
 401
 402 /* number of statistic command */
 403 #define STATS_QUERY_CMD_COUNT 16
 404
 405 /* niv list table size */
 406 #define AFEX_LIST_TABLE_SIZE 4096
 407
 408 /* invalid VNIC Id. used in VNIC classification */
 409 #define INVALID_VNIC_ID 0xFF
 410
 411 /* used for indicating an undefined RAM offset in the IRO arrays */
 412 #define UNDEF_IRO 0x80000000
 413
 414 /* used for defining the amount of FCoE tasks supported for PF */
 415 #define MAX_FCOE_FUNCS_PER_ENGINE 2
 416 #define MAX_NUM_FCOE_TASKS_PER_ENGINE \
 417         4096 /*Each port can have at max 1 function*/
 418
 419 #endif /* ECORE_FW_DEFS_H */