1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2007-2013 Broadcom Corporation.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc.
9 * Copyright (c) 2015-2018 Cavium Inc.
10 * All rights reserved.
16 #include "ecore_mfw_req.h"
17 #include "ecore_fw_defs.h"
18 #include "ecore_hsi.h"
19 #include "ecore_reg.h"
21 static elink_status_t
elink_link_reset(struct elink_params
*params
,
22 struct elink_vars
*vars
,
23 uint8_t reset_ext_phy
);
24 static elink_status_t
elink_check_half_open_conn(struct elink_params
*params
,
25 struct elink_vars
*vars
,
27 static elink_status_t
elink_sfp_module_detection(struct elink_phy
*phy
,
28 struct elink_params
*params
);
30 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
31 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
32 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
33 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
34 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
36 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
37 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
38 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
39 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
40 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
41 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
42 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
43 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
44 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
45 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
46 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
47 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
48 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
49 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
50 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
51 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
52 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
54 #define MDIO_REG_BANK_RX0 0x80b0
55 #define MDIO_RX0_RX_STATUS 0x10
56 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
57 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
58 #define MDIO_RX0_RX_EQ_BOOST 0x1c
59 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
60 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
62 #define MDIO_REG_BANK_RX1 0x80c0
63 #define MDIO_RX1_RX_EQ_BOOST 0x1c
64 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
65 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
67 #define MDIO_REG_BANK_RX2 0x80d0
68 #define MDIO_RX2_RX_EQ_BOOST 0x1c
69 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
70 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
72 #define MDIO_REG_BANK_RX3 0x80e0
73 #define MDIO_RX3_RX_EQ_BOOST 0x1c
74 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
75 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
77 #define MDIO_REG_BANK_RX_ALL 0x80f0
78 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
79 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
80 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
82 #define MDIO_REG_BANK_TX0 0x8060
83 #define MDIO_TX0_TX_DRIVER 0x17
84 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
85 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
86 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
87 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
88 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
89 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
90 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
91 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
92 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
94 #define MDIO_REG_BANK_TX1 0x8070
95 #define MDIO_TX1_TX_DRIVER 0x17
96 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
97 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
98 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
99 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
100 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
101 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
102 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
103 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
104 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
106 #define MDIO_REG_BANK_TX2 0x8080
107 #define MDIO_TX2_TX_DRIVER 0x17
108 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
109 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
110 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
111 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
112 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
113 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
114 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
115 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
116 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
118 #define MDIO_REG_BANK_TX3 0x8090
119 #define MDIO_TX3_TX_DRIVER 0x17
120 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
121 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
122 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
123 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
124 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
125 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
126 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
127 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
128 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
130 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
131 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
133 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
134 #define MDIO_BLOCK1_LANE_CTRL0 0x15
135 #define MDIO_BLOCK1_LANE_CTRL1 0x16
136 #define MDIO_BLOCK1_LANE_CTRL2 0x17
137 #define MDIO_BLOCK1_LANE_PRBS 0x19
139 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
140 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
141 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
142 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
143 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
144 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
145 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
146 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
147 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
148 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
150 #define MDIO_REG_BANK_GP_STATUS 0x8120
151 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
152 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
153 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
154 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
155 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
156 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
157 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
158 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
159 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
160 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
161 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
162 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
163 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
164 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
165 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
182 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
183 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
184 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
185 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
186 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
187 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
188 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
190 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
191 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
192 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
193 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
194 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
195 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
196 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
197 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
198 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
199 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
200 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
201 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
202 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
203 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
204 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
205 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
206 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
207 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
208 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
209 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
210 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
211 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
212 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
213 #define MDIO_SERDES_DIGITAL_MISC1 0x18
214 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
215 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
216 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
217 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
218 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
219 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
220 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
221 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
222 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
223 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
224 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
225 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
226 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
227 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
228 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
229 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
230 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
231 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
233 #define MDIO_REG_BANK_OVER_1G 0x8320
234 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
235 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
236 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
237 #define MDIO_OVER_1G_UP1 0x19
238 #define MDIO_OVER_1G_UP1_2_5G 0x0001
239 #define MDIO_OVER_1G_UP1_5G 0x0002
240 #define MDIO_OVER_1G_UP1_6G 0x0004
241 #define MDIO_OVER_1G_UP1_10G 0x0010
242 #define MDIO_OVER_1G_UP1_10GH 0x0008
243 #define MDIO_OVER_1G_UP1_12G 0x0020
244 #define MDIO_OVER_1G_UP1_12_5G 0x0040
245 #define MDIO_OVER_1G_UP1_13G 0x0080
246 #define MDIO_OVER_1G_UP1_15G 0x0100
247 #define MDIO_OVER_1G_UP1_16G 0x0200
248 #define MDIO_OVER_1G_UP2 0x1A
249 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
250 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
251 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
252 #define MDIO_OVER_1G_UP3 0x1B
253 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
254 #define MDIO_OVER_1G_LP_UP1 0x1C
255 #define MDIO_OVER_1G_LP_UP2 0x1D
256 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
257 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
258 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
259 #define MDIO_OVER_1G_LP_UP3 0x1E
261 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
262 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
263 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
264 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
266 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
267 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
268 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
269 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
271 #define MDIO_REG_BANK_CL73_USERB0 0x8370
272 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
273 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
274 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
275 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
276 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
277 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
278 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
279 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
280 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
281 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
282 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
284 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
285 #define MDIO_AER_BLOCK_AER_REG 0x1E
287 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
288 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
289 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
290 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
291 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
292 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
293 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
294 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
295 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
296 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
297 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
298 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
299 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
300 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
301 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
302 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
303 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
304 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
305 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
306 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
307 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
308 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
309 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
310 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
311 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
312 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
313 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
314 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
315 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
316 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
318 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
319 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
320 Theotherbitsarereservedandshouldbezero*/
321 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
323 #define MDIO_PMA_DEVAD 0x1
325 #define MDIO_PMA_REG_CTRL 0x0
326 #define MDIO_PMA_REG_STATUS 0x1
327 #define MDIO_PMA_REG_10G_CTRL2 0x7
328 #define MDIO_PMA_REG_TX_DISABLE 0x0009
329 #define MDIO_PMA_REG_RX_SD 0xa
331 #define MDIO_PMA_REG_BNX2X_CTRL 0x0096
332 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
333 #define MDIO_PMA_LASI_RXCTRL 0x9000
334 #define MDIO_PMA_LASI_TXCTRL 0x9001
335 #define MDIO_PMA_LASI_CTRL 0x9002
336 #define MDIO_PMA_LASI_RXSTAT 0x9003
337 #define MDIO_PMA_LASI_TXSTAT 0x9004
338 #define MDIO_PMA_LASI_STAT 0x9005
339 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
340 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
341 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
342 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
343 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
344 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
345 #define MDIO_PMA_REG_GEN_CTRL 0xca10
346 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
347 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
348 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
349 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
350 #define MDIO_PMA_REG_ROM_VER1 0xca19
351 #define MDIO_PMA_REG_ROM_VER2 0xca1a
352 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
353 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
354 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
355 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
356 #define MDIO_PMA_REG_LRM_MODE 0xca3f
357 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
358 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
360 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
361 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
362 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
363 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
364 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
365 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
366 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
367 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
368 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
369 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
370 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
371 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
373 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
374 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
375 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
376 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
377 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
378 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
379 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
380 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
381 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
382 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
384 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
385 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
386 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
387 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
388 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
390 #define MDIO_PMA_REG_7101_RESET 0xc000
391 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
392 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
393 #define MDIO_PMA_REG_7101_VER1 0xc026
394 #define MDIO_PMA_REG_7101_VER2 0xc027
396 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
397 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
398 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
399 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
400 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
401 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
402 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
403 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
404 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
405 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
407 #define MDIO_WIS_DEVAD 0x2
409 #define MDIO_WIS_REG_LASI_CNTL 0x9002
410 #define MDIO_WIS_REG_LASI_STATUS 0x9005
412 #define MDIO_PCS_DEVAD 0x3
413 #define MDIO_PCS_REG_STATUS 0x0020
414 #define MDIO_PCS_REG_LASI_STATUS 0x9005
415 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
416 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
417 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
418 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
419 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
420 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
421 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
422 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
423 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
425 #define MDIO_XS_DEVAD 0x4
426 #define MDIO_XS_REG_STATUS 0x0001
427 #define MDIO_XS_PLL_SEQUENCER 0x8000
428 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
430 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
431 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
432 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
433 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
434 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
436 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
438 #define MDIO_AN_DEVAD 0x7
440 #define MDIO_AN_REG_CTRL 0x0000
441 #define MDIO_AN_REG_STATUS 0x0001
442 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
443 #define MDIO_AN_REG_ADV_PAUSE 0x0010
444 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
445 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
446 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
447 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
448 #define MDIO_AN_REG_ADV 0x0011
449 #define MDIO_AN_REG_ADV2 0x0012
450 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
451 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
452 #define MDIO_AN_REG_MASTER_STATUS 0x0021
453 #define MDIO_AN_REG_EEE_ADV 0x003c
454 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
456 #define MDIO_AN_REG_LINK_STATUS 0x8304
457 #define MDIO_AN_REG_CL37_CL73 0x8370
458 #define MDIO_AN_REG_CL37_AN 0xffe0
459 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
460 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
461 #define MDIO_AN_REG_1000T_STATUS 0xffea
463 #define MDIO_AN_REG_8073_2_5G 0x8329
464 #define MDIO_AN_REG_8073_BAM 0x8350
466 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
467 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
468 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
469 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
470 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
471 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
472 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
473 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
474 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
475 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
476 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
477 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
478 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
480 /* BNX2X84823 only */
481 #define MDIO_CTL_DEVAD 0x1e
482 #define MDIO_CTL_REG_84823_MEDIA 0x401a
483 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
484 /* These pins configure the BNX2X84823 interface to MAC after reset. */
485 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
486 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
487 /* These pins configure the BNX2X84823 interface to Line after reset. */
488 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
489 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
490 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
491 /* When this pin is active high during reset, 10GBASE-T core is power
492 * down, When it is active low the 10GBASE-T is power up
494 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
495 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
496 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
497 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
498 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
499 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
500 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
501 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
502 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
503 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
504 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
505 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
507 /* BNX2X84833 only */
508 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
509 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
510 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
511 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
512 #define MDIO_84833_SUPER_ISOLATE 0x8000
513 /* These are mailbox register set used by 84833. */
514 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
515 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
516 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
517 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
518 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
519 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
520 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
521 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
522 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
523 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
524 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
525 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
526 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
527 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
528 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
529 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
530 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
531 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
533 /* Mailbox command set used by 84833. */
534 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
535 #define PHY84833_CMD_GET_EEE_MODE 0x8008
536 #define PHY84833_CMD_SET_EEE_MODE 0x8009
537 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
538 /* Mailbox status set used by 84833. */
539 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
540 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
541 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
542 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
543 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
544 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
545 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
546 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
547 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
549 /* Warpcore clause 45 addressing */
550 #define MDIO_WC_DEVAD 0x3
551 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
552 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
553 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
554 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
555 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
556 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
557 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
558 #define MDIO_WC_REG_PCS_STATUS2 0x0021
559 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
560 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
561 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
562 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
563 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
564 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
565 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
566 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
567 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
568 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
569 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
570 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
571 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
572 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
573 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
574 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
575 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
576 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
577 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
578 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
579 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
580 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
581 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
582 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
583 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
584 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
585 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
586 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
587 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
588 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
589 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
590 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
591 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
592 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
593 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
594 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
595 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
596 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
597 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
598 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
599 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
600 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
601 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
602 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
603 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
604 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
605 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
606 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
607 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
608 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
609 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
610 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
611 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
612 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
613 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
614 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
615 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
616 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
617 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
618 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
619 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
620 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
621 #define MDIO_WC_REG_DSC_SMC 0x8213
622 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
623 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
624 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
625 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
626 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
627 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
628 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
629 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
630 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
631 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
632 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
633 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
634 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
635 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
636 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
637 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
638 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
639 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
640 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
641 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
642 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
643 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
644 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
645 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
646 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
647 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
648 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
649 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
650 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
651 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
652 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
653 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
654 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
655 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
656 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
657 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
658 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
659 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
660 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
661 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
662 #define MDIO_WC_REG_RX66_SCW0 0x83c2
663 #define MDIO_WC_REG_RX66_SCW1 0x83c3
664 #define MDIO_WC_REG_RX66_SCW2 0x83c4
665 #define MDIO_WC_REG_RX66_SCW3 0x83c5
666 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
667 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
668 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
669 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
670 #define MDIO_WC_REG_FX100_CTRL1 0x8400
671 #define MDIO_WC_REG_FX100_CTRL3 0x8402
672 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
673 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
674 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
675 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
676 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
677 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
678 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
679 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
680 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
681 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
682 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
683 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
684 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
685 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
687 #define MDIO_WC_REG_AERBLK_AER 0xffde
688 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
689 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
691 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
692 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
693 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
695 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
697 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
700 #define MDIO_REG_GPHY_MII_STATUS 0x1
701 #define MDIO_REG_GPHY_PHYID_LSB 0x3
702 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
703 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
704 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
705 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
706 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
707 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
708 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
709 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
710 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
711 #define MDIO_REG_GPHY_AUX_STATUS 0x19
712 #define MDIO_REG_INTR_STATUS 0x1a
713 #define MDIO_REG_INTR_MASK 0x1b
714 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
715 #define MDIO_REG_GPHY_SHADOW 0x1c
716 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
717 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
718 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
719 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
720 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
722 typedef elink_status_t(*read_sfp_module_eeprom_func_p
) (struct elink_phy
* phy
,
723 struct elink_params
*
730 /********************************************************/
731 #define ELINK_ETH_HLEN 14
732 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
733 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
734 #define ELINK_ETH_MIN_PACKET_SIZE 60
735 #define ELINK_ETH_MAX_PACKET_SIZE 1500
736 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
737 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
738 #define WC_LANE_MAX 4
739 #define I2C_SWITCH_WIDTH 2
742 #define I2C_WA_RETRY_CNT 3
743 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
744 #define MCPR_IMC_COMMAND_READ_OP 1
745 #define MCPR_IMC_COMMAND_WRITE_OP 2
747 /* LED Blink rate that will achieve ~15.9Hz */
748 #define LED_BLINK_RATE_VAL_E3 354
749 #define LED_BLINK_RATE_VAL_E1X_E2 480
750 /***********************************************************/
751 /* Shortcut definitions */
752 /***********************************************************/
754 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
756 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
757 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
758 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
759 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
760 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
761 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
762 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
763 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
764 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
765 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
766 #define ELINK_NIG_MASK_MI_INT \
767 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
768 #define ELINK_NIG_MASK_XGXS0_LINK10G \
769 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
770 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
771 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
772 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
773 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
775 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
776 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
777 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
779 #define ELINK_XGXS_RESET_BITS \
780 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
781 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
782 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
783 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
784 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
786 #define ELINK_SERDES_RESET_BITS \
787 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
788 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
789 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
790 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
792 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
793 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
794 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
795 #define ELINK_AUTONEG_PARALLEL \
796 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
797 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
798 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
799 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
801 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
802 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
803 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
804 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
805 #define ELINK_GP_STATUS_SPEED_MASK \
806 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
807 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
808 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
809 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
810 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
811 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
812 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
813 #define ELINK_GP_STATUS_10G_HIG \
814 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
815 #define ELINK_GP_STATUS_10G_CX4 \
816 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
817 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
818 #define ELINK_GP_STATUS_10G_KX4 \
819 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
820 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
821 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
822 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
823 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
824 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
825 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
826 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
827 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
828 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
829 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
830 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
831 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
832 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
833 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
834 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
835 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
836 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
837 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
838 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
839 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
841 #define ELINK_LINK_UPDATE_MASK \
842 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
843 LINK_STATUS_LINK_UP | \
844 LINK_STATUS_PHYSICAL_LINK_FLAG | \
845 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
846 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
847 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
848 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
849 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
850 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
852 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
853 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
854 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
855 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
857 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
858 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
859 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
860 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
862 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
863 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
864 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
866 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
867 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
868 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
870 #define ELINK_EDC_MODE_LINEAR 0x0022
871 #define ELINK_EDC_MODE_LIMITING 0x0044
872 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
873 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
876 #define DCBX_INVALID_COS (0xFF)
878 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
879 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
880 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
881 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
882 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
884 #define ELINK_MAX_PACKET_SIZE (9700)
885 #define MAX_KR_LINK_RETRY 4
887 /**********************************************************/
889 /**********************************************************/
891 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
892 elink_cl45_write(_sc, _phy, \
893 (_phy)->def_md_devad, \
894 (_bank + (_addr & 0xf)), \
897 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
898 elink_cl45_read(_sc, _phy, \
899 (_phy)->def_md_devad, \
900 (_bank + (_addr & 0xf)), \
903 static uint32_t elink_bits_en(struct bnx2x_softc
*sc
, uint32_t reg
, uint32_t bits
)
905 uint32_t val
= REG_RD(sc
, reg
);
908 REG_WR(sc
, reg
, val
);
912 static uint32_t elink_bits_dis(struct bnx2x_softc
*sc
, uint32_t reg
,
915 uint32_t val
= REG_RD(sc
, reg
);
918 REG_WR(sc
, reg
, val
);
923 * elink_check_lfa - This function checks if link reinitialization is required,
924 * or link flap can be avoided.
926 * @params: link parameters
927 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
930 static int elink_check_lfa(struct elink_params
*params
)
932 uint32_t link_status
, cfg_idx
, lfa_mask
, cfg_size
;
933 uint32_t cur_speed_cap_mask
, cur_req_fc_auto_adv
, additional_config
;
934 uint32_t saved_val
, req_val
, eee_status
;
935 struct bnx2x_softc
*sc
= params
->sc
;
938 REG_RD(sc
, params
->lfa_base
+
939 offsetof(struct shmem_lfa
, additional_config
));
941 /* NOTE: must be first condition checked -
942 * to verify DCC bit is cleared in any case!
944 if (additional_config
& NO_LFA_DUE_TO_DCC_MASK
) {
945 PMD_DRV_LOG(DEBUG
, "No LFA due to DCC flap after clp exit");
946 REG_WR(sc
, params
->lfa_base
+
947 offsetof(struct shmem_lfa
, additional_config
),
948 additional_config
& ~NO_LFA_DUE_TO_DCC_MASK
);
949 return LFA_DCC_LFA_DISABLED
;
952 /* Verify that link is up */
953 link_status
= REG_RD(sc
, params
->shmem_base
+
954 offsetof(struct shmem_region
,
955 port_mb
[params
->port
].link_status
));
956 if (!(link_status
& LINK_STATUS_LINK_UP
))
957 return LFA_LINK_DOWN
;
959 /* if loaded after BOOT from SAN, don't flap the link in any case and
960 * rely on link set by preboot driver
962 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_BOOT_FROM_SAN
)
965 /* Verify that loopback mode is not set */
966 if (params
->loopback_mode
)
967 return LFA_LOOPBACK_ENABLED
;
969 /* Verify that MFW supports LFA */
970 if (!params
->lfa_base
)
971 return LFA_MFW_IS_TOO_OLD
;
973 if (params
->num_phys
== 3) {
975 lfa_mask
= 0xffffffff;
982 saved_val
= REG_RD(sc
, params
->lfa_base
+
983 offsetof(struct shmem_lfa
, req_duplex
));
984 req_val
= params
->req_duplex
[0] | (params
->req_duplex
[1] << 16);
985 if ((saved_val
& lfa_mask
) != (req_val
& lfa_mask
)) {
986 PMD_DRV_LOG(INFO
, "Duplex mismatch %x vs. %x",
987 (saved_val
& lfa_mask
), (req_val
& lfa_mask
));
988 return LFA_DUPLEX_MISMATCH
;
990 /* Compare Flow Control */
991 saved_val
= REG_RD(sc
, params
->lfa_base
+
992 offsetof(struct shmem_lfa
, req_flow_ctrl
));
993 req_val
= params
->req_flow_ctrl
[0] | (params
->req_flow_ctrl
[1] << 16);
994 if ((saved_val
& lfa_mask
) != (req_val
& lfa_mask
)) {
995 PMD_DRV_LOG(DEBUG
, "Flow control mismatch %x vs. %x",
996 (saved_val
& lfa_mask
), (req_val
& lfa_mask
));
997 return LFA_FLOW_CTRL_MISMATCH
;
999 /* Compare Link Speed */
1000 saved_val
= REG_RD(sc
, params
->lfa_base
+
1001 offsetof(struct shmem_lfa
, req_line_speed
));
1002 req_val
= params
->req_line_speed
[0] | (params
->req_line_speed
[1] << 16);
1003 if ((saved_val
& lfa_mask
) != (req_val
& lfa_mask
)) {
1004 PMD_DRV_LOG(DEBUG
, "Link speed mismatch %x vs. %x",
1005 (saved_val
& lfa_mask
), (req_val
& lfa_mask
));
1006 return LFA_LINK_SPEED_MISMATCH
;
1009 for (cfg_idx
= 0; cfg_idx
< cfg_size
; cfg_idx
++) {
1010 cur_speed_cap_mask
= REG_RD(sc
, params
->lfa_base
+
1011 offsetof(struct shmem_lfa
,
1012 speed_cap_mask
[cfg_idx
]));
1014 if (cur_speed_cap_mask
!= params
->speed_cap_mask
[cfg_idx
]) {
1015 PMD_DRV_LOG(DEBUG
, "Speed Cap mismatch %x vs. %x",
1017 params
->speed_cap_mask
[cfg_idx
]);
1018 return LFA_SPEED_CAP_MISMATCH
;
1022 cur_req_fc_auto_adv
=
1023 REG_RD(sc
, params
->lfa_base
+
1024 offsetof(struct shmem_lfa
, additional_config
)) &
1025 REQ_FC_AUTO_ADV_MASK
;
1027 if ((uint16_t) cur_req_fc_auto_adv
!= params
->req_fc_auto_adv
) {
1028 PMD_DRV_LOG(DEBUG
, "Flow Ctrl AN mismatch %x vs. %x",
1029 cur_req_fc_auto_adv
, params
->req_fc_auto_adv
);
1030 return LFA_FLOW_CTRL_MISMATCH
;
1033 eee_status
= REG_RD(sc
, params
->shmem2_base
+
1034 offsetof(struct shmem2_region
,
1035 eee_status
[params
->port
]));
1037 if (((eee_status
& SHMEM_EEE_LPI_REQUESTED_BIT
) ^
1038 (params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
)) ||
1039 ((eee_status
& SHMEM_EEE_REQUESTED_BIT
) ^
1040 (params
->eee_mode
& ELINK_EEE_MODE_ADV_LPI
))) {
1041 PMD_DRV_LOG(DEBUG
, "EEE mismatch %x vs. %x", params
->eee_mode
,
1043 return LFA_EEE_MISMATCH
;
1046 /* LFA conditions are met */
1050 /******************************************************************/
1051 /* EPIO/GPIO section */
1052 /******************************************************************/
1053 static void elink_get_epio(struct bnx2x_softc
*sc
, uint32_t epio_pin
,
1056 uint32_t epio_mask
, gp_oenable
;
1059 if (epio_pin
> 31) {
1060 PMD_DRV_LOG(DEBUG
, "Invalid EPIO pin %d to get", epio_pin
);
1064 epio_mask
= 1 << epio_pin
;
1065 /* Set this EPIO to output */
1066 gp_oenable
= REG_RD(sc
, MCP_REG_MCPR_GP_OENABLE
);
1067 REG_WR(sc
, MCP_REG_MCPR_GP_OENABLE
, gp_oenable
& ~epio_mask
);
1069 *en
= (REG_RD(sc
, MCP_REG_MCPR_GP_INPUTS
) & epio_mask
) >> epio_pin
;
1072 static void elink_set_epio(struct bnx2x_softc
*sc
, uint32_t epio_pin
, uint32_t en
)
1074 uint32_t epio_mask
, gp_output
, gp_oenable
;
1077 if (epio_pin
> 31) {
1078 PMD_DRV_LOG(DEBUG
, "Invalid EPIO pin %d to set", epio_pin
);
1081 PMD_DRV_LOG(DEBUG
, "Setting EPIO pin %d to %d", epio_pin
, en
);
1082 epio_mask
= 1 << epio_pin
;
1083 /* Set this EPIO to output */
1084 gp_output
= REG_RD(sc
, MCP_REG_MCPR_GP_OUTPUTS
);
1086 gp_output
|= epio_mask
;
1088 gp_output
&= ~epio_mask
;
1090 REG_WR(sc
, MCP_REG_MCPR_GP_OUTPUTS
, gp_output
);
1092 /* Set the value for this EPIO */
1093 gp_oenable
= REG_RD(sc
, MCP_REG_MCPR_GP_OENABLE
);
1094 REG_WR(sc
, MCP_REG_MCPR_GP_OENABLE
, gp_oenable
| epio_mask
);
1097 static void elink_set_cfg_pin(struct bnx2x_softc
*sc
, uint32_t pin_cfg
,
1100 if (pin_cfg
== PIN_CFG_NA
)
1102 if (pin_cfg
>= PIN_CFG_EPIO0
) {
1103 elink_set_epio(sc
, pin_cfg
- PIN_CFG_EPIO0
, val
);
1105 uint8_t gpio_num
= (pin_cfg
- PIN_CFG_GPIO0_P0
) & 0x3;
1106 uint8_t gpio_port
= (pin_cfg
- PIN_CFG_GPIO0_P0
) >> 2;
1107 elink_cb_gpio_write(sc
, gpio_num
, (uint8_t) val
, gpio_port
);
1111 static uint32_t elink_get_cfg_pin(struct bnx2x_softc
*sc
, uint32_t pin_cfg
,
1114 if (pin_cfg
== PIN_CFG_NA
)
1115 return ELINK_STATUS_ERROR
;
1116 if (pin_cfg
>= PIN_CFG_EPIO0
) {
1117 elink_get_epio(sc
, pin_cfg
- PIN_CFG_EPIO0
, val
);
1119 uint8_t gpio_num
= (pin_cfg
- PIN_CFG_GPIO0_P0
) & 0x3;
1120 uint8_t gpio_port
= (pin_cfg
- PIN_CFG_GPIO0_P0
) >> 2;
1121 *val
= elink_cb_gpio_read(sc
, gpio_num
, gpio_port
);
1123 return ELINK_STATUS_OK
;
1127 /******************************************************************/
1129 /******************************************************************/
1130 static void elink_update_pfc_xmac(struct elink_params
*params
,
1131 struct elink_vars
*vars
)
1133 struct bnx2x_softc
*sc
= params
->sc
;
1135 uint32_t pause_val
, pfc0_val
, pfc1_val
;
1137 /* XMAC base adrr */
1138 xmac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
1140 /* Initialize pause and pfc registers */
1141 pause_val
= 0x18000;
1142 pfc0_val
= 0xFFFF8000;
1145 /* No PFC support */
1146 if (!(params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)) {
1148 /* RX flow control - Process pause frame in receive direction
1150 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
)
1151 pause_val
|= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN
;
1153 /* TX flow control - Send pause packet when buffer is full */
1154 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
)
1155 pause_val
|= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN
;
1156 } else { /* PFC support */
1157 pfc1_val
|= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN
|
1158 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN
|
1159 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN
|
1160 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN
|
1161 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON
;
1162 /* Write pause and PFC registers */
1163 REG_WR(sc
, xmac_base
+ XMAC_REG_PAUSE_CTRL
, pause_val
);
1164 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL
, pfc0_val
);
1165 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
, pfc1_val
);
1166 pfc1_val
&= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON
;
1170 /* Write pause and PFC registers */
1171 REG_WR(sc
, xmac_base
+ XMAC_REG_PAUSE_CTRL
, pause_val
);
1172 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL
, pfc0_val
);
1173 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
, pfc1_val
);
1175 /* Set MAC address for source TX Pause/PFC frames */
1176 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL_SA_LO
,
1177 ((params
->mac_addr
[2] << 24) |
1178 (params
->mac_addr
[3] << 16) |
1179 (params
->mac_addr
[4] << 8) | (params
->mac_addr
[5])));
1180 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL_SA_HI
,
1181 ((params
->mac_addr
[0] << 8) | (params
->mac_addr
[1])));
1186 /******************************************************************/
1187 /* MAC/PBF section */
1188 /******************************************************************/
1189 static void elink_set_mdio_clk(struct bnx2x_softc
*sc
, uint32_t emac_base
)
1191 uint32_t new_mode
, cur_mode
;
1193 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1194 * (a value of 49==0x31) and make sure that the AUTO poll is off
1196 cur_mode
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_MDIO_MODE
);
1198 if (USES_WARPCORE(sc
))
1199 clc_cnt
= 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
;
1201 clc_cnt
= 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
;
1203 if (((cur_mode
& EMAC_MDIO_MODE_CLOCK_CNT
) == clc_cnt
) &&
1204 (cur_mode
& (EMAC_MDIO_MODE_CLAUSE_45
)))
1207 new_mode
= cur_mode
&
1208 ~(EMAC_MDIO_MODE_AUTO_POLL
| EMAC_MDIO_MODE_CLOCK_CNT
);
1209 new_mode
|= clc_cnt
;
1210 new_mode
|= (EMAC_MDIO_MODE_CLAUSE_45
);
1212 PMD_DRV_LOG(DEBUG
, "Changing emac_mode from 0x%x to 0x%x",
1213 cur_mode
, new_mode
);
1214 REG_WR(sc
, emac_base
+ EMAC_REG_EMAC_MDIO_MODE
, new_mode
);
1218 static void elink_set_mdio_emac_per_phy(struct bnx2x_softc
*sc
,
1219 struct elink_params
*params
)
1222 /* Set mdio clock per phy */
1223 for (phy_index
= ELINK_INT_PHY
; phy_index
< params
->num_phys
;
1225 elink_set_mdio_clk(sc
, params
->phy
[phy_index
].mdio_ctrl
);
1228 static uint8_t elink_is_4_port_mode(struct bnx2x_softc
*sc
)
1230 uint32_t port4mode_ovwr_val
;
1231 /* Check 4-port override enabled */
1232 port4mode_ovwr_val
= REG_RD(sc
, MISC_REG_PORT4MODE_EN_OVWR
);
1233 if (port4mode_ovwr_val
& (1 << 0)) {
1234 /* Return 4-port mode override value */
1235 return (port4mode_ovwr_val
& (1 << 1)) == (1 << 1);
1237 /* Return 4-port mode from input pin */
1238 return (uint8_t) REG_RD(sc
, MISC_REG_PORT4MODE_EN
);
1241 static void elink_emac_init(struct elink_params
*params
)
1243 /* reset and unreset the emac core */
1244 struct bnx2x_softc
*sc
= params
->sc
;
1245 uint8_t port
= params
->port
;
1246 uint32_t emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
1250 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1251 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
1253 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1254 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
1256 /* init emac - use read-modify-write */
1257 /* self clear reset */
1258 val
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_MODE
);
1259 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_MODE
,
1260 (val
| EMAC_MODE_RESET
));
1264 val
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_MODE
);
1265 PMD_DRV_LOG(DEBUG
, "EMAC reset reg is %u", val
);
1267 PMD_DRV_LOG(DEBUG
, "EMAC timeout!");
1271 } while (val
& EMAC_MODE_RESET
);
1273 elink_set_mdio_emac_per_phy(sc
, params
);
1274 /* Set mac address */
1275 val
= ((params
->mac_addr
[0] << 8) | params
->mac_addr
[1]);
1276 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_MAC_MATCH
, val
);
1278 val
= ((params
->mac_addr
[2] << 24) |
1279 (params
->mac_addr
[3] << 16) |
1280 (params
->mac_addr
[4] << 8) | params
->mac_addr
[5]);
1281 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_MAC_MATCH
+ 4, val
);
1284 static void elink_set_xumac_nig(struct elink_params
*params
,
1285 uint16_t tx_pause_en
, uint8_t enable
)
1287 struct bnx2x_softc
*sc
= params
->sc
;
1289 REG_WR(sc
, params
->port
? NIG_REG_P1_MAC_IN_EN
: NIG_REG_P0_MAC_IN_EN
,
1291 REG_WR(sc
, params
->port
? NIG_REG_P1_MAC_OUT_EN
: NIG_REG_P0_MAC_OUT_EN
,
1293 REG_WR(sc
, params
->port
? NIG_REG_P1_MAC_PAUSE_OUT_EN
:
1294 NIG_REG_P0_MAC_PAUSE_OUT_EN
, tx_pause_en
);
1297 static void elink_set_umac_rxtx(struct elink_params
*params
, uint8_t en
)
1299 uint32_t umac_base
= params
->port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
1301 struct bnx2x_softc
*sc
= params
->sc
;
1302 if (!(REG_RD(sc
, MISC_REG_RESET_REG_2
) &
1303 (MISC_REGISTERS_RESET_REG_2_UMAC0
<< params
->port
)))
1305 val
= REG_RD(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
);
1307 val
|= (UMAC_COMMAND_CONFIG_REG_TX_ENA
|
1308 UMAC_COMMAND_CONFIG_REG_RX_ENA
);
1310 val
&= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA
|
1311 UMAC_COMMAND_CONFIG_REG_RX_ENA
);
1312 /* Disable RX and TX */
1313 REG_WR(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1316 static void elink_umac_enable(struct elink_params
*params
,
1317 struct elink_vars
*vars
, uint8_t lb
)
1320 uint32_t umac_base
= params
->port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
1321 struct bnx2x_softc
*sc
= params
->sc
;
1323 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1324 (MISC_REGISTERS_RESET_REG_2_UMAC0
<< params
->port
));
1327 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1328 (MISC_REGISTERS_RESET_REG_2_UMAC0
<< params
->port
));
1330 PMD_DRV_LOG(DEBUG
, "enabling UMAC");
1332 /* This register opens the gate for the UMAC despite its name */
1333 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
* 4, 1);
1335 val
= UMAC_COMMAND_CONFIG_REG_PROMIS_EN
|
1336 UMAC_COMMAND_CONFIG_REG_PAD_EN
|
1337 UMAC_COMMAND_CONFIG_REG_SW_RESET
|
1338 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK
;
1339 switch (vars
->line_speed
) {
1340 case ELINK_SPEED_10
:
1343 case ELINK_SPEED_100
:
1346 case ELINK_SPEED_1000
:
1349 case ELINK_SPEED_2500
:
1353 PMD_DRV_LOG(DEBUG
, "Invalid speed for UMAC %d",
1357 if (!(vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
1358 val
|= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE
;
1360 if (!(vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
))
1361 val
|= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE
;
1363 if (vars
->duplex
== DUPLEX_HALF
)
1364 val
|= UMAC_COMMAND_CONFIG_REG_HD_ENA
;
1366 REG_WR(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1369 /* Configure UMAC for EEE */
1370 if (vars
->eee_status
& SHMEM_EEE_ADV_STATUS_MASK
) {
1371 PMD_DRV_LOG(DEBUG
, "configured UMAC for EEE");
1372 REG_WR(sc
, umac_base
+ UMAC_REG_UMAC_EEE_CTRL
,
1373 UMAC_UMAC_EEE_CTRL_REG_EEE_EN
);
1374 REG_WR(sc
, umac_base
+ UMAC_REG_EEE_WAKE_TIMER
, 0x11);
1376 REG_WR(sc
, umac_base
+ UMAC_REG_UMAC_EEE_CTRL
, 0x0);
1379 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1380 REG_WR(sc
, umac_base
+ UMAC_REG_MAC_ADDR0
,
1381 ((params
->mac_addr
[2] << 24) |
1382 (params
->mac_addr
[3] << 16) |
1383 (params
->mac_addr
[4] << 8) | (params
->mac_addr
[5])));
1384 REG_WR(sc
, umac_base
+ UMAC_REG_MAC_ADDR1
,
1385 ((params
->mac_addr
[0] << 8) | (params
->mac_addr
[1])));
1387 /* Enable RX and TX */
1388 val
&= ~UMAC_COMMAND_CONFIG_REG_PAD_EN
;
1389 val
|= UMAC_COMMAND_CONFIG_REG_TX_ENA
| UMAC_COMMAND_CONFIG_REG_RX_ENA
;
1390 REG_WR(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1393 /* Remove SW Reset */
1394 val
&= ~UMAC_COMMAND_CONFIG_REG_SW_RESET
;
1396 /* Check loopback mode */
1398 val
|= UMAC_COMMAND_CONFIG_REG_LOOP_ENA
;
1399 REG_WR(sc
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1401 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1402 * length used by the MAC receive logic to check frames.
1404 REG_WR(sc
, umac_base
+ UMAC_REG_MAXFR
, 0x2710);
1405 elink_set_xumac_nig(params
,
1406 ((vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
) != 0), 1);
1407 vars
->mac_type
= ELINK_MAC_TYPE_UMAC
;
1411 /* Define the XMAC mode */
1412 static void elink_xmac_init(struct elink_params
*params
, uint32_t max_speed
)
1414 struct bnx2x_softc
*sc
= params
->sc
;
1415 uint32_t is_port4mode
= elink_is_4_port_mode(sc
);
1417 /* In 4-port mode, need to set the mode only once, so if XMAC is
1418 * already out of reset, it means the mode has already been set,
1419 * and it must not* reset the XMAC again, since it controls both
1423 if (((CHIP_NUM(sc
) == CHIP_NUM_57840_4_10
) ||
1424 (CHIP_NUM(sc
) == CHIP_NUM_57840_2_20
) ||
1425 (CHIP_NUM(sc
) == CHIP_NUM_57840_OBS
)) &&
1427 (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
1428 MISC_REGISTERS_RESET_REG_2_XMAC
)) {
1429 PMD_DRV_LOG(DEBUG
, "XMAC already out of reset in 4-port mode");
1434 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1435 MISC_REGISTERS_RESET_REG_2_XMAC
);
1438 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1439 MISC_REGISTERS_RESET_REG_2_XMAC
);
1441 PMD_DRV_LOG(DEBUG
, "Init XMAC to 2 ports x 10G per path");
1443 /* Set the number of ports on the system side to up to 2 */
1444 REG_WR(sc
, MISC_REG_XMAC_CORE_PORT_MODE
, 1);
1446 /* Set the number of ports on the Warp Core to 10G */
1447 REG_WR(sc
, MISC_REG_XMAC_PHY_PORT_MODE
, 3);
1449 /* Set the number of ports on the system side to 1 */
1450 REG_WR(sc
, MISC_REG_XMAC_CORE_PORT_MODE
, 0);
1451 if (max_speed
== ELINK_SPEED_10000
) {
1453 "Init XMAC to 10G x 1 port per path");
1454 /* Set the number of ports on the Warp Core to 10G */
1455 REG_WR(sc
, MISC_REG_XMAC_PHY_PORT_MODE
, 3);
1458 "Init XMAC to 20G x 2 ports per path");
1459 /* Set the number of ports on the Warp Core to 20G */
1460 REG_WR(sc
, MISC_REG_XMAC_PHY_PORT_MODE
, 1);
1464 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1465 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
);
1468 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1469 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
);
1473 static void elink_set_xmac_rxtx(struct elink_params
*params
, uint8_t en
)
1475 uint8_t port
= params
->port
;
1476 struct bnx2x_softc
*sc
= params
->sc
;
1477 uint32_t pfc_ctrl
, xmac_base
= (port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
1480 if (REG_RD(sc
, MISC_REG_RESET_REG_2
) & MISC_REGISTERS_RESET_REG_2_XMAC
) {
1481 /* Send an indication to change the state in the NIG back to XON
1482 * Clearing this bit enables the next set of this bit to get
1485 pfc_ctrl
= REG_RD(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
);
1486 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
,
1487 (pfc_ctrl
& ~(1 << 1)));
1488 REG_WR(sc
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
,
1489 (pfc_ctrl
| (1 << 1)));
1490 PMD_DRV_LOG(DEBUG
, "Disable XMAC on port %x", port
);
1491 val
= REG_RD(sc
, xmac_base
+ XMAC_REG_CTRL
);
1493 val
|= (XMAC_CTRL_REG_TX_EN
| XMAC_CTRL_REG_RX_EN
);
1495 val
&= ~(XMAC_CTRL_REG_TX_EN
| XMAC_CTRL_REG_RX_EN
);
1496 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL
, val
);
1500 static elink_status_t
elink_xmac_enable(struct elink_params
*params
,
1501 struct elink_vars
*vars
, uint8_t lb
)
1503 uint32_t val
, xmac_base
;
1504 struct bnx2x_softc
*sc
= params
->sc
;
1505 PMD_DRV_LOG(DEBUG
, "enabling XMAC");
1507 xmac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
1509 elink_xmac_init(params
, vars
->line_speed
);
1511 /* This register determines on which events the MAC will assert
1512 * error on the i/f to the NIG along w/ EOP.
1515 /* This register tells the NIG whether to send traffic to UMAC
1518 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
* 4, 0);
1520 /* When XMAC is in XLGMII mode, disable sending idles for fault
1523 if (!(params
->phy
[ELINK_INT_PHY
].flags
& ELINK_FLAGS_TX_ERROR_CHECK
)) {
1524 REG_WR(sc
, xmac_base
+ XMAC_REG_RX_LSS_CTRL
,
1525 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE
|
1526 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE
));
1527 REG_WR(sc
, xmac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
, 0);
1528 REG_WR(sc
, xmac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
,
1529 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS
|
1530 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS
);
1532 /* Set Max packet size */
1533 REG_WR(sc
, xmac_base
+ XMAC_REG_RX_MAX_SIZE
, 0x2710);
1535 /* CRC append for Tx packets */
1536 REG_WR(sc
, xmac_base
+ XMAC_REG_TX_CTRL
, 0xC800);
1539 elink_update_pfc_xmac(params
, vars
);
1541 if (vars
->eee_status
& SHMEM_EEE_ADV_STATUS_MASK
) {
1542 PMD_DRV_LOG(DEBUG
, "Setting XMAC for EEE");
1543 REG_WR(sc
, xmac_base
+ XMAC_REG_EEE_TIMERS_HI
, 0x1380008);
1544 REG_WR(sc
, xmac_base
+ XMAC_REG_EEE_CTRL
, 0x1);
1546 REG_WR(sc
, xmac_base
+ XMAC_REG_EEE_CTRL
, 0x0);
1549 /* Enable TX and RX */
1550 val
= XMAC_CTRL_REG_TX_EN
| XMAC_CTRL_REG_RX_EN
;
1552 /* Set MAC in XLGMII mode for dual-mode */
1553 if ((vars
->line_speed
== ELINK_SPEED_20000
) &&
1554 (params
->phy
[ELINK_INT_PHY
].supported
&
1555 ELINK_SUPPORTED_20000baseKR2_Full
))
1556 val
|= XMAC_CTRL_REG_XLGMII_ALIGN_ENB
;
1558 /* Check loopback mode */
1560 val
|= XMAC_CTRL_REG_LINE_LOCAL_LPBK
;
1561 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL
, val
);
1562 elink_set_xumac_nig(params
,
1563 ((vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
) != 0), 1);
1565 vars
->mac_type
= ELINK_MAC_TYPE_XMAC
;
1567 return ELINK_STATUS_OK
;
1570 static elink_status_t
elink_emac_enable(struct elink_params
*params
,
1571 struct elink_vars
*vars
, uint8_t lb
)
1573 struct bnx2x_softc
*sc
= params
->sc
;
1574 uint8_t port
= params
->port
;
1575 uint32_t emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
1578 PMD_DRV_LOG(DEBUG
, "enabling EMAC");
1581 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1582 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
1584 /* enable emac and not bmac */
1585 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ port
* 4, 1);
1587 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
1588 uint32_t ser_lane
= ((params
->lane_config
&
1589 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
1590 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
1592 PMD_DRV_LOG(DEBUG
, "XGXS");
1593 /* select the master lanes (out of 0-3) */
1594 REG_WR(sc
, NIG_REG_XGXS_LANE_SEL_P0
+ port
* 4, ser_lane
);
1596 REG_WR(sc
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
* 4, 1);
1598 } else { /* SerDes */
1599 PMD_DRV_LOG(DEBUG
, "SerDes");
1601 REG_WR(sc
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
* 4, 0);
1604 elink_bits_en(sc
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
1605 EMAC_RX_MODE_RESET
);
1606 elink_bits_en(sc
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
1607 EMAC_TX_MODE_RESET
);
1609 /* pause enable/disable */
1610 elink_bits_dis(sc
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
1611 EMAC_RX_MODE_FLOW_EN
);
1613 elink_bits_dis(sc
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
1614 (EMAC_TX_MODE_EXT_PAUSE_EN
|
1615 EMAC_TX_MODE_FLOW_EN
));
1616 if (!(params
->feature_config_flags
&
1617 ELINK_FEATURE_CONFIG_PFC_ENABLED
)) {
1618 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
)
1619 elink_bits_en(sc
, emac_base
+
1620 EMAC_REG_EMAC_RX_MODE
,
1621 EMAC_RX_MODE_FLOW_EN
);
1623 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
)
1624 elink_bits_en(sc
, emac_base
+
1625 EMAC_REG_EMAC_TX_MODE
,
1626 (EMAC_TX_MODE_EXT_PAUSE_EN
|
1627 EMAC_TX_MODE_FLOW_EN
));
1629 elink_bits_en(sc
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
1630 EMAC_TX_MODE_FLOW_EN
);
1632 /* KEEP_VLAN_TAG, promiscuous */
1633 val
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_RX_MODE
);
1634 val
|= EMAC_RX_MODE_KEEP_VLAN_TAG
| EMAC_RX_MODE_PROMISCUOUS
;
1636 /* Setting this bit causes MAC control frames (except for pause
1637 * frames) to be passed on for processing. This setting has no
1638 * affect on the operation of the pause frames. This bit effects
1639 * all packets regardless of RX Parser packet sorting logic.
1640 * Turn the PFC off to make sure we are in Xon state before
1643 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_RX_PFC_MODE
, 0);
1644 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
) {
1645 PMD_DRV_LOG(DEBUG
, "PFC is enabled");
1646 /* Enable PFC again */
1647 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_RX_PFC_MODE
,
1648 EMAC_REG_RX_PFC_MODE_RX_EN
|
1649 EMAC_REG_RX_PFC_MODE_TX_EN
|
1650 EMAC_REG_RX_PFC_MODE_PRIORITIES
);
1652 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_RX_PFC_PARAM
,
1654 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT
) |
1656 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT
)));
1657 val
|= EMAC_RX_MODE_KEEP_MAC_CONTROL
;
1659 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_RX_MODE
, val
);
1662 val
= REG_RD(sc
, emac_base
+ EMAC_REG_EMAC_MODE
);
1667 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_MODE
, val
);
1670 REG_WR(sc
, NIG_REG_NIG_EMAC0_EN
+ port
* 4, 1);
1672 /* Enable emac for jumbo packets */
1673 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_RX_MTU_SIZE
,
1674 (EMAC_RX_MTU_SIZE_JUMBO_ENA
|
1675 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+
1676 ELINK_ETH_OVREHEAD
)));
1679 REG_WR(sc
, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC
+ port
* 4, 0x1);
1681 /* Disable the NIG in/out to the bmac */
1682 REG_WR(sc
, NIG_REG_BMAC0_IN_EN
+ port
* 4, 0x0);
1683 REG_WR(sc
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
* 4, 0x0);
1684 REG_WR(sc
, NIG_REG_BMAC0_OUT_EN
+ port
* 4, 0x0);
1686 /* Enable the NIG in/out to the emac */
1687 REG_WR(sc
, NIG_REG_EMAC0_IN_EN
+ port
* 4, 0x1);
1689 if ((params
->feature_config_flags
&
1690 ELINK_FEATURE_CONFIG_PFC_ENABLED
) ||
1691 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
1694 REG_WR(sc
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
* 4, val
);
1695 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
* 4, 0x1);
1697 REG_WR(sc
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4, 0x0);
1699 vars
->mac_type
= ELINK_MAC_TYPE_EMAC
;
1700 return ELINK_STATUS_OK
;
1703 static void elink_update_pfc_bmac1(struct elink_params
*params
,
1704 struct elink_vars
*vars
)
1706 uint32_t wb_data
[2];
1707 struct bnx2x_softc
*sc
= params
->sc
;
1708 uint32_t bmac_addr
= params
->port
? NIG_REG_INGRESS_BMAC1_MEM
:
1709 NIG_REG_INGRESS_BMAC0_MEM
;
1711 uint32_t val
= 0x14;
1712 if ((!(params
->feature_config_flags
&
1713 ELINK_FEATURE_CONFIG_PFC_ENABLED
)) &&
1714 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
))
1715 /* Enable BigMAC to react on received Pause packets */
1719 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_RX_CONTROL
, wb_data
, 2);
1723 if (!(params
->feature_config_flags
&
1724 ELINK_FEATURE_CONFIG_PFC_ENABLED
) &&
1725 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
1729 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_TX_CONTROL
, wb_data
, 2);
1732 static void elink_update_pfc_bmac2(struct elink_params
*params
,
1733 struct elink_vars
*vars
, uint8_t is_lb
)
1735 /* Set rx control: Strip CRC and enable BigMAC to relay
1736 * control packets to the system as well
1738 uint32_t wb_data
[2];
1739 struct bnx2x_softc
*sc
= params
->sc
;
1740 uint32_t bmac_addr
= params
->port
? NIG_REG_INGRESS_BMAC1_MEM
:
1741 NIG_REG_INGRESS_BMAC0_MEM
;
1742 uint32_t val
= 0x14;
1744 if ((!(params
->feature_config_flags
&
1745 ELINK_FEATURE_CONFIG_PFC_ENABLED
)) &&
1746 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
))
1747 /* Enable BigMAC to react on received Pause packets */
1751 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_RX_CONTROL
, wb_data
, 2);
1756 if (!(params
->feature_config_flags
&
1757 ELINK_FEATURE_CONFIG_PFC_ENABLED
) &&
1758 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
1762 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_TX_CONTROL
, wb_data
, 2);
1764 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
) {
1765 PMD_DRV_LOG(DEBUG
, "PFC is enabled");
1766 /* Enable PFC RX & TX & STATS and set 8 COS */
1768 wb_data
[0] |= (1 << 0); /* RX */
1769 wb_data
[0] |= (1 << 1); /* TX */
1770 wb_data
[0] |= (1 << 2); /* Force initial Xon */
1771 wb_data
[0] |= (1 << 3); /* 8 cos */
1772 wb_data
[0] |= (1 << 5); /* STATS */
1774 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_PFC_CONTROL
,
1776 /* Clear the force Xon */
1777 wb_data
[0] &= ~(1 << 2);
1779 PMD_DRV_LOG(DEBUG
, "PFC is disabled");
1780 /* Disable PFC RX & TX & STATS and set 8 COS */
1785 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_PFC_CONTROL
, wb_data
, 2);
1787 /* Set Time (based unit is 512 bit time) between automatic
1788 * re-sending of PP packets amd enable automatic re-send of
1789 * Per-Priroity Packet as long as pp_gen is asserted and
1790 * pp_disable is low.
1793 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
1794 val
|= (1 << 16); /* enable automatic re-send */
1798 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_TX_PAUSE_CONTROL
,
1802 val
= 0x3; /* Enable RX and TX */
1804 val
|= 0x4; /* Local loopback */
1805 PMD_DRV_LOG(DEBUG
, "enable bmac loopback");
1807 /* When PFC enabled, Pass pause frames towards the NIG. */
1808 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
1809 val
|= ((1 << 6) | (1 << 5));
1813 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_BMAC_CONTROL
, wb_data
, 2);
1816 /******************************************************************************
1818 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1819 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1820 ******************************************************************************/
1821 static elink_status_t
elink_pfc_nig_rx_priority_mask(struct bnx2x_softc
*sc
,
1823 uint32_t priority_mask
,
1826 uint32_t nig_reg_rx_priority_mask_add
= 0;
1828 switch (cos_entry
) {
1830 nig_reg_rx_priority_mask_add
= (port
) ?
1831 NIG_REG_P1_RX_COS0_PRIORITY_MASK
:
1832 NIG_REG_P0_RX_COS0_PRIORITY_MASK
;
1835 nig_reg_rx_priority_mask_add
= (port
) ?
1836 NIG_REG_P1_RX_COS1_PRIORITY_MASK
:
1837 NIG_REG_P0_RX_COS1_PRIORITY_MASK
;
1840 nig_reg_rx_priority_mask_add
= (port
) ?
1841 NIG_REG_P1_RX_COS2_PRIORITY_MASK
:
1842 NIG_REG_P0_RX_COS2_PRIORITY_MASK
;
1846 return ELINK_STATUS_ERROR
;
1847 nig_reg_rx_priority_mask_add
= NIG_REG_P0_RX_COS3_PRIORITY_MASK
;
1851 return ELINK_STATUS_ERROR
;
1852 nig_reg_rx_priority_mask_add
= NIG_REG_P0_RX_COS4_PRIORITY_MASK
;
1856 return ELINK_STATUS_ERROR
;
1857 nig_reg_rx_priority_mask_add
= NIG_REG_P0_RX_COS5_PRIORITY_MASK
;
1861 REG_WR(sc
, nig_reg_rx_priority_mask_add
, priority_mask
);
1863 return ELINK_STATUS_OK
;
1866 static void elink_update_mng(struct elink_params
*params
, uint32_t link_status
)
1868 struct bnx2x_softc
*sc
= params
->sc
;
1870 REG_WR(sc
, params
->shmem_base
+
1871 offsetof(struct shmem_region
,
1872 port_mb
[params
->port
].link_status
), link_status
);
1875 static void elink_update_link_attr(struct elink_params
*params
,
1878 struct bnx2x_softc
*sc
= params
->sc
;
1880 if (SHMEM2_HAS(sc
, link_attr_sync
))
1881 REG_WR(sc
, params
->shmem2_base
+
1882 offsetof(struct shmem2_region
,
1883 link_attr_sync
[params
->port
]), link_attr
);
1886 static void elink_update_pfc_nig(struct elink_params
*params
,
1887 struct elink_nig_brb_pfc_port_params
1890 uint32_t xcm_mask
= 0, ppp_enable
= 0, pause_enable
= 0, llfc_out_en
=
1892 uint32_t llfc_enable
= 0, xcm_out_en
= 0, hwpfc_enable
= 0;
1893 uint32_t pkt_priority_to_cos
= 0;
1894 struct bnx2x_softc
*sc
= params
->sc
;
1895 uint8_t port
= params
->port
;
1897 int set_pfc
= params
->feature_config_flags
&
1898 ELINK_FEATURE_CONFIG_PFC_ENABLED
;
1899 PMD_DRV_LOG(DEBUG
, "updating pfc nig parameters");
1901 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
1902 * MAC control frames (that are not pause packets)
1903 * will be forwarded to the XCM.
1905 xcm_mask
= REG_RD(sc
, port
? NIG_REG_LLH1_XCM_MASK
:
1906 NIG_REG_LLH0_XCM_MASK
);
1907 /* NIG params will override non PFC params, since it's possible to
1908 * do transition from PFC to SAFC
1918 xcm_mask
&= ~(port
? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN
:
1919 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN
);
1924 llfc_out_en
= nig_params
->llfc_out_en
;
1925 llfc_enable
= nig_params
->llfc_enable
;
1926 pause_enable
= nig_params
->pause_enable
;
1927 } else /* Default non PFC mode - PAUSE */
1930 xcm_mask
|= (port
? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN
:
1931 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN
);
1936 REG_WR(sc
, port
? NIG_REG_BRB1_PAUSE_IN_EN
:
1937 NIG_REG_BRB0_PAUSE_IN_EN
, pause_enable
);
1938 REG_WR(sc
, port
? NIG_REG_LLFC_OUT_EN_1
:
1939 NIG_REG_LLFC_OUT_EN_0
, llfc_out_en
);
1940 REG_WR(sc
, port
? NIG_REG_LLFC_ENABLE_1
:
1941 NIG_REG_LLFC_ENABLE_0
, llfc_enable
);
1942 REG_WR(sc
, port
? NIG_REG_PAUSE_ENABLE_1
:
1943 NIG_REG_PAUSE_ENABLE_0
, pause_enable
);
1945 REG_WR(sc
, port
? NIG_REG_PPP_ENABLE_1
:
1946 NIG_REG_PPP_ENABLE_0
, ppp_enable
);
1948 REG_WR(sc
, port
? NIG_REG_LLH1_XCM_MASK
:
1949 NIG_REG_LLH0_XCM_MASK
, xcm_mask
);
1951 REG_WR(sc
, port
? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1
:
1952 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0
, 0x7);
1954 /* Output enable for RX_XCM # IF */
1955 REG_WR(sc
, port
? NIG_REG_XCM1_OUT_EN
:
1956 NIG_REG_XCM0_OUT_EN
, xcm_out_en
);
1958 /* HW PFC TX enable */
1959 REG_WR(sc
, port
? NIG_REG_P1_HWPFC_ENABLE
:
1960 NIG_REG_P0_HWPFC_ENABLE
, hwpfc_enable
);
1964 pkt_priority_to_cos
= nig_params
->pkt_priority_to_cos
;
1966 for (i
= 0; i
< nig_params
->num_of_rx_cos_priority_mask
; i
++)
1967 elink_pfc_nig_rx_priority_mask(sc
, i
,
1969 rx_cos_priority_mask
[i
],
1972 REG_WR(sc
, port
? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1
:
1973 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0
,
1974 nig_params
->llfc_high_priority_classes
);
1976 REG_WR(sc
, port
? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1
:
1977 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0
,
1978 nig_params
->llfc_low_priority_classes
);
1980 REG_WR(sc
, port
? NIG_REG_P1_PKT_PRIORITY_TO_COS
:
1981 NIG_REG_P0_PKT_PRIORITY_TO_COS
, pkt_priority_to_cos
);
1984 elink_status_t
elink_update_pfc(struct elink_params
*params
,
1985 struct elink_vars
*vars
,
1986 struct elink_nig_brb_pfc_port_params
1989 /* The PFC and pause are orthogonal to one another, meaning when
1990 * PFC is enabled, the pause are disabled, and when PFC is
1991 * disabled, pause are set according to the pause result.
1994 struct bnx2x_softc
*sc
= params
->sc
;
1995 elink_status_t elink_status
= ELINK_STATUS_OK
;
1996 uint8_t bmac_loopback
= (params
->loopback_mode
== ELINK_LOOPBACK_BMAC
);
1998 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
1999 vars
->link_status
|= LINK_STATUS_PFC_ENABLED
;
2001 vars
->link_status
&= ~LINK_STATUS_PFC_ENABLED
;
2003 elink_update_mng(params
, vars
->link_status
);
2005 /* Update NIG params */
2006 elink_update_pfc_nig(params
, pfc_params
);
2009 return elink_status
;
2011 PMD_DRV_LOG(DEBUG
, "About to update PFC in BMAC");
2013 if (CHIP_IS_E3(sc
)) {
2014 if (vars
->mac_type
== ELINK_MAC_TYPE_XMAC
)
2015 elink_update_pfc_xmac(params
, vars
);
2017 val
= REG_RD(sc
, MISC_REG_RESET_REG_2
);
2019 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< params
->port
))
2021 PMD_DRV_LOG(DEBUG
, "About to update PFC in EMAC");
2022 elink_emac_enable(params
, vars
, 0);
2023 return elink_status
;
2026 elink_update_pfc_bmac2(params
, vars
, bmac_loopback
);
2028 elink_update_pfc_bmac1(params
, vars
);
2031 if ((params
->feature_config_flags
&
2032 ELINK_FEATURE_CONFIG_PFC_ENABLED
) ||
2033 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
2035 REG_WR(sc
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ params
->port
* 4, val
);
2037 return elink_status
;
2040 static elink_status_t
elink_bmac1_enable(struct elink_params
*params
,
2041 struct elink_vars
*vars
, uint8_t is_lb
)
2043 struct bnx2x_softc
*sc
= params
->sc
;
2044 uint8_t port
= params
->port
;
2045 uint32_t bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
2046 NIG_REG_INGRESS_BMAC0_MEM
;
2047 uint32_t wb_data
[2];
2050 PMD_DRV_LOG(DEBUG
, "Enabling BigMAC1");
2055 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_BMAC_XGXS_CONTROL
,
2059 wb_data
[0] = ((params
->mac_addr
[2] << 24) |
2060 (params
->mac_addr
[3] << 16) |
2061 (params
->mac_addr
[4] << 8) | params
->mac_addr
[5]);
2062 wb_data
[1] = ((params
->mac_addr
[0] << 8) | params
->mac_addr
[1]);
2063 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_TX_SOURCE_ADDR
, wb_data
, 2);
2069 PMD_DRV_LOG(DEBUG
, "enable bmac loopback");
2073 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_BMAC_CONTROL
, wb_data
, 2);
2076 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2078 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_RX_MAX_SIZE
, wb_data
, 2);
2080 elink_update_pfc_bmac1(params
, vars
);
2083 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2085 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_TX_MAX_SIZE
, wb_data
, 2);
2087 /* Set cnt max size */
2088 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2090 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_CNT_MAX_SIZE
, wb_data
, 2);
2092 /* Configure SAFC */
2093 wb_data
[0] = 0x1000200;
2095 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC_REGISTER_RX_LLFC_MSG_FLDS
,
2098 return ELINK_STATUS_OK
;
2101 static elink_status_t
elink_bmac2_enable(struct elink_params
*params
,
2102 struct elink_vars
*vars
, uint8_t is_lb
)
2104 struct bnx2x_softc
*sc
= params
->sc
;
2105 uint8_t port
= params
->port
;
2106 uint32_t bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
2107 NIG_REG_INGRESS_BMAC0_MEM
;
2108 uint32_t wb_data
[2];
2110 PMD_DRV_LOG(DEBUG
, "Enabling BigMAC2");
2114 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_BMAC_CONTROL
, wb_data
, 2);
2117 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2120 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_BMAC_XGXS_CONTROL
,
2126 wb_data
[0] = ((params
->mac_addr
[2] << 24) |
2127 (params
->mac_addr
[3] << 16) |
2128 (params
->mac_addr
[4] << 8) | params
->mac_addr
[5]);
2129 wb_data
[1] = ((params
->mac_addr
[0] << 8) | params
->mac_addr
[1]);
2130 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_TX_SOURCE_ADDR
,
2135 /* Configure SAFC */
2136 wb_data
[0] = 0x1000200;
2138 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS
,
2143 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2145 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_RX_MAX_SIZE
, wb_data
, 2);
2149 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
;
2151 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_TX_MAX_SIZE
, wb_data
, 2);
2153 /* Set cnt max size */
2154 wb_data
[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+ ELINK_ETH_OVREHEAD
- 2;
2156 REG_WR_DMAE(sc
, bmac_addr
+ BIGMAC2_REGISTER_CNT_MAX_SIZE
, wb_data
, 2);
2158 elink_update_pfc_bmac2(params
, vars
, is_lb
);
2160 return ELINK_STATUS_OK
;
2163 static elink_status_t
elink_bmac_enable(struct elink_params
*params
,
2164 struct elink_vars
*vars
,
2165 uint8_t is_lb
, uint8_t reset_bmac
)
2167 elink_status_t rc
= ELINK_STATUS_OK
;
2168 uint8_t port
= params
->port
;
2169 struct bnx2x_softc
*sc
= params
->sc
;
2171 /* Reset and unreset the BigMac */
2173 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
2174 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
2178 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
2179 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
2181 /* Enable access for bmac registers */
2182 REG_WR(sc
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4, 0x1);
2184 /* Enable BMAC according to BMAC type */
2186 rc
= elink_bmac2_enable(params
, vars
, is_lb
);
2188 rc
= elink_bmac1_enable(params
, vars
, is_lb
);
2189 REG_WR(sc
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
* 4, 0x1);
2190 REG_WR(sc
, NIG_REG_XGXS_LANE_SEL_P0
+ port
* 4, 0x0);
2191 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ port
* 4, 0x0);
2193 if ((params
->feature_config_flags
&
2194 ELINK_FEATURE_CONFIG_PFC_ENABLED
) ||
2195 (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
))
2197 REG_WR(sc
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
* 4, val
);
2198 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
* 4, 0x0);
2199 REG_WR(sc
, NIG_REG_EMAC0_IN_EN
+ port
* 4, 0x0);
2200 REG_WR(sc
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
* 4, 0x0);
2201 REG_WR(sc
, NIG_REG_BMAC0_IN_EN
+ port
* 4, 0x1);
2202 REG_WR(sc
, NIG_REG_BMAC0_OUT_EN
+ port
* 4, 0x1);
2204 vars
->mac_type
= ELINK_MAC_TYPE_BMAC
;
2208 static void elink_set_bmac_rx(struct bnx2x_softc
*sc
, uint8_t port
, uint8_t en
)
2210 uint32_t bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
2211 NIG_REG_INGRESS_BMAC0_MEM
;
2212 uint32_t wb_data
[2];
2213 uint32_t nig_bmac_enable
=
2214 REG_RD(sc
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4);
2217 bmac_addr
+= BIGMAC2_REGISTER_BMAC_CONTROL
;
2219 bmac_addr
+= BIGMAC_REGISTER_BMAC_CONTROL
;
2220 /* Only if the bmac is out of reset */
2221 if (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
2222 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
) && nig_bmac_enable
) {
2223 /* Clear Rx Enable bit in BMAC_CONTROL register */
2224 REG_RD_DMAE(sc
, bmac_addr
, wb_data
, 2);
2226 wb_data
[0] |= ELINK_BMAC_CONTROL_RX_ENABLE
;
2228 wb_data
[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE
;
2229 REG_WR_DMAE(sc
, bmac_addr
, wb_data
, 2);
2234 static elink_status_t
elink_pbf_update(struct elink_params
*params
,
2235 uint32_t flow_ctrl
, uint32_t line_speed
)
2237 struct bnx2x_softc
*sc
= params
->sc
;
2238 uint8_t port
= params
->port
;
2239 uint32_t init_crd
, crd
;
2240 uint32_t count
= 1000;
2243 REG_WR(sc
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
* 4, 0x1);
2245 /* Wait for init credit */
2246 init_crd
= REG_RD(sc
, PBF_REG_P0_INIT_CRD
+ port
* 4);
2247 crd
= REG_RD(sc
, PBF_REG_P0_CREDIT
+ port
* 8);
2248 PMD_DRV_LOG(DEBUG
, "init_crd 0x%x crd 0x%x", init_crd
, crd
);
2250 while ((init_crd
!= crd
) && count
) {
2252 crd
= REG_RD(sc
, PBF_REG_P0_CREDIT
+ port
* 8);
2255 crd
= REG_RD(sc
, PBF_REG_P0_CREDIT
+ port
* 8);
2256 if (init_crd
!= crd
) {
2257 PMD_DRV_LOG(DEBUG
, "BUG! init_crd 0x%x != crd 0x%x",
2259 return ELINK_STATUS_ERROR
;
2262 if (flow_ctrl
& ELINK_FLOW_CTRL_RX
||
2263 line_speed
== ELINK_SPEED_10
||
2264 line_speed
== ELINK_SPEED_100
||
2265 line_speed
== ELINK_SPEED_1000
|| line_speed
== ELINK_SPEED_2500
) {
2266 REG_WR(sc
, PBF_REG_P0_PAUSE_ENABLE
+ port
* 4, 1);
2267 /* Update threshold */
2268 REG_WR(sc
, PBF_REG_P0_ARB_THRSH
+ port
* 4, 0);
2269 /* Update init credit */
2270 init_crd
= 778; /* (800-18-4) */
2273 uint32_t thresh
= (ELINK_ETH_MAX_JUMBO_PACKET_SIZE
+
2274 ELINK_ETH_OVREHEAD
) / 16;
2275 REG_WR(sc
, PBF_REG_P0_PAUSE_ENABLE
+ port
* 4, 0);
2276 /* Update threshold */
2277 REG_WR(sc
, PBF_REG_P0_ARB_THRSH
+ port
* 4, thresh
);
2278 /* Update init credit */
2279 switch (line_speed
) {
2280 case ELINK_SPEED_10000
:
2281 init_crd
= thresh
+ 553 - 22;
2284 PMD_DRV_LOG(DEBUG
, "Invalid line_speed 0x%x",
2286 return ELINK_STATUS_ERROR
;
2289 REG_WR(sc
, PBF_REG_P0_INIT_CRD
+ port
* 4, init_crd
);
2290 PMD_DRV_LOG(DEBUG
, "PBF updated to speed %d credit %d",
2291 line_speed
, init_crd
);
2293 /* Probe the credit changes */
2294 REG_WR(sc
, PBF_REG_INIT_P0
+ port
* 4, 0x1);
2296 REG_WR(sc
, PBF_REG_INIT_P0
+ port
* 4, 0x0);
2299 REG_WR(sc
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
* 4, 0x0);
2300 return ELINK_STATUS_OK
;
2304 * elink_get_emac_base - retrive emac base address
2306 * @bp: driver handle
2307 * @mdc_mdio_access: access type
2310 * This function selects the MDC/MDIO access (through emac0 or
2311 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2312 * phy has a default access mode, which could also be overridden
2313 * by nvram configuration. This parameter, whether this is the
2314 * default phy configuration, or the nvram overrun
2315 * configuration, is passed here as mdc_mdio_access and selects
2316 * the emac_base for the CL45 read/writes operations
2318 static uint32_t elink_get_emac_base(struct bnx2x_softc
*sc
,
2319 uint32_t mdc_mdio_access
, uint8_t port
)
2321 uint32_t emac_base
= 0;
2322 switch (mdc_mdio_access
) {
2323 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE
:
2325 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0
:
2326 if (REG_RD(sc
, NIG_REG_PORT_SWAP
))
2327 emac_base
= GRCBASE_EMAC1
;
2329 emac_base
= GRCBASE_EMAC0
;
2331 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
:
2332 if (REG_RD(sc
, NIG_REG_PORT_SWAP
))
2333 emac_base
= GRCBASE_EMAC0
;
2335 emac_base
= GRCBASE_EMAC1
;
2337 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
:
2338 emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
2340 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED
:
2341 emac_base
= (port
) ? GRCBASE_EMAC0
: GRCBASE_EMAC1
;
2350 /******************************************************************/
2351 /* CL22 access functions */
2352 /******************************************************************/
2353 static elink_status_t
elink_cl22_write(struct bnx2x_softc
*sc
,
2354 struct elink_phy
*phy
,
2355 uint16_t reg
, uint16_t val
)
2359 elink_status_t rc
= ELINK_STATUS_OK
;
2360 /* Switch to CL22 */
2361 mode
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
2362 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
,
2363 mode
& ~EMAC_MDIO_MODE_CLAUSE_45
);
2366 tmp
= ((phy
->addr
<< 21) | (reg
<< 16) | val
|
2367 EMAC_MDIO_COMM_COMMAND_WRITE_22
| EMAC_MDIO_COMM_START_BUSY
);
2368 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
2370 for (i
= 0; i
< 50; i
++) {
2373 tmp
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
2374 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
2379 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
2380 PMD_DRV_LOG(DEBUG
, "write phy register failed");
2381 rc
= ELINK_STATUS_TIMEOUT
;
2383 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, mode
);
2387 static elink_status_t
elink_cl22_read(struct bnx2x_softc
*sc
,
2388 struct elink_phy
*phy
,
2389 uint16_t reg
, uint16_t * ret_val
)
2393 elink_status_t rc
= ELINK_STATUS_OK
;
2395 /* Switch to CL22 */
2396 mode
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
2397 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
,
2398 mode
& ~EMAC_MDIO_MODE_CLAUSE_45
);
2401 val
= ((phy
->addr
<< 21) | (reg
<< 16) |
2402 EMAC_MDIO_COMM_COMMAND_READ_22
| EMAC_MDIO_COMM_START_BUSY
);
2403 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
2405 for (i
= 0; i
< 50; i
++) {
2408 val
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
2409 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
2410 *ret_val
= (uint16_t) (val
& EMAC_MDIO_COMM_DATA
);
2415 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
2416 PMD_DRV_LOG(DEBUG
, "read phy register failed");
2419 rc
= ELINK_STATUS_TIMEOUT
;
2421 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, mode
);
2425 /******************************************************************/
2426 /* CL45 access functions */
2427 /******************************************************************/
2428 static elink_status_t
elink_cl45_read(struct bnx2x_softc
*sc
,
2429 struct elink_phy
*phy
, uint8_t devad
,
2430 uint16_t reg
, uint16_t * ret_val
)
2434 elink_status_t rc
= ELINK_STATUS_OK
;
2435 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_G
) {
2436 elink_set_mdio_clk(sc
, phy
->mdio_ctrl
);
2439 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_B0
)
2440 elink_bits_en(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
2441 EMAC_MDIO_STATUS_10MB
);
2443 val
= ((phy
->addr
<< 21) | (devad
<< 16) | reg
|
2444 EMAC_MDIO_COMM_COMMAND_ADDRESS
| EMAC_MDIO_COMM_START_BUSY
);
2445 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
2447 for (i
= 0; i
< 50; i
++) {
2450 val
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
2451 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
2456 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
2457 PMD_DRV_LOG(DEBUG
, "read phy register failed");
2458 elink_cb_event_log(sc
, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT
); // "MDC/MDIO access timeout"
2461 rc
= ELINK_STATUS_TIMEOUT
;
2464 val
= ((phy
->addr
<< 21) | (devad
<< 16) |
2465 EMAC_MDIO_COMM_COMMAND_READ_45
|
2466 EMAC_MDIO_COMM_START_BUSY
);
2467 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
2469 for (i
= 0; i
< 50; i
++) {
2472 val
= REG_RD(sc
, phy
->mdio_ctrl
+
2473 EMAC_REG_EMAC_MDIO_COMM
);
2474 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
2476 (uint16_t) (val
& EMAC_MDIO_COMM_DATA
);
2480 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
2481 PMD_DRV_LOG(DEBUG
, "read phy register failed");
2482 elink_cb_event_log(sc
, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT
); // "MDC/MDIO access timeout"
2485 rc
= ELINK_STATUS_TIMEOUT
;
2488 /* Work around for E3 A0 */
2489 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA
) {
2490 phy
->flags
^= ELINK_FLAGS_DUMMY_READ
;
2491 if (phy
->flags
& ELINK_FLAGS_DUMMY_READ
) {
2493 elink_cl45_read(sc
, phy
, devad
, 0xf, &temp_val
);
2497 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_B0
)
2498 elink_bits_dis(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
2499 EMAC_MDIO_STATUS_10MB
);
2503 static elink_status_t
elink_cl45_write(struct bnx2x_softc
*sc
,
2504 struct elink_phy
*phy
, uint8_t devad
,
2505 uint16_t reg
, uint16_t val
)
2509 elink_status_t rc
= ELINK_STATUS_OK
;
2510 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_G
) {
2511 elink_set_mdio_clk(sc
, phy
->mdio_ctrl
);
2514 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_B0
)
2515 elink_bits_en(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
2516 EMAC_MDIO_STATUS_10MB
);
2519 tmp
= ((phy
->addr
<< 21) | (devad
<< 16) | reg
|
2520 EMAC_MDIO_COMM_COMMAND_ADDRESS
| EMAC_MDIO_COMM_START_BUSY
);
2521 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
2523 for (i
= 0; i
< 50; i
++) {
2526 tmp
= REG_RD(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
2527 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
2532 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
2533 PMD_DRV_LOG(DEBUG
, "write phy register failed");
2534 elink_cb_event_log(sc
, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT
); // "MDC/MDIO access timeout"
2536 rc
= ELINK_STATUS_TIMEOUT
;
2539 tmp
= ((phy
->addr
<< 21) | (devad
<< 16) | val
|
2540 EMAC_MDIO_COMM_COMMAND_WRITE_45
|
2541 EMAC_MDIO_COMM_START_BUSY
);
2542 REG_WR(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
2544 for (i
= 0; i
< 50; i
++) {
2547 tmp
= REG_RD(sc
, phy
->mdio_ctrl
+
2548 EMAC_REG_EMAC_MDIO_COMM
);
2549 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
2554 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
2555 PMD_DRV_LOG(DEBUG
, "write phy register failed");
2556 elink_cb_event_log(sc
, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT
); // "MDC/MDIO access timeout"
2558 rc
= ELINK_STATUS_TIMEOUT
;
2561 /* Work around for E3 A0 */
2562 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA
) {
2563 phy
->flags
^= ELINK_FLAGS_DUMMY_READ
;
2564 if (phy
->flags
& ELINK_FLAGS_DUMMY_READ
) {
2566 elink_cl45_read(sc
, phy
, devad
, 0xf, &temp_val
);
2569 if (phy
->flags
& ELINK_FLAGS_MDC_MDIO_WA_B0
)
2570 elink_bits_dis(sc
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
2571 EMAC_MDIO_STATUS_10MB
);
2575 /******************************************************************/
2577 /******************************************************************/
2578 static uint8_t elink_eee_has_cap(struct elink_params
*params
)
2580 struct bnx2x_softc
*sc
= params
->sc
;
2582 if (REG_RD(sc
, params
->shmem2_base
) <=
2583 offsetof(struct shmem2_region
, eee_status
[params
->port
]))
2589 static elink_status_t
elink_eee_nvram_to_time(uint32_t nvram_mode
,
2590 uint32_t * idle_timer
)
2592 switch (nvram_mode
) {
2593 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED
:
2594 *idle_timer
= ELINK_EEE_MODE_NVRAM_BALANCED_TIME
;
2596 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE
:
2597 *idle_timer
= ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME
;
2599 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY
:
2600 *idle_timer
= ELINK_EEE_MODE_NVRAM_LATENCY_TIME
;
2607 return ELINK_STATUS_OK
;
2610 static elink_status_t
elink_eee_time_to_nvram(uint32_t idle_timer
,
2611 uint32_t * nvram_mode
)
2613 switch (idle_timer
) {
2614 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME
:
2615 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED
;
2617 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME
:
2618 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE
;
2620 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME
:
2621 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY
;
2624 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
;
2628 return ELINK_STATUS_OK
;
2631 static uint32_t elink_eee_calc_timer(struct elink_params
*params
)
2633 uint32_t eee_mode
, eee_idle
;
2634 struct bnx2x_softc
*sc
= params
->sc
;
2636 if (params
->eee_mode
& ELINK_EEE_MODE_OVERRIDE_NVRAM
) {
2637 if (params
->eee_mode
& ELINK_EEE_MODE_OUTPUT_TIME
) {
2638 /* time value in eee_mode --> used directly */
2639 eee_idle
= params
->eee_mode
& ELINK_EEE_MODE_TIMER_MASK
;
2641 /* hsi value in eee_mode --> time */
2642 if (elink_eee_nvram_to_time(params
->eee_mode
&
2643 ELINK_EEE_MODE_NVRAM_MASK
,
2648 /* hsi values in nvram --> time */
2649 eee_mode
= ((REG_RD(sc
, params
->shmem_base
+
2650 offsetof(struct shmem_region
,
2651 dev_info
.port_feature_config
2653 port
].eee_power_mode
)) &
2654 PORT_FEAT_CFG_EEE_POWER_MODE_MASK
) >>
2655 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
);
2657 if (elink_eee_nvram_to_time(eee_mode
, &eee_idle
))
2664 static elink_status_t
elink_eee_set_timers(struct elink_params
*params
,
2665 struct elink_vars
*vars
)
2667 uint32_t eee_idle
= 0, eee_mode
;
2668 struct bnx2x_softc
*sc
= params
->sc
;
2670 eee_idle
= elink_eee_calc_timer(params
);
2673 REG_WR(sc
, MISC_REG_CPMU_LP_IDLE_THR_P0
+ (params
->port
<< 2),
2675 } else if ((params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
) &&
2676 (params
->eee_mode
& ELINK_EEE_MODE_OVERRIDE_NVRAM
) &&
2677 (params
->eee_mode
& ELINK_EEE_MODE_OUTPUT_TIME
)) {
2678 PMD_DRV_LOG(DEBUG
, "Error: Tx LPI is enabled with timer 0");
2679 return ELINK_STATUS_ERROR
;
2682 vars
->eee_status
&= ~(SHMEM_EEE_TIMER_MASK
| SHMEM_EEE_TIME_OUTPUT_BIT
);
2683 if (params
->eee_mode
& ELINK_EEE_MODE_OUTPUT_TIME
) {
2684 /* eee_idle in 1u --> eee_status in 16u */
2686 vars
->eee_status
|= (eee_idle
& SHMEM_EEE_TIMER_MASK
) |
2687 SHMEM_EEE_TIME_OUTPUT_BIT
;
2689 if (elink_eee_time_to_nvram(eee_idle
, &eee_mode
))
2690 return ELINK_STATUS_ERROR
;
2691 vars
->eee_status
|= eee_mode
;
2694 return ELINK_STATUS_OK
;
2697 static elink_status_t
elink_eee_initial_config(struct elink_params
*params
,
2698 struct elink_vars
*vars
,
2701 vars
->eee_status
|= ((uint32_t) mode
) << SHMEM_EEE_SUPPORTED_SHIFT
;
2703 /* Propagate params' bits --> vars (for migration exposure) */
2704 if (params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
)
2705 vars
->eee_status
|= SHMEM_EEE_LPI_REQUESTED_BIT
;
2707 vars
->eee_status
&= ~SHMEM_EEE_LPI_REQUESTED_BIT
;
2709 if (params
->eee_mode
& ELINK_EEE_MODE_ADV_LPI
)
2710 vars
->eee_status
|= SHMEM_EEE_REQUESTED_BIT
;
2712 vars
->eee_status
&= ~SHMEM_EEE_REQUESTED_BIT
;
2714 return elink_eee_set_timers(params
, vars
);
2717 static elink_status_t
elink_eee_disable(struct elink_phy
*phy
,
2718 struct elink_params
*params
,
2719 struct elink_vars
*vars
)
2721 struct bnx2x_softc
*sc
= params
->sc
;
2723 /* Make Certain LPI is disabled */
2724 REG_WR(sc
, MISC_REG_CPMU_LP_FW_ENABLE_P0
+ (params
->port
<< 2), 0);
2726 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_EEE_ADV
, 0x0);
2728 vars
->eee_status
&= ~SHMEM_EEE_ADV_STATUS_MASK
;
2730 return ELINK_STATUS_OK
;
2733 static elink_status_t
elink_eee_advertise(struct elink_phy
*phy
,
2734 struct elink_params
*params
,
2735 struct elink_vars
*vars
,
2738 struct bnx2x_softc
*sc
= params
->sc
;
2741 /* Mask events preventing LPI generation */
2742 REG_WR(sc
, MISC_REG_CPMU_LP_MASK_EXT_P0
+ (params
->port
<< 2), 0xfc20);
2744 if (modes
& SHMEM_EEE_10G_ADV
) {
2745 PMD_DRV_LOG(DEBUG
, "Advertise 10GBase-T EEE");
2748 if (modes
& SHMEM_EEE_1G_ADV
) {
2749 PMD_DRV_LOG(DEBUG
, "Advertise 1GBase-T EEE");
2753 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_EEE_ADV
, val
);
2755 vars
->eee_status
&= ~SHMEM_EEE_ADV_STATUS_MASK
;
2756 vars
->eee_status
|= (modes
<< SHMEM_EEE_ADV_STATUS_SHIFT
);
2758 return ELINK_STATUS_OK
;
2761 static void elink_update_mng_eee(struct elink_params
*params
,
2762 uint32_t eee_status
)
2764 struct bnx2x_softc
*sc
= params
->sc
;
2766 if (elink_eee_has_cap(params
))
2767 REG_WR(sc
, params
->shmem2_base
+
2768 offsetof(struct shmem2_region
,
2769 eee_status
[params
->port
]), eee_status
);
2772 static void elink_eee_an_resolve(struct elink_phy
*phy
,
2773 struct elink_params
*params
,
2774 struct elink_vars
*vars
)
2776 struct bnx2x_softc
*sc
= params
->sc
;
2777 uint16_t adv
= 0, lp
= 0;
2778 uint32_t lp_adv
= 0;
2781 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_EEE_ADV
, &adv
);
2782 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_LP_EEE_ADV
, &lp
);
2785 lp_adv
|= SHMEM_EEE_100M_ADV
;
2787 if (vars
->line_speed
== ELINK_SPEED_100
)
2789 PMD_DRV_LOG(DEBUG
, "EEE negotiated - 100M");
2793 lp_adv
|= SHMEM_EEE_1G_ADV
;
2795 if (vars
->line_speed
== ELINK_SPEED_1000
)
2797 PMD_DRV_LOG(DEBUG
, "EEE negotiated - 1G");
2801 lp_adv
|= SHMEM_EEE_10G_ADV
;
2803 if (vars
->line_speed
== ELINK_SPEED_10000
)
2805 PMD_DRV_LOG(DEBUG
, "EEE negotiated - 10G");
2809 vars
->eee_status
&= ~SHMEM_EEE_LP_ADV_STATUS_MASK
;
2810 vars
->eee_status
|= (lp_adv
<< SHMEM_EEE_LP_ADV_STATUS_SHIFT
);
2813 PMD_DRV_LOG(DEBUG
, "EEE is active");
2814 vars
->eee_status
|= SHMEM_EEE_ACTIVE_BIT
;
2818 /******************************************************************/
2819 /* BSC access functions from E3 */
2820 /******************************************************************/
2821 static void elink_bsc_module_sel(struct elink_params
*params
)
2824 uint32_t board_cfg
, sfp_ctrl
;
2825 uint32_t i2c_pins
[I2C_SWITCH_WIDTH
], i2c_val
[I2C_SWITCH_WIDTH
];
2826 struct bnx2x_softc
*sc
= params
->sc
;
2827 uint8_t port
= params
->port
;
2828 /* Read I2C output PINs */
2829 board_cfg
= REG_RD(sc
, params
->shmem_base
+
2830 offsetof(struct shmem_region
,
2831 dev_info
.shared_hw_config
.board
));
2832 i2c_pins
[I2C_BSC0
] = board_cfg
& SHARED_HW_CFG_E3_I2C_MUX0_MASK
;
2833 i2c_pins
[I2C_BSC1
] = (board_cfg
& SHARED_HW_CFG_E3_I2C_MUX1_MASK
) >>
2834 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT
;
2836 /* Read I2C output value */
2837 sfp_ctrl
= REG_RD(sc
, params
->shmem_base
+
2838 offsetof(struct shmem_region
,
2839 dev_info
.port_hw_config
[port
].
2841 i2c_val
[I2C_BSC0
] = (sfp_ctrl
& PORT_HW_CFG_E3_I2C_MUX0_MASK
) > 0;
2842 i2c_val
[I2C_BSC1
] = (sfp_ctrl
& PORT_HW_CFG_E3_I2C_MUX1_MASK
) > 0;
2843 PMD_DRV_LOG(DEBUG
, "Setting BSC switch");
2844 for (idx
= 0; idx
< I2C_SWITCH_WIDTH
; idx
++)
2845 elink_set_cfg_pin(sc
, i2c_pins
[idx
], i2c_val
[idx
]);
2848 static elink_status_t
elink_bsc_read(struct elink_params
*params
,
2849 struct bnx2x_softc
*sc
,
2853 uint8_t xfer_cnt
, uint32_t * data_array
)
2856 elink_status_t rc
= ELINK_STATUS_OK
;
2858 if (xfer_cnt
> 16) {
2859 PMD_DRV_LOG(DEBUG
, "invalid xfer_cnt %d. Max is 16 bytes",
2861 return ELINK_STATUS_ERROR
;
2864 elink_bsc_module_sel(params
);
2866 xfer_cnt
= 16 - lc_addr
;
2868 /* Enable the engine */
2869 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2870 val
|= MCPR_IMC_COMMAND_ENABLE
;
2871 REG_WR(sc
, MCP_REG_MCPR_IMC_COMMAND
, val
);
2873 /* Program slave device ID */
2874 val
= (sl_devid
<< 16) | sl_addr
;
2875 REG_WR(sc
, MCP_REG_MCPR_IMC_SLAVE_CONTROL
, val
);
2877 /* Start xfer with 0 byte to update the address pointer ??? */
2878 val
= (MCPR_IMC_COMMAND_ENABLE
) |
2879 (MCPR_IMC_COMMAND_WRITE_OP
<<
2880 MCPR_IMC_COMMAND_OPERATION_BITSHIFT
) |
2881 (lc_addr
<< MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT
) | (0);
2882 REG_WR(sc
, MCP_REG_MCPR_IMC_COMMAND
, val
);
2884 /* Poll for completion */
2886 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2887 while (((val
>> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT
) & 0x3) != 1) {
2889 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2891 PMD_DRV_LOG(DEBUG
, "wr 0 byte timed out after %d try",
2893 rc
= ELINK_STATUS_TIMEOUT
;
2897 if (rc
== ELINK_STATUS_TIMEOUT
)
2900 /* Start xfer with read op */
2901 val
= (MCPR_IMC_COMMAND_ENABLE
) |
2902 (MCPR_IMC_COMMAND_READ_OP
<<
2903 MCPR_IMC_COMMAND_OPERATION_BITSHIFT
) |
2904 (lc_addr
<< MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT
) |
2906 REG_WR(sc
, MCP_REG_MCPR_IMC_COMMAND
, val
);
2908 /* Poll for completion */
2910 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2911 while (((val
>> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT
) & 0x3) != 1) {
2913 val
= REG_RD(sc
, MCP_REG_MCPR_IMC_COMMAND
);
2915 PMD_DRV_LOG(DEBUG
, "rd op timed out after %d try", i
);
2916 rc
= ELINK_STATUS_TIMEOUT
;
2920 if (rc
== ELINK_STATUS_TIMEOUT
)
2923 for (i
= (lc_addr
>> 2); i
< 4; i
++) {
2924 data_array
[i
] = REG_RD(sc
, (MCP_REG_MCPR_IMC_DATAREG0
+ i
* 4));
2926 data_array
[i
] = ((data_array
[i
] & 0x000000ff) << 24) |
2927 ((data_array
[i
] & 0x0000ff00) << 8) |
2928 ((data_array
[i
] & 0x00ff0000) >> 8) |
2929 ((data_array
[i
] & 0xff000000) >> 24);
2935 static void elink_cl45_read_or_write(struct bnx2x_softc
*sc
,
2936 struct elink_phy
*phy
, uint8_t devad
,
2937 uint16_t reg
, uint16_t or_val
)
2940 elink_cl45_read(sc
, phy
, devad
, reg
, &val
);
2941 elink_cl45_write(sc
, phy
, devad
, reg
, val
| or_val
);
2944 static void elink_cl45_read_and_write(struct bnx2x_softc
*sc
,
2945 struct elink_phy
*phy
,
2946 uint8_t devad
, uint16_t reg
,
2950 elink_cl45_read(sc
, phy
, devad
, reg
, &val
);
2951 elink_cl45_write(sc
, phy
, devad
, reg
, val
& and_val
);
2954 static uint8_t elink_get_warpcore_lane(struct elink_params
*params
)
2957 struct bnx2x_softc
*sc
= params
->sc
;
2958 uint32_t path_swap
, path_swap_ovr
;
2962 port
= params
->port
;
2964 if (elink_is_4_port_mode(sc
)) {
2965 uint32_t port_swap
, port_swap_ovr
;
2967 /* Figure out path swap value */
2968 path_swap_ovr
= REG_RD(sc
, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR
);
2969 if (path_swap_ovr
& 0x1)
2970 path_swap
= (path_swap_ovr
& 0x2);
2972 path_swap
= REG_RD(sc
, MISC_REG_FOUR_PORT_PATH_SWAP
);
2977 /* Figure out port swap value */
2978 port_swap_ovr
= REG_RD(sc
, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR
);
2979 if (port_swap_ovr
& 0x1)
2980 port_swap
= (port_swap_ovr
& 0x2);
2982 port_swap
= REG_RD(sc
, MISC_REG_FOUR_PORT_PORT_SWAP
);
2987 lane
= (port
<< 1) + path
;
2988 } else { /* Two port mode - no port swap */
2990 /* Figure out path swap value */
2991 path_swap_ovr
= REG_RD(sc
, MISC_REG_TWO_PORT_PATH_SWAP_OVWR
);
2992 if (path_swap_ovr
& 0x1) {
2993 path_swap
= (path_swap_ovr
& 0x2);
2995 path_swap
= REG_RD(sc
, MISC_REG_TWO_PORT_PATH_SWAP
);
3005 static void elink_set_aer_mmd(struct elink_params
*params
,
3006 struct elink_phy
*phy
)
3009 uint16_t offset
, aer_val
;
3010 struct bnx2x_softc
*sc
= params
->sc
;
3011 ser_lane
= ((params
->lane_config
&
3012 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
3013 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
3015 offset
= (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) ?
3016 (phy
->addr
+ ser_lane
) : 0;
3018 if (USES_WARPCORE(sc
)) {
3019 aer_val
= elink_get_warpcore_lane(params
);
3020 /* In Dual-lane mode, two lanes are joined together,
3021 * so in order to configure them, the AER broadcast method is
3023 * 0x200 is the broadcast address for lanes 0,1
3024 * 0x201 is the broadcast address for lanes 2,3
3026 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)
3027 aer_val
= (aer_val
>> 1) | 0x200;
3028 } else if (CHIP_IS_E2(sc
))
3029 aer_val
= 0x3800 + offset
- 1;
3031 aer_val
= 0x3800 + offset
;
3033 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3034 MDIO_AER_BLOCK_AER_REG
, aer_val
);
3038 /******************************************************************/
3039 /* Internal phy section */
3040 /******************************************************************/
3042 static void elink_set_serdes_access(struct bnx2x_softc
*sc
, uint8_t port
)
3044 uint32_t emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
3047 REG_WR(sc
, NIG_REG_SERDES0_CTRL_MD_ST
+ port
* 0x10, 1);
3048 REG_WR(sc
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245f8000);
3050 REG_WR(sc
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245d000f);
3053 REG_WR(sc
, NIG_REG_SERDES0_CTRL_MD_ST
+ port
* 0x10, 0);
3056 static void elink_serdes_deassert(struct bnx2x_softc
*sc
, uint8_t port
)
3060 PMD_DRV_LOG(DEBUG
, "elink_serdes_deassert");
3062 val
= ELINK_SERDES_RESET_BITS
<< (port
* 16);
3064 /* Reset and unreset the SerDes/XGXS */
3065 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
, val
);
3067 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_SET
, val
);
3069 elink_set_serdes_access(sc
, port
);
3071 REG_WR(sc
, NIG_REG_SERDES0_CTRL_MD_DEVAD
+ port
* 0x10,
3072 ELINK_DEFAULT_PHY_DEV_ADDR
);
3075 static void elink_xgxs_specific_func(struct elink_phy
*phy
,
3076 struct elink_params
*params
,
3079 struct bnx2x_softc
*sc
= params
->sc
;
3081 case ELINK_PHY_INIT
:
3082 /* Set correct devad */
3083 REG_WR(sc
, NIG_REG_XGXS0_CTRL_MD_ST
+ params
->port
* 0x18, 0);
3084 REG_WR(sc
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ params
->port
* 0x18,
3090 static void elink_xgxs_deassert(struct elink_params
*params
)
3092 struct bnx2x_softc
*sc
= params
->sc
;
3095 PMD_DRV_LOG(DEBUG
, "elink_xgxs_deassert");
3096 port
= params
->port
;
3098 val
= ELINK_XGXS_RESET_BITS
<< (port
* 16);
3100 /* Reset and unreset the SerDes/XGXS */
3101 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
, val
);
3103 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_SET
, val
);
3104 elink_xgxs_specific_func(¶ms
->phy
[ELINK_INT_PHY
], params
,
3108 static void elink_calc_ieee_aneg_adv(struct elink_phy
*phy
,
3109 struct elink_params
*params
,
3112 *ieee_fc
= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX
;
3113 /* Resolve pause mode and advertisement Please refer to Table
3114 * 28B-3 of the 802.3ab-1999 spec
3117 switch (phy
->req_flow_ctrl
) {
3118 case ELINK_FLOW_CTRL_AUTO
:
3119 switch (params
->req_fc_auto_adv
) {
3120 case ELINK_FLOW_CTRL_BOTH
:
3121 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3123 case ELINK_FLOW_CTRL_RX
:
3124 case ELINK_FLOW_CTRL_TX
:
3126 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
3132 case ELINK_FLOW_CTRL_TX
:
3133 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
3136 case ELINK_FLOW_CTRL_RX
:
3137 case ELINK_FLOW_CTRL_BOTH
:
3138 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3141 case ELINK_FLOW_CTRL_NONE
:
3143 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
;
3146 PMD_DRV_LOG(DEBUG
, "ieee_fc = 0x%x", *ieee_fc
);
3149 static void set_phy_vars(struct elink_params
*params
, struct elink_vars
*vars
)
3151 uint8_t actual_phy_idx
, phy_index
, link_cfg_idx
;
3152 uint8_t phy_config_swapped
= params
->multi_phy_config
&
3153 PORT_HW_CFG_PHY_SWAPPED_ENABLED
;
3154 for (phy_index
= ELINK_INT_PHY
; phy_index
< params
->num_phys
;
3156 link_cfg_idx
= ELINK_LINK_CONFIG_IDX(phy_index
);
3157 actual_phy_idx
= phy_index
;
3158 if (phy_config_swapped
) {
3159 if (phy_index
== ELINK_EXT_PHY1
)
3160 actual_phy_idx
= ELINK_EXT_PHY2
;
3161 else if (phy_index
== ELINK_EXT_PHY2
)
3162 actual_phy_idx
= ELINK_EXT_PHY1
;
3164 params
->phy
[actual_phy_idx
].req_flow_ctrl
=
3165 params
->req_flow_ctrl
[link_cfg_idx
];
3167 params
->phy
[actual_phy_idx
].req_line_speed
=
3168 params
->req_line_speed
[link_cfg_idx
];
3170 params
->phy
[actual_phy_idx
].speed_cap_mask
=
3171 params
->speed_cap_mask
[link_cfg_idx
];
3173 params
->phy
[actual_phy_idx
].req_duplex
=
3174 params
->req_duplex
[link_cfg_idx
];
3176 if (params
->req_line_speed
[link_cfg_idx
] ==
3177 ELINK_SPEED_AUTO_NEG
)
3178 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_ENABLED
;
3180 PMD_DRV_LOG(DEBUG
, "req_flow_ctrl %x, req_line_speed %x,"
3181 " speed_cap_mask %x",
3182 params
->phy
[actual_phy_idx
].req_flow_ctrl
,
3183 params
->phy
[actual_phy_idx
].req_line_speed
,
3184 params
->phy
[actual_phy_idx
].speed_cap_mask
);
3188 static void elink_ext_phy_set_pause(struct elink_params
*params
,
3189 struct elink_phy
*phy
,
3190 struct elink_vars
*vars
)
3193 struct bnx2x_softc
*sc
= params
->sc
;
3194 /* Read modify write pause advertizing */
3195 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV_PAUSE
, &val
);
3197 val
&= ~MDIO_AN_REG_ADV_PAUSE_BOTH
;
3199 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3200 elink_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
3201 if ((vars
->ieee_fc
&
3202 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
3203 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
3204 val
|= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC
;
3206 if ((vars
->ieee_fc
&
3207 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
3208 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
3209 val
|= MDIO_AN_REG_ADV_PAUSE_PAUSE
;
3211 PMD_DRV_LOG(DEBUG
, "Ext phy AN advertize 0x%x", val
);
3212 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV_PAUSE
, val
);
3215 static void elink_pause_resolve(struct elink_vars
*vars
, uint32_t pause_result
)
3217 switch (pause_result
) { /* ASYM P ASYM P */
3218 case 0xb: /* 1 0 1 1 */
3219 vars
->flow_ctrl
= ELINK_FLOW_CTRL_TX
;
3222 case 0xe: /* 1 1 1 0 */
3223 vars
->flow_ctrl
= ELINK_FLOW_CTRL_RX
;
3226 case 0x5: /* 0 1 0 1 */
3227 case 0x7: /* 0 1 1 1 */
3228 case 0xd: /* 1 1 0 1 */
3229 case 0xf: /* 1 1 1 1 */
3230 vars
->flow_ctrl
= ELINK_FLOW_CTRL_BOTH
;
3236 if (pause_result
& (1 << 0))
3237 vars
->link_status
|= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE
;
3238 if (pause_result
& (1 << 1))
3239 vars
->link_status
|= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE
;
3243 static void elink_ext_phy_update_adv_fc(struct elink_phy
*phy
,
3244 struct elink_params
*params
,
3245 struct elink_vars
*vars
)
3247 uint16_t ld_pause
; /* local */
3248 uint16_t lp_pause
; /* link partner */
3249 uint16_t pause_result
;
3250 struct bnx2x_softc
*sc
= params
->sc
;
3251 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
) {
3252 elink_cl22_read(sc
, phy
, 0x4, &ld_pause
);
3253 elink_cl22_read(sc
, phy
, 0x5, &lp_pause
);
3254 } else if (CHIP_IS_E3(sc
) && ELINK_SINGLE_MEDIA_DIRECT(params
)) {
3255 uint8_t lane
= elink_get_warpcore_lane(params
);
3256 uint16_t gp_status
, gp_mask
;
3257 elink_cl45_read(sc
, phy
,
3258 MDIO_AN_DEVAD
, MDIO_WC_REG_GP2_STATUS_GP_2_4
,
3260 gp_mask
= (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL
|
3261 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP
) <<
3263 if ((gp_status
& gp_mask
) == gp_mask
) {
3264 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
3265 MDIO_AN_REG_ADV_PAUSE
, &ld_pause
);
3266 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
3267 MDIO_AN_REG_LP_AUTO_NEG
, &lp_pause
);
3269 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
3270 MDIO_AN_REG_CL37_FC_LD
, &ld_pause
);
3271 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
3272 MDIO_AN_REG_CL37_FC_LP
, &lp_pause
);
3273 ld_pause
= ((ld_pause
&
3274 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
)
3276 lp_pause
= ((lp_pause
&
3277 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
)
3281 elink_cl45_read(sc
, phy
,
3283 MDIO_AN_REG_ADV_PAUSE
, &ld_pause
);
3284 elink_cl45_read(sc
, phy
,
3286 MDIO_AN_REG_LP_AUTO_NEG
, &lp_pause
);
3288 pause_result
= (ld_pause
& MDIO_AN_REG_ADV_PAUSE_MASK
) >> 8;
3289 pause_result
|= (lp_pause
& MDIO_AN_REG_ADV_PAUSE_MASK
) >> 10;
3290 PMD_DRV_LOG(DEBUG
, "Ext PHY pause result 0x%x", pause_result
);
3291 elink_pause_resolve(vars
, pause_result
);
3295 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy
*phy
,
3296 struct elink_params
*params
,
3297 struct elink_vars
*vars
)
3300 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
3301 if (phy
->req_flow_ctrl
!= ELINK_FLOW_CTRL_AUTO
) {
3302 /* Update the advertised flow-controled of LD/LP in AN */
3303 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)
3304 elink_ext_phy_update_adv_fc(phy
, params
, vars
);
3305 /* But set the flow-control result as the requested one */
3306 vars
->flow_ctrl
= phy
->req_flow_ctrl
;
3307 } else if (phy
->req_line_speed
!= ELINK_SPEED_AUTO_NEG
)
3308 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
3309 else if (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
3311 elink_ext_phy_update_adv_fc(phy
, params
, vars
);
3316 /******************************************************************/
3317 /* Warpcore section */
3318 /******************************************************************/
3319 /* The init_internal_warpcore should mirror the xgxs,
3320 * i.e. reset the lane (if needed), set aer for the
3321 * init configuration, and set/clear SGMII flag. Internal
3322 * phy init is done purely in phy_init stage.
3324 #define WC_TX_DRIVER(post2, idriver, ipre) \
3325 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3326 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3327 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3329 #define WC_TX_FIR(post, main, pre) \
3330 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3331 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3332 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3334 static void elink_warpcore_enable_AN_KR2(struct elink_phy
*phy
,
3335 struct elink_params
*params
,
3336 struct elink_vars
*vars
)
3338 struct bnx2x_softc
*sc
= params
->sc
;
3340 static struct elink_reg_set reg_set
[] = {
3341 /* Step 1 - Program the TX/RX alignment markers */
3342 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL5
, 0xa157},
3343 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL7
, 0xcbe2},
3344 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL6
, 0x7537},
3345 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL9
, 0xa157},
3346 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_RX_CTRL11
, 0xcbe2},
3347 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_RX_CTRL10
, 0x7537},
3348 /* Step 2 - Configure the NP registers */
3349 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_USERB0_CTRL
, 0x000a},
3350 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CTRL1
, 0x6400},
3351 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CTRL3
, 0x0620},
3352 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CODE_FIELD
, 0x0157},
3353 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI1
, 0x6464},
3354 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI2
, 0x3150},
3355 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI3
, 0x3150},
3356 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE
, 0x0157},
3357 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_LD_UD_CODE
, 0x0620}
3359 PMD_DRV_LOG(DEBUG
, "Enabling 20G-KR2");
3361 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3362 MDIO_WC_REG_CL49_USERB0_CTRL
, (3 << 6));
3364 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
3365 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3368 /* Start KR2 work-around timer which handles BNX2X8073 link-parner */
3369 vars
->link_attr_sync
|= LINK_ATTR_SYNC_KR2_ENABLE
;
3370 elink_update_link_attr(params
, vars
->link_attr_sync
);
3373 static void elink_disable_kr2(struct elink_params
*params
,
3374 struct elink_vars
*vars
, struct elink_phy
*phy
)
3376 struct bnx2x_softc
*sc
= params
->sc
;
3378 static struct elink_reg_set reg_set
[] = {
3379 /* Step 1 - Program the TX/RX alignment markers */
3380 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL5
, 0x7690},
3381 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL7
, 0xe647},
3382 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL6
, 0xc4f0},
3383 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_TX_CTRL9
, 0x7690},
3384 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_RX_CTRL11
, 0xe647},
3385 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL82_USERB1_RX_CTRL10
, 0xc4f0},
3386 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_USERB0_CTRL
, 0x000c},
3387 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CTRL1
, 0x6000},
3388 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CTRL3
, 0x0000},
3389 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL73_BAM_CODE_FIELD
, 0x0002},
3390 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI1
, 0x0000},
3391 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI2
, 0x0af7},
3392 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_OUI3
, 0x0af7},
3393 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE
, 0x0002},
3394 {MDIO_WC_DEVAD
, MDIO_WC_REG_ETA_CL73_LD_UD_CODE
, 0x0000}
3396 PMD_DRV_LOG(DEBUG
, "Disabling 20G-KR2");
3398 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
3399 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3401 vars
->link_attr_sync
&= ~LINK_ATTR_SYNC_KR2_ENABLE
;
3402 elink_update_link_attr(params
, vars
->link_attr_sync
);
3404 vars
->check_kr2_recovery_cnt
= ELINK_CHECK_KR2_RECOVERY_CNT
;
3407 static void elink_warpcore_set_lpi_passthrough(struct elink_phy
*phy
,
3408 struct elink_params
*params
)
3410 struct bnx2x_softc
*sc
= params
->sc
;
3412 PMD_DRV_LOG(DEBUG
, "Configure WC for LPI pass through");
3413 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3414 MDIO_WC_REG_EEE_COMBO_CONTROL0
, 0x7c);
3415 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3416 MDIO_WC_REG_DIGITAL4_MISC5
, 0xc000);
3419 static void elink_warpcore_restart_AN_KR(struct elink_phy
*phy
,
3420 struct elink_params
*params
)
3422 /* Restart autoneg on the leading lane only */
3423 struct bnx2x_softc
*sc
= params
->sc
;
3424 uint16_t lane
= elink_get_warpcore_lane(params
);
3425 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3426 MDIO_AER_BLOCK_AER_REG
, lane
);
3427 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
3428 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x1200);
3431 elink_set_aer_mmd(params
, phy
);
3434 static void elink_warpcore_enable_AN_KR(struct elink_phy
*phy
,
3435 struct elink_params
*params
,
3436 struct elink_vars
*vars
)
3438 uint16_t lane
, i
, cl72_ctrl
, an_adv
= 0;
3439 struct bnx2x_softc
*sc
= params
->sc
;
3440 static struct elink_reg_set reg_set
[] = {
3441 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, 0x7},
3442 {MDIO_PMA_DEVAD
, MDIO_WC_REG_IEEE0BLK_AUTONEGNP
, 0x0},
3443 {MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_CONTROL
, 0x7415},
3444 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_MISC2
, 0x6190},
3445 /* Disable Autoneg: re-enable it after adv is done. */
3446 {MDIO_AN_DEVAD
, MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0},
3447 {MDIO_PMA_DEVAD
, MDIO_WC_REG_PMD_KR_CONTROL
, 0x2},
3448 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP
, 0},
3450 PMD_DRV_LOG(DEBUG
, "Enable Auto Negotiation for KR");
3451 /* Set to default registers that may be overridden by 10G force */
3452 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
3453 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3456 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3457 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
, &cl72_ctrl
);
3458 cl72_ctrl
&= 0x08ff;
3459 cl72_ctrl
|= 0x3800;
3460 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3461 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
, cl72_ctrl
);
3463 /* Check adding advertisement for 1G KX */
3464 if (((vars
->line_speed
== ELINK_SPEED_AUTO_NEG
) &&
3465 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
3466 (vars
->line_speed
== ELINK_SPEED_1000
)) {
3467 uint16_t addr
= MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
;
3470 /* Enable CL37 1G Parallel Detect */
3471 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
, addr
, 0x1);
3472 PMD_DRV_LOG(DEBUG
, "Advertize 1G");
3474 if (((vars
->line_speed
== ELINK_SPEED_AUTO_NEG
) &&
3475 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) ||
3476 (vars
->line_speed
== ELINK_SPEED_10000
)) {
3477 /* Check adding advertisement for 10G KR */
3479 /* Enable 10G Parallel Detect */
3480 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3481 MDIO_AER_BLOCK_AER_REG
, 0);
3483 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
3484 MDIO_WC_REG_PAR_DET_10G_CTRL
, 1);
3485 elink_set_aer_mmd(params
, phy
);
3486 PMD_DRV_LOG(DEBUG
, "Advertize 10G");
3489 /* Set Transmit PMD settings */
3490 lane
= elink_get_warpcore_lane(params
);
3491 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3492 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * lane
,
3493 WC_TX_DRIVER(0x02, 0x06, 0x09));
3494 /* Configure the next lane if dual mode */
3495 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)
3496 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3497 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * (lane
+ 1),
3498 WC_TX_DRIVER(0x02, 0x06, 0x09));
3499 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3500 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL
, 0x03f0);
3501 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3502 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL
, 0x03f0);
3504 /* Advertised speeds */
3505 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
3506 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1
, an_adv
);
3508 /* Advertised and set FEC (Forward Error Correction) */
3509 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
3510 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2
,
3511 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY
|
3512 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ
));
3514 /* Enable CL37 BAM */
3515 if (REG_RD(sc
, params
->shmem_base
+
3516 offsetof(struct shmem_region
,
3517 dev_info
.port_hw_config
[params
->port
].
3519 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED
) {
3520 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3521 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL
,
3523 PMD_DRV_LOG(DEBUG
, "Enable CL37 BAM on KR");
3526 /* Advertise pause */
3527 elink_ext_phy_set_pause(params
, phy
, vars
);
3528 vars
->rx_tx_asic_rst
= MAX_KR_LINK_RETRY
;
3529 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3530 MDIO_WC_REG_DIGITAL5_MISC7
, 0x100);
3532 /* Over 1G - AN local device user page 1 */
3533 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3534 MDIO_WC_REG_DIGITAL3_UP1
, 0x1f);
3536 if (((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
3537 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
)) ||
3538 (phy
->req_line_speed
== ELINK_SPEED_20000
)) {
3540 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3541 MDIO_AER_BLOCK_AER_REG
, lane
);
3543 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3544 MDIO_WC_REG_RX1_PCI_CTRL
+
3545 (0x10 * lane
), (1 << 11));
3547 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3548 MDIO_WC_REG_XGXS_X2_CONTROL3
, 0x7);
3549 elink_set_aer_mmd(params
, phy
);
3551 elink_warpcore_enable_AN_KR2(phy
, params
, vars
);
3553 elink_disable_kr2(params
, vars
, phy
);
3556 /* Enable Autoneg: only on the main lane */
3557 elink_warpcore_restart_AN_KR(phy
, params
);
3560 static void elink_warpcore_set_10G_KR(struct elink_phy
*phy
,
3561 struct elink_params
*params
)
3563 struct bnx2x_softc
*sc
= params
->sc
;
3564 uint16_t val16
, i
, lane
;
3565 static struct elink_reg_set reg_set
[] = {
3566 /* Disable Autoneg */
3567 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, 0x7},
3568 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
,
3570 {MDIO_AN_DEVAD
, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1
, 0},
3571 {MDIO_AN_DEVAD
, MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x0},
3572 {MDIO_WC_DEVAD
, MDIO_WC_REG_DIGITAL3_UP1
, 0x1},
3573 {MDIO_WC_DEVAD
, MDIO_WC_REG_DIGITAL5_MISC7
, 0xa},
3574 /* Leave cl72 training enable, needed for KR */
3575 {MDIO_PMA_DEVAD
, MDIO_WC_REG_PMD_KR_CONTROL
, 0x2}
3578 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
3579 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3582 lane
= elink_get_warpcore_lane(params
);
3583 /* Global registers */
3584 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3585 MDIO_AER_BLOCK_AER_REG
, 0);
3586 /* Disable CL36 PCS Tx */
3587 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3588 MDIO_WC_REG_XGXSBLK1_LANECTRL0
, &val16
);
3589 val16
&= ~(0x0011 << lane
);
3590 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3591 MDIO_WC_REG_XGXSBLK1_LANECTRL0
, val16
);
3593 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3594 MDIO_WC_REG_XGXSBLK1_LANECTRL1
, &val16
);
3595 val16
|= (0x0303 << (lane
<< 1));
3596 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3597 MDIO_WC_REG_XGXSBLK1_LANECTRL1
, val16
);
3599 elink_set_aer_mmd(params
, phy
);
3600 /* Set speed via PMA/PMD register */
3601 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
,
3602 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x2040);
3604 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
,
3605 MDIO_WC_REG_IEEE0BLK_AUTONEGNP
, 0xB);
3607 /* Enable encoded forced speed */
3608 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3609 MDIO_WC_REG_SERDESDIGITAL_MISC2
, 0x30);
3611 /* Turn TX scramble payload only the 64/66 scrambler */
3612 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_TX66_CONTROL
, 0x9);
3614 /* Turn RX scramble payload only the 64/66 scrambler */
3615 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3616 MDIO_WC_REG_RX66_CONTROL
, 0xF9);
3618 /* Set and clear loopback to cause a reset to 64/66 decoder */
3619 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3620 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x4000);
3621 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3622 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x0);
3626 static void elink_warpcore_set_10G_XFI(struct elink_phy
*phy
,
3627 struct elink_params
*params
,
3630 struct bnx2x_softc
*sc
= params
->sc
;
3631 uint16_t misc1_val
, tap_val
, tx_driver_val
, lane
, val
;
3632 uint32_t cfg_tap_val
, tx_drv_brdct
, tx_equal
;
3634 /* Hold rxSeqStart */
3635 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3636 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0
, 0x8000);
3638 /* Hold tx_fifo_reset */
3639 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3640 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
, 0x1);
3642 /* Disable CL73 AN */
3643 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0);
3645 /* Disable 100FX Enable and Auto-Detect */
3646 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3647 MDIO_WC_REG_FX100_CTRL1
, 0xFFFA);
3649 /* Disable 100FX Idle detect */
3650 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3651 MDIO_WC_REG_FX100_CTRL3
, 0x0080);
3653 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3654 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3655 MDIO_WC_REG_DIGITAL4_MISC3
, 0xFF7F);
3657 /* Turn off auto-detect & fiber mode */
3658 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3659 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
3662 /* Set filter_force_link, disable_false_link and parallel_detect */
3663 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3664 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, &val
);
3665 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3666 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
3667 ((val
| 0x0006) & 0xFFFE));
3670 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3671 MDIO_WC_REG_SERDESDIGITAL_MISC1
, &misc1_val
);
3673 misc1_val
&= ~(0x1f);
3677 tap_val
= WC_TX_FIR(0x08, 0x37, 0x00);
3678 tx_driver_val
= WC_TX_DRIVER(0x00, 0x02, 0x03);
3680 cfg_tap_val
= REG_RD(sc
, params
->shmem_base
+
3681 offsetof(struct shmem_region
,
3682 dev_info
.port_hw_config
[params
->
3683 port
].sfi_tap_values
));
3685 tx_equal
= cfg_tap_val
& PORT_HW_CFG_TX_EQUALIZATION_MASK
;
3687 tx_drv_brdct
= (cfg_tap_val
&
3688 PORT_HW_CFG_TX_DRV_BROADCAST_MASK
) >>
3689 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT
;
3693 /* TAP values are controlled by nvram, if value there isn't 0 */
3695 tap_val
= (uint16_t) tx_equal
;
3697 tap_val
= WC_TX_FIR(0x0f, 0x2b, 0x02);
3701 WC_TX_DRIVER(0x03, (uint16_t) tx_drv_brdct
, 0x06);
3703 tx_driver_val
= WC_TX_DRIVER(0x03, 0x02, 0x06);
3705 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3706 MDIO_WC_REG_SERDESDIGITAL_MISC1
, misc1_val
);
3708 /* Set Transmit PMD settings */
3709 lane
= elink_get_warpcore_lane(params
);
3710 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3711 MDIO_WC_REG_TX_FIR_TAP
,
3712 tap_val
| MDIO_WC_REG_TX_FIR_TAP_ENABLE
);
3713 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3714 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * lane
,
3717 /* Enable fiber mode, enable and invert sig_det */
3718 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3719 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
, 0xd);
3721 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3722 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3723 MDIO_WC_REG_DIGITAL4_MISC3
, 0x8080);
3725 elink_warpcore_set_lpi_passthrough(phy
, params
);
3727 /* 10G XFI Full Duplex */
3728 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3729 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x100);
3731 /* Release tx_fifo_reset */
3732 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3733 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
,
3735 /* Release rxSeqStart */
3736 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3737 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0
, 0x7FFF);
3740 static void elink_warpcore_set_20G_force_KR2(struct elink_phy
*phy
,
3741 struct elink_params
*params
)
3744 struct bnx2x_softc
*sc
= params
->sc
;
3745 /* Set global registers, so set AER lane to 0 */
3746 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3747 MDIO_AER_BLOCK_AER_REG
, 0);
3749 /* Disable sequencer */
3750 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3751 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
, ~(1 << 13));
3753 elink_set_aer_mmd(params
, phy
);
3755 elink_cl45_read_and_write(sc
, phy
, MDIO_PMA_DEVAD
,
3756 MDIO_WC_REG_PMD_KR_CONTROL
, ~(1 << 1));
3757 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0);
3759 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3760 MDIO_WC_REG_CL73_USERB0_CTRL
, &val
);
3763 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3764 MDIO_WC_REG_CL73_USERB0_CTRL
, val
);
3766 /* Set 20G KR2 force speed */
3767 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3768 MDIO_WC_REG_SERDESDIGITAL_MISC1
, 0x1f);
3770 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3771 MDIO_WC_REG_DIGITAL4_MISC3
, (1 << 7));
3773 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3774 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
, &val
);
3777 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3778 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
, val
);
3779 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3780 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP
, 0x835A);
3782 /* Enable sequencer (over lane 0) */
3783 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3784 MDIO_AER_BLOCK_AER_REG
, 0);
3786 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3787 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
, (1 << 13));
3789 elink_set_aer_mmd(params
, phy
);
3792 static void elink_warpcore_set_20G_DXGXS(struct bnx2x_softc
*sc
,
3793 struct elink_phy
*phy
, uint16_t lane
)
3795 /* Rx0 anaRxControl1G */
3796 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3797 MDIO_WC_REG_RX0_ANARXCONTROL1G
, 0x90);
3799 /* Rx2 anaRxControl1G */
3800 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3801 MDIO_WC_REG_RX2_ANARXCONTROL1G
, 0x90);
3803 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_SCW0
, 0xE070);
3805 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_SCW1
, 0xC0D0);
3807 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_SCW2
, 0xA0B0);
3809 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_SCW3
, 0x8090);
3811 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3812 MDIO_WC_REG_RX66_SCW0_MASK
, 0xF0F0);
3814 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3815 MDIO_WC_REG_RX66_SCW1_MASK
, 0xF0F0);
3817 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3818 MDIO_WC_REG_RX66_SCW2_MASK
, 0xF0F0);
3820 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3821 MDIO_WC_REG_RX66_SCW3_MASK
, 0xF0F0);
3823 /* Serdes Digital Misc1 */
3824 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3825 MDIO_WC_REG_SERDESDIGITAL_MISC1
, 0x6008);
3827 /* Serdes Digital4 Misc3 */
3828 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3829 MDIO_WC_REG_DIGITAL4_MISC3
, 0x8088);
3831 /* Set Transmit PMD settings */
3832 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3833 MDIO_WC_REG_TX_FIR_TAP
,
3834 (WC_TX_FIR(0x12, 0x2d, 0x00) |
3835 MDIO_WC_REG_TX_FIR_TAP_ENABLE
));
3836 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3837 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * lane
,
3838 WC_TX_DRIVER(0x02, 0x02, 0x02));
3841 static void elink_warpcore_set_sgmii_speed(struct elink_phy
*phy
,
3842 struct elink_params
*params
,
3844 uint8_t always_autoneg
)
3846 struct bnx2x_softc
*sc
= params
->sc
;
3847 uint16_t val16
, digctrl_kx1
, digctrl_kx2
;
3849 /* Clear XFI clock comp in non-10G single lane mode. */
3850 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
3851 MDIO_WC_REG_RX66_CONTROL
, ~(3 << 13));
3853 elink_warpcore_set_lpi_passthrough(phy
, params
);
3855 if (always_autoneg
|| phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) {
3857 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3858 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
,
3860 PMD_DRV_LOG(DEBUG
, "set SGMII AUTONEG");
3862 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3863 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, &val16
);
3865 switch (phy
->req_line_speed
) {
3866 case ELINK_SPEED_10
:
3868 case ELINK_SPEED_100
:
3871 case ELINK_SPEED_1000
:
3876 "Speed not supported: 0x%x",
3877 phy
->req_line_speed
);
3881 if (phy
->req_duplex
== DUPLEX_FULL
)
3884 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3885 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, val16
);
3887 PMD_DRV_LOG(DEBUG
, "set SGMII force speed %d",
3888 phy
->req_line_speed
);
3889 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3890 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, &val16
);
3891 PMD_DRV_LOG(DEBUG
, " (readback) %x", val16
);
3894 /* SGMII Slave mode and disable signal detect */
3895 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3896 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
, &digctrl_kx1
);
3900 digctrl_kx1
&= 0xff4a;
3902 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3903 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
, digctrl_kx1
);
3905 /* Turn off parallel detect */
3906 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3907 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, &digctrl_kx2
);
3908 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3909 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
3910 (digctrl_kx2
& ~(1 << 2)));
3912 /* Re-enable parallel detect */
3913 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3914 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
3915 (digctrl_kx2
| (1 << 2)));
3917 /* Enable autodet */
3918 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3919 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
3920 (digctrl_kx1
| 0x10));
3923 static void elink_warpcore_reset_lane(struct bnx2x_softc
*sc
,
3924 struct elink_phy
*phy
, uint8_t reset
)
3927 /* Take lane out of reset after configuration is finished */
3928 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3929 MDIO_WC_REG_DIGITAL5_MISC6
, &val
);
3934 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3935 MDIO_WC_REG_DIGITAL5_MISC6
, val
);
3936 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
3937 MDIO_WC_REG_DIGITAL5_MISC6
, &val
);
3940 /* Clear SFI/XFI link settings registers */
3941 static void elink_warpcore_clear_regs(struct elink_phy
*phy
,
3942 struct elink_params
*params
,
3945 struct bnx2x_softc
*sc
= params
->sc
;
3947 static struct elink_reg_set wc_regs
[] = {
3948 {MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0},
3949 {MDIO_WC_DEVAD
, MDIO_WC_REG_FX100_CTRL1
, 0x014a},
3950 {MDIO_WC_DEVAD
, MDIO_WC_REG_FX100_CTRL3
, 0x0800},
3951 {MDIO_WC_DEVAD
, MDIO_WC_REG_DIGITAL4_MISC3
, 0x8008},
3952 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
3954 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
3956 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
,
3958 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_MISC1
, 0x6000},
3959 {MDIO_WC_DEVAD
, MDIO_WC_REG_TX_FIR_TAP
, 0x0000},
3960 {MDIO_WC_DEVAD
, MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x2040},
3961 {MDIO_WC_DEVAD
, MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, 0x0140}
3963 /* Set XFI clock comp as default. */
3964 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
3965 MDIO_WC_REG_RX66_CONTROL
, (3 << 13));
3967 for (i
= 0; i
< ARRAY_SIZE(wc_regs
); i
++)
3968 elink_cl45_write(sc
, phy
, wc_regs
[i
].devad
, wc_regs
[i
].reg
,
3971 lane
= elink_get_warpcore_lane(params
);
3972 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
3973 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10 * lane
, 0x0990);
3977 static elink_status_t
elink_get_mod_abs_int_cfg(struct bnx2x_softc
*sc
,
3978 uint32_t shmem_base
,
3981 uint8_t * gpio_port
)
3986 if (CHIP_IS_E3(sc
)) {
3987 cfg_pin
= (REG_RD(sc
, shmem_base
+
3988 offsetof(struct shmem_region
,
3989 dev_info
.port_hw_config
[port
].
3991 PORT_HW_CFG_E3_MOD_ABS_MASK
) >>
3992 PORT_HW_CFG_E3_MOD_ABS_SHIFT
;
3994 /* Should not happen. This function called upon interrupt
3995 * triggered by GPIO ( since EPIO can only generate interrupts
3997 * So if this function was called and none of the GPIOs was set,
3998 * it means the shit hit the fan.
4000 if ((cfg_pin
< PIN_CFG_GPIO0_P0
) ||
4001 (cfg_pin
> PIN_CFG_GPIO3_P1
)) {
4003 "No cfg pin %x for module detect indication",
4005 return ELINK_STATUS_ERROR
;
4008 *gpio_num
= (cfg_pin
- PIN_CFG_GPIO0_P0
) & 0x3;
4009 *gpio_port
= (cfg_pin
- PIN_CFG_GPIO0_P0
) >> 2;
4011 *gpio_num
= MISC_REGISTERS_GPIO_3
;
4015 return ELINK_STATUS_OK
;
4018 static int elink_is_sfp_module_plugged(struct elink_params
*params
)
4020 struct bnx2x_softc
*sc
= params
->sc
;
4021 uint8_t gpio_num
, gpio_port
;
4023 if (elink_get_mod_abs_int_cfg(sc
,
4024 params
->shmem_base
, params
->port
,
4025 &gpio_num
, &gpio_port
) != ELINK_STATUS_OK
)
4027 gpio_val
= elink_cb_gpio_read(sc
, gpio_num
, gpio_port
);
4029 /* Call the handling function in case module is detected */
4036 static int elink_warpcore_get_sigdet(struct elink_phy
*phy
,
4037 struct elink_params
*params
)
4039 uint16_t gp2_status_reg0
, lane
;
4040 struct bnx2x_softc
*sc
= params
->sc
;
4042 lane
= elink_get_warpcore_lane(params
);
4044 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_GP2_STATUS_GP_2_0
,
4047 return (gp2_status_reg0
>> (8 + lane
)) & 0x1;
4050 static void elink_warpcore_config_runtime(struct elink_phy
*phy
,
4051 struct elink_params
*params
,
4052 struct elink_vars
*vars
)
4054 struct bnx2x_softc
*sc
= params
->sc
;
4055 uint32_t serdes_net_if
;
4056 uint16_t gp_status1
= 0, lnkup
= 0, lnkup_kr
= 0;
4058 vars
->turn_to_run_wc_rt
= vars
->turn_to_run_wc_rt
? 0 : 1;
4060 if (!vars
->turn_to_run_wc_rt
)
4063 if (vars
->rx_tx_asic_rst
) {
4064 uint16_t lane
= elink_get_warpcore_lane(params
);
4065 serdes_net_if
= (REG_RD(sc
, params
->shmem_base
+
4066 offsetof(struct shmem_region
,
4067 dev_info
.port_hw_config
4070 PORT_HW_CFG_NET_SERDES_IF_MASK
);
4072 switch (serdes_net_if
) {
4073 case PORT_HW_CFG_NET_SERDES_IF_KR
:
4074 /* Do we get link yet? */
4075 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
, 0x81d1,
4077 lnkup
= (gp_status1
>> (8 + lane
)) & 0x1; /* 1G */
4079 lnkup_kr
= (gp_status1
>> (12 + lane
)) & 0x1;
4081 if (lnkup_kr
|| lnkup
) {
4082 vars
->rx_tx_asic_rst
= 0;
4084 /* Reset the lane to see if link comes up. */
4085 elink_warpcore_reset_lane(sc
, phy
, 1);
4086 elink_warpcore_reset_lane(sc
, phy
, 0);
4088 /* Restart Autoneg */
4089 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
4090 MDIO_WC_REG_IEEE0BLK_MIICNTL
,
4093 vars
->rx_tx_asic_rst
--;
4094 PMD_DRV_LOG(DEBUG
, "0x%x retry left",
4095 vars
->rx_tx_asic_rst
);
4104 /*params->rx_tx_asic_rst */
4107 static void elink_warpcore_config_sfi(struct elink_phy
*phy
,
4108 struct elink_params
*params
)
4110 uint16_t lane
= elink_get_warpcore_lane(params
);
4112 elink_warpcore_clear_regs(phy
, params
, lane
);
4113 if ((params
->req_line_speed
[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY
)] ==
4114 ELINK_SPEED_10000
) &&
4115 (phy
->media_type
!= ELINK_ETH_PHY_SFP_1G_FIBER
)) {
4116 PMD_DRV_LOG(DEBUG
, "Setting 10G SFI");
4117 elink_warpcore_set_10G_XFI(phy
, params
, 0);
4119 PMD_DRV_LOG(DEBUG
, "Setting 1G Fiber");
4120 elink_warpcore_set_sgmii_speed(phy
, params
, 1, 0);
4124 static void elink_sfp_e3_set_transmitter(struct elink_params
*params
,
4125 struct elink_phy
*phy
, uint8_t tx_en
)
4127 struct bnx2x_softc
*sc
= params
->sc
;
4129 uint8_t port
= params
->port
;
4131 cfg_pin
= REG_RD(sc
, params
->shmem_base
+
4132 offsetof(struct shmem_region
,
4133 dev_info
.port_hw_config
[port
].e3_sfp_ctrl
)) &
4134 PORT_HW_CFG_E3_TX_LASER_MASK
;
4135 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4136 PMD_DRV_LOG(DEBUG
, "Setting WC TX to %d", tx_en
);
4138 /* For 20G, the expected pin to be used is 3 pins after the current */
4139 elink_set_cfg_pin(sc
, cfg_pin
, tx_en
^ 1);
4140 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
)
4141 elink_set_cfg_pin(sc
, cfg_pin
+ 3, tx_en
^ 1);
4144 static uint8_t elink_warpcore_config_init(struct elink_phy
*phy
,
4145 struct elink_params
*params
,
4146 struct elink_vars
*vars
)
4148 struct bnx2x_softc
*sc
= params
->sc
;
4149 uint32_t serdes_net_if
;
4151 uint16_t lane
= elink_get_warpcore_lane(params
);
4152 serdes_net_if
= (REG_RD(sc
, params
->shmem_base
+
4153 offsetof(struct shmem_region
,
4154 dev_info
.port_hw_config
[params
->port
].
4156 PORT_HW_CFG_NET_SERDES_IF_MASK
);
4158 "Begin Warpcore init, link_speed %d, "
4159 "serdes_net_if = 0x%x", vars
->line_speed
, serdes_net_if
);
4160 elink_set_aer_mmd(params
, phy
);
4161 elink_warpcore_reset_lane(sc
, phy
, 1);
4162 vars
->phy_flags
|= PHY_XGXS_FLAG
;
4163 if ((serdes_net_if
== PORT_HW_CFG_NET_SERDES_IF_SGMII
) ||
4164 (phy
->req_line_speed
&&
4165 ((phy
->req_line_speed
== ELINK_SPEED_100
) ||
4166 (phy
->req_line_speed
== ELINK_SPEED_10
)))) {
4167 vars
->phy_flags
|= PHY_SGMII_FLAG
;
4168 PMD_DRV_LOG(DEBUG
, "Setting SGMII mode");
4169 elink_warpcore_clear_regs(phy
, params
, lane
);
4170 elink_warpcore_set_sgmii_speed(phy
, params
, 0, 1);
4172 switch (serdes_net_if
) {
4173 case PORT_HW_CFG_NET_SERDES_IF_KR
:
4174 /* Enable KR Auto Neg */
4175 if (params
->loopback_mode
!= ELINK_LOOPBACK_EXT
)
4176 elink_warpcore_enable_AN_KR(phy
, params
, vars
);
4178 PMD_DRV_LOG(DEBUG
, "Setting KR 10G-Force");
4179 elink_warpcore_set_10G_KR(phy
, params
);
4183 case PORT_HW_CFG_NET_SERDES_IF_XFI
:
4184 elink_warpcore_clear_regs(phy
, params
, lane
);
4185 if (vars
->line_speed
== ELINK_SPEED_10000
) {
4186 PMD_DRV_LOG(DEBUG
, "Setting 10G XFI");
4187 elink_warpcore_set_10G_XFI(phy
, params
, 1);
4189 if (ELINK_SINGLE_MEDIA_DIRECT(params
)) {
4190 PMD_DRV_LOG(DEBUG
, "1G Fiber");
4193 PMD_DRV_LOG(DEBUG
, "10/100/1G SGMII");
4196 elink_warpcore_set_sgmii_speed(phy
,
4203 case PORT_HW_CFG_NET_SERDES_IF_SFI
:
4204 /* Issue Module detection if module is plugged, or
4205 * enabled transmitter to avoid current leakage in case
4206 * no module is connected
4208 if ((params
->loopback_mode
== ELINK_LOOPBACK_NONE
) ||
4209 (params
->loopback_mode
== ELINK_LOOPBACK_EXT
)) {
4210 if (elink_is_sfp_module_plugged(params
))
4211 elink_sfp_module_detection(phy
, params
);
4213 elink_sfp_e3_set_transmitter(params
,
4217 elink_warpcore_config_sfi(phy
, params
);
4220 case PORT_HW_CFG_NET_SERDES_IF_DXGXS
:
4221 if (vars
->line_speed
!= ELINK_SPEED_20000
) {
4222 PMD_DRV_LOG(DEBUG
, "Speed not supported yet");
4225 PMD_DRV_LOG(DEBUG
, "Setting 20G DXGXS");
4226 elink_warpcore_set_20G_DXGXS(sc
, phy
, lane
);
4227 /* Issue Module detection */
4229 elink_sfp_module_detection(phy
, params
);
4231 case PORT_HW_CFG_NET_SERDES_IF_KR2
:
4232 if (!params
->loopback_mode
) {
4233 elink_warpcore_enable_AN_KR(phy
, params
, vars
);
4235 PMD_DRV_LOG(DEBUG
, "Setting KR 20G-Force");
4236 elink_warpcore_set_20G_force_KR2(phy
, params
);
4241 "Unsupported Serdes Net Interface 0x%x",
4247 /* Take lane out of reset after configuration is finished */
4248 elink_warpcore_reset_lane(sc
, phy
, 0);
4249 PMD_DRV_LOG(DEBUG
, "Exit config init");
4254 static void elink_warpcore_link_reset(struct elink_phy
*phy
,
4255 struct elink_params
*params
)
4257 struct bnx2x_softc
*sc
= params
->sc
;
4258 uint16_t val16
, lane
;
4259 elink_sfp_e3_set_transmitter(params
, phy
, 0);
4260 elink_set_mdio_emac_per_phy(sc
, params
);
4261 elink_set_aer_mmd(params
, phy
);
4262 /* Global register */
4263 elink_warpcore_reset_lane(sc
, phy
, 1);
4265 /* Clear loopback settings (if any) */
4267 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
4268 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, 0xBFFF);
4270 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
4271 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0xfffe);
4273 /* Update those 1-copy registers */
4274 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
4275 MDIO_AER_BLOCK_AER_REG
, 0);
4276 /* Enable 1G MDIO (1-copy) */
4277 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
4278 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
, ~0x10);
4280 elink_cl45_read_and_write(sc
, phy
, MDIO_WC_DEVAD
,
4281 MDIO_WC_REG_XGXSBLK1_LANECTRL2
, 0xff00);
4282 lane
= elink_get_warpcore_lane(params
);
4283 /* Disable CL36 PCS Tx */
4284 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
4285 MDIO_WC_REG_XGXSBLK1_LANECTRL0
, &val16
);
4286 val16
|= (0x11 << lane
);
4287 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)
4288 val16
|= (0x22 << lane
);
4289 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
4290 MDIO_WC_REG_XGXSBLK1_LANECTRL0
, val16
);
4292 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
4293 MDIO_WC_REG_XGXSBLK1_LANECTRL1
, &val16
);
4294 val16
&= ~(0x0303 << (lane
<< 1));
4295 val16
|= (0x0101 << (lane
<< 1));
4296 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
) {
4297 val16
&= ~(0x0c0c << (lane
<< 1));
4298 val16
|= (0x0404 << (lane
<< 1));
4301 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
4302 MDIO_WC_REG_XGXSBLK1_LANECTRL1
, val16
);
4304 elink_set_aer_mmd(params
, phy
);
4308 static void elink_set_warpcore_loopback(struct elink_phy
*phy
,
4309 struct elink_params
*params
)
4311 struct bnx2x_softc
*sc
= params
->sc
;
4314 PMD_DRV_LOG(DEBUG
, "Setting Warpcore loopback type %x, speed %d",
4315 params
->loopback_mode
, phy
->req_line_speed
);
4317 if (phy
->req_line_speed
< ELINK_SPEED_10000
||
4318 phy
->supported
& ELINK_SUPPORTED_20000baseKR2_Full
) {
4319 /* 10/100/1000/20G-KR2 */
4321 /* Update those 1-copy registers */
4322 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
4323 MDIO_AER_BLOCK_AER_REG
, 0);
4324 /* Enable 1G MDIO (1-copy) */
4325 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
4326 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
,
4328 /* Set 1G loopback based on lane (1-copy) */
4329 lane
= elink_get_warpcore_lane(params
);
4330 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
4331 MDIO_WC_REG_XGXSBLK1_LANECTRL2
, &val16
);
4332 val16
|= (1 << lane
);
4333 if (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)
4334 val16
|= (2 << lane
);
4335 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
4336 MDIO_WC_REG_XGXSBLK1_LANECTRL2
, val16
);
4338 /* Switch back to 4-copy registers */
4339 elink_set_aer_mmd(params
, phy
);
4341 /* 10G / 20G-DXGXS */
4342 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
4343 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
,
4345 elink_cl45_read_or_write(sc
, phy
, MDIO_WC_DEVAD
,
4346 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x1);
4350 static void elink_sync_link(struct elink_params
*params
,
4351 struct elink_vars
*vars
)
4353 struct bnx2x_softc
*sc
= params
->sc
;
4354 uint8_t link_10g_plus
;
4355 if (vars
->link_status
& LINK_STATUS_PHYSICAL_LINK_FLAG
)
4356 vars
->phy_flags
|= PHY_PHYSICAL_LINK_FLAG
;
4357 vars
->link_up
= (vars
->link_status
& LINK_STATUS_LINK_UP
);
4358 if (vars
->link_up
) {
4359 PMD_DRV_LOG(DEBUG
, "phy link up");
4361 vars
->phy_link_up
= 1;
4362 vars
->duplex
= DUPLEX_FULL
;
4363 switch (vars
->link_status
& LINK_STATUS_SPEED_AND_DUPLEX_MASK
) {
4364 case ELINK_LINK_10THD
:
4365 vars
->duplex
= DUPLEX_HALF
;
4367 case ELINK_LINK_10TFD
:
4368 vars
->line_speed
= ELINK_SPEED_10
;
4371 case ELINK_LINK_100TXHD
:
4372 vars
->duplex
= DUPLEX_HALF
;
4374 case ELINK_LINK_100T4
:
4375 case ELINK_LINK_100TXFD
:
4376 vars
->line_speed
= ELINK_SPEED_100
;
4379 case ELINK_LINK_1000THD
:
4380 vars
->duplex
= DUPLEX_HALF
;
4382 case ELINK_LINK_1000TFD
:
4383 vars
->line_speed
= ELINK_SPEED_1000
;
4386 case ELINK_LINK_2500THD
:
4387 vars
->duplex
= DUPLEX_HALF
;
4389 case ELINK_LINK_2500TFD
:
4390 vars
->line_speed
= ELINK_SPEED_2500
;
4393 case ELINK_LINK_10GTFD
:
4394 vars
->line_speed
= ELINK_SPEED_10000
;
4396 case ELINK_LINK_20GTFD
:
4397 vars
->line_speed
= ELINK_SPEED_20000
;
4402 vars
->flow_ctrl
= 0;
4403 if (vars
->link_status
& LINK_STATUS_TX_FLOW_CONTROL_ENABLED
)
4404 vars
->flow_ctrl
|= ELINK_FLOW_CTRL_TX
;
4406 if (vars
->link_status
& LINK_STATUS_RX_FLOW_CONTROL_ENABLED
)
4407 vars
->flow_ctrl
|= ELINK_FLOW_CTRL_RX
;
4409 if (!vars
->flow_ctrl
)
4410 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
4412 if (vars
->line_speed
&&
4413 ((vars
->line_speed
== ELINK_SPEED_10
) ||
4414 (vars
->line_speed
== ELINK_SPEED_100
))) {
4415 vars
->phy_flags
|= PHY_SGMII_FLAG
;
4417 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
4419 if (vars
->line_speed
&&
4420 USES_WARPCORE(sc
) && (vars
->line_speed
== ELINK_SPEED_1000
))
4421 vars
->phy_flags
|= PHY_SGMII_FLAG
;
4422 /* Anything 10 and over uses the bmac */
4423 link_10g_plus
= (vars
->line_speed
>= ELINK_SPEED_10000
);
4425 if (link_10g_plus
) {
4426 if (USES_WARPCORE(sc
))
4427 vars
->mac_type
= ELINK_MAC_TYPE_XMAC
;
4429 vars
->mac_type
= ELINK_MAC_TYPE_BMAC
;
4431 if (USES_WARPCORE(sc
))
4432 vars
->mac_type
= ELINK_MAC_TYPE_UMAC
;
4434 vars
->mac_type
= ELINK_MAC_TYPE_EMAC
;
4436 } else { /* Link down */
4437 PMD_DRV_LOG(DEBUG
, "phy link down");
4439 vars
->phy_link_up
= 0;
4441 vars
->line_speed
= 0;
4442 vars
->duplex
= DUPLEX_FULL
;
4443 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
4445 /* Indicate no mac active */
4446 vars
->mac_type
= ELINK_MAC_TYPE_NONE
;
4447 if (vars
->link_status
& LINK_STATUS_PHYSICAL_LINK_FLAG
)
4448 vars
->phy_flags
|= PHY_HALF_OPEN_CONN_FLAG
;
4449 if (vars
->link_status
& LINK_STATUS_SFP_TX_FAULT
)
4450 vars
->phy_flags
|= PHY_SFP_TX_FAULT_FLAG
;
4454 void elink_link_status_update(struct elink_params
*params
,
4455 struct elink_vars
*vars
)
4457 struct bnx2x_softc
*sc
= params
->sc
;
4458 uint8_t port
= params
->port
;
4459 uint32_t sync_offset
, media_types
;
4460 /* Update PHY configuration */
4461 set_phy_vars(params
, vars
);
4463 vars
->link_status
= REG_RD(sc
, params
->shmem_base
+
4464 offsetof(struct shmem_region
,
4465 port_mb
[port
].link_status
));
4467 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4468 if (params
->loopback_mode
!= ELINK_LOOPBACK_NONE
&&
4469 params
->loopback_mode
!= ELINK_LOOPBACK_EXT
)
4470 vars
->link_status
|= LINK_STATUS_LINK_UP
;
4472 if (elink_eee_has_cap(params
))
4473 vars
->eee_status
= REG_RD(sc
, params
->shmem2_base
+
4474 offsetof(struct shmem2_region
,
4475 eee_status
[params
->port
]));
4477 vars
->phy_flags
= PHY_XGXS_FLAG
;
4478 elink_sync_link(params
, vars
);
4479 /* Sync media type */
4480 sync_offset
= params
->shmem_base
+
4481 offsetof(struct shmem_region
,
4482 dev_info
.port_hw_config
[port
].media_type
);
4483 media_types
= REG_RD(sc
, sync_offset
);
4485 params
->phy
[ELINK_INT_PHY
].media_type
=
4486 (media_types
& PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
) >>
4487 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT
;
4488 params
->phy
[ELINK_EXT_PHY1
].media_type
=
4489 (media_types
& PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK
) >>
4490 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
;
4491 params
->phy
[ELINK_EXT_PHY2
].media_type
=
4492 (media_types
& PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK
) >>
4493 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT
;
4494 PMD_DRV_LOG(DEBUG
, "media_types = 0x%x", media_types
);
4496 /* Sync AEU offset */
4497 sync_offset
= params
->shmem_base
+
4498 offsetof(struct shmem_region
,
4499 dev_info
.port_hw_config
[port
].aeu_int_mask
);
4501 vars
->aeu_int_mask
= REG_RD(sc
, sync_offset
);
4503 /* Sync PFC status */
4504 if (vars
->link_status
& LINK_STATUS_PFC_ENABLED
)
4505 params
->feature_config_flags
|=
4506 ELINK_FEATURE_CONFIG_PFC_ENABLED
;
4508 params
->feature_config_flags
&=
4509 ~ELINK_FEATURE_CONFIG_PFC_ENABLED
;
4511 if (SHMEM2_HAS(sc
, link_attr_sync
))
4512 vars
->link_attr_sync
= SHMEM2_RD(sc
,
4513 link_attr_sync
[params
->port
]);
4515 PMD_DRV_LOG(DEBUG
, "link_status 0x%x phy_link_up %x int_mask 0x%x",
4516 vars
->link_status
, vars
->phy_link_up
, vars
->aeu_int_mask
);
4517 PMD_DRV_LOG(DEBUG
, "line_speed %x duplex %x flow_ctrl 0x%x",
4518 vars
->line_speed
, vars
->duplex
, vars
->flow_ctrl
);
4521 static void elink_set_master_ln(struct elink_params
*params
,
4522 struct elink_phy
*phy
)
4524 struct bnx2x_softc
*sc
= params
->sc
;
4525 uint16_t new_master_ln
, ser_lane
;
4526 ser_lane
= ((params
->lane_config
&
4527 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
4528 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
4530 /* Set the master_ln for AN */
4531 CL22_RD_OVER_CL45(sc
, phy
,
4532 MDIO_REG_BANK_XGXS_BLOCK2
,
4533 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
, &new_master_ln
);
4535 CL22_WR_OVER_CL45(sc
, phy
,
4536 MDIO_REG_BANK_XGXS_BLOCK2
,
4537 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
,
4538 (new_master_ln
| ser_lane
));
4541 static elink_status_t
elink_reset_unicore(struct elink_params
*params
,
4542 struct elink_phy
*phy
,
4545 struct bnx2x_softc
*sc
= params
->sc
;
4546 uint16_t mii_control
;
4548 CL22_RD_OVER_CL45(sc
, phy
,
4549 MDIO_REG_BANK_COMBO_IEEE0
,
4550 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
4552 /* Reset the unicore */
4553 CL22_WR_OVER_CL45(sc
, phy
,
4554 MDIO_REG_BANK_COMBO_IEEE0
,
4555 MDIO_COMBO_IEEE0_MII_CONTROL
,
4556 (mii_control
| MDIO_COMBO_IEEO_MII_CONTROL_RESET
));
4558 elink_set_serdes_access(sc
, params
->port
);
4560 /* Wait for the reset to self clear */
4561 for (i
= 0; i
< ELINK_MDIO_ACCESS_TIMEOUT
; i
++) {
4564 /* The reset erased the previous bank value */
4565 CL22_RD_OVER_CL45(sc
, phy
,
4566 MDIO_REG_BANK_COMBO_IEEE0
,
4567 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
4569 if (!(mii_control
& MDIO_COMBO_IEEO_MII_CONTROL_RESET
)) {
4571 return ELINK_STATUS_OK
;
4575 elink_cb_event_log(sc
, ELINK_LOG_ID_PHY_UNINITIALIZED
, params
->port
); // "Warning: PHY was not initialized,"
4578 PMD_DRV_LOG(DEBUG
, "BUG! XGXS is still in reset!");
4579 return ELINK_STATUS_ERROR
;
4583 static void elink_set_swap_lanes(struct elink_params
*params
,
4584 struct elink_phy
*phy
)
4586 struct bnx2x_softc
*sc
= params
->sc
;
4587 /* Each two bits represents a lane number:
4588 * No swap is 0123 => 0x1b no need to enable the swap
4590 uint16_t rx_lane_swap
, tx_lane_swap
;
4592 rx_lane_swap
= ((params
->lane_config
&
4593 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK
) >>
4594 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT
);
4595 tx_lane_swap
= ((params
->lane_config
&
4596 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK
) >>
4597 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT
);
4599 if (rx_lane_swap
!= 0x1b) {
4600 CL22_WR_OVER_CL45(sc
, phy
,
4601 MDIO_REG_BANK_XGXS_BLOCK2
,
4602 MDIO_XGXS_BLOCK2_RX_LN_SWAP
,
4604 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE
|
4605 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE
));
4607 CL22_WR_OVER_CL45(sc
, phy
,
4608 MDIO_REG_BANK_XGXS_BLOCK2
,
4609 MDIO_XGXS_BLOCK2_RX_LN_SWAP
, 0);
4612 if (tx_lane_swap
!= 0x1b) {
4613 CL22_WR_OVER_CL45(sc
, phy
,
4614 MDIO_REG_BANK_XGXS_BLOCK2
,
4615 MDIO_XGXS_BLOCK2_TX_LN_SWAP
,
4617 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE
));
4619 CL22_WR_OVER_CL45(sc
, phy
,
4620 MDIO_REG_BANK_XGXS_BLOCK2
,
4621 MDIO_XGXS_BLOCK2_TX_LN_SWAP
, 0);
4625 static void elink_set_parallel_detection(struct elink_phy
*phy
,
4626 struct elink_params
*params
)
4628 struct bnx2x_softc
*sc
= params
->sc
;
4630 CL22_RD_OVER_CL45(sc
, phy
,
4631 MDIO_REG_BANK_SERDES_DIGITAL
,
4632 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
, &control2
);
4633 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
4634 control2
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN
;
4636 control2
&= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN
;
4637 PMD_DRV_LOG(DEBUG
, "phy->speed_cap_mask = 0x%x, control2 = 0x%x",
4638 phy
->speed_cap_mask
, control2
);
4639 CL22_WR_OVER_CL45(sc
, phy
,
4640 MDIO_REG_BANK_SERDES_DIGITAL
,
4641 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
, control2
);
4643 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
4644 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
4645 PMD_DRV_LOG(DEBUG
, "XGXS");
4647 CL22_WR_OVER_CL45(sc
, phy
,
4648 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4649 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK
,
4650 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT
);
4652 CL22_RD_OVER_CL45(sc
, phy
,
4653 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4654 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
4658 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN
;
4660 CL22_WR_OVER_CL45(sc
, phy
,
4661 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4662 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
4665 /* Disable parallel detection of HiG */
4666 CL22_WR_OVER_CL45(sc
, phy
,
4667 MDIO_REG_BANK_XGXS_BLOCK2
,
4668 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G
,
4669 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS
|
4670 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS
);
4674 static void elink_set_autoneg(struct elink_phy
*phy
,
4675 struct elink_params
*params
,
4676 struct elink_vars
*vars
, uint8_t enable_cl73
)
4678 struct bnx2x_softc
*sc
= params
->sc
;
4682 CL22_RD_OVER_CL45(sc
, phy
,
4683 MDIO_REG_BANK_COMBO_IEEE0
,
4684 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
4686 /* CL37 Autoneg Enabled */
4687 if (vars
->line_speed
== ELINK_SPEED_AUTO_NEG
)
4688 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
;
4689 else /* CL37 Autoneg Disabled */
4690 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
4691 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
);
4693 CL22_WR_OVER_CL45(sc
, phy
,
4694 MDIO_REG_BANK_COMBO_IEEE0
,
4695 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
4697 /* Enable/Disable Autodetection */
4699 CL22_RD_OVER_CL45(sc
, phy
,
4700 MDIO_REG_BANK_SERDES_DIGITAL
,
4701 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, ®_val
);
4702 reg_val
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN
|
4703 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
);
4704 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
;
4705 if (vars
->line_speed
== ELINK_SPEED_AUTO_NEG
)
4706 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
4708 reg_val
&= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
4710 CL22_WR_OVER_CL45(sc
, phy
,
4711 MDIO_REG_BANK_SERDES_DIGITAL
,
4712 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, reg_val
);
4714 /* Enable TetonII and BAM autoneg */
4715 CL22_RD_OVER_CL45(sc
, phy
,
4716 MDIO_REG_BANK_BAM_NEXT_PAGE
,
4717 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
, ®_val
);
4718 if (vars
->line_speed
== ELINK_SPEED_AUTO_NEG
) {
4719 /* Enable BAM aneg Mode and TetonII aneg Mode */
4720 reg_val
|= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
4721 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
4723 /* TetonII and BAM Autoneg Disabled */
4724 reg_val
&= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
4725 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
4727 CL22_WR_OVER_CL45(sc
, phy
,
4728 MDIO_REG_BANK_BAM_NEXT_PAGE
,
4729 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
, reg_val
);
4732 /* Enable Cl73 FSM status bits */
4733 CL22_WR_OVER_CL45(sc
, phy
,
4734 MDIO_REG_BANK_CL73_USERB0
,
4735 MDIO_CL73_USERB0_CL73_UCTRL
, 0xe);
4737 /* Enable BAM Station Manager */
4738 CL22_WR_OVER_CL45(sc
, phy
,
4739 MDIO_REG_BANK_CL73_USERB0
,
4740 MDIO_CL73_USERB0_CL73_BAM_CTRL1
,
4741 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN
|
4742 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
4744 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN
);
4746 /* Advertise CL73 link speeds */
4747 CL22_RD_OVER_CL45(sc
, phy
,
4748 MDIO_REG_BANK_CL73_IEEEB1
,
4749 MDIO_CL73_IEEEB1_AN_ADV2
, ®_val
);
4750 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
4751 reg_val
|= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
;
4752 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
4753 reg_val
|= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
;
4755 CL22_WR_OVER_CL45(sc
, phy
,
4756 MDIO_REG_BANK_CL73_IEEEB1
,
4757 MDIO_CL73_IEEEB1_AN_ADV2
, reg_val
);
4759 /* CL73 Autoneg Enabled */
4760 reg_val
= MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
;
4762 } else /* CL73 Autoneg Disabled */
4765 CL22_WR_OVER_CL45(sc
, phy
,
4766 MDIO_REG_BANK_CL73_IEEEB0
,
4767 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
, reg_val
);
4770 /* Program SerDes, forced speed */
4771 static void elink_program_serdes(struct elink_phy
*phy
,
4772 struct elink_params
*params
,
4773 struct elink_vars
*vars
)
4775 struct bnx2x_softc
*sc
= params
->sc
;
4778 /* Program duplex, disable autoneg and sgmii */
4779 CL22_RD_OVER_CL45(sc
, phy
,
4780 MDIO_REG_BANK_COMBO_IEEE0
,
4781 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
4782 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
|
4783 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
4784 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
);
4785 if (phy
->req_duplex
== DUPLEX_FULL
)
4786 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
4787 CL22_WR_OVER_CL45(sc
, phy
,
4788 MDIO_REG_BANK_COMBO_IEEE0
,
4789 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
4792 * - needed only if the speed is greater than 1G (2.5G or 10G)
4794 CL22_RD_OVER_CL45(sc
, phy
,
4795 MDIO_REG_BANK_SERDES_DIGITAL
,
4796 MDIO_SERDES_DIGITAL_MISC1
, ®_val
);
4797 /* Clearing the speed value before setting the right speed */
4798 PMD_DRV_LOG(DEBUG
, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x", reg_val
);
4800 reg_val
&= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK
|
4801 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
4803 if (!((vars
->line_speed
== ELINK_SPEED_1000
) ||
4804 (vars
->line_speed
== ELINK_SPEED_100
) ||
4805 (vars
->line_speed
== ELINK_SPEED_10
))) {
4807 reg_val
|= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M
|
4808 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
4809 if (vars
->line_speed
== ELINK_SPEED_10000
)
4811 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4
;
4814 CL22_WR_OVER_CL45(sc
, phy
,
4815 MDIO_REG_BANK_SERDES_DIGITAL
,
4816 MDIO_SERDES_DIGITAL_MISC1
, reg_val
);
4820 static void elink_set_brcm_cl37_advertisement(struct elink_phy
*phy
,
4821 struct elink_params
*params
)
4823 struct bnx2x_softc
*sc
= params
->sc
;
4826 /* Set extended capabilities */
4827 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
)
4828 val
|= MDIO_OVER_1G_UP1_2_5G
;
4829 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
4830 val
|= MDIO_OVER_1G_UP1_10G
;
4831 CL22_WR_OVER_CL45(sc
, phy
,
4832 MDIO_REG_BANK_OVER_1G
, MDIO_OVER_1G_UP1
, val
);
4834 CL22_WR_OVER_CL45(sc
, phy
,
4835 MDIO_REG_BANK_OVER_1G
, MDIO_OVER_1G_UP3
, 0x400);
4838 static void elink_set_ieee_aneg_advertisement(struct elink_phy
*phy
,
4839 struct elink_params
*params
,
4842 struct bnx2x_softc
*sc
= params
->sc
;
4844 /* For AN, we are always publishing full duplex */
4846 CL22_WR_OVER_CL45(sc
, phy
,
4847 MDIO_REG_BANK_COMBO_IEEE0
,
4848 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
, ieee_fc
);
4849 CL22_RD_OVER_CL45(sc
, phy
,
4850 MDIO_REG_BANK_CL73_IEEEB1
,
4851 MDIO_CL73_IEEEB1_AN_ADV1
, &val
);
4852 val
&= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH
;
4853 val
|= ((ieee_fc
<< 3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK
);
4854 CL22_WR_OVER_CL45(sc
, phy
,
4855 MDIO_REG_BANK_CL73_IEEEB1
,
4856 MDIO_CL73_IEEEB1_AN_ADV1
, val
);
4859 static void elink_restart_autoneg(struct elink_phy
*phy
,
4860 struct elink_params
*params
,
4861 uint8_t enable_cl73
)
4863 struct bnx2x_softc
*sc
= params
->sc
;
4864 uint16_t mii_control
;
4866 PMD_DRV_LOG(DEBUG
, "elink_restart_autoneg");
4867 /* Enable and restart BAM/CL37 aneg */
4870 CL22_RD_OVER_CL45(sc
, phy
,
4871 MDIO_REG_BANK_CL73_IEEEB0
,
4872 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
4875 CL22_WR_OVER_CL45(sc
, phy
,
4876 MDIO_REG_BANK_CL73_IEEEB0
,
4877 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
4879 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
|
4880 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN
));
4883 CL22_RD_OVER_CL45(sc
, phy
,
4884 MDIO_REG_BANK_COMBO_IEEE0
,
4885 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
4887 "elink_restart_autoneg mii_control before = 0x%x",
4889 CL22_WR_OVER_CL45(sc
, phy
,
4890 MDIO_REG_BANK_COMBO_IEEE0
,
4891 MDIO_COMBO_IEEE0_MII_CONTROL
,
4893 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
4894 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
));
4898 static void elink_initialize_sgmii_process(struct elink_phy
*phy
,
4899 struct elink_params
*params
,
4900 struct elink_vars
*vars
)
4902 struct bnx2x_softc
*sc
= params
->sc
;
4905 /* In SGMII mode, the unicore is always slave */
4907 CL22_RD_OVER_CL45(sc
, phy
,
4908 MDIO_REG_BANK_SERDES_DIGITAL
,
4909 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, &control1
);
4910 control1
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
;
4911 /* Set sgmii mode (and not fiber) */
4912 control1
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
|
4913 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
|
4914 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE
);
4915 CL22_WR_OVER_CL45(sc
, phy
,
4916 MDIO_REG_BANK_SERDES_DIGITAL
,
4917 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, control1
);
4919 /* If forced speed */
4920 if (!(vars
->line_speed
== ELINK_SPEED_AUTO_NEG
)) {
4921 /* Set speed, disable autoneg */
4922 uint16_t mii_control
;
4924 CL22_RD_OVER_CL45(sc
, phy
,
4925 MDIO_REG_BANK_COMBO_IEEE0
,
4926 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
4927 mii_control
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
4928 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
|
4929 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
);
4931 switch (vars
->line_speed
) {
4932 case ELINK_SPEED_100
:
4934 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100
;
4936 case ELINK_SPEED_1000
:
4938 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000
;
4940 case ELINK_SPEED_10
:
4941 /* There is nothing to set for 10M */
4944 /* Invalid speed for SGMII */
4945 PMD_DRV_LOG(DEBUG
, "Invalid line_speed 0x%x",
4950 /* Setting the full duplex */
4951 if (phy
->req_duplex
== DUPLEX_FULL
)
4952 mii_control
|= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
4953 CL22_WR_OVER_CL45(sc
, phy
,
4954 MDIO_REG_BANK_COMBO_IEEE0
,
4955 MDIO_COMBO_IEEE0_MII_CONTROL
, mii_control
);
4957 } else { /* AN mode */
4958 /* Enable and restart AN */
4959 elink_restart_autoneg(phy
, params
, 0);
4965 static elink_status_t
elink_direct_parallel_detect_used(struct elink_phy
*phy
,
4969 struct bnx2x_softc
*sc
= params
->sc
;
4970 uint16_t pd_10g
, status2_1000x
;
4971 if (phy
->req_line_speed
!= ELINK_SPEED_AUTO_NEG
)
4972 return ELINK_STATUS_OK
;
4973 CL22_RD_OVER_CL45(sc
, phy
,
4974 MDIO_REG_BANK_SERDES_DIGITAL
,
4975 MDIO_SERDES_DIGITAL_A_1000X_STATUS2
, &status2_1000x
);
4976 CL22_RD_OVER_CL45(sc
, phy
,
4977 MDIO_REG_BANK_SERDES_DIGITAL
,
4978 MDIO_SERDES_DIGITAL_A_1000X_STATUS2
, &status2_1000x
);
4979 if (status2_1000x
& MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED
) {
4980 PMD_DRV_LOG(DEBUG
, "1G parallel detect link on port %d",
4982 return ELINK_STATUS_ERROR
;
4985 CL22_RD_OVER_CL45(sc
, phy
,
4986 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4987 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS
, &pd_10g
);
4989 if (pd_10g
& MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK
) {
4990 PMD_DRV_LOG(DEBUG
, "10G parallel detect link on port %d",
4992 return ELINK_STATUS_ERROR
;
4994 return ELINK_STATUS_OK
;
4997 static void elink_update_adv_fc(struct elink_phy
*phy
,
4998 struct elink_params
*params
,
4999 struct elink_vars
*vars
, uint32_t gp_status
)
5001 uint16_t ld_pause
; /* local driver */
5002 uint16_t lp_pause
; /* link partner */
5003 uint16_t pause_result
;
5004 struct bnx2x_softc
*sc
= params
->sc
;
5006 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE
|
5007 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE
)) ==
5008 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE
|
5009 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE
)) {
5011 CL22_RD_OVER_CL45(sc
, phy
,
5012 MDIO_REG_BANK_CL73_IEEEB1
,
5013 MDIO_CL73_IEEEB1_AN_ADV1
, &ld_pause
);
5014 CL22_RD_OVER_CL45(sc
, phy
,
5015 MDIO_REG_BANK_CL73_IEEEB1
,
5016 MDIO_CL73_IEEEB1_AN_LP_ADV1
, &lp_pause
);
5017 pause_result
= (ld_pause
&
5018 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK
) >> 8;
5019 pause_result
|= (lp_pause
&
5020 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK
) >> 10;
5021 PMD_DRV_LOG(DEBUG
, "pause_result CL73 0x%x", pause_result
);
5023 CL22_RD_OVER_CL45(sc
, phy
,
5024 MDIO_REG_BANK_COMBO_IEEE0
,
5025 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
, &ld_pause
);
5026 CL22_RD_OVER_CL45(sc
, phy
,
5027 MDIO_REG_BANK_COMBO_IEEE0
,
5028 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1
,
5030 pause_result
= (ld_pause
&
5031 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) >> 5;
5032 pause_result
|= (lp_pause
&
5033 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) >> 7;
5034 PMD_DRV_LOG(DEBUG
, "pause_result CL37 0x%x", pause_result
);
5036 elink_pause_resolve(vars
, pause_result
);
5040 static void elink_flow_ctrl_resolve(struct elink_phy
*phy
,
5041 struct elink_params
*params
,
5042 struct elink_vars
*vars
, uint32_t gp_status
)
5044 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
5046 /* Resolve from gp_status in case of AN complete and not sgmii */
5047 if (phy
->req_flow_ctrl
!= ELINK_FLOW_CTRL_AUTO
) {
5048 /* Update the advertised flow-controled of LD/LP in AN */
5049 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)
5050 elink_update_adv_fc(phy
, params
, vars
, gp_status
);
5051 /* But set the flow-control result as the requested one */
5052 vars
->flow_ctrl
= phy
->req_flow_ctrl
;
5053 } else if (phy
->req_line_speed
!= ELINK_SPEED_AUTO_NEG
)
5054 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
5055 else if ((gp_status
& ELINK_MDIO_AN_CL73_OR_37_COMPLETE
) &&
5056 (!(vars
->phy_flags
& PHY_SGMII_FLAG
))) {
5057 if (elink_direct_parallel_detect_used(phy
, params
)) {
5058 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
5061 elink_update_adv_fc(phy
, params
, vars
, gp_status
);
5063 PMD_DRV_LOG(DEBUG
, "flow_ctrl 0x%x", vars
->flow_ctrl
);
5066 static void elink_check_fallback_to_cl37(struct elink_phy
*phy
,
5067 struct elink_params
*params
)
5069 struct bnx2x_softc
*sc
= params
->sc
;
5070 uint16_t rx_status
, ustat_val
, cl37_fsm_received
;
5071 PMD_DRV_LOG(DEBUG
, "elink_check_fallback_to_cl37");
5072 /* Step 1: Make sure signal is detected */
5073 CL22_RD_OVER_CL45(sc
, phy
,
5074 MDIO_REG_BANK_RX0
, MDIO_RX0_RX_STATUS
, &rx_status
);
5075 if ((rx_status
& MDIO_RX0_RX_STATUS_SIGDET
) !=
5076 (MDIO_RX0_RX_STATUS_SIGDET
)) {
5077 PMD_DRV_LOG(DEBUG
, "Signal is not detected. Restoring CL73."
5078 "rx_status(0x80b0) = 0x%x", rx_status
);
5079 CL22_WR_OVER_CL45(sc
, phy
,
5080 MDIO_REG_BANK_CL73_IEEEB0
,
5081 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
5082 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
);
5085 /* Step 2: Check CL73 state machine */
5086 CL22_RD_OVER_CL45(sc
, phy
,
5087 MDIO_REG_BANK_CL73_USERB0
,
5088 MDIO_CL73_USERB0_CL73_USTAT1
, &ustat_val
);
5090 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
5091 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) !=
5092 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
5093 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) {
5094 PMD_DRV_LOG(DEBUG
, "CL73 state-machine is not stable. "
5095 "ustat_val(0x8371) = 0x%x", ustat_val
);
5098 /* Step 3: Check CL37 Message Pages received to indicate LP
5099 * supports only CL37
5101 CL22_RD_OVER_CL45(sc
, phy
,
5102 MDIO_REG_BANK_REMOTE_PHY
,
5103 MDIO_REMOTE_PHY_MISC_RX_STATUS
, &cl37_fsm_received
);
5104 if ((cl37_fsm_received
&
5105 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
5106 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) !=
5107 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
5108 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) {
5109 PMD_DRV_LOG(DEBUG
, "No CL37 FSM were received. "
5110 "misc_rx_status(0x8330) = 0x%x", cl37_fsm_received
);
5113 /* The combined cl37/cl73 fsm state information indicating that
5114 * we are connected to a device which does not support cl73, but
5115 * does support cl37 BAM. In this case we disable cl73 and
5116 * restart cl37 auto-neg
5120 CL22_WR_OVER_CL45(sc
, phy
,
5121 MDIO_REG_BANK_CL73_IEEEB0
,
5122 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
, 0);
5123 /* Restart CL37 autoneg */
5124 elink_restart_autoneg(phy
, params
, 0);
5125 PMD_DRV_LOG(DEBUG
, "Disabling CL73, and restarting CL37 autoneg");
5128 static void elink_xgxs_an_resolve(struct elink_phy
*phy
,
5129 struct elink_params
*params
,
5130 struct elink_vars
*vars
, uint32_t gp_status
)
5132 if (gp_status
& ELINK_MDIO_AN_CL73_OR_37_COMPLETE
)
5133 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
5135 if (elink_direct_parallel_detect_used(phy
, params
))
5136 vars
->link_status
|= LINK_STATUS_PARALLEL_DETECTION_USED
;
5139 static elink_status_t
elink_get_link_speed_duplex(struct elink_phy
*phy
,
5140 struct elink_params
*params __rte_unused
,
5141 struct elink_vars
*vars
,
5142 uint16_t is_link_up
,
5143 uint16_t speed_mask
,
5146 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)
5147 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_ENABLED
;
5149 PMD_DRV_LOG(DEBUG
, "phy link up");
5151 vars
->phy_link_up
= 1;
5152 vars
->link_status
|= LINK_STATUS_LINK_UP
;
5154 switch (speed_mask
) {
5155 case ELINK_GP_STATUS_10M
:
5156 vars
->line_speed
= ELINK_SPEED_10
;
5157 if (is_duplex
== DUPLEX_FULL
)
5158 vars
->link_status
|= ELINK_LINK_10TFD
;
5160 vars
->link_status
|= ELINK_LINK_10THD
;
5163 case ELINK_GP_STATUS_100M
:
5164 vars
->line_speed
= ELINK_SPEED_100
;
5165 if (is_duplex
== DUPLEX_FULL
)
5166 vars
->link_status
|= ELINK_LINK_100TXFD
;
5168 vars
->link_status
|= ELINK_LINK_100TXHD
;
5171 case ELINK_GP_STATUS_1G
:
5172 case ELINK_GP_STATUS_1G_KX
:
5173 vars
->line_speed
= ELINK_SPEED_1000
;
5174 if (is_duplex
== DUPLEX_FULL
)
5175 vars
->link_status
|= ELINK_LINK_1000TFD
;
5177 vars
->link_status
|= ELINK_LINK_1000THD
;
5180 case ELINK_GP_STATUS_2_5G
:
5181 vars
->line_speed
= ELINK_SPEED_2500
;
5182 if (is_duplex
== DUPLEX_FULL
)
5183 vars
->link_status
|= ELINK_LINK_2500TFD
;
5185 vars
->link_status
|= ELINK_LINK_2500THD
;
5188 case ELINK_GP_STATUS_5G
:
5189 case ELINK_GP_STATUS_6G
:
5191 "link speed unsupported gp_status 0x%x",
5193 return ELINK_STATUS_ERROR
;
5195 case ELINK_GP_STATUS_10G_KX4
:
5196 case ELINK_GP_STATUS_10G_HIG
:
5197 case ELINK_GP_STATUS_10G_CX4
:
5198 case ELINK_GP_STATUS_10G_KR
:
5199 case ELINK_GP_STATUS_10G_SFI
:
5200 case ELINK_GP_STATUS_10G_XFI
:
5201 vars
->line_speed
= ELINK_SPEED_10000
;
5202 vars
->link_status
|= ELINK_LINK_10GTFD
;
5204 case ELINK_GP_STATUS_20G_DXGXS
:
5205 case ELINK_GP_STATUS_20G_KR2
:
5206 vars
->line_speed
= ELINK_SPEED_20000
;
5207 vars
->link_status
|= ELINK_LINK_20GTFD
;
5211 "link speed unsupported gp_status 0x%x",
5213 return ELINK_STATUS_ERROR
;
5215 } else { /* link_down */
5216 PMD_DRV_LOG(DEBUG
, "phy link down");
5218 vars
->phy_link_up
= 0;
5220 vars
->duplex
= DUPLEX_FULL
;
5221 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
5222 vars
->mac_type
= ELINK_MAC_TYPE_NONE
;
5224 PMD_DRV_LOG(DEBUG
, " phy_link_up %x line_speed %d",
5225 vars
->phy_link_up
, vars
->line_speed
);
5226 return ELINK_STATUS_OK
;
5229 static uint8_t elink_link_settings_status(struct elink_phy
*phy
,
5230 struct elink_params
*params
,
5231 struct elink_vars
*vars
)
5233 struct bnx2x_softc
*sc
= params
->sc
;
5235 uint16_t gp_status
, duplex
= DUPLEX_HALF
, link_up
= 0, speed_mask
;
5236 elink_status_t rc
= ELINK_STATUS_OK
;
5238 /* Read gp_status */
5239 CL22_RD_OVER_CL45(sc
, phy
,
5240 MDIO_REG_BANK_GP_STATUS
,
5241 MDIO_GP_STATUS_TOP_AN_STATUS1
, &gp_status
);
5242 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS
)
5243 duplex
= DUPLEX_FULL
;
5244 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
)
5246 speed_mask
= gp_status
& ELINK_GP_STATUS_SPEED_MASK
;
5247 PMD_DRV_LOG(DEBUG
, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x",
5248 gp_status
, link_up
, speed_mask
);
5249 rc
= elink_get_link_speed_duplex(phy
, params
, vars
, link_up
, speed_mask
,
5251 if (rc
== ELINK_STATUS_ERROR
)
5254 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
) {
5255 if (ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5256 vars
->duplex
= duplex
;
5257 elink_flow_ctrl_resolve(phy
, params
, vars
, gp_status
);
5258 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)
5259 elink_xgxs_an_resolve(phy
, params
, vars
,
5262 } else { /* Link_down */
5263 if ((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
5264 ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5265 /* Check signal is detected */
5266 elink_check_fallback_to_cl37(phy
, params
);
5270 /* Read LP advertised speeds */
5271 if (ELINK_SINGLE_MEDIA_DIRECT(params
) &&
5272 (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
)) {
5275 CL22_RD_OVER_CL45(sc
, phy
, MDIO_REG_BANK_CL73_IEEEB1
,
5276 MDIO_CL73_IEEEB1_AN_LP_ADV2
, &val
);
5278 if (val
& MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
)
5279 vars
->link_status
|=
5280 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
5281 if (val
& (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
|
5282 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR
))
5283 vars
->link_status
|=
5284 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5286 CL22_RD_OVER_CL45(sc
, phy
, MDIO_REG_BANK_OVER_1G
,
5287 MDIO_OVER_1G_LP_UP1
, &val
);
5289 if (val
& MDIO_OVER_1G_UP1_2_5G
)
5290 vars
->link_status
|=
5291 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE
;
5292 if (val
& (MDIO_OVER_1G_UP1_10G
| MDIO_OVER_1G_UP1_10GH
))
5293 vars
->link_status
|=
5294 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5297 PMD_DRV_LOG(DEBUG
, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5298 vars
->duplex
, vars
->flow_ctrl
, vars
->link_status
);
5302 static uint8_t elink_warpcore_read_status(struct elink_phy
*phy
,
5303 struct elink_params
*params
,
5304 struct elink_vars
*vars
)
5306 struct bnx2x_softc
*sc
= params
->sc
;
5308 uint16_t gp_status1
, gp_speed
, link_up
, duplex
= DUPLEX_FULL
;
5309 elink_status_t rc
= ELINK_STATUS_OK
;
5310 lane
= elink_get_warpcore_lane(params
);
5311 /* Read gp_status */
5312 if ((params
->loopback_mode
) && (phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)) {
5313 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5314 MDIO_WC_REG_DIGITAL5_LINK_STATUS
, &link_up
);
5315 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5316 MDIO_WC_REG_DIGITAL5_LINK_STATUS
, &link_up
);
5318 } else if ((phy
->req_line_speed
> ELINK_SPEED_10000
) &&
5319 (phy
->supported
& ELINK_SUPPORTED_20000baseMLD2_Full
)) {
5320 uint16_t temp_link_up
;
5321 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
, 1, &temp_link_up
);
5322 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
, 1, &link_up
);
5323 PMD_DRV_LOG(DEBUG
, "PCS RX link status = 0x%x-->0x%x",
5324 temp_link_up
, link_up
);
5325 link_up
&= (1 << 2);
5327 elink_ext_phy_resolve_fc(phy
, params
, vars
);
5329 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5330 MDIO_WC_REG_GP2_STATUS_GP_2_1
, &gp_status1
);
5331 PMD_DRV_LOG(DEBUG
, "0x81d1 = 0x%x", gp_status1
);
5332 /* Check for either KR, 1G, or AN up. */
5333 link_up
= ((gp_status1
>> 8) |
5334 (gp_status1
>> 12) | (gp_status1
)) & (1 << lane
);
5335 if (phy
->supported
& ELINK_SUPPORTED_20000baseKR2_Full
) {
5337 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
5338 MDIO_AN_REG_STATUS
, &an_link
);
5339 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
5340 MDIO_AN_REG_STATUS
, &an_link
);
5341 link_up
|= (an_link
& (1 << 2));
5343 if (link_up
&& ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5344 uint16_t pd
, gp_status4
;
5345 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) {
5346 /* Check Autoneg complete */
5347 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5348 MDIO_WC_REG_GP2_STATUS_GP_2_4
,
5350 if (gp_status4
& ((1 << 12) << lane
))
5351 vars
->link_status
|=
5352 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
5354 /* Check parallel detect used */
5355 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5356 MDIO_WC_REG_PAR_DET_10G_STATUS
,
5359 vars
->link_status
|=
5360 LINK_STATUS_PARALLEL_DETECTION_USED
;
5362 elink_ext_phy_resolve_fc(phy
, params
, vars
);
5363 vars
->duplex
= duplex
;
5367 if ((vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) &&
5368 ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5371 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
5372 MDIO_AN_REG_LP_AUTO_NEG2
, &val
);
5374 if (val
& MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
)
5375 vars
->link_status
|=
5376 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
5377 if (val
& (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
|
5378 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR
))
5379 vars
->link_status
|=
5380 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5382 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5383 MDIO_WC_REG_DIGITAL3_LP_UP1
, &val
);
5385 if (val
& MDIO_OVER_1G_UP1_2_5G
)
5386 vars
->link_status
|=
5387 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE
;
5388 if (val
& (MDIO_OVER_1G_UP1_10G
| MDIO_OVER_1G_UP1_10GH
))
5389 vars
->link_status
|=
5390 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5395 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5396 MDIO_WC_REG_GP2_STATUS_GP_2_2
, &gp_speed
);
5398 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
5399 MDIO_WC_REG_GP2_STATUS_GP_2_3
, &gp_speed
);
5401 PMD_DRV_LOG(DEBUG
, "lane %d gp_speed 0x%x", lane
, gp_speed
);
5403 if ((lane
& 1) == 0)
5406 link_up
= ! !link_up
;
5408 /* Reset the TX FIFO to fix SGMII issue */
5409 rc
= elink_get_link_speed_duplex(phy
, params
, vars
, link_up
, gp_speed
,
5412 /* In case of KR link down, start up the recovering procedure */
5413 if ((!link_up
) && (phy
->media_type
== ELINK_ETH_PHY_KR
) &&
5414 (!(phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
)))
5415 vars
->rx_tx_asic_rst
= MAX_KR_LINK_RETRY
;
5417 PMD_DRV_LOG(DEBUG
, "duplex %x flow_ctrl 0x%x link_status 0x%x",
5418 vars
->duplex
, vars
->flow_ctrl
, vars
->link_status
);
5422 static void elink_set_gmii_tx_driver(struct elink_params
*params
)
5424 struct bnx2x_softc
*sc
= params
->sc
;
5425 struct elink_phy
*phy
= ¶ms
->phy
[ELINK_INT_PHY
];
5431 CL22_RD_OVER_CL45(sc
, phy
,
5432 MDIO_REG_BANK_OVER_1G
, MDIO_OVER_1G_LP_UP2
, &lp_up2
);
5434 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5435 lp_up2
= (((lp_up2
& MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK
) >>
5436 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT
) <<
5437 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT
);
5442 for (bank
= MDIO_REG_BANK_TX0
; bank
<= MDIO_REG_BANK_TX3
;
5443 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
)) {
5444 CL22_RD_OVER_CL45(sc
, phy
,
5445 bank
, MDIO_TX0_TX_DRIVER
, &tx_driver
);
5447 /* Replace tx_driver bits [15:12] */
5448 if (lp_up2
!= (tx_driver
& MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
)) {
5449 tx_driver
&= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
;
5450 tx_driver
|= lp_up2
;
5451 CL22_WR_OVER_CL45(sc
, phy
,
5452 bank
, MDIO_TX0_TX_DRIVER
, tx_driver
);
5457 static elink_status_t
elink_emac_program(struct elink_params
*params
,
5458 struct elink_vars
*vars
)
5460 struct bnx2x_softc
*sc
= params
->sc
;
5461 uint8_t port
= params
->port
;
5464 PMD_DRV_LOG(DEBUG
, "setting link speed & duplex");
5465 elink_bits_dis(sc
, GRCBASE_EMAC0
+ port
* 0x400 +
5467 (EMAC_MODE_25G_MODE
|
5468 EMAC_MODE_PORT_MII_10M
| EMAC_MODE_HALF_DUPLEX
));
5469 switch (vars
->line_speed
) {
5470 case ELINK_SPEED_10
:
5471 mode
|= EMAC_MODE_PORT_MII_10M
;
5474 case ELINK_SPEED_100
:
5475 mode
|= EMAC_MODE_PORT_MII
;
5478 case ELINK_SPEED_1000
:
5479 mode
|= EMAC_MODE_PORT_GMII
;
5482 case ELINK_SPEED_2500
:
5483 mode
|= (EMAC_MODE_25G_MODE
| EMAC_MODE_PORT_GMII
);
5487 /* 10G not valid for EMAC */
5488 PMD_DRV_LOG(DEBUG
, "Invalid line_speed 0x%x", vars
->line_speed
);
5489 return ELINK_STATUS_ERROR
;
5492 if (vars
->duplex
== DUPLEX_HALF
)
5493 mode
|= EMAC_MODE_HALF_DUPLEX
;
5495 GRCBASE_EMAC0
+ port
* 0x400 + EMAC_REG_EMAC_MODE
, mode
);
5497 elink_set_led(params
, vars
, ELINK_LED_MODE_OPER
, vars
->line_speed
);
5498 return ELINK_STATUS_OK
;
5501 static void elink_set_preemphasis(struct elink_phy
*phy
,
5502 struct elink_params
*params
)
5505 uint16_t bank
, i
= 0;
5506 struct bnx2x_softc
*sc
= params
->sc
;
5508 for (bank
= MDIO_REG_BANK_RX0
, i
= 0; bank
<= MDIO_REG_BANK_RX3
;
5509 bank
+= (MDIO_REG_BANK_RX1
- MDIO_REG_BANK_RX0
), i
++) {
5510 CL22_WR_OVER_CL45(sc
, phy
,
5512 MDIO_RX0_RX_EQ_BOOST
, phy
->rx_preemphasis
[i
]);
5515 for (bank
= MDIO_REG_BANK_TX0
, i
= 0; bank
<= MDIO_REG_BANK_TX3
;
5516 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
), i
++) {
5517 CL22_WR_OVER_CL45(sc
, phy
,
5519 MDIO_TX0_TX_DRIVER
, phy
->tx_preemphasis
[i
]);
5523 static uint8_t elink_xgxs_config_init(struct elink_phy
*phy
,
5524 struct elink_params
*params
,
5525 struct elink_vars
*vars
)
5527 uint8_t enable_cl73
= (ELINK_SINGLE_MEDIA_DIRECT(params
) ||
5528 (params
->loopback_mode
== ELINK_LOOPBACK_XGXS
));
5530 if (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) {
5531 if (ELINK_SINGLE_MEDIA_DIRECT(params
) &&
5532 (params
->feature_config_flags
&
5533 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
))
5534 elink_set_preemphasis(phy
, params
);
5536 /* Forced speed requested? */
5537 if (vars
->line_speed
!= ELINK_SPEED_AUTO_NEG
||
5538 (ELINK_SINGLE_MEDIA_DIRECT(params
) &&
5539 params
->loopback_mode
== ELINK_LOOPBACK_EXT
)) {
5540 PMD_DRV_LOG(DEBUG
, "not SGMII, no AN");
5542 /* Disable autoneg */
5543 elink_set_autoneg(phy
, params
, vars
, 0);
5545 /* Program speed and duplex */
5546 elink_program_serdes(phy
, params
, vars
);
5548 } else { /* AN_mode */
5549 PMD_DRV_LOG(DEBUG
, "not SGMII, AN");
5552 elink_set_brcm_cl37_advertisement(phy
, params
);
5554 /* Program duplex & pause advertisement (for aneg) */
5555 elink_set_ieee_aneg_advertisement(phy
, params
,
5558 /* Enable autoneg */
5559 elink_set_autoneg(phy
, params
, vars
, enable_cl73
);
5561 /* Enable and restart AN */
5562 elink_restart_autoneg(phy
, params
, enable_cl73
);
5565 } else { /* SGMII mode */
5566 PMD_DRV_LOG(DEBUG
, "SGMII");
5568 elink_initialize_sgmii_process(phy
, params
, vars
);
5574 static elink_status_t
elink_prepare_xgxs(struct elink_phy
*phy
,
5575 struct elink_params
*params
,
5576 struct elink_vars
*vars
)
5579 vars
->phy_flags
|= PHY_XGXS_FLAG
;
5580 if ((phy
->req_line_speed
&&
5581 ((phy
->req_line_speed
== ELINK_SPEED_100
) ||
5582 (phy
->req_line_speed
== ELINK_SPEED_10
))) ||
5583 (!phy
->req_line_speed
&&
5584 (phy
->speed_cap_mask
>=
5585 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
) &&
5586 (phy
->speed_cap_mask
<
5587 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
5588 (phy
->type
== PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD
))
5589 vars
->phy_flags
|= PHY_SGMII_FLAG
;
5591 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
5593 elink_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
5594 elink_set_aer_mmd(params
, phy
);
5595 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
5596 elink_set_master_ln(params
, phy
);
5598 rc
= elink_reset_unicore(params
, phy
, 0);
5599 /* Reset the SerDes and wait for reset bit return low */
5600 if (rc
!= ELINK_STATUS_OK
)
5603 elink_set_aer_mmd(params
, phy
);
5604 /* Setting the masterLn_def again after the reset */
5605 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) {
5606 elink_set_master_ln(params
, phy
);
5607 elink_set_swap_lanes(params
, phy
);
5613 static uint16_t elink_wait_reset_complete(struct bnx2x_softc
*sc
,
5614 struct elink_phy
*phy
,
5615 struct elink_params
*params
)
5618 /* Wait for soft reset to get cleared up to 1 sec */
5619 for (cnt
= 0; cnt
< 1000; cnt
++) {
5620 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
)
5621 elink_cl22_read(sc
, phy
, MDIO_PMA_REG_CTRL
, &ctrl
);
5623 elink_cl45_read(sc
, phy
,
5625 MDIO_PMA_REG_CTRL
, &ctrl
);
5626 if (!(ctrl
& (1 << 15)))
5632 elink_cb_event_log(sc
, ELINK_LOG_ID_PHY_UNINITIALIZED
, params
->port
); // "Warning: PHY was not initialized,"
5635 PMD_DRV_LOG(DEBUG
, "control reg 0x%x (after %d ms)", ctrl
, cnt
);
5639 static void elink_link_int_enable(struct elink_params
*params
)
5641 uint8_t port
= params
->port
;
5643 struct bnx2x_softc
*sc
= params
->sc
;
5645 /* Setting the status to report on link up for either XGXS or SerDes */
5646 if (CHIP_IS_E3(sc
)) {
5647 mask
= ELINK_NIG_MASK_XGXS0_LINK_STATUS
;
5648 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
)))
5649 mask
|= ELINK_NIG_MASK_MI_INT
;
5650 } else if (params
->switch_cfg
== ELINK_SWITCH_CFG_10G
) {
5651 mask
= (ELINK_NIG_MASK_XGXS0_LINK10G
|
5652 ELINK_NIG_MASK_XGXS0_LINK_STATUS
);
5653 PMD_DRV_LOG(DEBUG
, "enabled XGXS interrupt");
5654 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
)) &&
5655 params
->phy
[ELINK_INT_PHY
].type
!=
5656 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) {
5657 mask
|= ELINK_NIG_MASK_MI_INT
;
5658 PMD_DRV_LOG(DEBUG
, "enabled external phy int");
5661 } else { /* SerDes */
5662 mask
= ELINK_NIG_MASK_SERDES0_LINK_STATUS
;
5663 PMD_DRV_LOG(DEBUG
, "enabled SerDes interrupt");
5664 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
)) &&
5665 params
->phy
[ELINK_INT_PHY
].type
!=
5666 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN
) {
5667 mask
|= ELINK_NIG_MASK_MI_INT
;
5668 PMD_DRV_LOG(DEBUG
, "enabled external phy int");
5671 elink_bits_en(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
* 4, mask
);
5673 PMD_DRV_LOG(DEBUG
, "port %x, is_xgxs %x, int_status 0x%x", port
,
5674 (params
->switch_cfg
== ELINK_SWITCH_CFG_10G
),
5675 REG_RD(sc
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
* 4));
5676 PMD_DRV_LOG(DEBUG
, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x",
5677 REG_RD(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
* 4),
5678 REG_RD(sc
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+ port
* 0x18),
5680 NIG_REG_SERDES0_STATUS_LINK_STATUS
+ port
* 0x3c));
5681 PMD_DRV_LOG(DEBUG
, " 10G %x, XGXS_LINK %x",
5682 REG_RD(sc
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
* 0x68),
5683 REG_RD(sc
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
* 0x68));
5686 static void elink_rearm_latch_signal(struct bnx2x_softc
*sc
, uint8_t port
,
5689 uint32_t latch_status
= 0;
5691 /* Disable the MI INT ( external phy int ) by writing 1 to the
5692 * status register. Link down indication is high-active-signal,
5693 * so in this case we need to write the status to clear the XOR
5695 /* Read Latched signals */
5696 latch_status
= REG_RD(sc
, NIG_REG_LATCH_STATUS_0
+ port
* 8);
5697 PMD_DRV_LOG(DEBUG
, "latch_status = 0x%x", latch_status
);
5698 /* Handle only those with latched-signal=up. */
5701 NIG_REG_STATUS_INTERRUPT_PORT0
5702 + port
* 4, ELINK_NIG_STATUS_EMAC0_MI_INT
);
5705 NIG_REG_STATUS_INTERRUPT_PORT0
5706 + port
* 4, ELINK_NIG_STATUS_EMAC0_MI_INT
);
5708 if (latch_status
& 1) {
5710 /* For all latched-signal=up : Re-Arm Latch signals */
5711 REG_WR(sc
, NIG_REG_LATCH_STATUS_0
+ port
* 8,
5712 (latch_status
& 0xfffe) | (latch_status
& 1));
5714 /* For all latched-signal=up,Write original_signal to status */
5717 static void elink_link_int_ack(struct elink_params
*params
,
5718 struct elink_vars
*vars
, uint8_t is_10g_plus
)
5720 struct bnx2x_softc
*sc
= params
->sc
;
5721 uint8_t port
= params
->port
;
5723 /* First reset all status we assume only one line will be
5726 elink_bits_dis(sc
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
* 4,
5727 (ELINK_NIG_STATUS_XGXS0_LINK10G
|
5728 ELINK_NIG_STATUS_XGXS0_LINK_STATUS
|
5729 ELINK_NIG_STATUS_SERDES0_LINK_STATUS
));
5730 if (vars
->phy_link_up
) {
5731 if (USES_WARPCORE(sc
))
5732 mask
= ELINK_NIG_STATUS_XGXS0_LINK_STATUS
;
5735 mask
= ELINK_NIG_STATUS_XGXS0_LINK10G
;
5736 else if (params
->switch_cfg
== ELINK_SWITCH_CFG_10G
) {
5737 /* Disable the link interrupt by writing 1 to
5738 * the relevant lane in the status register
5741 ((params
->lane_config
&
5742 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
5743 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
5744 mask
= ((1 << ser_lane
) <<
5745 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE
);
5747 mask
= ELINK_NIG_STATUS_SERDES0_LINK_STATUS
;
5749 PMD_DRV_LOG(DEBUG
, "Ack link up interrupt with mask 0x%x",
5752 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
* 4, mask
);
5756 static uint8_t elink_format_ver(uint32_t num
, uint8_t * str
,
5759 uint8_t *str_ptr
= str
;
5760 uint32_t mask
= 0xf0000000;
5761 uint8_t shift
= 8 * 4;
5763 uint8_t remove_leading_zeros
= 1;
5765 /* Need more than 10chars for this format */
5768 return ELINK_STATUS_ERROR
;
5773 digit
= ((num
& mask
) >> shift
);
5774 if (digit
== 0 && remove_leading_zeros
) {
5777 } else if (digit
< 0xa)
5778 *str_ptr
= digit
+ '0';
5780 *str_ptr
= digit
- 0xa + 'a';
5781 remove_leading_zeros
= 0;
5785 if (shift
== 4 * 4) {
5789 remove_leading_zeros
= 1;
5792 return ELINK_STATUS_OK
;
5795 static uint8_t elink_null_format_ver(__rte_unused
uint32_t spirom_ver
,
5796 uint8_t * str
, uint16_t * len
)
5800 return ELINK_STATUS_OK
;
5803 static void elink_set_xgxs_loopback(struct elink_phy
*phy
,
5804 struct elink_params
*params
)
5806 uint8_t port
= params
->port
;
5807 struct bnx2x_softc
*sc
= params
->sc
;
5809 if (phy
->req_line_speed
!= ELINK_SPEED_1000
) {
5810 uint32_t md_devad
= 0;
5812 PMD_DRV_LOG(DEBUG
, "XGXS 10G loopback enable");
5814 if (!CHIP_IS_E3(sc
)) {
5815 /* Change the uni_phy_addr in the nig */
5816 md_devad
= REG_RD(sc
, (NIG_REG_XGXS0_CTRL_MD_DEVAD
+
5819 REG_WR(sc
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
* 0x18,
5823 elink_cl45_write(sc
, phy
,
5825 (MDIO_REG_BANK_AER_BLOCK
+
5826 (MDIO_AER_BLOCK_AER_REG
& 0xf)), 0x2800);
5828 elink_cl45_write(sc
, phy
,
5830 (MDIO_REG_BANK_CL73_IEEEB0
+
5831 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL
& 0xf)),
5834 /* Set aer mmd back */
5835 elink_set_aer_mmd(params
, phy
);
5837 if (!CHIP_IS_E3(sc
)) {
5839 REG_WR(sc
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
* 0x18,
5844 PMD_DRV_LOG(DEBUG
, "XGXS 1G loopback enable");
5845 elink_cl45_read(sc
, phy
, 5,
5846 (MDIO_REG_BANK_COMBO_IEEE0
+
5847 (MDIO_COMBO_IEEE0_MII_CONTROL
& 0xf)),
5849 elink_cl45_write(sc
, phy
, 5,
5850 (MDIO_REG_BANK_COMBO_IEEE0
+
5851 (MDIO_COMBO_IEEE0_MII_CONTROL
& 0xf)),
5853 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK
);
5857 elink_status_t
elink_set_led(struct elink_params
*params
,
5858 struct elink_vars
*vars
, uint8_t mode
,
5861 uint8_t port
= params
->port
;
5862 uint16_t hw_led_mode
= params
->hw_led_mode
;
5863 elink_status_t rc
= ELINK_STATUS_OK
;
5866 uint32_t emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
5867 struct bnx2x_softc
*sc
= params
->sc
;
5868 PMD_DRV_LOG(DEBUG
, "elink_set_led: port %x, mode %d", port
, mode
);
5869 PMD_DRV_LOG(DEBUG
, "speed 0x%x, hw_led_mode 0x%x", speed
, hw_led_mode
);
5871 for (phy_idx
= ELINK_EXT_PHY1
; phy_idx
< ELINK_MAX_PHYS
; phy_idx
++) {
5872 if (params
->phy
[phy_idx
].set_link_led
) {
5873 params
->phy
[phy_idx
].set_link_led(¶ms
->phy
[phy_idx
],
5879 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
5880 case ELINK_LED_MODE_OFF
:
5881 REG_WR(sc
, NIG_REG_LED_10G_P0
+ port
* 4, 0);
5882 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4,
5883 SHARED_HW_CFG_LED_MAC1
);
5885 tmp
= elink_cb_reg_read(sc
, emac_base
+ EMAC_REG_EMAC_LED
);
5886 if (params
->phy
[ELINK_EXT_PHY1
].type
==
5887 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
)
5888 tmp
&= ~(EMAC_LED_1000MB_OVERRIDE
|
5889 EMAC_LED_100MB_OVERRIDE
|
5890 EMAC_LED_10MB_OVERRIDE
);
5892 tmp
|= EMAC_LED_OVERRIDE
;
5894 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_LED
, tmp
);
5897 case ELINK_LED_MODE_OPER
:
5898 /* For all other phys, OPER mode is same as ON, so in case
5899 * link is down, do nothing
5904 case ELINK_LED_MODE_ON
:
5905 if (((params
->phy
[ELINK_EXT_PHY1
].type
==
5906 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
) ||
5907 (params
->phy
[ELINK_EXT_PHY1
].type
==
5908 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
)) &&
5909 CHIP_IS_E2(sc
) && params
->num_phys
== 2) {
5910 /* This is a work-around for E2+8727 Configurations */
5911 if (mode
== ELINK_LED_MODE_ON
||
5912 speed
== ELINK_SPEED_10000
) {
5913 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4, 0);
5914 REG_WR(sc
, NIG_REG_LED_10G_P0
+ port
* 4, 1);
5917 elink_cb_reg_read(sc
,
5920 elink_cb_reg_write(sc
,
5923 (tmp
| EMAC_LED_OVERRIDE
));
5924 /* Return here without enabling traffic
5925 * LED blink and setting rate in ON mode.
5926 * In oper mode, enabling LED blink
5927 * and setting rate is needed.
5929 if (mode
== ELINK_LED_MODE_ON
)
5932 } else if (ELINK_SINGLE_MEDIA_DIRECT(params
)) {
5933 /* This is a work-around for HW issue found when link
5936 if ((!CHIP_IS_E3(sc
)) ||
5937 (CHIP_IS_E3(sc
) && mode
== ELINK_LED_MODE_ON
))
5938 REG_WR(sc
, NIG_REG_LED_10G_P0
+ port
* 4, 1);
5940 if (CHIP_IS_E1x(sc
) ||
5941 CHIP_IS_E2(sc
) || (mode
== ELINK_LED_MODE_ON
))
5942 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4, 0);
5944 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4,
5946 } else if ((params
->phy
[ELINK_EXT_PHY1
].type
==
5947 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
) &&
5948 (mode
== ELINK_LED_MODE_ON
)) {
5949 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4, 0);
5951 elink_cb_reg_read(sc
,
5952 emac_base
+ EMAC_REG_EMAC_LED
);
5953 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_LED
,
5954 tmp
| EMAC_LED_OVERRIDE
|
5955 EMAC_LED_1000MB_OVERRIDE
);
5956 /* Break here; otherwise, it'll disable the
5957 * intended override.
5961 uint32_t nig_led_mode
= ((params
->hw_led_mode
<<
5962 SHARED_HW_CFG_LED_MODE_SHIFT
)
5964 SHARED_HW_CFG_LED_EXTPHY2
)
5965 ? (SHARED_HW_CFG_LED_PHY1
>>
5966 SHARED_HW_CFG_LED_MODE_SHIFT
) : hw_led_mode
;
5967 REG_WR(sc
, NIG_REG_LED_MODE_P0
+ port
* 4,
5971 REG_WR(sc
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+ port
* 4,
5973 /* Set blinking rate to ~15.9Hz */
5975 REG_WR(sc
, NIG_REG_LED_CONTROL_BLINK_RATE_P0
+ port
* 4,
5976 LED_BLINK_RATE_VAL_E3
);
5978 REG_WR(sc
, NIG_REG_LED_CONTROL_BLINK_RATE_P0
+ port
* 4,
5979 LED_BLINK_RATE_VAL_E1X_E2
);
5980 REG_WR(sc
, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0
+ port
* 4, 1);
5981 tmp
= elink_cb_reg_read(sc
, emac_base
+ EMAC_REG_EMAC_LED
);
5982 elink_cb_reg_write(sc
, emac_base
+ EMAC_REG_EMAC_LED
,
5983 (tmp
& (~EMAC_LED_OVERRIDE
)));
5988 rc
= ELINK_STATUS_ERROR
;
5989 PMD_DRV_LOG(DEBUG
, "elink_set_led: Invalid led mode %d", mode
);
5996 static elink_status_t
elink_link_initialize(struct elink_params
*params
,
5997 struct elink_vars
*vars
)
5999 elink_status_t rc
= ELINK_STATUS_OK
;
6000 uint8_t phy_index
, non_ext_phy
;
6001 struct bnx2x_softc
*sc
= params
->sc
;
6002 /* In case of external phy existence, the line speed would be the
6003 * line speed linked up by the external phy. In case it is direct
6004 * only, then the line_speed during initialization will be
6005 * equal to the req_line_speed
6007 vars
->line_speed
= params
->phy
[ELINK_INT_PHY
].req_line_speed
;
6009 /* Initialize the internal phy in case this is a direct board
6010 * (no external phys), or this board has external phy which requires
6013 if (!USES_WARPCORE(sc
))
6014 elink_prepare_xgxs(¶ms
->phy
[ELINK_INT_PHY
], params
, vars
);
6015 /* init ext phy and enable link state int */
6016 non_ext_phy
= (ELINK_SINGLE_MEDIA_DIRECT(params
) ||
6017 (params
->loopback_mode
== ELINK_LOOPBACK_XGXS
));
6020 (params
->phy
[ELINK_EXT_PHY1
].flags
& ELINK_FLAGS_INIT_XGXS_FIRST
) ||
6021 (params
->loopback_mode
== ELINK_LOOPBACK_EXT_PHY
)) {
6022 struct elink_phy
*phy
= ¶ms
->phy
[ELINK_INT_PHY
];
6023 if (vars
->line_speed
== ELINK_SPEED_AUTO_NEG
&&
6024 (CHIP_IS_E1x(sc
) || CHIP_IS_E2(sc
)))
6025 elink_set_parallel_detection(phy
, params
);
6026 if (params
->phy
[ELINK_INT_PHY
].config_init
)
6027 params
->phy
[ELINK_INT_PHY
].config_init(phy
,
6031 /* Re-read this value in case it was changed inside config_init due to
6032 * limitations of optic module
6034 vars
->line_speed
= params
->phy
[ELINK_INT_PHY
].req_line_speed
;
6036 /* Init external phy */
6038 if (params
->phy
[ELINK_INT_PHY
].supported
&
6039 ELINK_SUPPORTED_FIBRE
)
6040 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
6042 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< params
->num_phys
;
6044 /* No need to initialize second phy in case of first
6045 * phy only selection. In case of second phy, we do
6046 * need to initialize the first phy, since they are
6049 if (params
->phy
[phy_index
].supported
&
6050 ELINK_SUPPORTED_FIBRE
)
6051 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
6053 if (phy_index
== ELINK_EXT_PHY2
&&
6054 (elink_phy_selection(params
) ==
6055 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
)) {
6057 "Not initializing second phy");
6060 params
->phy
[phy_index
].config_init(¶ms
->
6065 /* Reset the interrupt indication after phy was initialized */
6066 elink_bits_dis(sc
, NIG_REG_STATUS_INTERRUPT_PORT0
+
6068 (ELINK_NIG_STATUS_XGXS0_LINK10G
|
6069 ELINK_NIG_STATUS_XGXS0_LINK_STATUS
|
6070 ELINK_NIG_STATUS_SERDES0_LINK_STATUS
|
6071 ELINK_NIG_MASK_MI_INT
));
6075 static void elink_int_link_reset(__rte_unused
struct elink_phy
*phy
,
6076 struct elink_params
*params
)
6078 /* Reset the SerDes/XGXS */
6079 REG_WR(params
->sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
,
6080 (0x1ff << (params
->port
* 16)));
6083 static void elink_common_ext_link_reset(__rte_unused
struct elink_phy
*phy
,
6084 struct elink_params
*params
)
6086 struct bnx2x_softc
*sc
= params
->sc
;
6090 gpio_port
= SC_PATH(sc
);
6092 gpio_port
= params
->port
;
6093 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
6094 MISC_REGISTERS_GPIO_OUTPUT_LOW
, gpio_port
);
6095 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
6096 MISC_REGISTERS_GPIO_OUTPUT_LOW
, gpio_port
);
6097 PMD_DRV_LOG(DEBUG
, "reset external PHY");
6100 static elink_status_t
elink_update_link_down(struct elink_params
*params
,
6101 struct elink_vars
*vars
)
6103 struct bnx2x_softc
*sc
= params
->sc
;
6104 uint8_t port
= params
->port
;
6106 PMD_DRV_LOG(DEBUG
, "Port %x: Link is down", port
);
6107 elink_set_led(params
, vars
, ELINK_LED_MODE_OFF
, 0);
6108 vars
->phy_flags
&= ~PHY_PHYSICAL_LINK_FLAG
;
6109 /* Indicate no mac active */
6110 vars
->mac_type
= ELINK_MAC_TYPE_NONE
;
6112 /* Update shared memory */
6113 vars
->link_status
&= ~ELINK_LINK_UPDATE_MASK
;
6114 vars
->line_speed
= 0;
6115 elink_update_mng(params
, vars
->link_status
);
6117 /* Activate nig drain */
6118 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
* 4, 1);
6121 if (!CHIP_IS_E3(sc
))
6122 REG_WR(sc
, NIG_REG_NIG_EMAC0_EN
+ port
* 4, 0);
6125 /* Reset BigMac/Xmac */
6126 if (CHIP_IS_E1x(sc
) || CHIP_IS_E2(sc
))
6127 elink_set_bmac_rx(sc
, params
->port
, 0);
6129 if (CHIP_IS_E3(sc
)) {
6130 /* Prevent LPI Generation by chip */
6131 REG_WR(sc
, MISC_REG_CPMU_LP_FW_ENABLE_P0
+ (params
->port
<< 2),
6133 REG_WR(sc
, MISC_REG_CPMU_LP_MASK_ENT_P0
+ (params
->port
<< 2),
6135 vars
->eee_status
&= ~(SHMEM_EEE_LP_ADV_STATUS_MASK
|
6136 SHMEM_EEE_ACTIVE_BIT
);
6138 elink_update_mng_eee(params
, vars
->eee_status
);
6139 elink_set_xmac_rxtx(params
, 0);
6140 elink_set_umac_rxtx(params
, 0);
6143 return ELINK_STATUS_OK
;
6146 static elink_status_t
elink_update_link_up(struct elink_params
*params
,
6147 struct elink_vars
*vars
,
6150 struct bnx2x_softc
*sc
= params
->sc
;
6151 uint8_t phy_idx
, port
= params
->port
;
6152 elink_status_t rc
= ELINK_STATUS_OK
;
6154 vars
->link_status
|= (LINK_STATUS_LINK_UP
|
6155 LINK_STATUS_PHYSICAL_LINK_FLAG
);
6156 vars
->phy_flags
|= PHY_PHYSICAL_LINK_FLAG
;
6158 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_TX
)
6159 vars
->link_status
|= LINK_STATUS_TX_FLOW_CONTROL_ENABLED
;
6161 if (vars
->flow_ctrl
& ELINK_FLOW_CTRL_RX
)
6162 vars
->link_status
|= LINK_STATUS_RX_FLOW_CONTROL_ENABLED
;
6163 if (USES_WARPCORE(sc
)) {
6165 if (elink_xmac_enable(params
, vars
, 0) ==
6166 ELINK_STATUS_NO_LINK
) {
6167 PMD_DRV_LOG(DEBUG
, "Found errors on XMAC");
6169 vars
->phy_flags
|= PHY_HALF_OPEN_CONN_FLAG
;
6170 vars
->link_status
&= ~LINK_STATUS_LINK_UP
;
6173 elink_umac_enable(params
, vars
, 0);
6174 elink_set_led(params
, vars
,
6175 ELINK_LED_MODE_OPER
, vars
->line_speed
);
6177 if ((vars
->eee_status
& SHMEM_EEE_ACTIVE_BIT
) &&
6178 (vars
->eee_status
& SHMEM_EEE_LPI_REQUESTED_BIT
)) {
6179 PMD_DRV_LOG(DEBUG
, "Enabling LPI assertion");
6180 REG_WR(sc
, MISC_REG_CPMU_LP_FW_ENABLE_P0
+
6181 (params
->port
<< 2), 1);
6182 REG_WR(sc
, MISC_REG_CPMU_LP_DR_ENABLE
, 1);
6183 REG_WR(sc
, MISC_REG_CPMU_LP_MASK_ENT_P0
+
6184 (params
->port
<< 2), 0xfc20);
6187 if ((CHIP_IS_E1x(sc
) || CHIP_IS_E2(sc
))) {
6189 if (elink_bmac_enable(params
, vars
, 0, 1) ==
6190 ELINK_STATUS_NO_LINK
) {
6191 PMD_DRV_LOG(DEBUG
, "Found errors on BMAC");
6193 vars
->phy_flags
|= PHY_HALF_OPEN_CONN_FLAG
;
6194 vars
->link_status
&= ~LINK_STATUS_LINK_UP
;
6197 elink_set_led(params
, vars
,
6198 ELINK_LED_MODE_OPER
, ELINK_SPEED_10000
);
6200 rc
= elink_emac_program(params
, vars
);
6201 elink_emac_enable(params
, vars
, 0);
6204 if ((vars
->link_status
&
6205 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
)
6206 && (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) &&
6207 ELINK_SINGLE_MEDIA_DIRECT(params
))
6208 elink_set_gmii_tx_driver(params
);
6213 if (CHIP_IS_E1x(sc
))
6214 rc
|= elink_pbf_update(params
, vars
->flow_ctrl
,
6218 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
* 4, 0);
6220 /* Update shared memory */
6221 elink_update_mng(params
, vars
->link_status
);
6222 elink_update_mng_eee(params
, vars
->eee_status
);
6223 /* Check remote fault */
6224 for (phy_idx
= ELINK_INT_PHY
; phy_idx
< ELINK_MAX_PHYS
; phy_idx
++) {
6225 if (params
->phy
[phy_idx
].flags
& ELINK_FLAGS_TX_ERROR_CHECK
) {
6226 elink_check_half_open_conn(params
, vars
, 0);
6234 /* The elink_link_update function should be called upon link
6236 * Link is considered up as follows:
6237 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6239 * - SINGLE_MEDIA - The link between the 577xx and the external
6240 * phy (XGXS) need to up as well as the external link of the
6242 * - DUAL_MEDIA - The link between the 577xx and the first
6243 * external phy needs to be up, and at least one of the 2
6244 * external phy link must be up.
6246 elink_status_t
elink_link_update(struct elink_params
* params
,
6247 struct elink_vars
* vars
)
6249 struct bnx2x_softc
*sc
= params
->sc
;
6250 struct elink_vars phy_vars
[ELINK_MAX_PHYS
];
6251 uint8_t port
= params
->port
;
6252 uint8_t link_10g_plus
, phy_index
;
6253 uint8_t ext_phy_link_up
= 0, cur_link_up
;
6254 elink_status_t rc
= ELINK_STATUS_OK
;
6255 __rte_unused
uint8_t is_mi_int
= 0;
6256 uint16_t ext_phy_line_speed
= 0, prev_line_speed
= vars
->line_speed
;
6257 uint8_t active_external_phy
= ELINK_INT_PHY
;
6258 vars
->phy_flags
&= ~PHY_HALF_OPEN_CONN_FLAG
;
6259 vars
->link_status
&= ~ELINK_LINK_UPDATE_MASK
;
6260 for (phy_index
= ELINK_INT_PHY
; phy_index
< params
->num_phys
;
6262 phy_vars
[phy_index
].flow_ctrl
= 0;
6263 phy_vars
[phy_index
].link_status
= ETH_LINK_DOWN
;
6264 phy_vars
[phy_index
].line_speed
= 0;
6265 phy_vars
[phy_index
].duplex
= DUPLEX_FULL
;
6266 phy_vars
[phy_index
].phy_link_up
= 0;
6267 phy_vars
[phy_index
].link_up
= 0;
6268 phy_vars
[phy_index
].fault_detected
= 0;
6269 /* different consideration, since vars holds inner state */
6270 phy_vars
[phy_index
].eee_status
= vars
->eee_status
;
6273 if (USES_WARPCORE(sc
))
6274 elink_set_aer_mmd(params
, ¶ms
->phy
[ELINK_INT_PHY
]);
6276 PMD_DRV_LOG(DEBUG
, "port %x, XGXS?%x, int_status 0x%x",
6277 port
, (vars
->phy_flags
& PHY_XGXS_FLAG
),
6278 REG_RD(sc
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
* 4));
6280 is_mi_int
= (uint8_t) (REG_RD(sc
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+
6282 PMD_DRV_LOG(DEBUG
, "int_mask 0x%x MI_INT %x, SERDES_LINK %x",
6283 REG_RD(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
* 4),
6286 NIG_REG_SERDES0_STATUS_LINK_STATUS
+ port
* 0x3c));
6288 PMD_DRV_LOG(DEBUG
, " 10G %x, XGXS_LINK %x",
6289 REG_RD(sc
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
* 0x68),
6290 REG_RD(sc
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
* 0x68));
6293 if (!CHIP_IS_E3(sc
))
6294 REG_WR(sc
, NIG_REG_NIG_EMAC0_EN
+ port
* 4, 0);
6297 * Check external link change only for external phys, and apply
6298 * priority selection between them in case the link on both phys
6299 * is up. Note that instead of the common vars, a temporary
6300 * vars argument is used since each phy may have different link/
6301 * speed/duplex result
6303 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< params
->num_phys
;
6305 struct elink_phy
*phy
= ¶ms
->phy
[phy_index
];
6306 if (!phy
->read_status
)
6308 /* Read link status and params of this ext phy */
6309 cur_link_up
= phy
->read_status(phy
, params
,
6310 &phy_vars
[phy_index
]);
6312 PMD_DRV_LOG(DEBUG
, "phy in index %d link is up",
6315 PMD_DRV_LOG(DEBUG
, "phy in index %d link is down",
6320 if (!ext_phy_link_up
) {
6321 ext_phy_link_up
= 1;
6322 active_external_phy
= phy_index
;
6324 switch (elink_phy_selection(params
)) {
6325 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
:
6326 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
:
6327 /* In this option, the first PHY makes sure to pass the
6328 * traffic through itself only.
6329 * Its not clear how to reset the link on the second phy
6331 active_external_phy
= ELINK_EXT_PHY1
;
6333 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
:
6334 /* In this option, the first PHY makes sure to pass the
6335 * traffic through the second PHY.
6337 active_external_phy
= ELINK_EXT_PHY2
;
6340 /* Link indication on both PHYs with the following cases
6342 * - FIRST_PHY means that second phy wasn't initialized,
6343 * hence its link is expected to be down
6344 * - SECOND_PHY means that first phy should not be able
6345 * to link up by itself (using configuration)
6346 * - DEFAULT should be overridden during initialization
6348 PMD_DRV_LOG(DEBUG
, "Invalid link indication"
6349 "mpc=0x%x. DISABLING LINK !!!",
6350 params
->multi_phy_config
);
6351 ext_phy_link_up
= 0;
6356 prev_line_speed
= vars
->line_speed
;
6358 * Read the status of the internal phy. In case of
6359 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6360 * otherwise this is the link between the 577xx and the first
6363 if (params
->phy
[ELINK_INT_PHY
].read_status
)
6364 params
->phy
[ELINK_INT_PHY
].read_status(¶ms
->
6367 /* The INT_PHY flow control reside in the vars. This include the
6368 * case where the speed or flow control are not set to AUTO.
6369 * Otherwise, the active external phy flow control result is set
6370 * to the vars. The ext_phy_line_speed is needed to check if the
6371 * speed is different between the internal phy and external phy.
6372 * This case may be result of intermediate link speed change.
6374 if (active_external_phy
> ELINK_INT_PHY
) {
6375 vars
->flow_ctrl
= phy_vars
[active_external_phy
].flow_ctrl
;
6376 /* Link speed is taken from the XGXS. AN and FC result from
6379 vars
->link_status
|= phy_vars
[active_external_phy
].link_status
;
6381 /* if active_external_phy is first PHY and link is up - disable
6382 * disable TX on second external PHY
6384 if (active_external_phy
== ELINK_EXT_PHY1
) {
6385 if (params
->phy
[ELINK_EXT_PHY2
].phy_specific_func
) {
6386 PMD_DRV_LOG(DEBUG
, "Disabling TX on EXT_PHY2");
6387 params
->phy
[ELINK_EXT_PHY2
].
6388 phy_specific_func(¶ms
->
6389 phy
[ELINK_EXT_PHY2
],
6390 params
, ELINK_DISABLE_TX
);
6394 ext_phy_line_speed
= phy_vars
[active_external_phy
].line_speed
;
6395 vars
->duplex
= phy_vars
[active_external_phy
].duplex
;
6396 if (params
->phy
[active_external_phy
].supported
&
6397 ELINK_SUPPORTED_FIBRE
)
6398 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
6400 vars
->link_status
&= ~LINK_STATUS_SERDES_LINK
;
6402 vars
->eee_status
= phy_vars
[active_external_phy
].eee_status
;
6404 PMD_DRV_LOG(DEBUG
, "Active external phy selected: %x",
6405 active_external_phy
);
6408 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< params
->num_phys
;
6410 if (params
->phy
[phy_index
].flags
&
6411 ELINK_FLAGS_REARM_LATCH_SIGNAL
) {
6412 elink_rearm_latch_signal(sc
, port
,
6414 active_external_phy
);
6418 PMD_DRV_LOG(DEBUG
, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6419 " ext_phy_line_speed = %d", vars
->flow_ctrl
,
6420 vars
->link_status
, ext_phy_line_speed
);
6421 /* Upon link speed change set the NIG into drain mode. Comes to
6422 * deals with possible FIFO glitch due to clk change when speed
6423 * is decreased without link down indicator
6426 if (vars
->phy_link_up
) {
6427 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
)) && ext_phy_link_up
&&
6428 (ext_phy_line_speed
!= vars
->line_speed
)) {
6429 PMD_DRV_LOG(DEBUG
, "Internal link speed %d is"
6430 " different than the external"
6431 " link speed %d", vars
->line_speed
,
6432 ext_phy_line_speed
);
6433 vars
->phy_link_up
= 0;
6434 } else if (prev_line_speed
!= vars
->line_speed
) {
6436 NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4,
6442 /* Anything 10 and over uses the bmac */
6443 link_10g_plus
= (vars
->line_speed
>= ELINK_SPEED_10000
);
6445 elink_link_int_ack(params
, vars
, link_10g_plus
);
6447 /* In case external phy link is up, and internal link is down
6448 * (not initialized yet probably after link initialization, it
6449 * needs to be initialized.
6450 * Note that after link down-up as result of cable plug, the xgxs
6451 * link would probably become up again without the need
6454 if (!(ELINK_SINGLE_MEDIA_DIRECT(params
))) {
6455 PMD_DRV_LOG(DEBUG
, "ext_phy_link_up = %d, int_link_up = %d,"
6456 " init_preceding = %d", ext_phy_link_up
,
6458 params
->phy
[ELINK_EXT_PHY1
].flags
&
6459 ELINK_FLAGS_INIT_XGXS_FIRST
);
6460 if (!(params
->phy
[ELINK_EXT_PHY1
].flags
&
6461 ELINK_FLAGS_INIT_XGXS_FIRST
)
6462 && ext_phy_link_up
&& !vars
->phy_link_up
) {
6463 vars
->line_speed
= ext_phy_line_speed
;
6464 if (vars
->line_speed
< ELINK_SPEED_1000
)
6465 vars
->phy_flags
|= PHY_SGMII_FLAG
;
6467 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
6469 if (params
->phy
[ELINK_INT_PHY
].config_init
)
6470 params
->phy
[ELINK_INT_PHY
].config_init(¶ms
->
6477 /* Link is up only if both local phy and external phy (in case of
6478 * non-direct board) are up and no fault detected on active PHY.
6480 vars
->link_up
= (vars
->phy_link_up
&&
6482 ELINK_SINGLE_MEDIA_DIRECT(params
)) &&
6483 (phy_vars
[active_external_phy
].fault_detected
== 0));
6485 /* Update the PFC configuration in case it was changed */
6486 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
6487 vars
->link_status
|= LINK_STATUS_PFC_ENABLED
;
6489 vars
->link_status
&= ~LINK_STATUS_PFC_ENABLED
;
6492 rc
= elink_update_link_up(params
, vars
, link_10g_plus
);
6494 rc
= elink_update_link_down(params
, vars
);
6496 /* Update MCP link status was changed */
6498 feature_config_flags
& ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX
)
6499 elink_cb_fw_command(sc
, DRV_MSG_CODE_LINK_STATUS_CHANGED
, 0);
6504 /*****************************************************************************/
6505 /* External Phy section */
6506 /*****************************************************************************/
6507 static void elink_ext_phy_hw_reset(struct bnx2x_softc
*sc
, uint8_t port
)
6509 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
6510 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
6512 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
6513 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
6516 static void elink_save_spirom_version(struct bnx2x_softc
*sc
,
6517 __rte_unused
uint8_t port
,
6518 uint32_t spirom_ver
, uint32_t ver_addr
)
6520 PMD_DRV_LOG(DEBUG
, "FW version 0x%x:0x%x for port %d",
6521 (uint16_t) (spirom_ver
>> 16), (uint16_t) spirom_ver
, port
);
6524 REG_WR(sc
, ver_addr
, spirom_ver
);
6527 static void elink_save_bnx2x_spirom_ver(struct bnx2x_softc
*sc
,
6528 struct elink_phy
*phy
, uint8_t port
)
6530 uint16_t fw_ver1
, fw_ver2
;
6532 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
6533 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
6534 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
6535 MDIO_PMA_REG_ROM_VER2
, &fw_ver2
);
6536 elink_save_spirom_version(sc
, port
,
6537 (uint32_t) (fw_ver1
<< 16 | fw_ver2
),
6541 static void elink_ext_phy_10G_an_resolve(struct bnx2x_softc
*sc
,
6542 struct elink_phy
*phy
,
6543 struct elink_vars
*vars
)
6546 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_STATUS
, &val
);
6547 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_STATUS
, &val
);
6549 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
6550 if ((val
& (1 << 0)) == 0)
6551 vars
->link_status
|= LINK_STATUS_PARALLEL_DETECTION_USED
;
6554 /******************************************************************/
6555 /* common BNX2X8073/BNX2X8727 PHY SECTION */
6556 /******************************************************************/
6557 static void elink_8073_resolve_fc(struct elink_phy
*phy
,
6558 struct elink_params
*params
,
6559 struct elink_vars
*vars
)
6561 struct bnx2x_softc
*sc
= params
->sc
;
6562 if (phy
->req_line_speed
== ELINK_SPEED_10
||
6563 phy
->req_line_speed
== ELINK_SPEED_100
) {
6564 vars
->flow_ctrl
= phy
->req_flow_ctrl
;
6568 if (elink_ext_phy_resolve_fc(phy
, params
, vars
) &&
6569 (vars
->flow_ctrl
== ELINK_FLOW_CTRL_NONE
)) {
6570 uint16_t pause_result
;
6571 uint16_t ld_pause
; /* local */
6572 uint16_t lp_pause
; /* link partner */
6573 elink_cl45_read(sc
, phy
,
6575 MDIO_AN_REG_CL37_FC_LD
, &ld_pause
);
6577 elink_cl45_read(sc
, phy
,
6579 MDIO_AN_REG_CL37_FC_LP
, &lp_pause
);
6580 pause_result
= (ld_pause
&
6581 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 5;
6582 pause_result
|= (lp_pause
&
6583 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 7;
6585 elink_pause_resolve(vars
, pause_result
);
6586 PMD_DRV_LOG(DEBUG
, "Ext PHY CL37 pause result 0x%x",
6591 static elink_status_t
elink_8073_8727_external_rom_boot(struct bnx2x_softc
*sc
,
6592 struct elink_phy
*phy
,
6596 uint16_t fw_ver1
= 0, fw_msgout
;
6597 elink_status_t rc
= ELINK_STATUS_OK
;
6599 /* Boot port from external ROM */
6601 elink_cl45_write(sc
, phy
,
6602 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x0001);
6604 /* Ucode reboot and rst */
6605 elink_cl45_write(sc
, phy
,
6606 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x008c);
6608 elink_cl45_write(sc
, phy
,
6609 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
6611 /* Reset internal microprocessor */
6612 elink_cl45_write(sc
, phy
,
6614 MDIO_PMA_REG_GEN_CTRL
,
6615 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
6617 /* Release srst bit */
6618 elink_cl45_write(sc
, phy
,
6620 MDIO_PMA_REG_GEN_CTRL
,
6621 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
6623 /* Delay 100ms per the PHY specifications */
6626 /* 8073 sometimes taking longer to download */
6631 "elink_8073_8727_external_rom_boot port %x:"
6632 "Download failed. fw version = 0x%x",
6634 rc
= ELINK_STATUS_ERROR
;
6638 elink_cl45_read(sc
, phy
,
6640 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
6641 elink_cl45_read(sc
, phy
,
6643 MDIO_PMA_REG_M8051_MSGOUT_REG
, &fw_msgout
);
6646 } while (fw_ver1
== 0 || fw_ver1
== 0x4321 ||
6647 ((fw_msgout
& 0xff) != 0x03 && (phy
->type
==
6648 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073
)));
6650 /* Clear ser_boot_ctl bit */
6651 elink_cl45_write(sc
, phy
,
6652 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
6653 elink_save_bnx2x_spirom_ver(sc
, phy
, port
);
6656 "elink_8073_8727_external_rom_boot port %x:"
6657 "Download complete. fw version = 0x%x", port
, fw_ver1
);
6662 /******************************************************************/
6663 /* BNX2X8073 PHY SECTION */
6664 /******************************************************************/
6665 static elink_status_t
elink_8073_is_snr_needed(struct bnx2x_softc
*sc
,
6666 struct elink_phy
*phy
)
6668 /* This is only required for 8073A1, version 102 only */
6671 /* Read 8073 HW revision */
6672 elink_cl45_read(sc
, phy
,
6673 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_CHIP_REV
, &val
);
6676 /* No need to workaround in 8073 A1 */
6677 return ELINK_STATUS_OK
;
6680 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_ROM_VER2
, &val
);
6682 /* SNR should be applied only for version 0x102 */
6684 return ELINK_STATUS_OK
;
6686 return ELINK_STATUS_ERROR
;
6689 static elink_status_t
elink_8073_xaui_wa(struct bnx2x_softc
*sc
,
6690 struct elink_phy
*phy
)
6692 uint16_t val
, cnt
, cnt1
;
6694 elink_cl45_read(sc
, phy
,
6695 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_CHIP_REV
, &val
);
6698 /* No need to workaround in 8073 A1 */
6699 return ELINK_STATUS_OK
;
6701 /* XAUI workaround in 8073 A0: */
6703 /* After loading the boot ROM and restarting Autoneg, poll
6707 for (cnt
= 0; cnt
< 1000; cnt
++) {
6708 elink_cl45_read(sc
, phy
,
6710 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
, &val
);
6711 /* If bit [14] = 0 or bit [13] = 0, continue on with
6712 * system initialization (XAUI work-around not required, as
6713 * these bits indicate 2.5G or 1G link up).
6715 if (!(val
& (1 << 14)) || !(val
& (1 << 13))) {
6716 PMD_DRV_LOG(DEBUG
, "XAUI work-around not required");
6717 return ELINK_STATUS_OK
;
6718 } else if (!(val
& (1 << 15))) {
6719 PMD_DRV_LOG(DEBUG
, "bit 15 went off");
6720 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6721 * MSB (bit15) goes to 1 (indicating that the XAUI
6722 * workaround has completed), then continue on with
6723 * system initialization.
6725 for (cnt1
= 0; cnt1
< 1000; cnt1
++) {
6726 elink_cl45_read(sc
, phy
,
6728 MDIO_PMA_REG_8073_XAUI_WA
,
6730 if (val
& (1 << 15)) {
6732 "XAUI workaround has completed");
6733 return ELINK_STATUS_OK
;
6741 PMD_DRV_LOG(DEBUG
, "Warning: XAUI work-around timeout !!!");
6742 return ELINK_STATUS_ERROR
;
6745 static void elink_807x_force_10G(struct bnx2x_softc
*sc
, struct elink_phy
*phy
)
6747 /* Force KR or KX */
6748 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x2040);
6749 elink_cl45_write(sc
, phy
,
6750 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, 0x000b);
6751 elink_cl45_write(sc
, phy
,
6752 MDIO_PMA_DEVAD
, MDIO_PMA_REG_BNX2X_CTRL
, 0x0000);
6753 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x0000);
6756 static void elink_8073_set_pause_cl37(struct elink_params
*params
,
6757 struct elink_phy
*phy
,
6758 struct elink_vars
*vars
)
6761 struct bnx2x_softc
*sc
= params
->sc
;
6762 elink_cl45_read(sc
, phy
,
6763 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, &cl37_val
);
6765 cl37_val
&= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
6766 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6767 elink_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
6768 if ((vars
->ieee_fc
&
6769 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) ==
6770 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) {
6771 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
;
6773 if ((vars
->ieee_fc
&
6774 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
6775 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
6776 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
6778 if ((vars
->ieee_fc
&
6779 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
6780 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
6781 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
6783 PMD_DRV_LOG(DEBUG
, "Ext phy AN advertize cl37 0x%x", cl37_val
);
6785 elink_cl45_write(sc
, phy
,
6786 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, cl37_val
);
6790 static void elink_8073_specific_func(struct elink_phy
*phy
,
6791 struct elink_params
*params
,
6794 struct bnx2x_softc
*sc
= params
->sc
;
6796 case ELINK_PHY_INIT
:
6798 elink_cl45_write(sc
, phy
,
6799 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
6801 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
,
6807 static uint8_t elink_8073_config_init(struct elink_phy
*phy
,
6808 struct elink_params
*params
,
6809 struct elink_vars
*vars
)
6811 struct bnx2x_softc
*sc
= params
->sc
;
6812 uint16_t val
= 0, tmp1
;
6814 PMD_DRV_LOG(DEBUG
, "Init 8073");
6817 gpio_port
= SC_PATH(sc
);
6819 gpio_port
= params
->port
;
6820 /* Restore normal power mode */
6821 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
6822 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, gpio_port
);
6824 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
6825 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, gpio_port
);
6827 elink_8073_specific_func(phy
, params
, ELINK_PHY_INIT
);
6828 elink_8073_set_pause_cl37(params
, phy
, vars
);
6830 elink_cl45_read(sc
, phy
,
6831 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &tmp1
);
6833 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &tmp1
);
6835 PMD_DRV_LOG(DEBUG
, "Before rom RX_ALARM(port1): 0x%x", tmp1
);
6837 /* Swap polarity if required - Must be done only in non-1G mode */
6838 if (params
->lane_config
& PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED
) {
6839 /* Configure the 8073 to swap _P and _N of the KR lines */
6840 PMD_DRV_LOG(DEBUG
, "Swapping polarity for the 8073");
6841 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6842 elink_cl45_read(sc
, phy
,
6844 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL
, &val
);
6845 elink_cl45_write(sc
, phy
,
6847 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL
,
6851 /* Enable CL37 BAM */
6852 if (REG_RD(sc
, params
->shmem_base
+
6853 offsetof(struct shmem_region
,
6854 dev_info
.port_hw_config
[params
->port
].
6856 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED
) {
6858 elink_cl45_read(sc
, phy
,
6859 MDIO_AN_DEVAD
, MDIO_AN_REG_8073_BAM
, &val
);
6860 elink_cl45_write(sc
, phy
,
6861 MDIO_AN_DEVAD
, MDIO_AN_REG_8073_BAM
, val
| 1);
6862 PMD_DRV_LOG(DEBUG
, "Enable CL37 BAM on KR");
6864 if (params
->loopback_mode
== ELINK_LOOPBACK_EXT
) {
6865 elink_807x_force_10G(sc
, phy
);
6866 PMD_DRV_LOG(DEBUG
, "Forced speed 10G on 807X");
6867 return ELINK_STATUS_OK
;
6869 elink_cl45_write(sc
, phy
,
6870 MDIO_PMA_DEVAD
, MDIO_PMA_REG_BNX2X_CTRL
, 0x0002);
6872 if (phy
->req_line_speed
!= ELINK_SPEED_AUTO_NEG
) {
6873 if (phy
->req_line_speed
== ELINK_SPEED_10000
) {
6875 } else if (phy
->req_line_speed
== ELINK_SPEED_2500
) {
6877 /* Note that 2.5G works only when used with 1G
6884 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
6887 /* Note that 2.5G works only when used with 1G advertisement */
6888 if (phy
->speed_cap_mask
&
6889 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
|
6890 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
6892 PMD_DRV_LOG(DEBUG
, "807x autoneg val = 0x%x", val
);
6895 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV
, val
);
6896 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_8073_2_5G
, &tmp1
);
6898 if (((phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
) &&
6899 (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
)) ||
6900 (phy
->req_line_speed
== ELINK_SPEED_2500
)) {
6902 /* Allow 2.5G for A1 and above */
6903 elink_cl45_read(sc
, phy
,
6904 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_CHIP_REV
,
6906 PMD_DRV_LOG(DEBUG
, "Add 2.5G");
6912 PMD_DRV_LOG(DEBUG
, "Disable 2.5G");
6916 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_8073_2_5G
, tmp1
);
6917 /* Add support for CL37 (passive mode) II */
6919 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, &tmp1
);
6920 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
,
6921 (tmp1
| ((phy
->req_duplex
== DUPLEX_FULL
) ?
6924 /* Add support for CL37 (passive mode) III */
6925 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1000);
6927 /* The SNR will improve about 2db by changing BW and FEE main
6928 * tap. Rest commands are executed after link is up
6929 * Change FFE main cursor to 5 in EDC register
6931 if (elink_8073_is_snr_needed(sc
, phy
))
6932 elink_cl45_write(sc
, phy
,
6933 MDIO_PMA_DEVAD
, MDIO_PMA_REG_EDC_FFE_MAIN
,
6936 /* Enable FEC (Forware Error Correction) Request in the AN */
6937 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV2
, &tmp1
);
6939 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV2
, tmp1
);
6941 elink_ext_phy_set_pause(params
, phy
, vars
);
6943 /* Restart autoneg */
6945 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x1200);
6946 PMD_DRV_LOG(DEBUG
, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x",
6947 ((val
& (1 << 5)) > 0), ((val
& (1 << 7)) > 0));
6948 return ELINK_STATUS_OK
;
6951 static uint8_t elink_8073_read_status(struct elink_phy
*phy
,
6952 struct elink_params
*params
,
6953 struct elink_vars
*vars
)
6955 struct bnx2x_softc
*sc
= params
->sc
;
6956 uint8_t link_up
= 0;
6957 uint16_t val1
, val2
;
6958 uint16_t link_status
= 0;
6959 uint16_t an1000_status
= 0;
6961 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
6963 PMD_DRV_LOG(DEBUG
, "8703 LASI status 0x%x", val1
);
6965 /* Clear the interrupt LASI status register */
6966 elink_cl45_read(sc
, phy
, MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &val2
);
6967 elink_cl45_read(sc
, phy
, MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &val1
);
6968 PMD_DRV_LOG(DEBUG
, "807x PCS status 0x%x->0x%x", val2
, val1
);
6970 elink_cl45_read(sc
, phy
,
6971 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &val1
);
6973 /* Check the LASI */
6974 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &val2
);
6976 PMD_DRV_LOG(DEBUG
, "KR 0x9003 0x%x", val2
);
6978 /* Check the link status */
6979 elink_cl45_read(sc
, phy
, MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &val2
);
6980 PMD_DRV_LOG(DEBUG
, "KR PCS status 0x%x", val2
);
6982 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val2
);
6983 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val1
);
6984 link_up
= ((val1
& 4) == 4);
6985 PMD_DRV_LOG(DEBUG
, "PMA_REG_STATUS=0x%x", val1
);
6987 if (link_up
&& ((phy
->req_line_speed
!= ELINK_SPEED_10000
))) {
6988 if (elink_8073_xaui_wa(sc
, phy
) != 0)
6991 elink_cl45_read(sc
, phy
,
6992 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &an1000_status
);
6993 elink_cl45_read(sc
, phy
,
6994 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &an1000_status
);
6996 /* Check the link status on 1.1.2 */
6997 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val2
);
6998 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val1
);
6999 PMD_DRV_LOG(DEBUG
, "KR PMA status 0x%x->0x%x,"
7000 "an_link_status=0x%x", val2
, val1
, an1000_status
);
7002 link_up
= (((val1
& 4) == 4) || (an1000_status
& (1 << 1)));
7003 if (link_up
&& elink_8073_is_snr_needed(sc
, phy
)) {
7004 /* The SNR will improve about 2dbby changing the BW and FEE main
7005 * tap. The 1st write to change FFE main tap is set before
7006 * restart AN. Change PLL Bandwidth in EDC register
7008 elink_cl45_write(sc
, phy
,
7009 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PLL_BANDWIDTH
,
7012 /* Change CDR Bandwidth in EDC register */
7013 elink_cl45_write(sc
, phy
,
7014 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CDR_BANDWIDTH
,
7017 elink_cl45_read(sc
, phy
,
7018 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
7021 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7022 if ((link_status
& (1 << 2)) && (!(link_status
& (1 << 15)))) {
7024 vars
->line_speed
= ELINK_SPEED_10000
;
7025 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 10G",
7027 } else if ((link_status
& (1 << 1)) && (!(link_status
& (1 << 14)))) {
7029 vars
->line_speed
= ELINK_SPEED_2500
;
7030 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 2.5G",
7032 } else if ((link_status
& (1 << 0)) && (!(link_status
& (1 << 13)))) {
7034 vars
->line_speed
= ELINK_SPEED_1000
;
7035 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 1G",
7039 PMD_DRV_LOG(DEBUG
, "port %x: External link is down",
7044 /* Swap polarity if required */
7045 if (params
->lane_config
& PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED
) {
7046 /* Configure the 8073 to swap P and N of the KR lines */
7047 elink_cl45_read(sc
, phy
,
7049 MDIO_XS_REG_8073_RX_CTRL_PCIE
, &val1
);
7050 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7051 * when it`s in 10G mode.
7053 if (vars
->line_speed
== ELINK_SPEED_1000
) {
7054 PMD_DRV_LOG(DEBUG
, "Swapping 1G polarity for"
7060 elink_cl45_write(sc
, phy
,
7062 MDIO_XS_REG_8073_RX_CTRL_PCIE
, val1
);
7064 elink_ext_phy_10G_an_resolve(sc
, phy
, vars
);
7065 elink_8073_resolve_fc(phy
, params
, vars
);
7066 vars
->duplex
= DUPLEX_FULL
;
7069 if (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
7070 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
7071 MDIO_AN_REG_LP_AUTO_NEG2
, &val1
);
7073 if (val1
& (1 << 5))
7074 vars
->link_status
|=
7075 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
7076 if (val1
& (1 << 7))
7077 vars
->link_status
|=
7078 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
7084 static void elink_8073_link_reset(__rte_unused
struct elink_phy
*phy
,
7085 struct elink_params
*params
)
7087 struct bnx2x_softc
*sc
= params
->sc
;
7090 gpio_port
= SC_PATH(sc
);
7092 gpio_port
= params
->port
;
7093 PMD_DRV_LOG(DEBUG
, "Setting 8073 port %d into low power mode",
7095 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
7096 MISC_REGISTERS_GPIO_OUTPUT_LOW
, gpio_port
);
7099 /******************************************************************/
7100 /* BNX2X8705 PHY SECTION */
7101 /******************************************************************/
7102 static uint8_t elink_8705_config_init(struct elink_phy
*phy
,
7103 struct elink_params
*params
,
7104 __rte_unused
struct elink_vars
7107 struct bnx2x_softc
*sc
= params
->sc
;
7108 PMD_DRV_LOG(DEBUG
, "init 8705");
7109 /* Restore normal power mode */
7110 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
7111 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
7113 elink_ext_phy_hw_reset(sc
, params
->port
);
7114 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0xa040);
7115 elink_wait_reset_complete(sc
, phy
, params
);
7117 elink_cl45_write(sc
, phy
,
7118 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL
, 0x8288);
7119 elink_cl45_write(sc
, phy
,
7120 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
, 0x7fbf);
7121 elink_cl45_write(sc
, phy
,
7122 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CMU_PLL_BYPASS
, 0x0100);
7123 elink_cl45_write(sc
, phy
, MDIO_WIS_DEVAD
, MDIO_WIS_REG_LASI_CNTL
, 0x1);
7124 /* BNX2X8705 doesn't have microcode, hence the 0 */
7125 elink_save_spirom_version(sc
, params
->port
, params
->shmem_base
, 0);
7126 return ELINK_STATUS_OK
;
7129 static uint8_t elink_8705_read_status(struct elink_phy
*phy
,
7130 struct elink_params
*params
,
7131 struct elink_vars
*vars
)
7133 uint8_t link_up
= 0;
7134 uint16_t val1
, rx_sd
;
7135 struct bnx2x_softc
*sc
= params
->sc
;
7136 PMD_DRV_LOG(DEBUG
, "read status 8705");
7137 elink_cl45_read(sc
, phy
,
7138 MDIO_WIS_DEVAD
, MDIO_WIS_REG_LASI_STATUS
, &val1
);
7139 PMD_DRV_LOG(DEBUG
, "8705 LASI status 0x%x", val1
);
7141 elink_cl45_read(sc
, phy
,
7142 MDIO_WIS_DEVAD
, MDIO_WIS_REG_LASI_STATUS
, &val1
);
7143 PMD_DRV_LOG(DEBUG
, "8705 LASI status 0x%x", val1
);
7145 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_SD
, &rx_sd
);
7147 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xc809, &val1
);
7148 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xc809, &val1
);
7150 PMD_DRV_LOG(DEBUG
, "8705 1.c809 val=0x%x", val1
);
7151 link_up
= ((rx_sd
& 0x1) && (val1
& (1 << 9))
7152 && ((val1
& (1 << 8)) == 0));
7154 vars
->line_speed
= ELINK_SPEED_10000
;
7155 elink_ext_phy_resolve_fc(phy
, params
, vars
);
7160 /******************************************************************/
7161 /* SFP+ module Section */
7162 /******************************************************************/
7163 static void elink_set_disable_pmd_transmit(struct elink_params
*params
,
7164 struct elink_phy
*phy
,
7167 struct bnx2x_softc
*sc
= params
->sc
;
7168 /* Disable transmitter only for bootcodes which can enable it afterwards
7172 if (params
->feature_config_flags
&
7173 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
) {
7174 PMD_DRV_LOG(DEBUG
, "Disabling PMD transmitter");
7176 PMD_DRV_LOG(DEBUG
, "NOT disabling PMD transmitter");
7180 PMD_DRV_LOG(DEBUG
, "Enabling PMD transmitter");
7182 elink_cl45_write(sc
, phy
,
7183 MDIO_PMA_DEVAD
, MDIO_PMA_REG_TX_DISABLE
, pmd_dis
);
7186 static uint8_t elink_get_gpio_port(struct elink_params
*params
)
7189 uint32_t swap_val
, swap_override
;
7190 struct bnx2x_softc
*sc
= params
->sc
;
7191 if (CHIP_IS_E2(sc
)) {
7192 gpio_port
= SC_PATH(sc
);
7194 gpio_port
= params
->port
;
7196 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
7197 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
7198 return gpio_port
^ (swap_val
&& swap_override
);
7201 static void elink_sfp_e1e2_set_transmitter(struct elink_params
*params
,
7202 struct elink_phy
*phy
, uint8_t tx_en
)
7205 uint8_t port
= params
->port
;
7206 struct bnx2x_softc
*sc
= params
->sc
;
7207 uint32_t tx_en_mode
;
7209 /* Disable/Enable transmitter ( TX laser of the SFP+ module.) */
7210 tx_en_mode
= REG_RD(sc
, params
->shmem_base
+
7211 offsetof(struct shmem_region
,
7212 dev_info
.port_hw_config
[port
].sfp_ctrl
)) &
7213 PORT_HW_CFG_TX_LASER_MASK
;
7214 PMD_DRV_LOG(DEBUG
, "Setting transmitter tx_en=%x for port %x "
7215 "mode = %x", tx_en
, port
, tx_en_mode
);
7216 switch (tx_en_mode
) {
7217 case PORT_HW_CFG_TX_LASER_MDIO
:
7219 elink_cl45_read(sc
, phy
,
7221 MDIO_PMA_REG_PHY_IDENTIFIER
, &val
);
7228 elink_cl45_write(sc
, phy
,
7230 MDIO_PMA_REG_PHY_IDENTIFIER
, val
);
7232 case PORT_HW_CFG_TX_LASER_GPIO0
:
7233 case PORT_HW_CFG_TX_LASER_GPIO1
:
7234 case PORT_HW_CFG_TX_LASER_GPIO2
:
7235 case PORT_HW_CFG_TX_LASER_GPIO3
:
7238 uint8_t gpio_port
, gpio_mode
;
7240 gpio_mode
= MISC_REGISTERS_GPIO_OUTPUT_HIGH
;
7242 gpio_mode
= MISC_REGISTERS_GPIO_OUTPUT_LOW
;
7244 gpio_pin
= tx_en_mode
- PORT_HW_CFG_TX_LASER_GPIO0
;
7245 gpio_port
= elink_get_gpio_port(params
);
7246 elink_cb_gpio_write(sc
, gpio_pin
, gpio_mode
, gpio_port
);
7250 PMD_DRV_LOG(DEBUG
, "Invalid TX_LASER_MDIO 0x%x", tx_en_mode
);
7255 static void elink_sfp_set_transmitter(struct elink_params
*params
,
7256 struct elink_phy
*phy
, uint8_t tx_en
)
7258 struct bnx2x_softc
*sc
= params
->sc
;
7259 PMD_DRV_LOG(DEBUG
, "Setting SFP+ transmitter to %d", tx_en
);
7261 elink_sfp_e3_set_transmitter(params
, phy
, tx_en
);
7263 elink_sfp_e1e2_set_transmitter(params
, phy
, tx_en
);
7266 static elink_status_t
elink_8726_read_sfp_module_eeprom(struct elink_phy
*phy
,
7273 __rte_unused
uint8_t
7276 struct bnx2x_softc
*sc
= params
->sc
;
7279 if (byte_cnt
> ELINK_SFP_EEPROM_PAGE_SIZE
) {
7280 PMD_DRV_LOG(DEBUG
, "Reading from eeprom is limited to 0xf");
7281 return ELINK_STATUS_ERROR
;
7283 /* Set the read command byte count */
7284 elink_cl45_write(sc
, phy
,
7285 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
7286 (byte_cnt
| (dev_addr
<< 8)));
7288 /* Set the read command address */
7289 elink_cl45_write(sc
, phy
,
7290 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
,
7293 /* Activate read command */
7294 elink_cl45_write(sc
, phy
,
7295 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
7298 /* Wait up to 500us for command complete status */
7299 for (i
= 0; i
< 100; i
++) {
7300 elink_cl45_read(sc
, phy
,
7302 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7303 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7304 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
7309 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
7310 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
7312 "Got bad status 0x%x when reading from SFP+ EEPROM",
7313 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
7314 return ELINK_STATUS_ERROR
;
7317 /* Read the buffer */
7318 for (i
= 0; i
< byte_cnt
; i
++) {
7319 elink_cl45_read(sc
, phy
,
7321 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF
+ i
, &val
);
7323 (uint8_t) (val
& MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK
);
7326 for (i
= 0; i
< 100; i
++) {
7327 elink_cl45_read(sc
, phy
,
7329 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7330 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7331 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
7332 return ELINK_STATUS_OK
;
7335 return ELINK_STATUS_ERROR
;
7338 static void elink_warpcore_power_module(struct elink_params
*params
,
7342 struct bnx2x_softc
*sc
= params
->sc
;
7344 pin_cfg
= (REG_RD(sc
, params
->shmem_base
+
7345 offsetof(struct shmem_region
,
7346 dev_info
.port_hw_config
[params
->port
].
7347 e3_sfp_ctrl
)) & PORT_HW_CFG_E3_PWR_DIS_MASK
)
7348 >> PORT_HW_CFG_E3_PWR_DIS_SHIFT
;
7350 if (pin_cfg
== PIN_CFG_NA
)
7352 PMD_DRV_LOG(DEBUG
, "Setting SFP+ module power to %d using pin cfg %d",
7354 /* Low ==> corresponding SFP+ module is powered
7355 * high ==> the SFP+ module is powered down
7357 elink_set_cfg_pin(sc
, pin_cfg
, power
^ 1);
7360 static elink_status_t
elink_warpcore_read_sfp_module_eeprom(__rte_unused
struct
7370 elink_status_t rc
= ELINK_STATUS_OK
;
7371 uint8_t i
, j
= 0, cnt
= 0;
7372 uint32_t data_array
[4];
7374 struct bnx2x_softc
*sc
= params
->sc
;
7376 if (byte_cnt
> ELINK_SFP_EEPROM_PAGE_SIZE
) {
7378 "Reading from eeprom is limited to 16 bytes");
7379 return ELINK_STATUS_ERROR
;
7382 /* 4 byte aligned address */
7383 addr32
= addr
& (~0x3);
7385 if ((!is_init
) && (cnt
== I2C_WA_PWR_ITER
)) {
7386 elink_warpcore_power_module(params
, 0);
7387 /* Note that 100us are not enough here */
7389 elink_warpcore_power_module(params
, 1);
7391 rc
= elink_bsc_read(params
, sc
, dev_addr
, addr32
, 0, byte_cnt
,
7393 } while ((rc
!= ELINK_STATUS_OK
) && (++cnt
< I2C_WA_RETRY_CNT
));
7395 if (rc
== ELINK_STATUS_OK
) {
7396 for (i
= (addr
- addr32
); i
< byte_cnt
+ (addr
- addr32
); i
++) {
7397 o_buf
[j
] = *((uint8_t *) data_array
+ i
);
7405 static elink_status_t
elink_8727_read_sfp_module_eeprom(struct elink_phy
*phy
,
7412 __rte_unused
uint8_t
7415 struct bnx2x_softc
*sc
= params
->sc
;
7418 if (byte_cnt
> ELINK_SFP_EEPROM_PAGE_SIZE
) {
7419 PMD_DRV_LOG(DEBUG
, "Reading from eeprom is limited to 0xf");
7420 return ELINK_STATUS_ERROR
;
7423 /* Set 2-wire transfer rate of SFP+ module EEPROM
7424 * to 100Khz since some DACs(direct attached cables) do
7425 * not work at 400Khz.
7427 elink_cl45_write(sc
, phy
,
7429 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR
,
7430 ((dev_addr
<< 8) | 1));
7432 /* Need to read from 1.8000 to clear it */
7433 elink_cl45_read(sc
, phy
,
7434 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7436 /* Set the read command byte count */
7437 elink_cl45_write(sc
, phy
,
7439 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
7440 ((byte_cnt
< 2) ? 2 : byte_cnt
));
7442 /* Set the read command address */
7443 elink_cl45_write(sc
, phy
,
7445 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
, addr
);
7446 /* Set the destination address */
7447 elink_cl45_write(sc
, phy
,
7449 0x8004, MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
);
7451 /* Activate read command */
7452 elink_cl45_write(sc
, phy
,
7454 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, 0x8002);
7455 /* Wait appropriate time for two-wire command to finish before
7456 * polling the status register
7460 /* Wait up to 500us for command complete status */
7461 for (i
= 0; i
< 100; i
++) {
7462 elink_cl45_read(sc
, phy
,
7464 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7465 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7466 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
7471 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
7472 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
7474 "Got bad status 0x%x when reading from SFP+ EEPROM",
7475 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
7476 return ELINK_STATUS_TIMEOUT
;
7479 /* Read the buffer */
7480 for (i
= 0; i
< byte_cnt
; i
++) {
7481 elink_cl45_read(sc
, phy
,
7483 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
+ i
, &val
);
7485 (uint8_t) (val
& MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK
);
7488 for (i
= 0; i
< 100; i
++) {
7489 elink_cl45_read(sc
, phy
,
7491 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7492 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7493 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
7494 return ELINK_STATUS_OK
;
7498 return ELINK_STATUS_ERROR
;
7501 static elink_status_t
elink_read_sfp_module_eeprom(struct elink_phy
*phy
,
7502 struct elink_params
*params
,
7508 elink_status_t rc
= ELINK_STATUS_OK
;
7510 uint8_t *user_data
= o_buf
;
7511 read_sfp_module_eeprom_func_p read_func
;
7513 if ((dev_addr
!= 0xa0) && (dev_addr
!= 0xa2)) {
7514 PMD_DRV_LOG(DEBUG
, "invalid dev_addr 0x%x", dev_addr
);
7515 return ELINK_STATUS_ERROR
;
7518 switch (phy
->type
) {
7519 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
:
7520 read_func
= elink_8726_read_sfp_module_eeprom
;
7522 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
7523 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
7524 read_func
= elink_8727_read_sfp_module_eeprom
;
7526 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
7527 read_func
= elink_warpcore_read_sfp_module_eeprom
;
7530 return ELINK_OP_NOT_SUPPORTED
;
7533 while (!rc
&& (byte_cnt
> 0)) {
7534 xfer_size
= (byte_cnt
> ELINK_SFP_EEPROM_PAGE_SIZE
) ?
7535 ELINK_SFP_EEPROM_PAGE_SIZE
: byte_cnt
;
7536 rc
= read_func(phy
, params
, dev_addr
, addr
, xfer_size
,
7538 byte_cnt
-= xfer_size
;
7539 user_data
+= xfer_size
;
7545 static elink_status_t
elink_get_edc_mode(struct elink_phy
*phy
,
7546 struct elink_params
*params
,
7547 uint16_t * edc_mode
)
7549 struct bnx2x_softc
*sc
= params
->sc
;
7550 uint32_t sync_offset
= 0, phy_idx
, media_types
;
7551 uint8_t gport
, val
[2], check_limiting_mode
= 0;
7552 *edc_mode
= ELINK_EDC_MODE_LIMITING
;
7553 phy
->media_type
= ELINK_ETH_PHY_UNSPECIFIED
;
7554 /* First check for copper cable */
7555 if (elink_read_sfp_module_eeprom(phy
,
7557 ELINK_I2C_DEV_ADDR_A0
,
7558 ELINK_SFP_EEPROM_CON_TYPE_ADDR
,
7559 2, (uint8_t *) val
) != 0) {
7560 PMD_DRV_LOG(DEBUG
, "Failed to read from SFP+ module EEPROM");
7561 return ELINK_STATUS_ERROR
;
7565 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER
:
7567 uint8_t copper_module_type
;
7568 phy
->media_type
= ELINK_ETH_PHY_DA_TWINAX
;
7569 /* Check if its active cable (includes SFP+ module)
7572 if (elink_read_sfp_module_eeprom(phy
,
7574 ELINK_I2C_DEV_ADDR_A0
,
7575 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR
,
7577 &copper_module_type
) !=
7580 "Failed to read copper-cable-type"
7581 " from SFP+ EEPROM");
7582 return ELINK_STATUS_ERROR
;
7585 if (copper_module_type
&
7586 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE
) {
7588 "Active Copper cable detected");
7590 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
7591 *edc_mode
= ELINK_EDC_MODE_ACTIVE_DAC
;
7593 check_limiting_mode
= 1;
7594 } else if (copper_module_type
&
7595 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE
)
7598 "Passive Copper cable detected");
7599 *edc_mode
= ELINK_EDC_MODE_PASSIVE_DAC
;
7602 "Unknown copper-cable-type 0x%x !!!",
7603 copper_module_type
);
7604 return ELINK_STATUS_ERROR
;
7608 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC
:
7609 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45
:
7610 check_limiting_mode
= 1;
7611 if ((val
[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK
|
7612 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK
|
7613 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK
)) == 0) {
7614 PMD_DRV_LOG(DEBUG
, "1G SFP module detected");
7615 gport
= params
->port
;
7616 phy
->media_type
= ELINK_ETH_PHY_SFP_1G_FIBER
;
7617 if (phy
->req_line_speed
!= ELINK_SPEED_1000
) {
7618 phy
->req_line_speed
= ELINK_SPEED_1000
;
7619 if (!CHIP_IS_E1x(sc
)) {
7620 gport
= SC_PATH(sc
) +
7621 (params
->port
<< 1);
7623 elink_cb_event_log(sc
, ELINK_LOG_ID_NON_10G_MODULE
, gport
); //"Warning: Link speed was forced to 1000Mbps."
7624 // " Current SFP module in port %d is not"
7625 // " compliant with 10G Ethernet",
7629 int idx
, cfg_idx
= 0;
7630 PMD_DRV_LOG(DEBUG
, "10G Optic module detected");
7631 for (idx
= ELINK_INT_PHY
; idx
< ELINK_MAX_PHYS
; idx
++) {
7632 if (params
->phy
[idx
].type
== phy
->type
) {
7633 cfg_idx
= ELINK_LINK_CONFIG_IDX(idx
);
7637 phy
->media_type
= ELINK_ETH_PHY_SFPP_10G_FIBER
;
7638 phy
->req_line_speed
= params
->req_line_speed
[cfg_idx
];
7642 PMD_DRV_LOG(DEBUG
, "Unable to determine module type 0x%x !!!",
7644 return ELINK_STATUS_ERROR
;
7646 sync_offset
= params
->shmem_base
+
7647 offsetof(struct shmem_region
,
7648 dev_info
.port_hw_config
[params
->port
].media_type
);
7649 media_types
= REG_RD(sc
, sync_offset
);
7650 /* Update media type for non-PMF sync */
7651 for (phy_idx
= ELINK_INT_PHY
; phy_idx
< ELINK_MAX_PHYS
; phy_idx
++) {
7652 if (&(params
->phy
[phy_idx
]) == phy
) {
7653 media_types
&= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
<<
7654 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
*
7658 media_type
& PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
) <<
7659 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
* phy_idx
));
7663 REG_WR(sc
, sync_offset
, media_types
);
7664 if (check_limiting_mode
) {
7665 uint8_t options
[ELINK_SFP_EEPROM_OPTIONS_SIZE
];
7666 if (elink_read_sfp_module_eeprom(phy
,
7668 ELINK_I2C_DEV_ADDR_A0
,
7669 ELINK_SFP_EEPROM_OPTIONS_ADDR
,
7670 ELINK_SFP_EEPROM_OPTIONS_SIZE
,
7673 "Failed to read Option field from module EEPROM");
7674 return ELINK_STATUS_ERROR
;
7676 if ((options
[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK
))
7677 *edc_mode
= ELINK_EDC_MODE_LINEAR
;
7679 *edc_mode
= ELINK_EDC_MODE_LIMITING
;
7681 PMD_DRV_LOG(DEBUG
, "EDC mode is set to 0x%x", *edc_mode
);
7682 return ELINK_STATUS_OK
;
7685 /* This function read the relevant field from the module (SFP+), and verify it
7686 * is compliant with this board
7688 static elink_status_t
elink_verify_sfp_module(struct elink_phy
*phy
,
7689 struct elink_params
*params
)
7691 struct bnx2x_softc
*sc
= params
->sc
;
7693 uint32_t fw_resp
, fw_cmd_param
;
7694 char vendor_name
[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE
+ 1];
7695 char vendor_pn
[ELINK_SFP_EEPROM_PART_NO_SIZE
+ 1];
7696 phy
->flags
&= ~ELINK_FLAGS_SFP_NOT_APPROVED
;
7697 val
= REG_RD(sc
, params
->shmem_base
+
7698 offsetof(struct shmem_region
,
7699 dev_info
.port_feature_config
[params
->port
].
7701 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
7702 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT
) {
7703 PMD_DRV_LOG(DEBUG
, "NOT enforcing module verification");
7704 return ELINK_STATUS_OK
;
7707 if (params
->feature_config_flags
&
7708 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
) {
7709 /* Use specific phy request */
7710 cmd
= DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL
;
7711 } else if (params
->feature_config_flags
&
7712 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
) {
7713 /* Use first phy request only in case of non-dual media */
7714 if (ELINK_DUAL_MEDIA(params
)) {
7716 "FW does not support OPT MDL verification");
7717 return ELINK_STATUS_ERROR
;
7719 cmd
= DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL
;
7721 /* No support in OPT MDL detection */
7722 PMD_DRV_LOG(DEBUG
, "FW does not support OPT MDL verification");
7723 return ELINK_STATUS_ERROR
;
7726 fw_cmd_param
= ELINK_FW_PARAM_SET(phy
->addr
, phy
->type
, phy
->mdio_ctrl
);
7727 fw_resp
= elink_cb_fw_command(sc
, cmd
, fw_cmd_param
);
7728 if (fw_resp
== FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS
) {
7729 PMD_DRV_LOG(DEBUG
, "Approved module");
7730 return ELINK_STATUS_OK
;
7733 /* Format the warning message */
7734 if (elink_read_sfp_module_eeprom(phy
,
7736 ELINK_I2C_DEV_ADDR_A0
,
7737 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR
,
7738 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE
,
7739 (uint8_t *) vendor_name
))
7740 vendor_name
[0] = '\0';
7742 vendor_name
[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE
] = '\0';
7743 if (elink_read_sfp_module_eeprom(phy
,
7745 ELINK_I2C_DEV_ADDR_A0
,
7746 ELINK_SFP_EEPROM_PART_NO_ADDR
,
7747 ELINK_SFP_EEPROM_PART_NO_SIZE
,
7748 (uint8_t *) vendor_pn
))
7749 vendor_pn
[0] = '\0';
7751 vendor_pn
[ELINK_SFP_EEPROM_PART_NO_SIZE
] = '\0';
7753 elink_cb_event_log(sc
, ELINK_LOG_ID_UNQUAL_IO_MODULE
, params
->port
, vendor_name
, vendor_pn
); // "Warning: Unqualified SFP+ module detected,"
7754 // " Port %d from %s part number %s",
7756 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) !=
7757 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG
)
7758 phy
->flags
|= ELINK_FLAGS_SFP_NOT_APPROVED
;
7759 return ELINK_STATUS_ERROR
;
7762 static elink_status_t
elink_wait_for_sfp_module_initialized(struct elink_phy
7770 /* Initialization time after hot-plug may take up to 300ms for
7771 * some phys type ( e.g. JDSU )
7774 for (timeout
= 0; timeout
< 60; timeout
++) {
7775 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
7776 rc
= elink_warpcore_read_sfp_module_eeprom(phy
, params
,
7777 ELINK_I2C_DEV_ADDR_A0
,
7781 rc
= elink_read_sfp_module_eeprom(phy
, params
,
7782 ELINK_I2C_DEV_ADDR_A0
,
7786 "SFP+ module initialization took %d ms",
7788 return ELINK_STATUS_OK
;
7792 rc
= elink_read_sfp_module_eeprom(phy
, params
, ELINK_I2C_DEV_ADDR_A0
,
7797 static void elink_8727_power_module(struct bnx2x_softc
*sc
,
7798 struct elink_phy
*phy
, uint8_t is_power_up
)
7800 /* Make sure GPIOs are not using for LED mode */
7802 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
7803 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7805 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7806 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7807 * where the 1st bit is the over-current(only input), and 2nd bit is
7808 * for power( only output )
7810 * In case of NOC feature is disabled and power is up, set GPIO control
7811 * as input to enable listening of over-current indication
7813 if (phy
->flags
& ELINK_FLAGS_NOC
)
7818 /* Set GPIO control to OUTPUT, and set the power bit
7819 * to according to the is_power_up
7823 elink_cl45_write(sc
, phy
,
7824 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_GPIO_CTRL
, val
);
7827 static elink_status_t
elink_8726_set_limiting_mode(struct bnx2x_softc
*sc
,
7828 struct elink_phy
*phy
,
7831 uint16_t cur_limiting_mode
;
7833 elink_cl45_read(sc
, phy
,
7835 MDIO_PMA_REG_ROM_VER2
, &cur_limiting_mode
);
7836 PMD_DRV_LOG(DEBUG
, "Current Limiting mode is 0x%x", cur_limiting_mode
);
7838 if (edc_mode
== ELINK_EDC_MODE_LIMITING
) {
7839 PMD_DRV_LOG(DEBUG
, "Setting LIMITING MODE");
7840 elink_cl45_write(sc
, phy
,
7842 MDIO_PMA_REG_ROM_VER2
,
7843 ELINK_EDC_MODE_LIMITING
);
7844 } else { /* LRM mode ( default ) */
7846 PMD_DRV_LOG(DEBUG
, "Setting LRM MODE");
7848 /* Changing to LRM mode takes quite few seconds. So do it only
7849 * if current mode is limiting (default is LRM)
7851 if (cur_limiting_mode
!= ELINK_EDC_MODE_LIMITING
)
7852 return ELINK_STATUS_OK
;
7854 elink_cl45_write(sc
, phy
,
7855 MDIO_PMA_DEVAD
, MDIO_PMA_REG_LRM_MODE
, 0);
7856 elink_cl45_write(sc
, phy
,
7857 MDIO_PMA_DEVAD
, MDIO_PMA_REG_ROM_VER2
, 0x128);
7858 elink_cl45_write(sc
, phy
,
7860 MDIO_PMA_REG_MISC_CTRL0
, 0x4008);
7861 elink_cl45_write(sc
, phy
,
7862 MDIO_PMA_DEVAD
, MDIO_PMA_REG_LRM_MODE
, 0xaaaa);
7864 return ELINK_STATUS_OK
;
7867 static elink_status_t
elink_8727_set_limiting_mode(struct bnx2x_softc
*sc
,
7868 struct elink_phy
*phy
,
7871 uint16_t phy_identifier
;
7872 uint16_t rom_ver2_val
;
7873 elink_cl45_read(sc
, phy
,
7875 MDIO_PMA_REG_PHY_IDENTIFIER
, &phy_identifier
);
7877 elink_cl45_write(sc
, phy
,
7879 MDIO_PMA_REG_PHY_IDENTIFIER
,
7880 (phy_identifier
& ~(1 << 9)));
7882 elink_cl45_read(sc
, phy
,
7883 MDIO_PMA_DEVAD
, MDIO_PMA_REG_ROM_VER2
, &rom_ver2_val
);
7884 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7885 elink_cl45_write(sc
, phy
,
7887 MDIO_PMA_REG_ROM_VER2
,
7888 (rom_ver2_val
& 0xff00) | (edc_mode
& 0x00ff));
7890 elink_cl45_write(sc
, phy
,
7892 MDIO_PMA_REG_PHY_IDENTIFIER
,
7893 (phy_identifier
| (1 << 9)));
7895 return ELINK_STATUS_OK
;
7898 static void elink_8727_specific_func(struct elink_phy
*phy
,
7899 struct elink_params
*params
,
7902 struct bnx2x_softc
*sc
= params
->sc
;
7905 case ELINK_DISABLE_TX
:
7906 elink_sfp_set_transmitter(params
, phy
, 0);
7908 case ELINK_ENABLE_TX
:
7909 if (!(phy
->flags
& ELINK_FLAGS_SFP_NOT_APPROVED
))
7910 elink_sfp_set_transmitter(params
, phy
, 1);
7912 case ELINK_PHY_INIT
:
7913 elink_cl45_write(sc
, phy
,
7914 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
7915 (1 << 2) | (1 << 5));
7916 elink_cl45_write(sc
, phy
,
7917 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_TXCTRL
, 0);
7918 elink_cl45_write(sc
, phy
,
7919 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x0006);
7920 /* Make MOD_ABS give interrupt on change */
7921 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
7922 MDIO_PMA_REG_8727_PCS_OPT_CTRL
, &val
);
7924 if (phy
->flags
& ELINK_FLAGS_NOC
)
7926 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
7927 * status which reflect SFP+ module over-current
7929 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
7930 val
&= 0xff8f; /* Reset bits 4-6 */
7931 elink_cl45_write(sc
, phy
,
7932 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
7936 PMD_DRV_LOG(DEBUG
, "Function 0x%x not supported by 8727",
7942 static void elink_set_e1e2_module_fault_led(struct elink_params
*params
,
7945 struct bnx2x_softc
*sc
= params
->sc
;
7947 uint32_t fault_led_gpio
= REG_RD(sc
, params
->shmem_base
+
7948 offsetof(struct shmem_region
,
7950 port_hw_config
[params
->port
].
7952 PORT_HW_CFG_FAULT_MODULE_LED_MASK
;
7953 switch (fault_led_gpio
) {
7954 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED
:
7956 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0
:
7957 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1
:
7958 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2
:
7959 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3
:
7961 uint8_t gpio_port
= elink_get_gpio_port(params
);
7962 uint16_t gpio_pin
= fault_led_gpio
-
7963 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0
;
7964 PMD_DRV_LOG(DEBUG
, "Set fault module-detected led "
7965 "pin %x port %x mode %x",
7966 gpio_pin
, gpio_port
, gpio_mode
);
7967 elink_cb_gpio_write(sc
, gpio_pin
, gpio_mode
, gpio_port
);
7971 PMD_DRV_LOG(DEBUG
, "Error: Invalid fault led mode 0x%x",
7976 static void elink_set_e3_module_fault_led(struct elink_params
*params
,
7980 uint8_t port
= params
->port
;
7981 struct bnx2x_softc
*sc
= params
->sc
;
7982 pin_cfg
= (REG_RD(sc
, params
->shmem_base
+
7983 offsetof(struct shmem_region
,
7984 dev_info
.port_hw_config
[port
].e3_sfp_ctrl
)) &
7985 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK
) >>
7986 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT
;
7987 PMD_DRV_LOG(DEBUG
, "Setting Fault LED to %d using pin cfg %d",
7988 gpio_mode
, pin_cfg
);
7989 elink_set_cfg_pin(sc
, pin_cfg
, gpio_mode
);
7992 static void elink_set_sfp_module_fault_led(struct elink_params
*params
,
7995 struct bnx2x_softc
*sc
= params
->sc
;
7996 PMD_DRV_LOG(DEBUG
, "Setting SFP+ module fault LED to %d", gpio_mode
);
7997 if (CHIP_IS_E3(sc
)) {
7998 /* Low ==> if SFP+ module is supported otherwise
7999 * High ==> if SFP+ module is not on the approved vendor list
8001 elink_set_e3_module_fault_led(params
, gpio_mode
);
8003 elink_set_e1e2_module_fault_led(params
, gpio_mode
);
8006 static void elink_warpcore_hw_reset(__rte_unused
struct elink_phy
*phy
,
8007 struct elink_params
*params
)
8009 struct bnx2x_softc
*sc
= params
->sc
;
8010 elink_warpcore_power_module(params
, 0);
8011 /* Put Warpcore in low power mode */
8012 REG_WR(sc
, MISC_REG_WC0_RESET
, 0x0c0e);
8014 /* Put LCPLL in low power mode */
8015 REG_WR(sc
, MISC_REG_LCPLL_E40_PWRDWN
, 1);
8016 REG_WR(sc
, MISC_REG_LCPLL_E40_RESETB_ANA
, 0);
8017 REG_WR(sc
, MISC_REG_LCPLL_E40_RESETB_DIG
, 0);
8020 static void elink_power_sfp_module(struct elink_params
*params
,
8021 struct elink_phy
*phy
, uint8_t power
)
8023 PMD_DRV_LOG(DEBUG
, "Setting SFP+ power to %x", power
);
8025 switch (phy
->type
) {
8026 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
8027 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
8028 elink_8727_power_module(params
->sc
, phy
, power
);
8030 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
8031 elink_warpcore_power_module(params
, power
);
8038 static void elink_warpcore_set_limiting_mode(struct elink_params
*params
,
8039 struct elink_phy
*phy
,
8043 uint16_t mode
= MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT
;
8044 struct bnx2x_softc
*sc
= params
->sc
;
8046 uint8_t lane
= elink_get_warpcore_lane(params
);
8047 /* This is a global register which controls all lanes */
8048 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
8049 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE
, &val
);
8050 val
&= ~(0xf << (lane
<< 2));
8053 case ELINK_EDC_MODE_LINEAR
:
8054 case ELINK_EDC_MODE_LIMITING
:
8055 mode
= MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT
;
8057 case ELINK_EDC_MODE_PASSIVE_DAC
:
8058 case ELINK_EDC_MODE_ACTIVE_DAC
:
8059 mode
= MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC
;
8065 val
|= (mode
<< (lane
<< 2));
8066 elink_cl45_write(sc
, phy
, MDIO_WC_DEVAD
,
8067 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE
, val
);
8069 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
8070 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE
, &val
);
8072 /* Restart microcode to re-read the new mode */
8073 elink_warpcore_reset_lane(sc
, phy
, 1);
8074 elink_warpcore_reset_lane(sc
, phy
, 0);
8078 static void elink_set_limiting_mode(struct elink_params
*params
,
8079 struct elink_phy
*phy
, uint16_t edc_mode
)
8081 switch (phy
->type
) {
8082 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
:
8083 elink_8726_set_limiting_mode(params
->sc
, phy
, edc_mode
);
8085 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
8086 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
8087 elink_8727_set_limiting_mode(params
->sc
, phy
, edc_mode
);
8089 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
8090 elink_warpcore_set_limiting_mode(params
, phy
, edc_mode
);
8095 static elink_status_t
elink_sfp_module_detection(struct elink_phy
*phy
,
8096 struct elink_params
*params
)
8098 struct bnx2x_softc
*sc
= params
->sc
;
8100 elink_status_t rc
= ELINK_STATUS_OK
;
8102 uint32_t val
= REG_RD(sc
, params
->shmem_base
+
8103 offsetof(struct shmem_region
,
8104 dev_info
.port_feature_config
[params
->
8107 /* Enabled transmitter by default */
8108 elink_sfp_set_transmitter(params
, phy
, 1);
8109 PMD_DRV_LOG(DEBUG
, "SFP+ module plugged in/out detected on port %d",
8111 /* Power up module */
8112 elink_power_sfp_module(params
, phy
, 1);
8113 if (elink_get_edc_mode(phy
, params
, &edc_mode
) != 0) {
8114 PMD_DRV_LOG(DEBUG
, "Failed to get valid module type");
8115 return ELINK_STATUS_ERROR
;
8116 } else if (elink_verify_sfp_module(phy
, params
) != 0) {
8117 /* Check SFP+ module compatibility */
8118 PMD_DRV_LOG(DEBUG
, "Module verification failed!!");
8119 rc
= ELINK_STATUS_ERROR
;
8120 /* Turn on fault module-detected led */
8121 elink_set_sfp_module_fault_led(params
,
8122 MISC_REGISTERS_GPIO_HIGH
);
8124 /* Check if need to power down the SFP+ module */
8125 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
8126 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN
) {
8127 PMD_DRV_LOG(DEBUG
, "Shutdown SFP+ module!!");
8128 elink_power_sfp_module(params
, phy
, 0);
8132 /* Turn off fault module-detected led */
8133 elink_set_sfp_module_fault_led(params
, MISC_REGISTERS_GPIO_LOW
);
8136 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8137 * is done automatically
8139 elink_set_limiting_mode(params
, phy
, edc_mode
);
8141 /* Disable transmit for this module if the module is not approved, and
8142 * laser needs to be disabled.
8145 ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
8146 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
))
8147 elink_sfp_set_transmitter(params
, phy
, 0);
8152 void elink_handle_module_detect_int(struct elink_params
*params
)
8154 struct bnx2x_softc
*sc
= params
->sc
;
8155 struct elink_phy
*phy
;
8157 uint8_t gpio_num
, gpio_port
;
8158 if (CHIP_IS_E3(sc
)) {
8159 phy
= ¶ms
->phy
[ELINK_INT_PHY
];
8160 /* Always enable TX laser,will be disabled in case of fault */
8161 elink_sfp_set_transmitter(params
, phy
, 1);
8163 phy
= ¶ms
->phy
[ELINK_EXT_PHY1
];
8165 if (elink_get_mod_abs_int_cfg(sc
, params
->shmem_base
,
8166 params
->port
, &gpio_num
, &gpio_port
) ==
8167 ELINK_STATUS_ERROR
) {
8168 PMD_DRV_LOG(DEBUG
, "Failed to get MOD_ABS interrupt config");
8172 /* Set valid module led off */
8173 elink_set_sfp_module_fault_led(params
, MISC_REGISTERS_GPIO_HIGH
);
8175 /* Get current gpio val reflecting module plugged in / out */
8176 gpio_val
= elink_cb_gpio_read(sc
, gpio_num
, gpio_port
);
8178 /* Call the handling function in case module is detected */
8179 if (gpio_val
== 0) {
8180 elink_set_mdio_emac_per_phy(sc
, params
);
8181 elink_set_aer_mmd(params
, phy
);
8183 elink_power_sfp_module(params
, phy
, 1);
8184 elink_cb_gpio_int_write(sc
, gpio_num
,
8185 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
,
8187 if (elink_wait_for_sfp_module_initialized(phy
, params
) == 0) {
8188 elink_sfp_module_detection(phy
, params
);
8189 if (CHIP_IS_E3(sc
)) {
8190 uint16_t rx_tx_in_reset
;
8191 /* In case WC is out of reset, reconfigure the
8192 * link speed while taking into account 1G
8193 * module limitation.
8195 elink_cl45_read(sc
, phy
,
8197 MDIO_WC_REG_DIGITAL5_MISC6
,
8199 if ((!rx_tx_in_reset
) &&
8200 (params
->link_flags
&
8201 ELINK_PHY_INITIALIZED
)) {
8202 elink_warpcore_reset_lane(sc
, phy
, 1);
8203 elink_warpcore_config_sfi(phy
, params
);
8204 elink_warpcore_reset_lane(sc
, phy
, 0);
8208 PMD_DRV_LOG(DEBUG
, "SFP+ module is not initialized");
8211 elink_cb_gpio_int_write(sc
, gpio_num
,
8212 MISC_REGISTERS_GPIO_INT_OUTPUT_SET
,
8214 /* Module was plugged out.
8215 * Disable transmit for this module
8217 phy
->media_type
= ELINK_ETH_PHY_NOT_PRESENT
;
8221 /******************************************************************/
8222 /* Used by 8706 and 8727 */
8223 /******************************************************************/
8224 static void elink_sfp_mask_fault(struct bnx2x_softc
*sc
,
8225 struct elink_phy
*phy
,
8226 uint16_t alarm_status_offset
,
8227 uint16_t alarm_ctrl_offset
)
8229 uint16_t alarm_status
, val
;
8230 elink_cl45_read(sc
, phy
,
8231 MDIO_PMA_DEVAD
, alarm_status_offset
, &alarm_status
);
8232 elink_cl45_read(sc
, phy
,
8233 MDIO_PMA_DEVAD
, alarm_status_offset
, &alarm_status
);
8234 /* Mask or enable the fault event. */
8235 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, alarm_ctrl_offset
, &val
);
8236 if (alarm_status
& (1 << 0))
8240 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, alarm_ctrl_offset
, val
);
8243 /******************************************************************/
8244 /* common BNX2X8706/BNX2X8726 PHY SECTION */
8245 /******************************************************************/
8246 static uint8_t elink_8706_8726_read_status(struct elink_phy
*phy
,
8247 struct elink_params
*params
,
8248 struct elink_vars
*vars
)
8250 uint8_t link_up
= 0;
8251 uint16_t val1
, val2
, rx_sd
, pcs_status
;
8252 struct bnx2x_softc
*sc
= params
->sc
;
8253 PMD_DRV_LOG(DEBUG
, "XGXS 8706/8726");
8254 /* Clear RX Alarm */
8255 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &val2
);
8257 elink_sfp_mask_fault(sc
, phy
, MDIO_PMA_LASI_TXSTAT
,
8258 MDIO_PMA_LASI_TXCTRL
);
8260 /* Clear LASI indication */
8261 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
8262 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val2
);
8263 PMD_DRV_LOG(DEBUG
, "8706/8726 LASI status 0x%x--> 0x%x", val1
, val2
);
8265 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_SD
, &rx_sd
);
8266 elink_cl45_read(sc
, phy
,
8267 MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &pcs_status
);
8268 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &val2
);
8269 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &val2
);
8271 PMD_DRV_LOG(DEBUG
, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8272 " link_status 0x%x", rx_sd
, pcs_status
, val2
);
8273 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8274 * are set, or if the autoneg bit 1 is set
8276 link_up
= ((rx_sd
& pcs_status
& 0x1) || (val2
& (1 << 1)));
8278 if (val2
& (1 << 1))
8279 vars
->line_speed
= ELINK_SPEED_1000
;
8281 vars
->line_speed
= ELINK_SPEED_10000
;
8282 elink_ext_phy_resolve_fc(phy
, params
, vars
);
8283 vars
->duplex
= DUPLEX_FULL
;
8286 /* Capture 10G link fault. Read twice to clear stale value. */
8287 if (vars
->line_speed
== ELINK_SPEED_10000
) {
8288 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8289 MDIO_PMA_LASI_TXSTAT
, &val1
);
8290 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8291 MDIO_PMA_LASI_TXSTAT
, &val1
);
8292 if (val1
& (1 << 0))
8293 vars
->fault_detected
= 1;
8299 /******************************************************************/
8300 /* BNX2X8706 PHY SECTION */
8301 /******************************************************************/
8302 static uint8_t elink_8706_config_init(struct elink_phy
*phy
,
8303 struct elink_params
*params
,
8304 __rte_unused
struct elink_vars
*vars
)
8306 uint32_t tx_en_mode
;
8307 uint16_t cnt
, val
, tmp1
;
8308 struct bnx2x_softc
*sc
= params
->sc
;
8310 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
8311 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
8313 elink_ext_phy_hw_reset(sc
, params
->port
);
8314 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0xa040);
8315 elink_wait_reset_complete(sc
, phy
, params
);
8317 /* Wait until fw is loaded */
8318 for (cnt
= 0; cnt
< 100; cnt
++) {
8319 elink_cl45_read(sc
, phy
,
8320 MDIO_PMA_DEVAD
, MDIO_PMA_REG_ROM_VER1
, &val
);
8325 PMD_DRV_LOG(DEBUG
, "XGXS 8706 is initialized after %d ms", cnt
);
8326 if ((params
->feature_config_flags
&
8327 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
8330 for (i
= 0; i
< 4; i
++) {
8331 reg
= MDIO_XS_8706_REG_BANK_RX0
+
8332 i
* (MDIO_XS_8706_REG_BANK_RX1
-
8333 MDIO_XS_8706_REG_BANK_RX0
);
8334 elink_cl45_read(sc
, phy
, MDIO_XS_DEVAD
, reg
, &val
);
8335 /* Clear first 3 bits of the control */
8337 /* Set control bits according to configuration */
8338 val
|= (phy
->rx_preemphasis
[i
] & 0x7);
8339 PMD_DRV_LOG(DEBUG
, "Setting RX Equalizer to BNX2X8706"
8340 " reg 0x%x <-- val 0x%x", reg
, val
);
8341 elink_cl45_write(sc
, phy
, MDIO_XS_DEVAD
, reg
, val
);
8345 if (phy
->req_line_speed
== ELINK_SPEED_10000
) {
8346 PMD_DRV_LOG(DEBUG
, "XGXS 8706 force 10Gbps");
8348 elink_cl45_write(sc
, phy
,
8350 MDIO_PMA_REG_DIGITAL_CTRL
, 0x400);
8351 elink_cl45_write(sc
, phy
,
8352 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_TXCTRL
, 0);
8353 /* Arm LASI for link and Tx fault. */
8354 elink_cl45_write(sc
, phy
,
8355 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 3);
8357 /* Force 1Gbps using autoneg with 1G advertisement */
8359 /* Allow CL37 through CL73 */
8360 PMD_DRV_LOG(DEBUG
, "XGXS 8706 AutoNeg");
8361 elink_cl45_write(sc
, phy
,
8362 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_CL73
, 0x040c);
8364 /* Enable Full-Duplex advertisement on CL37 */
8365 elink_cl45_write(sc
, phy
,
8366 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LP
, 0x0020);
8367 /* Enable CL37 AN */
8368 elink_cl45_write(sc
, phy
,
8369 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1000);
8371 elink_cl45_write(sc
, phy
,
8372 MDIO_AN_DEVAD
, MDIO_AN_REG_ADV
, (1 << 5));
8374 /* Enable clause 73 AN */
8375 elink_cl45_write(sc
, phy
,
8376 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x1200);
8377 elink_cl45_write(sc
, phy
,
8378 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
, 0x0400);
8379 elink_cl45_write(sc
, phy
,
8380 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x0004);
8382 elink_save_bnx2x_spirom_ver(sc
, phy
, params
->port
);
8384 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8385 * power mode, if TX Laser is disabled
8388 tx_en_mode
= REG_RD(sc
, params
->shmem_base
+
8389 offsetof(struct shmem_region
,
8390 dev_info
.port_hw_config
[params
->port
].
8392 & PORT_HW_CFG_TX_LASER_MASK
;
8394 if (tx_en_mode
== PORT_HW_CFG_TX_LASER_GPIO0
) {
8395 PMD_DRV_LOG(DEBUG
, "Enabling TXONOFF_PWRDN_DIS");
8396 elink_cl45_read(sc
, phy
,
8397 MDIO_PMA_DEVAD
, MDIO_PMA_REG_DIGITAL_CTRL
,
8400 elink_cl45_write(sc
, phy
,
8401 MDIO_PMA_DEVAD
, MDIO_PMA_REG_DIGITAL_CTRL
,
8405 return ELINK_STATUS_OK
;
8408 static uint8_t elink_8706_read_status(struct elink_phy
*phy
,
8409 struct elink_params
*params
,
8410 struct elink_vars
*vars
)
8412 return elink_8706_8726_read_status(phy
, params
, vars
);
8415 /******************************************************************/
8416 /* BNX2X8726 PHY SECTION */
8417 /******************************************************************/
8418 static void elink_8726_config_loopback(struct elink_phy
*phy
,
8419 struct elink_params
*params
)
8421 struct bnx2x_softc
*sc
= params
->sc
;
8422 PMD_DRV_LOG(DEBUG
, "PMA/PMD ext_phy_loopback: 8726");
8423 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x0001);
8426 static void elink_8726_external_rom_boot(struct elink_phy
*phy
,
8427 struct elink_params
*params
)
8429 struct bnx2x_softc
*sc
= params
->sc
;
8430 /* Need to wait 100ms after reset */
8433 /* Micro controller re-boot */
8434 elink_cl45_write(sc
, phy
,
8435 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x018B);
8437 /* Set soft reset */
8438 elink_cl45_write(sc
, phy
,
8440 MDIO_PMA_REG_GEN_CTRL
,
8441 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
8443 elink_cl45_write(sc
, phy
,
8444 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
8446 elink_cl45_write(sc
, phy
,
8448 MDIO_PMA_REG_GEN_CTRL
,
8449 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
8451 /* Wait for 150ms for microcode load */
8454 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8455 elink_cl45_write(sc
, phy
,
8456 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
8459 elink_save_bnx2x_spirom_ver(sc
, phy
, params
->port
);
8462 static uint8_t elink_8726_read_status(struct elink_phy
*phy
,
8463 struct elink_params
*params
,
8464 struct elink_vars
*vars
)
8466 struct bnx2x_softc
*sc
= params
->sc
;
8468 uint8_t link_up
= elink_8706_8726_read_status(phy
, params
, vars
);
8470 elink_cl45_read(sc
, phy
,
8471 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
,
8473 if (val1
& (1 << 15)) {
8474 PMD_DRV_LOG(DEBUG
, "Tx is disabled");
8476 vars
->line_speed
= 0;
8482 static uint8_t elink_8726_config_init(struct elink_phy
*phy
,
8483 struct elink_params
*params
,
8484 struct elink_vars
*vars
)
8486 struct bnx2x_softc
*sc
= params
->sc
;
8487 PMD_DRV_LOG(DEBUG
, "Initializing BNX2X8726");
8489 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1 << 15);
8490 elink_wait_reset_complete(sc
, phy
, params
);
8492 elink_8726_external_rom_boot(phy
, params
);
8494 /* Need to call module detected on initialization since the module
8495 * detection triggered by actual module insertion might occur before
8496 * driver is loaded, and when driver is loaded, it reset all
8497 * registers, including the transmitter
8499 elink_sfp_module_detection(phy
, params
);
8501 if (phy
->req_line_speed
== ELINK_SPEED_1000
) {
8502 PMD_DRV_LOG(DEBUG
, "Setting 1G force");
8503 elink_cl45_write(sc
, phy
,
8504 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x40);
8505 elink_cl45_write(sc
, phy
,
8506 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, 0xD);
8507 elink_cl45_write(sc
, phy
,
8508 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x5);
8509 elink_cl45_write(sc
, phy
,
8510 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
, 0x400);
8511 } else if ((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
8512 (phy
->speed_cap_mask
&
8513 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
) &&
8514 ((phy
->speed_cap_mask
&
8515 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
) !=
8516 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
8517 PMD_DRV_LOG(DEBUG
, "Setting 1G clause37");
8518 /* Set Flow control */
8519 elink_ext_phy_set_pause(params
, phy
, vars
);
8520 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV
, 0x20);
8521 elink_cl45_write(sc
, phy
,
8522 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_CL73
, 0x040c);
8523 elink_cl45_write(sc
, phy
,
8524 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, 0x0020);
8525 elink_cl45_write(sc
, phy
,
8526 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1000);
8527 elink_cl45_write(sc
, phy
,
8528 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x1200);
8529 /* Enable RX-ALARM control to receive interrupt for 1G speed
8532 elink_cl45_write(sc
, phy
,
8533 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x4);
8534 elink_cl45_write(sc
, phy
,
8535 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
, 0x400);
8537 } else { /* Default 10G. Set only LASI control */
8538 elink_cl45_write(sc
, phy
,
8539 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 1);
8542 /* Set TX PreEmphasis if needed */
8543 if ((params
->feature_config_flags
&
8544 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
8546 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8547 phy
->tx_preemphasis
[0], phy
->tx_preemphasis
[1]);
8548 elink_cl45_write(sc
, phy
,
8550 MDIO_PMA_REG_8726_TX_CTRL1
,
8551 phy
->tx_preemphasis
[0]);
8553 elink_cl45_write(sc
, phy
,
8555 MDIO_PMA_REG_8726_TX_CTRL2
,
8556 phy
->tx_preemphasis
[1]);
8559 return ELINK_STATUS_OK
;
8563 static void elink_8726_link_reset(struct elink_phy
*phy
,
8564 struct elink_params
*params
)
8566 struct bnx2x_softc
*sc
= params
->sc
;
8567 PMD_DRV_LOG(DEBUG
, "elink_8726_link_reset port %d", params
->port
);
8568 /* Set serial boot control for external load */
8569 elink_cl45_write(sc
, phy
,
8570 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x0001);
8573 /******************************************************************/
8574 /* BNX2X8727 PHY SECTION */
8575 /******************************************************************/
8577 static void elink_8727_set_link_led(struct elink_phy
*phy
,
8578 struct elink_params
*params
, uint8_t mode
)
8580 struct bnx2x_softc
*sc
= params
->sc
;
8581 uint16_t led_mode_bitmask
= 0;
8582 uint16_t gpio_pins_bitmask
= 0;
8584 /* Only NOC flavor requires to set the LED specifically */
8585 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
8588 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
8589 case ELINK_LED_MODE_OFF
:
8590 led_mode_bitmask
= 0;
8591 gpio_pins_bitmask
= 0x03;
8593 case ELINK_LED_MODE_ON
:
8594 led_mode_bitmask
= 0;
8595 gpio_pins_bitmask
= 0x02;
8597 case ELINK_LED_MODE_OPER
:
8598 led_mode_bitmask
= 0x60;
8599 gpio_pins_bitmask
= 0x11;
8602 elink_cl45_read(sc
, phy
,
8603 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_PCS_OPT_CTRL
, &val
);
8605 val
|= led_mode_bitmask
;
8606 elink_cl45_write(sc
, phy
,
8607 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_PCS_OPT_CTRL
, val
);
8608 elink_cl45_read(sc
, phy
,
8609 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_GPIO_CTRL
, &val
);
8611 val
|= gpio_pins_bitmask
;
8612 elink_cl45_write(sc
, phy
,
8613 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_GPIO_CTRL
, val
);
8616 static void elink_8727_hw_reset(__rte_unused
struct elink_phy
*phy
,
8617 struct elink_params
*params
)
8619 uint32_t swap_val
, swap_override
;
8621 /* The PHY reset is controlled by GPIO 1. Fake the port number
8622 * to cancel the swap done in set_gpio()
8624 struct bnx2x_softc
*sc
= params
->sc
;
8625 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
8626 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
8627 port
= (swap_val
&& swap_override
) ^ 1;
8628 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_1
,
8629 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
8632 static void elink_8727_config_speed(struct elink_phy
*phy
,
8633 struct elink_params
*params
)
8635 struct bnx2x_softc
*sc
= params
->sc
;
8637 /* Set option 1G speed */
8638 if ((phy
->req_line_speed
== ELINK_SPEED_1000
) ||
8639 (phy
->media_type
== ELINK_ETH_PHY_SFP_1G_FIBER
)) {
8640 PMD_DRV_LOG(DEBUG
, "Setting 1G force");
8641 elink_cl45_write(sc
, phy
,
8642 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x40);
8643 elink_cl45_write(sc
, phy
,
8644 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, 0xD);
8645 elink_cl45_read(sc
, phy
,
8646 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, &tmp1
);
8647 PMD_DRV_LOG(DEBUG
, "1.7 = 0x%x", tmp1
);
8648 /* Power down the XAUI until link is up in case of dual-media
8651 if (ELINK_DUAL_MEDIA(params
)) {
8652 elink_cl45_read(sc
, phy
,
8654 MDIO_PMA_REG_8727_PCS_GP
, &val
);
8656 elink_cl45_write(sc
, phy
,
8658 MDIO_PMA_REG_8727_PCS_GP
, val
);
8660 } else if ((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
8661 ((phy
->speed_cap_mask
&
8662 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) &&
8663 ((phy
->speed_cap_mask
&
8664 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
) !=
8665 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
8667 PMD_DRV_LOG(DEBUG
, "Setting 1G clause37");
8668 elink_cl45_write(sc
, phy
,
8669 MDIO_AN_DEVAD
, MDIO_AN_REG_8727_MISC_CTRL
, 0);
8670 elink_cl45_write(sc
, phy
,
8671 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1300);
8673 /* Since the 8727 has only single reset pin, need to set the 10G
8674 * registers although it is default
8676 elink_cl45_write(sc
, phy
,
8677 MDIO_AN_DEVAD
, MDIO_AN_REG_8727_MISC_CTRL
,
8679 elink_cl45_write(sc
, phy
,
8680 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x0100);
8681 elink_cl45_write(sc
, phy
,
8682 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x2040);
8683 elink_cl45_write(sc
, phy
,
8684 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
,
8689 static uint8_t elink_8727_config_init(struct elink_phy
*phy
,
8690 struct elink_params
*params
,
8691 __rte_unused
struct elink_vars
8694 uint32_t tx_en_mode
;
8695 uint16_t tmp1
, mod_abs
, tmp2
;
8696 struct bnx2x_softc
*sc
= params
->sc
;
8697 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8699 elink_wait_reset_complete(sc
, phy
, params
);
8701 PMD_DRV_LOG(DEBUG
, "Initializing BNX2X8727");
8703 elink_8727_specific_func(phy
, params
, ELINK_PHY_INIT
);
8704 /* Initially configure MOD_ABS to interrupt when module is
8707 elink_cl45_read(sc
, phy
,
8708 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
, &mod_abs
);
8709 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
8710 * When the EDC is off it locks onto a reference clock and avoids
8713 mod_abs
&= ~(1 << 8);
8714 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
8715 mod_abs
&= ~(1 << 9);
8716 elink_cl45_write(sc
, phy
,
8717 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
8719 /* Enable/Disable PHY transmitter output */
8720 elink_set_disable_pmd_transmit(params
, phy
, 0);
8722 elink_8727_power_module(sc
, phy
, 1);
8724 elink_cl45_read(sc
, phy
,
8725 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &tmp1
);
8727 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &tmp1
);
8729 elink_8727_config_speed(phy
, params
);
8731 /* Set TX PreEmphasis if needed */
8732 if ((params
->feature_config_flags
&
8733 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
8734 PMD_DRV_LOG(DEBUG
, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x",
8735 phy
->tx_preemphasis
[0], phy
->tx_preemphasis
[1]);
8736 elink_cl45_write(sc
, phy
,
8737 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_TX_CTRL1
,
8738 phy
->tx_preemphasis
[0]);
8740 elink_cl45_write(sc
, phy
,
8741 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_TX_CTRL2
,
8742 phy
->tx_preemphasis
[1]);
8745 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8746 * power mode, if TX Laser is disabled
8748 tx_en_mode
= REG_RD(sc
, params
->shmem_base
+
8749 offsetof(struct shmem_region
,
8750 dev_info
.port_hw_config
[params
->port
].
8752 & PORT_HW_CFG_TX_LASER_MASK
;
8754 if (tx_en_mode
== PORT_HW_CFG_TX_LASER_GPIO0
) {
8756 PMD_DRV_LOG(DEBUG
, "Enabling TXONOFF_PWRDN_DIS");
8757 elink_cl45_read(sc
, phy
,
8758 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_OPT_CFG_REG
,
8762 elink_cl45_write(sc
, phy
,
8763 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_OPT_CFG_REG
,
8765 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8766 MDIO_PMA_REG_PHY_IDENTIFIER
, &tmp2
);
8767 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
,
8768 MDIO_PMA_REG_PHY_IDENTIFIER
, (tmp2
& 0x7fff));
8771 return ELINK_STATUS_OK
;
8774 static void elink_8727_handle_mod_abs(struct elink_phy
*phy
,
8775 struct elink_params
*params
)
8777 struct bnx2x_softc
*sc
= params
->sc
;
8778 uint16_t mod_abs
, rx_alarm_status
;
8779 uint32_t val
= REG_RD(sc
, params
->shmem_base
+
8780 offsetof(struct shmem_region
,
8781 dev_info
.port_feature_config
[params
->
8783 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
,
8785 if (mod_abs
& (1 << 8)) {
8787 /* Module is absent */
8788 PMD_DRV_LOG(DEBUG
, "MOD_ABS indication show module is absent");
8789 phy
->media_type
= ELINK_ETH_PHY_NOT_PRESENT
;
8790 /* 1. Set mod_abs to detect next module
8792 * 2. Set EDC off by setting OPTXLOS signal input to low
8794 * When the EDC is off it locks onto a reference clock and
8795 * avoids becoming 'lost'.
8797 mod_abs
&= ~(1 << 8);
8798 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
8799 mod_abs
&= ~(1 << 9);
8800 elink_cl45_write(sc
, phy
,
8802 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
8804 /* Clear RX alarm since it stays up as long as
8805 * the mod_abs wasn't changed
8807 elink_cl45_read(sc
, phy
,
8809 MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
8812 /* Module is present */
8813 PMD_DRV_LOG(DEBUG
, "MOD_ABS indication show module is present");
8814 /* First disable transmitter, and if the module is ok, the
8815 * module_detection will enable it
8816 * 1. Set mod_abs to detect next module absent event ( bit 8)
8817 * 2. Restore the default polarity of the OPRXLOS signal and
8818 * this signal will then correctly indicate the presence or
8819 * absence of the Rx signal. (bit 9)
8821 mod_abs
|= (1 << 8);
8822 if (!(phy
->flags
& ELINK_FLAGS_NOC
))
8823 mod_abs
|= (1 << 9);
8824 elink_cl45_write(sc
, phy
,
8826 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
8828 /* Clear RX alarm since it stays up as long as the mod_abs
8829 * wasn't changed. This is need to be done before calling the
8830 * module detection, otherwise it will clear* the link update
8833 elink_cl45_read(sc
, phy
,
8835 MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
8837 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
8838 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
8839 elink_sfp_set_transmitter(params
, phy
, 0);
8841 if (elink_wait_for_sfp_module_initialized(phy
, params
) == 0) {
8842 elink_sfp_module_detection(phy
, params
);
8844 PMD_DRV_LOG(DEBUG
, "SFP+ module is not initialized");
8847 /* Reconfigure link speed based on module type limitations */
8848 elink_8727_config_speed(phy
, params
);
8851 PMD_DRV_LOG(DEBUG
, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status
);
8852 /* No need to check link status in case of module plugged in/out */
8855 static uint8_t elink_8727_read_status(struct elink_phy
*phy
,
8856 struct elink_params
*params
,
8857 struct elink_vars
*vars
)
8859 struct bnx2x_softc
*sc
= params
->sc
;
8860 uint8_t link_up
= 0, oc_port
= params
->port
;
8861 uint16_t link_status
= 0;
8862 uint16_t rx_alarm_status
, lasi_ctrl
, val1
;
8864 /* If PHY is not initialized, do not check link status */
8865 elink_cl45_read(sc
, phy
,
8866 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, &lasi_ctrl
);
8870 /* Check the LASI on Rx */
8871 elink_cl45_read(sc
, phy
,
8872 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
8873 vars
->line_speed
= 0;
8874 PMD_DRV_LOG(DEBUG
, "8727 RX_ALARM_STATUS 0x%x", rx_alarm_status
);
8876 elink_sfp_mask_fault(sc
, phy
, MDIO_PMA_LASI_TXSTAT
,
8877 MDIO_PMA_LASI_TXCTRL
);
8879 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
8881 PMD_DRV_LOG(DEBUG
, "8727 LASI status 0x%x", val1
);
8884 elink_cl45_read(sc
, phy
,
8885 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &val1
);
8887 /* If a module is present and there is need to check
8890 if (!(phy
->flags
& ELINK_FLAGS_NOC
) && !(rx_alarm_status
& (1 << 5))) {
8891 /* Check over-current using 8727 GPIO0 input */
8892 elink_cl45_read(sc
, phy
,
8893 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_GPIO_CTRL
,
8896 if ((val1
& (1 << 8)) == 0) {
8897 if (!CHIP_IS_E1x(sc
))
8898 oc_port
= SC_PATH(sc
) + (params
->port
<< 1);
8900 "8727 Power fault has been detected on port %d",
8902 elink_cb_event_log(sc
, ELINK_LOG_ID_OVER_CURRENT
, oc_port
); //"Error: Power fault on Port %d has "
8903 // "been detected and the power to "
8904 // "that SFP+ module has been removed "
8905 // "to prevent failure of the card. "
8906 // "Please remove the SFP+ module and "
8907 // "restart the system to clear this "
8909 /* Disable all RX_ALARMs except for mod_abs */
8910 elink_cl45_write(sc
, phy
,
8912 MDIO_PMA_LASI_RXCTRL
, (1 << 5));
8914 elink_cl45_read(sc
, phy
,
8916 MDIO_PMA_REG_PHY_IDENTIFIER
, &val1
);
8917 /* Wait for module_absent_event */
8919 elink_cl45_write(sc
, phy
,
8921 MDIO_PMA_REG_PHY_IDENTIFIER
, val1
);
8922 /* Clear RX alarm */
8923 elink_cl45_read(sc
, phy
,
8925 MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
8926 elink_8727_power_module(params
->sc
, phy
, 0);
8931 /* Over current check */
8932 /* When module absent bit is set, check module */
8933 if (rx_alarm_status
& (1 << 5)) {
8934 elink_8727_handle_mod_abs(phy
, params
);
8935 /* Enable all mod_abs and link detection bits */
8936 elink_cl45_write(sc
, phy
,
8937 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
8938 ((1 << 5) | (1 << 2)));
8941 if (!(phy
->flags
& ELINK_FLAGS_SFP_NOT_APPROVED
)) {
8942 PMD_DRV_LOG(DEBUG
, "Enabling 8727 TX laser");
8943 elink_sfp_set_transmitter(params
, phy
, 1);
8945 PMD_DRV_LOG(DEBUG
, "Tx is disabled");
8949 elink_cl45_read(sc
, phy
,
8951 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
, &link_status
);
8953 /* Bits 0..2 --> speed detected,
8954 * Bits 13..15--> link is down
8956 if ((link_status
& (1 << 2)) && (!(link_status
& (1 << 15)))) {
8958 vars
->line_speed
= ELINK_SPEED_10000
;
8959 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 10G",
8961 } else if ((link_status
& (1 << 0)) && (!(link_status
& (1 << 13)))) {
8963 vars
->line_speed
= ELINK_SPEED_1000
;
8964 PMD_DRV_LOG(DEBUG
, "port %x: External link up in 1G",
8968 PMD_DRV_LOG(DEBUG
, "port %x: External link is down",
8972 /* Capture 10G link fault. */
8973 if (vars
->line_speed
== ELINK_SPEED_10000
) {
8974 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8975 MDIO_PMA_LASI_TXSTAT
, &val1
);
8977 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
,
8978 MDIO_PMA_LASI_TXSTAT
, &val1
);
8980 if (val1
& (1 << 0)) {
8981 vars
->fault_detected
= 1;
8986 elink_ext_phy_resolve_fc(phy
, params
, vars
);
8987 vars
->duplex
= DUPLEX_FULL
;
8988 PMD_DRV_LOG(DEBUG
, "duplex = 0x%x", vars
->duplex
);
8991 if ((ELINK_DUAL_MEDIA(params
)) &&
8992 (phy
->req_line_speed
== ELINK_SPEED_1000
)) {
8993 elink_cl45_read(sc
, phy
,
8995 MDIO_PMA_REG_8727_PCS_GP
, &val1
);
8996 /* In case of dual-media board and 1G, power up the XAUI side,
8997 * otherwise power it down. For 10G it is done automatically
9003 elink_cl45_write(sc
, phy
,
9005 MDIO_PMA_REG_8727_PCS_GP
, val1
);
9010 static void elink_8727_link_reset(struct elink_phy
*phy
,
9011 struct elink_params
*params
)
9013 struct bnx2x_softc
*sc
= params
->sc
;
9015 /* Enable/Disable PHY transmitter output */
9016 elink_set_disable_pmd_transmit(params
, phy
, 1);
9018 /* Disable Transmitter */
9019 elink_sfp_set_transmitter(params
, phy
, 0);
9021 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0);
9025 /******************************************************************/
9026 /* BNX2X8481/BNX2X84823/BNX2X84833 PHY SECTION */
9027 /******************************************************************/
9028 static void elink_save_848xx_spirom_version(struct elink_phy
*phy
,
9029 struct bnx2x_softc
*sc
, uint8_t port
)
9031 uint16_t val
, fw_ver2
, cnt
, i
;
9032 static struct elink_reg_set reg_set
[] = {
9033 {MDIO_PMA_DEVAD
, 0xA819, 0x0014},
9034 {MDIO_PMA_DEVAD
, 0xA81A, 0xc200},
9035 {MDIO_PMA_DEVAD
, 0xA81B, 0x0000},
9036 {MDIO_PMA_DEVAD
, 0xA81C, 0x0300},
9037 {MDIO_PMA_DEVAD
, 0xA817, 0x0009}
9041 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9042 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9043 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
, 0x400f, &fw_ver1
);
9044 elink_save_spirom_version(sc
, port
, fw_ver1
& 0xfff,
9047 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9048 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9049 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
9050 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
,
9051 reg_set
[i
].reg
, reg_set
[i
].val
);
9053 for (cnt
= 0; cnt
< 100; cnt
++) {
9054 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xA818, &val
);
9060 PMD_DRV_LOG(DEBUG
, "Unable to read 848xx "
9061 "phy fw version(1)");
9062 elink_save_spirom_version(sc
, port
, 0, phy
->ver_addr
);
9066 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9067 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, 0xA819, 0x0000);
9068 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, 0xA81A, 0xc200);
9069 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, 0xA817, 0x000A);
9070 for (cnt
= 0; cnt
< 100; cnt
++) {
9071 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xA818, &val
);
9077 PMD_DRV_LOG(DEBUG
, "Unable to read 848xx phy fw "
9079 elink_save_spirom_version(sc
, port
, 0, phy
->ver_addr
);
9083 /* lower 16 bits of the register SPI_FW_STATUS */
9084 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xA81B, &fw_ver1
);
9085 /* upper 16 bits of register SPI_FW_STATUS */
9086 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, 0xA81C, &fw_ver2
);
9088 elink_save_spirom_version(sc
, port
, (fw_ver2
<< 16) | fw_ver1
,
9094 static void elink_848xx_set_led(struct bnx2x_softc
*sc
, struct elink_phy
*phy
)
9096 uint16_t val
, offset
, i
;
9097 static struct elink_reg_set reg_set
[] = {
9098 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LED1_MASK
, 0x0080},
9099 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LED2_MASK
, 0x0018},
9100 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LED3_MASK
, 0x0006},
9101 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LED3_BLINK
, 0x0000},
9102 {MDIO_PMA_DEVAD
, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH
,
9103 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ
},
9104 {MDIO_AN_DEVAD
, 0xFFFB, 0xFFFD}
9106 /* PHYC_CTL_LED_CTL */
9107 elink_cl45_read(sc
, phy
,
9108 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LINK_SIGNAL
, &val
);
9112 elink_cl45_write(sc
, phy
,
9113 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_LINK_SIGNAL
, val
);
9115 for (i
= 0; i
< ARRAY_SIZE(reg_set
); i
++)
9116 elink_cl45_write(sc
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
9119 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9120 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
))
9121 offset
= MDIO_PMA_REG_84833_CTL_LED_CTL_1
;
9123 offset
= MDIO_PMA_REG_84823_CTL_LED_CTL_1
;
9125 /* stretch_en for LED3 */
9126 elink_cl45_read_or_write(sc
, phy
,
9127 MDIO_PMA_DEVAD
, offset
,
9128 MDIO_PMA_REG_84823_LED3_STRETCH_EN
);
9131 static void elink_848xx_specific_func(struct elink_phy
*phy
,
9132 struct elink_params
*params
,
9135 struct bnx2x_softc
*sc
= params
->sc
;
9137 case ELINK_PHY_INIT
:
9138 if ((phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) &&
9139 (phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9140 /* Save spirom version */
9141 elink_save_848xx_spirom_version(phy
, sc
, params
->port
);
9143 /* This phy uses the NIG latch mechanism since link indication
9144 * arrives through its LED4 and not via its LASI signal, so we
9145 * get steady signal instead of clear on read
9147 elink_bits_en(sc
, NIG_REG_LATCH_BC_0
+ params
->port
* 4,
9148 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT
);
9150 elink_848xx_set_led(sc
, phy
);
9155 static elink_status_t
elink_848xx_cmn_config_init(struct elink_phy
*phy
,
9156 struct elink_params
*params
,
9157 struct elink_vars
*vars
)
9159 struct bnx2x_softc
*sc
= params
->sc
;
9160 uint16_t autoneg_val
, an_1000_val
, an_10_100_val
;
9162 elink_848xx_specific_func(phy
, params
, ELINK_PHY_INIT
);
9163 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x0000);
9165 /* set 1000 speed advertisement */
9166 elink_cl45_read(sc
, phy
,
9167 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_1000T_CTRL
,
9170 elink_ext_phy_set_pause(params
, phy
, vars
);
9171 elink_cl45_read(sc
, phy
,
9173 MDIO_AN_REG_8481_LEGACY_AN_ADV
, &an_10_100_val
);
9174 elink_cl45_read(sc
, phy
,
9175 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
9177 /* Disable forced speed */
9179 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
9180 an_10_100_val
&= ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8));
9182 if (((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
9183 (phy
->speed_cap_mask
&
9184 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
9185 (phy
->req_line_speed
== ELINK_SPEED_1000
)) {
9186 an_1000_val
|= (1 << 8);
9187 autoneg_val
|= (1 << 9 | 1 << 12);
9188 if (phy
->req_duplex
== DUPLEX_FULL
)
9189 an_1000_val
|= (1 << 9);
9190 PMD_DRV_LOG(DEBUG
, "Advertising 1G");
9192 an_1000_val
&= ~((1 << 8) | (1 << 9));
9194 elink_cl45_write(sc
, phy
,
9195 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_1000T_CTRL
,
9198 /* Set 10/100 speed advertisement */
9199 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) {
9200 if (phy
->speed_cap_mask
&
9201 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
) {
9202 /* Enable autoneg and restart autoneg for legacy speeds
9204 autoneg_val
|= (1 << 9 | 1 << 12);
9205 an_10_100_val
|= (1 << 8);
9206 PMD_DRV_LOG(DEBUG
, "Advertising 100M-FD");
9209 if (phy
->speed_cap_mask
&
9210 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
) {
9211 /* Enable autoneg and restart autoneg for legacy speeds
9213 autoneg_val
|= (1 << 9 | 1 << 12);
9214 an_10_100_val
|= (1 << 7);
9215 PMD_DRV_LOG(DEBUG
, "Advertising 100M-HD");
9218 if ((phy
->speed_cap_mask
&
9219 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
) &&
9220 (phy
->supported
& ELINK_SUPPORTED_10baseT_Full
)) {
9221 an_10_100_val
|= (1 << 6);
9222 autoneg_val
|= (1 << 9 | 1 << 12);
9223 PMD_DRV_LOG(DEBUG
, "Advertising 10M-FD");
9226 if ((phy
->speed_cap_mask
&
9227 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
) &&
9228 (phy
->supported
& ELINK_SUPPORTED_10baseT_Half
)) {
9229 an_10_100_val
|= (1 << 5);
9230 autoneg_val
|= (1 << 9 | 1 << 12);
9231 PMD_DRV_LOG(DEBUG
, "Advertising 10M-HD");
9235 /* Only 10/100 are allowed to work in FORCE mode */
9236 if ((phy
->req_line_speed
== ELINK_SPEED_100
) &&
9238 (ELINK_SUPPORTED_100baseT_Half
| ELINK_SUPPORTED_100baseT_Full
))) {
9239 autoneg_val
|= (1 << 13);
9240 /* Enabled AUTO-MDIX when autoneg is disabled */
9241 elink_cl45_write(sc
, phy
,
9242 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_AUX_CTRL
,
9243 (1 << 15 | 1 << 9 | 7 << 0));
9244 /* The PHY needs this set even for forced link. */
9245 an_10_100_val
|= (1 << 8) | (1 << 7);
9246 PMD_DRV_LOG(DEBUG
, "Setting 100M force");
9248 if ((phy
->req_line_speed
== ELINK_SPEED_10
) &&
9250 (ELINK_SUPPORTED_10baseT_Half
| ELINK_SUPPORTED_10baseT_Full
))) {
9251 /* Enabled AUTO-MDIX when autoneg is disabled */
9252 elink_cl45_write(sc
, phy
,
9253 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_AUX_CTRL
,
9254 (1 << 15 | 1 << 9 | 7 << 0));
9255 PMD_DRV_LOG(DEBUG
, "Setting 10M force");
9258 elink_cl45_write(sc
, phy
,
9259 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_LEGACY_AN_ADV
,
9262 if (phy
->req_duplex
== DUPLEX_FULL
)
9263 autoneg_val
|= (1 << 8);
9265 /* Always write this if this is not 84833/4.
9266 * For 84833/4, write it only when it's a forced speed.
9268 if (((phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) &&
9269 (phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) ||
9270 ((autoneg_val
& (1 << 12)) == 0))
9271 elink_cl45_write(sc
, phy
,
9273 MDIO_AN_REG_8481_LEGACY_MII_CTRL
, autoneg_val
);
9275 if (((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
9276 (phy
->speed_cap_mask
&
9277 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) ||
9278 (phy
->req_line_speed
== ELINK_SPEED_10000
)) {
9279 PMD_DRV_LOG(DEBUG
, "Advertising 10G");
9280 /* Restart autoneg for 10G */
9282 elink_cl45_read_or_write(sc
, phy
,
9284 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL
,
9286 elink_cl45_write(sc
, phy
,
9287 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x3200);
9289 elink_cl45_write(sc
, phy
,
9291 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL
, 1);
9293 return ELINK_STATUS_OK
;
9296 static uint8_t elink_8481_config_init(struct elink_phy
*phy
,
9297 struct elink_params
*params
,
9298 struct elink_vars
*vars
)
9300 struct bnx2x_softc
*sc
= params
->sc
;
9301 /* Restore normal power mode */
9302 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
9303 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
9306 elink_ext_phy_hw_reset(sc
, params
->port
);
9307 elink_wait_reset_complete(sc
, phy
, params
);
9309 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1 << 15);
9310 return elink_848xx_cmn_config_init(phy
, params
, vars
);
9313 #define PHY84833_CMDHDLR_WAIT 300
9314 #define PHY84833_CMDHDLR_MAX_ARGS 5
9315 static elink_status_t
elink_84833_cmd_hdlr(struct elink_phy
*phy
,
9316 struct elink_params
*params
,
9317 uint16_t fw_cmd
, uint16_t cmd_args
[],
9322 struct bnx2x_softc
*sc
= params
->sc
;
9323 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9324 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9325 MDIO_84833_CMD_HDLR_STATUS
,
9326 PHY84833_STATUS_CMD_OPEN_OVERRIDE
);
9327 for (idx
= 0; idx
< PHY84833_CMDHDLR_WAIT
; idx
++) {
9328 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9329 MDIO_84833_CMD_HDLR_STATUS
, &val
);
9330 if (val
== PHY84833_STATUS_CMD_OPEN_FOR_CMDS
)
9334 if (idx
>= PHY84833_CMDHDLR_WAIT
) {
9335 PMD_DRV_LOG(DEBUG
, "FW cmd: FW not ready.");
9336 return ELINK_STATUS_ERROR
;
9339 /* Prepare argument(s) and issue command */
9340 for (idx
= 0; idx
< argc
; idx
++) {
9341 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9342 MDIO_84833_CMD_HDLR_DATA1
+ idx
,
9345 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9346 MDIO_84833_CMD_HDLR_COMMAND
, fw_cmd
);
9347 for (idx
= 0; idx
< PHY84833_CMDHDLR_WAIT
; idx
++) {
9348 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9349 MDIO_84833_CMD_HDLR_STATUS
, &val
);
9350 if ((val
== PHY84833_STATUS_CMD_COMPLETE_PASS
) ||
9351 (val
== PHY84833_STATUS_CMD_COMPLETE_ERROR
))
9355 if ((idx
>= PHY84833_CMDHDLR_WAIT
) ||
9356 (val
== PHY84833_STATUS_CMD_COMPLETE_ERROR
)) {
9357 PMD_DRV_LOG(DEBUG
, "FW cmd failed.");
9358 return ELINK_STATUS_ERROR
;
9360 /* Gather returning data */
9361 for (idx
= 0; idx
< argc
; idx
++) {
9362 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9363 MDIO_84833_CMD_HDLR_DATA1
+ idx
,
9366 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9367 MDIO_84833_CMD_HDLR_STATUS
,
9368 PHY84833_STATUS_CMD_CLEAR_COMPLETE
);
9369 return ELINK_STATUS_OK
;
9372 static elink_status_t
elink_84833_pair_swap_cfg(struct elink_phy
*phy
,
9373 struct elink_params
*params
,
9374 __rte_unused
struct elink_vars
9378 uint16_t data
[PHY84833_CMDHDLR_MAX_ARGS
];
9379 elink_status_t status
;
9380 struct bnx2x_softc
*sc
= params
->sc
;
9382 /* Check for configuration. */
9383 pair_swap
= REG_RD(sc
, params
->shmem_base
+
9384 offsetof(struct shmem_region
,
9385 dev_info
.port_hw_config
[params
->port
].
9387 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK
;
9390 return ELINK_STATUS_OK
;
9392 /* Only the second argument is used for this command */
9393 data
[1] = (uint16_t) pair_swap
;
9395 status
= elink_84833_cmd_hdlr(phy
, params
,
9396 PHY84833_CMD_SET_PAIR_SWAP
, data
,
9397 PHY84833_CMDHDLR_MAX_ARGS
);
9398 if (status
== ELINK_STATUS_OK
) {
9399 PMD_DRV_LOG(DEBUG
, "Pairswap OK, val=0x%x", data
[1]);
9405 static uint8_t elink_84833_get_reset_gpios(struct bnx2x_softc
*sc
,
9406 uint32_t shmem_base_path
[],
9407 __rte_unused
uint32_t chip_id
)
9409 uint32_t reset_pin
[2];
9411 uint8_t reset_gpios
;
9412 if (CHIP_IS_E3(sc
)) {
9413 /* Assume that these will be GPIOs, not EPIOs. */
9414 for (idx
= 0; idx
< 2; idx
++) {
9415 /* Map config param to register bit. */
9416 reset_pin
[idx
] = REG_RD(sc
, shmem_base_path
[idx
] +
9417 offsetof(struct shmem_region
,
9422 (reset_pin
[idx
] & PORT_HW_CFG_E3_PHY_RESET_MASK
) >>
9423 PORT_HW_CFG_E3_PHY_RESET_SHIFT
;
9424 reset_pin
[idx
] -= PIN_CFG_GPIO0_P0
;
9425 reset_pin
[idx
] = (1 << reset_pin
[idx
]);
9427 reset_gpios
= (uint8_t) (reset_pin
[0] | reset_pin
[1]);
9429 /* E2, look from diff place of shmem. */
9430 for (idx
= 0; idx
< 2; idx
++) {
9431 reset_pin
[idx
] = REG_RD(sc
, shmem_base_path
[idx
] +
9432 offsetof(struct shmem_region
,
9436 reset_pin
[idx
] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK
;
9437 reset_pin
[idx
] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0
;
9438 reset_pin
[idx
] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT
;
9439 reset_pin
[idx
] = (1 << reset_pin
[idx
]);
9441 reset_gpios
= (uint8_t) (reset_pin
[0] | reset_pin
[1]);
9447 static void elink_84833_hw_reset_phy(struct elink_phy
*phy
,
9448 struct elink_params
*params
)
9450 struct bnx2x_softc
*sc
= params
->sc
;
9451 uint8_t reset_gpios
;
9452 uint32_t other_shmem_base_addr
= REG_RD(sc
, params
->shmem2_base
+
9453 offsetof(struct shmem2_region
,
9454 other_shmem_base_addr
));
9456 uint32_t shmem_base_path
[2];
9458 /* Work around for 84833 LED failure inside RESET status */
9459 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
9460 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
9461 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G
);
9462 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
9463 MDIO_AN_REG_8481_1G_100T_EXT_CTRL
,
9464 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF
);
9466 shmem_base_path
[0] = params
->shmem_base
;
9467 shmem_base_path
[1] = other_shmem_base_addr
;
9469 reset_gpios
= elink_84833_get_reset_gpios(sc
, shmem_base_path
,
9472 elink_cb_gpio_mult_write(sc
, reset_gpios
,
9473 MISC_REGISTERS_GPIO_OUTPUT_LOW
);
9475 PMD_DRV_LOG(DEBUG
, "84833 hw reset on pin values 0x%x", reset_gpios
);
9478 static elink_status_t
elink_8483x_disable_eee(struct elink_phy
*phy
,
9479 struct elink_params
*params
,
9480 struct elink_vars
*vars
)
9483 uint16_t cmd_args
= 0;
9485 PMD_DRV_LOG(DEBUG
, "Don't Advertise 10GBase-T EEE");
9487 /* Prevent Phy from working in EEE and advertising it */
9488 rc
= elink_84833_cmd_hdlr(phy
, params
,
9489 PHY84833_CMD_SET_EEE_MODE
, &cmd_args
, 1);
9490 if (rc
!= ELINK_STATUS_OK
) {
9491 PMD_DRV_LOG(DEBUG
, "EEE disable failed.");
9495 return elink_eee_disable(phy
, params
, vars
);
9498 static elink_status_t
elink_8483x_enable_eee(struct elink_phy
*phy
,
9499 struct elink_params
*params
,
9500 struct elink_vars
*vars
)
9503 uint16_t cmd_args
= 1;
9505 rc
= elink_84833_cmd_hdlr(phy
, params
,
9506 PHY84833_CMD_SET_EEE_MODE
, &cmd_args
, 1);
9507 if (rc
!= ELINK_STATUS_OK
) {
9508 PMD_DRV_LOG(DEBUG
, "EEE enable failed.");
9512 return elink_eee_advertise(phy
, params
, vars
, SHMEM_EEE_10G_ADV
);
9515 #define PHY84833_CONSTANT_LATENCY 1193
9516 static uint8_t elink_848x3_config_init(struct elink_phy
*phy
,
9517 struct elink_params
*params
,
9518 struct elink_vars
*vars
)
9520 struct bnx2x_softc
*sc
= params
->sc
;
9521 uint8_t port
, initialize
= 1;
9523 uint32_t actual_phy_selection
;
9524 uint16_t cmd_args
[PHY84833_CMDHDLR_MAX_ARGS
];
9525 elink_status_t rc
= ELINK_STATUS_OK
;
9529 if (!(CHIP_IS_E1x(sc
)))
9532 port
= params
->port
;
9534 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
) {
9535 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_3
,
9536 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
9539 elink_cl45_write(sc
, phy
,
9540 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x8000);
9543 elink_wait_reset_complete(sc
, phy
, params
);
9545 /* Wait for GPHY to come out of reset */
9547 if ((phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) &&
9548 (phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9549 /* BNX2X84823 requires that XGXS links up first @ 10G for normal
9553 temp
= vars
->line_speed
;
9554 vars
->line_speed
= ELINK_SPEED_10000
;
9555 elink_set_autoneg(¶ms
->phy
[ELINK_INT_PHY
], params
, vars
, 0);
9556 elink_program_serdes(¶ms
->phy
[ELINK_INT_PHY
], params
, vars
);
9557 vars
->line_speed
= temp
;
9560 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9561 MDIO_CTL_REG_84823_MEDIA
, &val
);
9562 val
&= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK
|
9563 MDIO_CTL_REG_84823_MEDIA_LINE_MASK
|
9564 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN
|
9565 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK
|
9566 MDIO_CTL_REG_84823_MEDIA_FIBER_1G
);
9568 if (CHIP_IS_E3(sc
)) {
9569 val
&= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK
|
9570 MDIO_CTL_REG_84823_MEDIA_LINE_MASK
);
9572 val
|= (MDIO_CTL_REG_84823_CTRL_MAC_XFI
|
9573 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L
);
9576 actual_phy_selection
= elink_phy_selection(params
);
9578 switch (actual_phy_selection
) {
9579 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
:
9580 /* Do nothing. Essentially this is like the priority copper */
9582 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
:
9583 val
|= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER
;
9585 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
:
9586 val
|= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER
;
9588 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
:
9589 /* Do nothing here. The first PHY won't be initialized at all */
9591 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
:
9592 val
|= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN
;
9596 if (params
->phy
[ELINK_EXT_PHY2
].req_line_speed
== ELINK_SPEED_1000
)
9597 val
|= MDIO_CTL_REG_84823_MEDIA_FIBER_1G
;
9599 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9600 MDIO_CTL_REG_84823_MEDIA
, val
);
9601 PMD_DRV_LOG(DEBUG
, "Multi_phy config = 0x%x, Media control = 0x%x",
9602 params
->multi_phy_config
, val
);
9604 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9605 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9606 elink_84833_pair_swap_cfg(phy
, params
, vars
);
9608 /* Keep AutogrEEEn disabled. */
9611 cmd_args
[2] = PHY84833_CONSTANT_LATENCY
+ 1;
9612 cmd_args
[3] = PHY84833_CONSTANT_LATENCY
;
9613 rc
= elink_84833_cmd_hdlr(phy
, params
,
9614 PHY84833_CMD_SET_EEE_MODE
, cmd_args
,
9615 PHY84833_CMDHDLR_MAX_ARGS
);
9616 if (rc
!= ELINK_STATUS_OK
) {
9617 PMD_DRV_LOG(DEBUG
, "Cfg AutogrEEEn failed.");
9621 rc
= elink_848xx_cmn_config_init(phy
, params
, vars
);
9623 elink_save_848xx_spirom_version(phy
, sc
, params
->port
);
9625 /* 84833 PHY has a better feature and doesn't need to support this. */
9626 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
) {
9627 uint32_t cms_enable
= REG_RD(sc
, params
->shmem_base
+
9628 offsetof(struct shmem_region
,
9630 port_hw_config
[params
->
9633 PORT_HW_CFG_ENABLE_CMS_MASK
;
9635 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9636 MDIO_CTL_REG_84823_USER_CTRL_REG
, &val
);
9638 val
|= MDIO_CTL_REG_84823_USER_CTRL_CMS
;
9640 val
&= ~MDIO_CTL_REG_84823_USER_CTRL_CMS
;
9641 elink_cl45_write(sc
, phy
, MDIO_CTL_DEVAD
,
9642 MDIO_CTL_REG_84823_USER_CTRL_REG
, val
);
9645 elink_cl45_read(sc
, phy
, MDIO_CTL_DEVAD
,
9646 MDIO_84833_TOP_CFG_FW_REV
, &val
);
9648 /* Configure EEE support */
9649 if ((val
>= MDIO_84833_TOP_CFG_FW_EEE
) &&
9650 (val
!= MDIO_84833_TOP_CFG_FW_NO_EEE
) &&
9651 elink_eee_has_cap(params
)) {
9652 rc
= elink_eee_initial_config(params
, vars
, SHMEM_EEE_10G_ADV
);
9653 if (rc
!= ELINK_STATUS_OK
) {
9654 PMD_DRV_LOG(DEBUG
, "Failed to configure EEE timers");
9655 elink_8483x_disable_eee(phy
, params
, vars
);
9659 if ((phy
->req_duplex
== DUPLEX_FULL
) &&
9660 (params
->eee_mode
& ELINK_EEE_MODE_ADV_LPI
) &&
9661 (elink_eee_calc_timer(params
) ||
9662 !(params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
)))
9663 rc
= elink_8483x_enable_eee(phy
, params
, vars
);
9665 rc
= elink_8483x_disable_eee(phy
, params
, vars
);
9666 if (rc
!= ELINK_STATUS_OK
) {
9667 PMD_DRV_LOG(DEBUG
, "Failed to set EEE advertisement");
9671 vars
->eee_status
&= ~SHMEM_EEE_SUPPORTED_MASK
;
9674 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9675 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) {
9676 /* Bring PHY out of super isolate mode as the final step. */
9677 elink_cl45_read_and_write(sc
, phy
,
9679 MDIO_84833_TOP_CFG_XGPHY_STRAP1
,
9681 MDIO_84833_SUPER_ISOLATE
);
9686 static uint8_t elink_848xx_read_status(struct elink_phy
*phy
,
9687 struct elink_params
*params
,
9688 struct elink_vars
*vars
)
9690 struct bnx2x_softc
*sc
= params
->sc
;
9691 uint16_t val
, val1
, val2
;
9692 uint8_t link_up
= 0;
9694 /* Check 10G-BaseT link status */
9695 /* Check PMD signal ok */
9696 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, 0xFFFA, &val1
);
9697 elink_cl45_read(sc
, phy
,
9698 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_PMD_SIGNAL
, &val2
);
9699 PMD_DRV_LOG(DEBUG
, "BNX2X848xx: PMD_SIGNAL 1.a811 = 0x%x", val2
);
9701 /* Check link 10G */
9702 if (val2
& (1 << 11)) {
9703 vars
->line_speed
= ELINK_SPEED_10000
;
9704 vars
->duplex
= DUPLEX_FULL
;
9706 elink_ext_phy_10G_an_resolve(sc
, phy
, vars
);
9707 } else { /* Check Legacy speed link */
9708 uint16_t legacy_status
, legacy_speed
, mii_ctrl
;
9710 /* Enable expansion register 0x42 (Operation mode status) */
9711 elink_cl45_write(sc
, phy
,
9713 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS
, 0xf42);
9715 /* Get legacy speed operation status */
9716 elink_cl45_read(sc
, phy
,
9718 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW
,
9721 PMD_DRV_LOG(DEBUG
, "Legacy speed status = 0x%x", legacy_status
);
9722 link_up
= ((legacy_status
& (1 << 11)) == (1 << 11));
9723 legacy_speed
= (legacy_status
& (3 << 9));
9724 if (legacy_speed
== (0 << 9))
9725 vars
->line_speed
= ELINK_SPEED_10
;
9726 else if (legacy_speed
== (1 << 9))
9727 vars
->line_speed
= ELINK_SPEED_100
;
9728 else if (legacy_speed
== (2 << 9))
9729 vars
->line_speed
= ELINK_SPEED_1000
;
9730 else { /* Should not happen: Treat as link down */
9731 vars
->line_speed
= 0;
9735 if (params
->feature_config_flags
&
9736 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST
) {
9737 elink_cl45_read(sc
, phy
,
9739 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
9741 /* For IEEE testing, check for a fake link. */
9742 link_up
|= ((mii_ctrl
& 0x3040) == 0x40);
9746 if (legacy_status
& (1 << 8))
9747 vars
->duplex
= DUPLEX_FULL
;
9749 vars
->duplex
= DUPLEX_HALF
;
9752 "Link is up in %dMbps, is_duplex_full= %d",
9754 (vars
->duplex
== DUPLEX_FULL
));
9755 /* Check legacy speed AN resolution */
9756 elink_cl45_read(sc
, phy
,
9758 MDIO_AN_REG_8481_LEGACY_MII_STATUS
,
9761 vars
->link_status
|=
9762 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
9763 elink_cl45_read(sc
, phy
,
9765 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION
,
9767 if ((val
& (1 << 0)) == 0)
9768 vars
->link_status
|=
9769 LINK_STATUS_PARALLEL_DETECTION_USED
;
9773 PMD_DRV_LOG(DEBUG
, "BNX2X848x3: link speed is %d",
9775 elink_ext_phy_resolve_fc(phy
, params
, vars
);
9777 /* Read LP advertised speeds */
9778 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
9779 MDIO_AN_REG_CL37_FC_LP
, &val
);
9781 vars
->link_status
|=
9782 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE
;
9784 vars
->link_status
|=
9785 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE
;
9787 vars
->link_status
|=
9788 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE
;
9790 vars
->link_status
|=
9791 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE
;
9793 vars
->link_status
|=
9794 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE
;
9796 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
9797 MDIO_AN_REG_1000T_STATUS
, &val
);
9799 if (val
& (1 << 10))
9800 vars
->link_status
|=
9801 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE
;
9802 if (val
& (1 << 11))
9803 vars
->link_status
|=
9804 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
9806 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
9807 MDIO_AN_REG_MASTER_STATUS
, &val
);
9809 if (val
& (1 << 11))
9810 vars
->link_status
|=
9811 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
9813 /* Determine if EEE was negotiated */
9814 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
9815 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
))
9816 elink_eee_an_resolve(phy
, params
, vars
);
9822 static uint8_t elink_848xx_format_ver(uint32_t raw_ver
, uint8_t * str
,
9825 elink_status_t status
= ELINK_STATUS_OK
;
9826 uint32_t spirom_ver
;
9827 spirom_ver
= ((raw_ver
& 0xF80) >> 7) << 16 | (raw_ver
& 0x7F);
9828 status
= elink_format_ver(spirom_ver
, str
, len
);
9832 static void elink_8481_hw_reset(__rte_unused
struct elink_phy
*phy
,
9833 struct elink_params
*params
)
9835 elink_cb_gpio_write(params
->sc
, MISC_REGISTERS_GPIO_1
,
9836 MISC_REGISTERS_GPIO_OUTPUT_LOW
, 0);
9837 elink_cb_gpio_write(params
->sc
, MISC_REGISTERS_GPIO_1
,
9838 MISC_REGISTERS_GPIO_OUTPUT_LOW
, 1);
9841 static void elink_8481_link_reset(struct elink_phy
*phy
,
9842 struct elink_params
*params
)
9844 elink_cl45_write(params
->sc
, phy
,
9845 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x0000);
9846 elink_cl45_write(params
->sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1);
9849 static void elink_848x3_link_reset(struct elink_phy
*phy
,
9850 struct elink_params
*params
)
9852 struct bnx2x_softc
*sc
= params
->sc
;
9856 if (!(CHIP_IS_E1x(sc
)))
9859 port
= params
->port
;
9861 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
) {
9862 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_3
,
9863 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
9865 elink_cl45_read(sc
, phy
,
9867 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, &val16
);
9868 val16
|= MDIO_84833_SUPER_ISOLATE
;
9869 elink_cl45_write(sc
, phy
,
9871 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, val16
);
9875 static void elink_848xx_set_link_led(struct elink_phy
*phy
,
9876 struct elink_params
*params
, uint8_t mode
)
9878 struct bnx2x_softc
*sc
= params
->sc
;
9880 __rte_unused
uint8_t port
;
9882 if (!(CHIP_IS_E1x(sc
)))
9885 port
= params
->port
;
9888 case ELINK_LED_MODE_OFF
:
9890 PMD_DRV_LOG(DEBUG
, "Port 0x%x: LED MODE OFF", port
);
9892 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
9893 SHARED_HW_CFG_LED_EXTPHY1
) {
9896 elink_cl45_write(sc
, phy
,
9898 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9900 elink_cl45_write(sc
, phy
,
9902 MDIO_PMA_REG_8481_LED2_MASK
, 0x0);
9904 elink_cl45_write(sc
, phy
,
9906 MDIO_PMA_REG_8481_LED3_MASK
, 0x0);
9908 elink_cl45_write(sc
, phy
,
9910 MDIO_PMA_REG_8481_LED5_MASK
, 0x0);
9913 elink_cl45_write(sc
, phy
,
9915 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9918 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
9920 PMD_DRV_LOG(DEBUG
, "Port 0x%x: LED MODE FRONT PANEL OFF", port
);
9922 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
9923 SHARED_HW_CFG_LED_EXTPHY1
) {
9926 elink_cl45_write(sc
, phy
,
9928 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9930 elink_cl45_write(sc
, phy
,
9932 MDIO_PMA_REG_8481_LED2_MASK
, 0x0);
9934 elink_cl45_write(sc
, phy
,
9936 MDIO_PMA_REG_8481_LED3_MASK
, 0x0);
9938 elink_cl45_write(sc
, phy
,
9940 MDIO_PMA_REG_8481_LED5_MASK
, 0x20);
9943 elink_cl45_write(sc
, phy
,
9945 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9946 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
) {
9947 /* Disable MI_INT interrupt before setting LED4
9948 * source to constant off.
9950 if (REG_RD(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+
9952 ELINK_NIG_MASK_MI_INT
) {
9953 params
->link_flags
|=
9954 ELINK_LINK_FLAGS_INT_DISABLED
;
9957 NIG_REG_MASK_INTERRUPT_PORT0
9959 ELINK_NIG_MASK_MI_INT
);
9961 elink_cl45_write(sc
, phy
,
9963 MDIO_PMA_REG_8481_SIGNAL_MASK
,
9968 case ELINK_LED_MODE_ON
:
9970 PMD_DRV_LOG(DEBUG
, "Port 0x%x: LED MODE ON", port
);
9972 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
9973 SHARED_HW_CFG_LED_EXTPHY1
) {
9974 /* Set control reg */
9975 elink_cl45_read(sc
, phy
,
9977 MDIO_PMA_REG_8481_LINK_SIGNAL
, &val
);
9981 elink_cl45_write(sc
, phy
,
9983 MDIO_PMA_REG_8481_LINK_SIGNAL
, val
);
9986 elink_cl45_write(sc
, phy
,
9988 MDIO_PMA_REG_8481_LED1_MASK
, 0x0);
9990 elink_cl45_write(sc
, phy
,
9992 MDIO_PMA_REG_8481_LED2_MASK
, 0x20);
9994 elink_cl45_write(sc
, phy
,
9996 MDIO_PMA_REG_8481_LED3_MASK
, 0x20);
9998 elink_cl45_write(sc
, phy
,
10000 MDIO_PMA_REG_8481_LED5_MASK
, 0x0);
10002 elink_cl45_write(sc
, phy
,
10004 MDIO_PMA_REG_8481_LED1_MASK
, 0x20);
10005 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
) {
10006 /* Disable MI_INT interrupt before setting LED4
10007 * source to constant on.
10009 if (REG_RD(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+
10010 params
->port
* 4) &
10011 ELINK_NIG_MASK_MI_INT
) {
10012 params
->link_flags
|=
10013 ELINK_LINK_FLAGS_INT_DISABLED
;
10016 NIG_REG_MASK_INTERRUPT_PORT0
10017 + params
->port
* 4,
10018 ELINK_NIG_MASK_MI_INT
);
10020 elink_cl45_write(sc
, phy
,
10022 MDIO_PMA_REG_8481_SIGNAL_MASK
,
10028 case ELINK_LED_MODE_OPER
:
10030 PMD_DRV_LOG(DEBUG
, "Port 0x%x: LED MODE OPER", port
);
10032 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
10033 SHARED_HW_CFG_LED_EXTPHY1
) {
10035 /* Set control reg */
10036 elink_cl45_read(sc
, phy
,
10038 MDIO_PMA_REG_8481_LINK_SIGNAL
, &val
);
10041 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK
)
10043 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT
))
10045 PMD_DRV_LOG(DEBUG
, "Setting LINK_SIGNAL");
10046 elink_cl45_write(sc
, phy
,
10048 MDIO_PMA_REG_8481_LINK_SIGNAL
,
10052 /* Set LED masks */
10053 elink_cl45_write(sc
, phy
,
10055 MDIO_PMA_REG_8481_LED1_MASK
, 0x10);
10057 elink_cl45_write(sc
, phy
,
10059 MDIO_PMA_REG_8481_LED2_MASK
, 0x80);
10061 elink_cl45_write(sc
, phy
,
10063 MDIO_PMA_REG_8481_LED3_MASK
, 0x98);
10065 elink_cl45_write(sc
, phy
,
10067 MDIO_PMA_REG_8481_LED5_MASK
, 0x40);
10070 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
10071 * sources are all wired through LED1, rather than only
10072 * 10G in other modes.
10074 val
= ((params
->hw_led_mode
<<
10075 SHARED_HW_CFG_LED_MODE_SHIFT
) ==
10076 SHARED_HW_CFG_LED_EXTPHY2
) ? 0x98 : 0x80;
10078 elink_cl45_write(sc
, phy
,
10080 MDIO_PMA_REG_8481_LED1_MASK
, val
);
10082 /* Tell LED3 to blink on source */
10083 elink_cl45_read(sc
, phy
,
10085 MDIO_PMA_REG_8481_LINK_SIGNAL
, &val
);
10087 val
|= (1 << 6); /* A83B[8:6]= 1 */
10088 elink_cl45_write(sc
, phy
,
10090 MDIO_PMA_REG_8481_LINK_SIGNAL
, val
);
10091 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
) {
10092 /* Restore LED4 source to external link,
10093 * and re-enable interrupts.
10095 elink_cl45_write(sc
, phy
,
10097 MDIO_PMA_REG_8481_SIGNAL_MASK
,
10099 if (params
->link_flags
&
10100 ELINK_LINK_FLAGS_INT_DISABLED
) {
10101 elink_link_int_enable(params
);
10102 params
->link_flags
&=
10103 ~ELINK_LINK_FLAGS_INT_DISABLED
;
10110 /* This is a workaround for E3+84833 until autoneg
10111 * restart is fixed in f/w
10113 if (CHIP_IS_E3(sc
)) {
10114 elink_cl45_read(sc
, phy
, MDIO_WC_DEVAD
,
10115 MDIO_WC_REG_GP2_STATUS_GP_2_1
, &val
);
10119 /******************************************************************/
10120 /* 54618SE PHY SECTION */
10121 /******************************************************************/
10122 static void elink_54618se_specific_func(struct elink_phy
*phy
,
10123 struct elink_params
*params
,
10126 struct bnx2x_softc
*sc
= params
->sc
;
10129 case ELINK_PHY_INIT
:
10130 /* Configure LED4: set to INTR (0x6). */
10131 /* Accessing shadow register 0xe. */
10132 elink_cl22_write(sc
, phy
,
10133 MDIO_REG_GPHY_SHADOW
,
10134 MDIO_REG_GPHY_SHADOW_LED_SEL2
);
10135 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_SHADOW
, &temp
);
10136 temp
&= ~(0xf << 4);
10137 temp
|= (0x6 << 4);
10138 elink_cl22_write(sc
, phy
,
10139 MDIO_REG_GPHY_SHADOW
,
10140 MDIO_REG_GPHY_SHADOW_WR_ENA
| temp
);
10141 /* Configure INTR based on link status change. */
10142 elink_cl22_write(sc
, phy
,
10143 MDIO_REG_INTR_MASK
,
10144 ~MDIO_REG_INTR_MASK_LINK_STATUS
);
10149 static uint8_t elink_54618se_config_init(struct elink_phy
*phy
,
10150 struct elink_params
*params
,
10151 struct elink_vars
*vars
)
10153 struct bnx2x_softc
*sc
= params
->sc
;
10155 uint16_t autoneg_val
, an_1000_val
, an_10_100_val
, fc_val
, temp
;
10158 PMD_DRV_LOG(DEBUG
, "54618SE cfg init");
10161 /* This works with E3 only, no need to check the chip
10162 * before determining the port.
10164 port
= params
->port
;
10166 cfg_pin
= (REG_RD(sc
, params
->shmem_base
+
10167 offsetof(struct shmem_region
,
10168 dev_info
.port_hw_config
[port
].
10170 PORT_HW_CFG_E3_PHY_RESET_MASK
) >>
10171 PORT_HW_CFG_E3_PHY_RESET_SHIFT
;
10173 /* Drive pin high to bring the GPHY out of reset. */
10174 elink_set_cfg_pin(sc
, cfg_pin
, 1);
10176 /* wait for GPHY to reset */
10180 elink_cl22_write(sc
, phy
, MDIO_PMA_REG_CTRL
, 0x8000);
10181 elink_wait_reset_complete(sc
, phy
, params
);
10183 /* Wait for GPHY to reset */
10186 elink_54618se_specific_func(phy
, params
, ELINK_PHY_INIT
);
10187 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10188 elink_cl22_write(sc
, phy
,
10189 MDIO_REG_GPHY_SHADOW
,
10190 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED
);
10191 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_SHADOW
, &temp
);
10192 temp
|= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD
;
10193 elink_cl22_write(sc
, phy
,
10194 MDIO_REG_GPHY_SHADOW
,
10195 MDIO_REG_GPHY_SHADOW_WR_ENA
| temp
);
10198 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10199 elink_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
10201 if ((vars
->ieee_fc
& MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
10202 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
)
10203 fc_val
|= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC
;
10205 if ((vars
->ieee_fc
& MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
10206 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
)
10207 fc_val
|= MDIO_AN_REG_ADV_PAUSE_PAUSE
;
10209 /* Read all advertisement */
10210 elink_cl22_read(sc
, phy
, 0x09, &an_1000_val
);
10212 elink_cl22_read(sc
, phy
, 0x04, &an_10_100_val
);
10214 elink_cl22_read(sc
, phy
, MDIO_PMA_REG_CTRL
, &autoneg_val
);
10216 /* Disable forced speed */
10218 ~((1 << 6) | (1 << 8) | (1 << 9) | (1 << 12) | (1 << 13));
10220 ~((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10) |
10223 if (((phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) &&
10224 (phy
->speed_cap_mask
&
10225 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
10226 (phy
->req_line_speed
== ELINK_SPEED_1000
)) {
10227 an_1000_val
|= (1 << 8);
10228 autoneg_val
|= (1 << 9 | 1 << 12);
10229 if (phy
->req_duplex
== DUPLEX_FULL
)
10230 an_1000_val
|= (1 << 9);
10231 PMD_DRV_LOG(DEBUG
, "Advertising 1G");
10233 an_1000_val
&= ~((1 << 8) | (1 << 9));
10235 elink_cl22_write(sc
, phy
, 0x09, an_1000_val
);
10236 elink_cl22_read(sc
, phy
, 0x09, &an_1000_val
);
10238 /* Advertise 10/100 link speed */
10239 if (phy
->req_line_speed
== ELINK_SPEED_AUTO_NEG
) {
10240 if (phy
->speed_cap_mask
&
10241 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
) {
10242 an_10_100_val
|= (1 << 5);
10243 autoneg_val
|= (1 << 9 | 1 << 12);
10244 PMD_DRV_LOG(DEBUG
, "Advertising 10M-HD");
10246 if (phy
->speed_cap_mask
&
10247 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
) {
10248 an_10_100_val
|= (1 << 6);
10249 autoneg_val
|= (1 << 9 | 1 << 12);
10250 PMD_DRV_LOG(DEBUG
, "Advertising 10M-FD");
10252 if (phy
->speed_cap_mask
&
10253 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
) {
10254 an_10_100_val
|= (1 << 7);
10255 autoneg_val
|= (1 << 9 | 1 << 12);
10256 PMD_DRV_LOG(DEBUG
, "Advertising 100M-HD");
10258 if (phy
->speed_cap_mask
&
10259 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
) {
10260 an_10_100_val
|= (1 << 8);
10261 autoneg_val
|= (1 << 9 | 1 << 12);
10262 PMD_DRV_LOG(DEBUG
, "Advertising 100M-FD");
10266 /* Only 10/100 are allowed to work in FORCE mode */
10267 if (phy
->req_line_speed
== ELINK_SPEED_100
) {
10268 autoneg_val
|= (1 << 13);
10269 /* Enabled AUTO-MDIX when autoneg is disabled */
10270 elink_cl22_write(sc
, phy
, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10271 PMD_DRV_LOG(DEBUG
, "Setting 100M force");
10273 if (phy
->req_line_speed
== ELINK_SPEED_10
) {
10274 /* Enabled AUTO-MDIX when autoneg is disabled */
10275 elink_cl22_write(sc
, phy
, 0x18, (1 << 15 | 1 << 9 | 7 << 0));
10276 PMD_DRV_LOG(DEBUG
, "Setting 10M force");
10279 if ((phy
->flags
& ELINK_FLAGS_EEE
) && elink_eee_has_cap(params
)) {
10282 elink_cl22_write(sc
, phy
, MDIO_REG_GPHY_EXP_ACCESS
,
10283 MDIO_REG_GPHY_EXP_ACCESS_TOP
|
10284 MDIO_REG_GPHY_EXP_TOP_2K_BUF
);
10285 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_EXP_ACCESS_GATE
, &temp
);
10287 elink_cl22_write(sc
, phy
, MDIO_REG_GPHY_EXP_ACCESS_GATE
, temp
);
10289 rc
= elink_eee_initial_config(params
, vars
, SHMEM_EEE_1G_ADV
);
10290 if (rc
!= ELINK_STATUS_OK
) {
10291 PMD_DRV_LOG(DEBUG
, "Failed to configure EEE timers");
10292 elink_eee_disable(phy
, params
, vars
);
10293 } else if ((params
->eee_mode
& ELINK_EEE_MODE_ADV_LPI
) &&
10294 (phy
->req_duplex
== DUPLEX_FULL
) &&
10295 (elink_eee_calc_timer(params
) ||
10296 !(params
->eee_mode
& ELINK_EEE_MODE_ENABLE_LPI
))) {
10297 /* Need to advertise EEE only when requested,
10298 * and either no LPI assertion was requested,
10299 * or it was requested and a valid timer was set.
10300 * Also notice full duplex is required for EEE.
10302 elink_eee_advertise(phy
, params
, vars
,
10305 PMD_DRV_LOG(DEBUG
, "Don't Advertise 1GBase-T EEE");
10306 elink_eee_disable(phy
, params
, vars
);
10309 vars
->eee_status
&= ~SHMEM_EEE_1G_ADV
<<
10310 SHMEM_EEE_SUPPORTED_SHIFT
;
10312 if (phy
->flags
& ELINK_FLAGS_EEE
) {
10313 /* Handle legacy auto-grEEEn */
10314 if (params
->feature_config_flags
&
10315 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED
) {
10317 PMD_DRV_LOG(DEBUG
, "Enabling Auto-GrEEEn");
10320 PMD_DRV_LOG(DEBUG
, "Don't Adv. EEE");
10322 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
,
10323 MDIO_AN_REG_EEE_ADV
, temp
);
10327 elink_cl22_write(sc
, phy
, 0x04, an_10_100_val
| fc_val
);
10329 if (phy
->req_duplex
== DUPLEX_FULL
)
10330 autoneg_val
|= (1 << 8);
10332 elink_cl22_write(sc
, phy
, MDIO_PMA_REG_CTRL
, autoneg_val
);
10334 return ELINK_STATUS_OK
;
10337 static void elink_5461x_set_link_led(struct elink_phy
*phy
,
10338 struct elink_params
*params
, uint8_t mode
)
10340 struct bnx2x_softc
*sc
= params
->sc
;
10343 elink_cl22_write(sc
, phy
,
10344 MDIO_REG_GPHY_SHADOW
, MDIO_REG_GPHY_SHADOW_LED_SEL1
);
10345 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_SHADOW
, &temp
);
10348 PMD_DRV_LOG(DEBUG
, "54618x set link led (mode=%x)", mode
);
10350 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
10351 case ELINK_LED_MODE_OFF
:
10354 case ELINK_LED_MODE_OPER
:
10357 case ELINK_LED_MODE_ON
:
10363 elink_cl22_write(sc
, phy
,
10364 MDIO_REG_GPHY_SHADOW
,
10365 MDIO_REG_GPHY_SHADOW_WR_ENA
| temp
);
10369 static void elink_54618se_link_reset(struct elink_phy
*phy
,
10370 struct elink_params
*params
)
10372 struct bnx2x_softc
*sc
= params
->sc
;
10376 /* In case of no EPIO routed to reset the GPHY, put it
10377 * in low power mode.
10379 elink_cl22_write(sc
, phy
, MDIO_PMA_REG_CTRL
, 0x800);
10380 /* This works with E3 only, no need to check the chip
10381 * before determining the port.
10383 port
= params
->port
;
10384 cfg_pin
= (REG_RD(sc
, params
->shmem_base
+
10385 offsetof(struct shmem_region
,
10386 dev_info
.port_hw_config
[port
].
10388 PORT_HW_CFG_E3_PHY_RESET_MASK
) >>
10389 PORT_HW_CFG_E3_PHY_RESET_SHIFT
;
10391 /* Drive pin low to put GPHY in reset. */
10392 elink_set_cfg_pin(sc
, cfg_pin
, 0);
10395 static uint8_t elink_54618se_read_status(struct elink_phy
*phy
,
10396 struct elink_params
*params
,
10397 struct elink_vars
*vars
)
10399 struct bnx2x_softc
*sc
= params
->sc
;
10401 uint8_t link_up
= 0;
10402 uint16_t legacy_status
, legacy_speed
;
10404 /* Get speed operation status */
10405 elink_cl22_read(sc
, phy
, MDIO_REG_GPHY_AUX_STATUS
, &legacy_status
);
10406 PMD_DRV_LOG(DEBUG
, "54618SE read_status: 0x%x", legacy_status
);
10408 /* Read status to clear the PHY interrupt. */
10409 elink_cl22_read(sc
, phy
, MDIO_REG_INTR_STATUS
, &val
);
10411 link_up
= ((legacy_status
& (1 << 2)) == (1 << 2));
10414 legacy_speed
= (legacy_status
& (7 << 8));
10415 if (legacy_speed
== (7 << 8)) {
10416 vars
->line_speed
= ELINK_SPEED_1000
;
10417 vars
->duplex
= DUPLEX_FULL
;
10418 } else if (legacy_speed
== (6 << 8)) {
10419 vars
->line_speed
= ELINK_SPEED_1000
;
10420 vars
->duplex
= DUPLEX_HALF
;
10421 } else if (legacy_speed
== (5 << 8)) {
10422 vars
->line_speed
= ELINK_SPEED_100
;
10423 vars
->duplex
= DUPLEX_FULL
;
10425 /* Omitting 100Base-T4 for now */
10426 else if (legacy_speed
== (3 << 8)) {
10427 vars
->line_speed
= ELINK_SPEED_100
;
10428 vars
->duplex
= DUPLEX_HALF
;
10429 } else if (legacy_speed
== (2 << 8)) {
10430 vars
->line_speed
= ELINK_SPEED_10
;
10431 vars
->duplex
= DUPLEX_FULL
;
10432 } else if (legacy_speed
== (1 << 8)) {
10433 vars
->line_speed
= ELINK_SPEED_10
;
10434 vars
->duplex
= DUPLEX_HALF
;
10435 } else /* Should not happen */
10436 vars
->line_speed
= 0;
10439 "Link is up in %dMbps, is_duplex_full= %d",
10440 vars
->line_speed
, (vars
->duplex
== DUPLEX_FULL
));
10442 /* Check legacy speed AN resolution */
10443 elink_cl22_read(sc
, phy
, 0x01, &val
);
10444 if (val
& (1 << 5))
10445 vars
->link_status
|=
10446 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
10447 elink_cl22_read(sc
, phy
, 0x06, &val
);
10448 if ((val
& (1 << 0)) == 0)
10449 vars
->link_status
|=
10450 LINK_STATUS_PARALLEL_DETECTION_USED
;
10452 PMD_DRV_LOG(DEBUG
, "BNX2X54618SE: link speed is %d",
10455 elink_ext_phy_resolve_fc(phy
, params
, vars
);
10457 if (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
10458 /* Report LP advertised speeds */
10459 elink_cl22_read(sc
, phy
, 0x5, &val
);
10461 if (val
& (1 << 5))
10462 vars
->link_status
|=
10463 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE
;
10464 if (val
& (1 << 6))
10465 vars
->link_status
|=
10466 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE
;
10467 if (val
& (1 << 7))
10468 vars
->link_status
|=
10469 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE
;
10470 if (val
& (1 << 8))
10471 vars
->link_status
|=
10472 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE
;
10473 if (val
& (1 << 9))
10474 vars
->link_status
|=
10475 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE
;
10477 elink_cl22_read(sc
, phy
, 0xa, &val
);
10478 if (val
& (1 << 10))
10479 vars
->link_status
|=
10480 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE
;
10481 if (val
& (1 << 11))
10482 vars
->link_status
|=
10483 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
10485 if ((phy
->flags
& ELINK_FLAGS_EEE
) &&
10486 elink_eee_has_cap(params
))
10487 elink_eee_an_resolve(phy
, params
, vars
);
10493 static void elink_54618se_config_loopback(struct elink_phy
*phy
,
10494 struct elink_params
*params
)
10496 struct bnx2x_softc
*sc
= params
->sc
;
10498 uint32_t umac_base
= params
->port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
10500 PMD_DRV_LOG(DEBUG
, "2PMA/PMD ext_phy_loopback: 54618se");
10502 /* Enable master/slave manual mmode and set to master */
10503 /* mii write 9 [bits set 11 12] */
10504 elink_cl22_write(sc
, phy
, 0x09, 3 << 11);
10506 /* forced 1G and disable autoneg */
10507 /* set val [mii read 0] */
10508 /* set val [expr $val & [bits clear 6 12 13]] */
10509 /* set val [expr $val | [bits set 6 8]] */
10510 /* mii write 0 $val */
10511 elink_cl22_read(sc
, phy
, 0x00, &val
);
10512 val
&= ~((1 << 6) | (1 << 12) | (1 << 13));
10513 val
|= (1 << 6) | (1 << 8);
10514 elink_cl22_write(sc
, phy
, 0x00, val
);
10516 /* Set external loopback and Tx using 6dB coding */
10517 /* mii write 0x18 7 */
10518 /* set val [mii read 0x18] */
10519 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10520 elink_cl22_write(sc
, phy
, 0x18, 7);
10521 elink_cl22_read(sc
, phy
, 0x18, &val
);
10522 elink_cl22_write(sc
, phy
, 0x18, val
| (1 << 10) | (1 << 15));
10524 /* This register opens the gate for the UMAC despite its name */
10525 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
* 4, 1);
10527 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10528 * length used by the MAC receive logic to check frames.
10530 REG_WR(sc
, umac_base
+ UMAC_REG_MAXFR
, 0x2710);
10533 /******************************************************************/
10534 /* SFX7101 PHY SECTION */
10535 /******************************************************************/
10536 static void elink_7101_config_loopback(struct elink_phy
*phy
,
10537 struct elink_params
*params
)
10539 struct bnx2x_softc
*sc
= params
->sc
;
10540 /* SFX7101_XGXS_TEST1 */
10541 elink_cl45_write(sc
, phy
,
10542 MDIO_XS_DEVAD
, MDIO_XS_SFX7101_XGXS_TEST1
, 0x100);
10545 static uint8_t elink_7101_config_init(struct elink_phy
*phy
,
10546 struct elink_params
*params
,
10547 struct elink_vars
*vars
)
10549 uint16_t fw_ver1
, fw_ver2
, val
;
10550 struct bnx2x_softc
*sc
= params
->sc
;
10551 PMD_DRV_LOG(DEBUG
, "Setting the SFX7101 LASI indication");
10553 /* Restore normal power mode */
10554 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
10555 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
10557 elink_ext_phy_hw_reset(sc
, params
->port
);
10558 elink_wait_reset_complete(sc
, phy
, params
);
10560 elink_cl45_write(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x1);
10561 PMD_DRV_LOG(DEBUG
, "Setting the SFX7101 LED to blink on traffic");
10562 elink_cl45_write(sc
, phy
,
10563 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7107_LED_CNTL
, (1 << 3));
10565 elink_ext_phy_set_pause(params
, phy
, vars
);
10566 /* Restart autoneg */
10567 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, &val
);
10569 elink_cl45_write(sc
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, val
);
10571 /* Save spirom version */
10572 elink_cl45_read(sc
, phy
,
10573 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7101_VER1
, &fw_ver1
);
10575 elink_cl45_read(sc
, phy
,
10576 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7101_VER2
, &fw_ver2
);
10577 elink_save_spirom_version(sc
, params
->port
,
10578 (uint32_t) (fw_ver1
<< 16 | fw_ver2
),
10580 return ELINK_STATUS_OK
;
10583 static uint8_t elink_7101_read_status(struct elink_phy
*phy
,
10584 struct elink_params
*params
,
10585 struct elink_vars
*vars
)
10587 struct bnx2x_softc
*sc
= params
->sc
;
10589 uint16_t val1
, val2
;
10590 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val2
);
10591 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
10592 PMD_DRV_LOG(DEBUG
, "10G-base-T LASI status 0x%x->0x%x", val2
, val1
);
10593 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val2
);
10594 elink_cl45_read(sc
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val1
);
10595 PMD_DRV_LOG(DEBUG
, "10G-base-T PMA status 0x%x->0x%x", val2
, val1
);
10596 link_up
= ((val1
& 4) == 4);
10597 /* If link is up print the AN outcome of the SFX7101 PHY */
10599 elink_cl45_read(sc
, phy
,
10600 MDIO_AN_DEVAD
, MDIO_AN_REG_MASTER_STATUS
,
10602 vars
->line_speed
= ELINK_SPEED_10000
;
10603 vars
->duplex
= DUPLEX_FULL
;
10604 PMD_DRV_LOG(DEBUG
, "SFX7101 AN status 0x%x->Master=%x",
10605 val2
, (val2
& (1 << 14)));
10606 elink_ext_phy_10G_an_resolve(sc
, phy
, vars
);
10607 elink_ext_phy_resolve_fc(phy
, params
, vars
);
10609 /* Read LP advertised speeds */
10610 if (val2
& (1 << 11))
10611 vars
->link_status
|=
10612 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
10617 static uint8_t elink_7101_format_ver(uint32_t spirom_ver
, uint8_t * str
,
10621 return ELINK_STATUS_ERROR
;
10622 str
[0] = (spirom_ver
& 0xFF);
10623 str
[1] = (spirom_ver
& 0xFF00) >> 8;
10624 str
[2] = (spirom_ver
& 0xFF0000) >> 16;
10625 str
[3] = (spirom_ver
& 0xFF000000) >> 24;
10628 return ELINK_STATUS_OK
;
10631 static void elink_7101_hw_reset(__rte_unused
struct elink_phy
*phy
,
10632 struct elink_params
*params
)
10634 /* Low power mode is controlled by GPIO 2 */
10635 elink_cb_gpio_write(params
->sc
, MISC_REGISTERS_GPIO_2
,
10636 MISC_REGISTERS_GPIO_OUTPUT_LOW
, params
->port
);
10637 /* The PHY reset is controlled by GPIO 1 */
10638 elink_cb_gpio_write(params
->sc
, MISC_REGISTERS_GPIO_1
,
10639 MISC_REGISTERS_GPIO_OUTPUT_LOW
, params
->port
);
10642 static void elink_7101_set_link_led(struct elink_phy
*phy
,
10643 struct elink_params
*params
, uint8_t mode
)
10646 struct bnx2x_softc
*sc
= params
->sc
;
10648 case ELINK_LED_MODE_FRONT_PANEL_OFF
:
10649 case ELINK_LED_MODE_OFF
:
10652 case ELINK_LED_MODE_ON
:
10655 case ELINK_LED_MODE_OPER
:
10659 elink_cl45_write(sc
, phy
,
10660 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7107_LINK_LED_CNTL
, val
);
10663 /******************************************************************/
10664 /* STATIC PHY DECLARATION */
10665 /******************************************************************/
10667 static const struct elink_phy phy_null
= {
10668 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
,
10671 .flags
= ELINK_FLAGS_INIT_XGXS_FIRST
,
10672 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10673 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10676 .media_type
= ELINK_ETH_PHY_NOT_PRESENT
,
10678 .req_flow_ctrl
= 0,
10679 .req_line_speed
= 0,
10680 .speed_cap_mask
= 0,
10683 .config_init
= NULL
,
10684 .read_status
= NULL
,
10685 .link_reset
= NULL
,
10686 .config_loopback
= NULL
,
10687 .format_fw_ver
= NULL
,
10689 .set_link_led
= NULL
,
10690 .phy_specific_func
= NULL
10693 static const struct elink_phy phy_serdes
= {
10694 .type
= PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
,
10698 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10699 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10701 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
10702 ELINK_SUPPORTED_10baseT_Full
|
10703 ELINK_SUPPORTED_100baseT_Half
|
10704 ELINK_SUPPORTED_100baseT_Full
|
10705 ELINK_SUPPORTED_1000baseT_Full
|
10706 ELINK_SUPPORTED_2500baseX_Full
|
10707 ELINK_SUPPORTED_TP
|
10708 ELINK_SUPPORTED_Autoneg
|
10709 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10710 .media_type
= ELINK_ETH_PHY_BASE_T
,
10712 .req_flow_ctrl
= 0,
10713 .req_line_speed
= 0,
10714 .speed_cap_mask
= 0,
10717 .config_init
= elink_xgxs_config_init
,
10718 .read_status
= elink_link_settings_status
,
10719 .link_reset
= elink_int_link_reset
,
10720 .config_loopback
= NULL
,
10721 .format_fw_ver
= NULL
,
10723 .set_link_led
= NULL
,
10724 .phy_specific_func
= NULL
10727 static const struct elink_phy phy_xgxs
= {
10728 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
,
10732 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10733 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10735 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
10736 ELINK_SUPPORTED_10baseT_Full
|
10737 ELINK_SUPPORTED_100baseT_Half
|
10738 ELINK_SUPPORTED_100baseT_Full
|
10739 ELINK_SUPPORTED_1000baseT_Full
|
10740 ELINK_SUPPORTED_2500baseX_Full
|
10741 ELINK_SUPPORTED_10000baseT_Full
|
10742 ELINK_SUPPORTED_FIBRE
|
10743 ELINK_SUPPORTED_Autoneg
|
10744 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10745 .media_type
= ELINK_ETH_PHY_CX4
,
10747 .req_flow_ctrl
= 0,
10748 .req_line_speed
= 0,
10749 .speed_cap_mask
= 0,
10752 .config_init
= elink_xgxs_config_init
,
10753 .read_status
= elink_link_settings_status
,
10754 .link_reset
= elink_int_link_reset
,
10755 .config_loopback
= elink_set_xgxs_loopback
,
10756 .format_fw_ver
= NULL
,
10758 .set_link_led
= NULL
,
10759 .phy_specific_func
= elink_xgxs_specific_func
10762 static const struct elink_phy phy_warpcore
= {
10763 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
,
10766 .flags
= ELINK_FLAGS_TX_ERROR_CHECK
,
10767 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10768 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10770 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
10771 ELINK_SUPPORTED_10baseT_Full
|
10772 ELINK_SUPPORTED_100baseT_Half
|
10773 ELINK_SUPPORTED_100baseT_Full
|
10774 ELINK_SUPPORTED_1000baseT_Full
|
10775 ELINK_SUPPORTED_10000baseT_Full
|
10776 ELINK_SUPPORTED_20000baseKR2_Full
|
10777 ELINK_SUPPORTED_20000baseMLD2_Full
|
10778 ELINK_SUPPORTED_FIBRE
|
10779 ELINK_SUPPORTED_Autoneg
|
10780 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10781 .media_type
= ELINK_ETH_PHY_UNSPECIFIED
,
10783 .req_flow_ctrl
= 0,
10784 .req_line_speed
= 0,
10785 .speed_cap_mask
= 0,
10786 /* req_duplex = */ 0,
10788 .config_init
= elink_warpcore_config_init
,
10789 .read_status
= elink_warpcore_read_status
,
10790 .link_reset
= elink_warpcore_link_reset
,
10791 .config_loopback
= elink_set_warpcore_loopback
,
10792 .format_fw_ver
= NULL
,
10793 .hw_reset
= elink_warpcore_hw_reset
,
10794 .set_link_led
= NULL
,
10795 .phy_specific_func
= NULL
10798 static const struct elink_phy phy_7101
= {
10799 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
,
10802 .flags
= ELINK_FLAGS_FAN_FAILURE_DET_REQ
,
10803 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10804 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10806 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10807 ELINK_SUPPORTED_TP
|
10808 ELINK_SUPPORTED_Autoneg
|
10809 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10810 .media_type
= ELINK_ETH_PHY_BASE_T
,
10812 .req_flow_ctrl
= 0,
10813 .req_line_speed
= 0,
10814 .speed_cap_mask
= 0,
10817 .config_init
= elink_7101_config_init
,
10818 .read_status
= elink_7101_read_status
,
10819 .link_reset
= elink_common_ext_link_reset
,
10820 .config_loopback
= elink_7101_config_loopback
,
10821 .format_fw_ver
= elink_7101_format_ver
,
10822 .hw_reset
= elink_7101_hw_reset
,
10823 .set_link_led
= elink_7101_set_link_led
,
10824 .phy_specific_func
= NULL
10827 static const struct elink_phy phy_8073
= {
10828 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073
,
10832 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10833 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10835 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10836 ELINK_SUPPORTED_2500baseX_Full
|
10837 ELINK_SUPPORTED_1000baseT_Full
|
10838 ELINK_SUPPORTED_FIBRE
|
10839 ELINK_SUPPORTED_Autoneg
|
10840 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10841 .media_type
= ELINK_ETH_PHY_KR
,
10843 .req_flow_ctrl
= 0,
10844 .req_line_speed
= 0,
10845 .speed_cap_mask
= 0,
10848 .config_init
= elink_8073_config_init
,
10849 .read_status
= elink_8073_read_status
,
10850 .link_reset
= elink_8073_link_reset
,
10851 .config_loopback
= NULL
,
10852 .format_fw_ver
= elink_format_ver
,
10854 .set_link_led
= NULL
,
10855 .phy_specific_func
= elink_8073_specific_func
10858 static const struct elink_phy phy_8705
= {
10859 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705
,
10862 .flags
= ELINK_FLAGS_INIT_XGXS_FIRST
,
10863 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10864 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10866 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10867 ELINK_SUPPORTED_FIBRE
|
10868 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10869 .media_type
= ELINK_ETH_PHY_XFP_FIBER
,
10871 .req_flow_ctrl
= 0,
10872 .req_line_speed
= 0,
10873 .speed_cap_mask
= 0,
10876 .config_init
= elink_8705_config_init
,
10877 .read_status
= elink_8705_read_status
,
10878 .link_reset
= elink_common_ext_link_reset
,
10879 .config_loopback
= NULL
,
10880 .format_fw_ver
= elink_null_format_ver
,
10882 .set_link_led
= NULL
,
10883 .phy_specific_func
= NULL
10886 static const struct elink_phy phy_8706
= {
10887 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706
,
10890 .flags
= ELINK_FLAGS_INIT_XGXS_FIRST
,
10891 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10892 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10894 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10895 ELINK_SUPPORTED_1000baseT_Full
|
10896 ELINK_SUPPORTED_FIBRE
|
10897 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10898 .media_type
= ELINK_ETH_PHY_SFPP_10G_FIBER
,
10900 .req_flow_ctrl
= 0,
10901 .req_line_speed
= 0,
10902 .speed_cap_mask
= 0,
10905 .config_init
= elink_8706_config_init
,
10906 .read_status
= elink_8706_read_status
,
10907 .link_reset
= elink_common_ext_link_reset
,
10908 .config_loopback
= NULL
,
10909 .format_fw_ver
= elink_format_ver
,
10911 .set_link_led
= NULL
,
10912 .phy_specific_func
= NULL
10915 static const struct elink_phy phy_8726
= {
10916 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
,
10919 .flags
= (ELINK_FLAGS_INIT_XGXS_FIRST
| ELINK_FLAGS_TX_ERROR_CHECK
),
10920 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10921 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10923 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10924 ELINK_SUPPORTED_1000baseT_Full
|
10925 ELINK_SUPPORTED_Autoneg
|
10926 ELINK_SUPPORTED_FIBRE
|
10927 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10928 .media_type
= ELINK_ETH_PHY_NOT_PRESENT
,
10930 .req_flow_ctrl
= 0,
10931 .req_line_speed
= 0,
10932 .speed_cap_mask
= 0,
10935 .config_init
= elink_8726_config_init
,
10936 .read_status
= elink_8726_read_status
,
10937 .link_reset
= elink_8726_link_reset
,
10938 .config_loopback
= elink_8726_config_loopback
,
10939 .format_fw_ver
= elink_format_ver
,
10941 .set_link_led
= NULL
,
10942 .phy_specific_func
= NULL
10945 static const struct elink_phy phy_8727
= {
10946 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
,
10949 .flags
= (ELINK_FLAGS_FAN_FAILURE_DET_REQ
| ELINK_FLAGS_TX_ERROR_CHECK
),
10950 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10951 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10953 .supported
= (ELINK_SUPPORTED_10000baseT_Full
|
10954 ELINK_SUPPORTED_1000baseT_Full
|
10955 ELINK_SUPPORTED_FIBRE
|
10956 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10957 .media_type
= ELINK_ETH_PHY_NOT_PRESENT
,
10959 .req_flow_ctrl
= 0,
10960 .req_line_speed
= 0,
10961 .speed_cap_mask
= 0,
10964 .config_init
= elink_8727_config_init
,
10965 .read_status
= elink_8727_read_status
,
10966 .link_reset
= elink_8727_link_reset
,
10967 .config_loopback
= NULL
,
10968 .format_fw_ver
= elink_format_ver
,
10969 .hw_reset
= elink_8727_hw_reset
,
10970 .set_link_led
= elink_8727_set_link_led
,
10971 .phy_specific_func
= elink_8727_specific_func
10974 static const struct elink_phy phy_8481
= {
10975 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481
,
10978 .flags
= ELINK_FLAGS_FAN_FAILURE_DET_REQ
|
10979 ELINK_FLAGS_REARM_LATCH_SIGNAL
,
10980 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10981 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
10983 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
10984 ELINK_SUPPORTED_10baseT_Full
|
10985 ELINK_SUPPORTED_100baseT_Half
|
10986 ELINK_SUPPORTED_100baseT_Full
|
10987 ELINK_SUPPORTED_1000baseT_Full
|
10988 ELINK_SUPPORTED_10000baseT_Full
|
10989 ELINK_SUPPORTED_TP
|
10990 ELINK_SUPPORTED_Autoneg
|
10991 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
10992 .media_type
= ELINK_ETH_PHY_BASE_T
,
10994 .req_flow_ctrl
= 0,
10995 .req_line_speed
= 0,
10996 .speed_cap_mask
= 0,
10999 .config_init
= elink_8481_config_init
,
11000 .read_status
= elink_848xx_read_status
,
11001 .link_reset
= elink_8481_link_reset
,
11002 .config_loopback
= NULL
,
11003 .format_fw_ver
= elink_848xx_format_ver
,
11004 .hw_reset
= elink_8481_hw_reset
,
11005 .set_link_led
= elink_848xx_set_link_led
,
11006 .phy_specific_func
= NULL
11009 static const struct elink_phy phy_84823
= {
11010 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
,
11013 .flags
= (ELINK_FLAGS_FAN_FAILURE_DET_REQ
|
11014 ELINK_FLAGS_REARM_LATCH_SIGNAL
| ELINK_FLAGS_TX_ERROR_CHECK
),
11015 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11016 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11018 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
11019 ELINK_SUPPORTED_10baseT_Full
|
11020 ELINK_SUPPORTED_100baseT_Half
|
11021 ELINK_SUPPORTED_100baseT_Full
|
11022 ELINK_SUPPORTED_1000baseT_Full
|
11023 ELINK_SUPPORTED_10000baseT_Full
|
11024 ELINK_SUPPORTED_TP
|
11025 ELINK_SUPPORTED_Autoneg
|
11026 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
11027 .media_type
= ELINK_ETH_PHY_BASE_T
,
11029 .req_flow_ctrl
= 0,
11030 .req_line_speed
= 0,
11031 .speed_cap_mask
= 0,
11034 .config_init
= elink_848x3_config_init
,
11035 .read_status
= elink_848xx_read_status
,
11036 .link_reset
= elink_848x3_link_reset
,
11037 .config_loopback
= NULL
,
11038 .format_fw_ver
= elink_848xx_format_ver
,
11040 .set_link_led
= elink_848xx_set_link_led
,
11041 .phy_specific_func
= elink_848xx_specific_func
11044 static const struct elink_phy phy_84833
= {
11045 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
,
11048 .flags
= (ELINK_FLAGS_FAN_FAILURE_DET_REQ
|
11049 ELINK_FLAGS_REARM_LATCH_SIGNAL
|
11050 ELINK_FLAGS_TX_ERROR_CHECK
| ELINK_FLAGS_TEMPERATURE
),
11051 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11052 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11054 .supported
= (ELINK_SUPPORTED_100baseT_Half
|
11055 ELINK_SUPPORTED_100baseT_Full
|
11056 ELINK_SUPPORTED_1000baseT_Full
|
11057 ELINK_SUPPORTED_10000baseT_Full
|
11058 ELINK_SUPPORTED_TP
|
11059 ELINK_SUPPORTED_Autoneg
|
11060 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
11061 .media_type
= ELINK_ETH_PHY_BASE_T
,
11063 .req_flow_ctrl
= 0,
11064 .req_line_speed
= 0,
11065 .speed_cap_mask
= 0,
11068 .config_init
= elink_848x3_config_init
,
11069 .read_status
= elink_848xx_read_status
,
11070 .link_reset
= elink_848x3_link_reset
,
11071 .config_loopback
= NULL
,
11072 .format_fw_ver
= elink_848xx_format_ver
,
11073 .hw_reset
= elink_84833_hw_reset_phy
,
11074 .set_link_led
= elink_848xx_set_link_led
,
11075 .phy_specific_func
= elink_848xx_specific_func
11078 static const struct elink_phy phy_84834
= {
11079 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
,
11082 .flags
= ELINK_FLAGS_FAN_FAILURE_DET_REQ
|
11083 ELINK_FLAGS_REARM_LATCH_SIGNAL
,
11084 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11085 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11087 .supported
= (ELINK_SUPPORTED_100baseT_Half
|
11088 ELINK_SUPPORTED_100baseT_Full
|
11089 ELINK_SUPPORTED_1000baseT_Full
|
11090 ELINK_SUPPORTED_10000baseT_Full
|
11091 ELINK_SUPPORTED_TP
|
11092 ELINK_SUPPORTED_Autoneg
|
11093 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
11094 .media_type
= ELINK_ETH_PHY_BASE_T
,
11096 .req_flow_ctrl
= 0,
11097 .req_line_speed
= 0,
11098 .speed_cap_mask
= 0,
11101 .config_init
= elink_848x3_config_init
,
11102 .read_status
= elink_848xx_read_status
,
11103 .link_reset
= elink_848x3_link_reset
,
11104 .config_loopback
= NULL
,
11105 .format_fw_ver
= elink_848xx_format_ver
,
11106 .hw_reset
= elink_84833_hw_reset_phy
,
11107 .set_link_led
= elink_848xx_set_link_led
,
11108 .phy_specific_func
= elink_848xx_specific_func
11111 static const struct elink_phy phy_54618se
= {
11112 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
,
11115 .flags
= ELINK_FLAGS_INIT_XGXS_FIRST
,
11116 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11117 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11119 .supported
= (ELINK_SUPPORTED_10baseT_Half
|
11120 ELINK_SUPPORTED_10baseT_Full
|
11121 ELINK_SUPPORTED_100baseT_Half
|
11122 ELINK_SUPPORTED_100baseT_Full
|
11123 ELINK_SUPPORTED_1000baseT_Full
|
11124 ELINK_SUPPORTED_TP
|
11125 ELINK_SUPPORTED_Autoneg
|
11126 ELINK_SUPPORTED_Pause
| ELINK_SUPPORTED_Asym_Pause
),
11127 .media_type
= ELINK_ETH_PHY_BASE_T
,
11129 .req_flow_ctrl
= 0,
11130 .req_line_speed
= 0,
11131 .speed_cap_mask
= 0,
11132 /* req_duplex = */ 0,
11134 .config_init
= elink_54618se_config_init
,
11135 .read_status
= elink_54618se_read_status
,
11136 .link_reset
= elink_54618se_link_reset
,
11137 .config_loopback
= elink_54618se_config_loopback
,
11138 .format_fw_ver
= NULL
,
11140 .set_link_led
= elink_5461x_set_link_led
,
11141 .phy_specific_func
= elink_54618se_specific_func
11144 /*****************************************************************/
11146 /* Populate the phy according. Main function: elink_populate_phy */
11148 /*****************************************************************/
11150 static void elink_populate_preemphasis(struct bnx2x_softc
*sc
,
11151 uint32_t shmem_base
,
11152 struct elink_phy
*phy
, uint8_t port
,
11155 /* Get the 4 lanes xgxs config rx and tx */
11156 uint32_t rx
= 0, tx
= 0, i
;
11157 for (i
= 0; i
< 2; i
++) {
11158 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
11159 * the shmem. When num_phys is greater than 1, than this value
11160 * applies only to ELINK_EXT_PHY1
11162 if (phy_index
== ELINK_INT_PHY
|| phy_index
== ELINK_EXT_PHY1
) {
11163 rx
= REG_RD(sc
, shmem_base
+
11164 offsetof(struct shmem_region
,
11165 dev_info
.port_hw_config
[port
].
11166 xgxs_config_rx
[i
<< 1]));
11168 tx
= REG_RD(sc
, shmem_base
+
11169 offsetof(struct shmem_region
,
11170 dev_info
.port_hw_config
[port
].
11171 xgxs_config_tx
[i
<< 1]));
11173 rx
= REG_RD(sc
, shmem_base
+
11174 offsetof(struct shmem_region
,
11175 dev_info
.port_hw_config
[port
].
11176 xgxs_config2_rx
[i
<< 1]));
11178 tx
= REG_RD(sc
, shmem_base
+
11179 offsetof(struct shmem_region
,
11180 dev_info
.port_hw_config
[port
].
11181 xgxs_config2_rx
[i
<< 1]));
11184 phy
->rx_preemphasis
[i
<< 1] = ((rx
>> 16) & 0xffff);
11185 phy
->rx_preemphasis
[(i
<< 1) + 1] = (rx
& 0xffff);
11187 phy
->tx_preemphasis
[i
<< 1] = ((tx
>> 16) & 0xffff);
11188 phy
->tx_preemphasis
[(i
<< 1) + 1] = (tx
& 0xffff);
11192 static uint32_t elink_get_ext_phy_config(struct bnx2x_softc
*sc
,
11193 uint32_t shmem_base
, uint8_t phy_index
,
11196 uint32_t ext_phy_config
= 0;
11197 switch (phy_index
) {
11198 case ELINK_EXT_PHY1
:
11199 ext_phy_config
= REG_RD(sc
, shmem_base
+
11200 offsetof(struct shmem_region
,
11201 dev_info
.port_hw_config
[port
].
11202 external_phy_config
));
11204 case ELINK_EXT_PHY2
:
11205 ext_phy_config
= REG_RD(sc
, shmem_base
+
11206 offsetof(struct shmem_region
,
11207 dev_info
.port_hw_config
[port
].
11208 external_phy_config2
));
11211 PMD_DRV_LOG(DEBUG
, "Invalid phy_index %d", phy_index
);
11212 return ELINK_STATUS_ERROR
;
11215 return ext_phy_config
;
11218 static elink_status_t
elink_populate_int_phy(struct bnx2x_softc
*sc
,
11219 uint32_t shmem_base
, uint8_t port
,
11220 struct elink_phy
*phy
)
11223 __rte_unused
uint32_t chip_id
;
11224 uint32_t switch_cfg
= (REG_RD(sc
, shmem_base
+
11225 offsetof(struct shmem_region
,
11227 port_feature_config
[port
].
11229 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
11231 (REG_RD(sc
, MISC_REG_CHIP_NUM
) << 16) |
11232 ((REG_RD(sc
, MISC_REG_CHIP_REV
) & 0xf) << 12);
11234 PMD_DRV_LOG(DEBUG
, ":chip_id = 0x%x", chip_id
);
11235 if (USES_WARPCORE(sc
)) {
11236 uint32_t serdes_net_if
;
11237 phy_addr
= REG_RD(sc
, MISC_REG_WC0_CTRL_PHY_ADDR
);
11238 *phy
= phy_warpcore
;
11239 if (REG_RD(sc
, MISC_REG_PORT4MODE_EN_OVWR
) == 0x3)
11240 phy
->flags
|= ELINK_FLAGS_4_PORT_MODE
;
11242 phy
->flags
&= ~ELINK_FLAGS_4_PORT_MODE
;
11243 /* Check Dual mode */
11244 serdes_net_if
= (REG_RD(sc
, shmem_base
+
11245 offsetof(struct shmem_region
,
11246 dev_info
.port_hw_config
[port
].
11248 PORT_HW_CFG_NET_SERDES_IF_MASK
);
11249 /* Set the appropriate supported and flags indications per
11250 * interface type of the chip
11252 switch (serdes_net_if
) {
11253 case PORT_HW_CFG_NET_SERDES_IF_SGMII
:
11254 phy
->supported
&= (ELINK_SUPPORTED_10baseT_Half
|
11255 ELINK_SUPPORTED_10baseT_Full
|
11256 ELINK_SUPPORTED_100baseT_Half
|
11257 ELINK_SUPPORTED_100baseT_Full
|
11258 ELINK_SUPPORTED_1000baseT_Full
|
11259 ELINK_SUPPORTED_FIBRE
|
11260 ELINK_SUPPORTED_Autoneg
|
11261 ELINK_SUPPORTED_Pause
|
11262 ELINK_SUPPORTED_Asym_Pause
);
11263 phy
->media_type
= ELINK_ETH_PHY_BASE_T
;
11265 case PORT_HW_CFG_NET_SERDES_IF_XFI
:
11266 phy
->supported
&= (ELINK_SUPPORTED_1000baseT_Full
|
11267 ELINK_SUPPORTED_10000baseT_Full
|
11268 ELINK_SUPPORTED_FIBRE
|
11269 ELINK_SUPPORTED_Pause
|
11270 ELINK_SUPPORTED_Asym_Pause
);
11271 phy
->media_type
= ELINK_ETH_PHY_XFP_FIBER
;
11273 case PORT_HW_CFG_NET_SERDES_IF_SFI
:
11274 phy
->supported
&= (ELINK_SUPPORTED_1000baseT_Full
|
11275 ELINK_SUPPORTED_10000baseT_Full
|
11276 ELINK_SUPPORTED_FIBRE
|
11277 ELINK_SUPPORTED_Pause
|
11278 ELINK_SUPPORTED_Asym_Pause
);
11279 phy
->media_type
= ELINK_ETH_PHY_SFPP_10G_FIBER
;
11281 case PORT_HW_CFG_NET_SERDES_IF_KR
:
11282 phy
->media_type
= ELINK_ETH_PHY_KR
;
11283 phy
->supported
&= (ELINK_SUPPORTED_1000baseT_Full
|
11284 ELINK_SUPPORTED_10000baseT_Full
|
11285 ELINK_SUPPORTED_FIBRE
|
11286 ELINK_SUPPORTED_Autoneg
|
11287 ELINK_SUPPORTED_Pause
|
11288 ELINK_SUPPORTED_Asym_Pause
);
11290 case PORT_HW_CFG_NET_SERDES_IF_DXGXS
:
11291 phy
->media_type
= ELINK_ETH_PHY_KR
;
11292 phy
->flags
|= ELINK_FLAGS_WC_DUAL_MODE
;
11293 phy
->supported
&= (ELINK_SUPPORTED_20000baseMLD2_Full
|
11294 ELINK_SUPPORTED_FIBRE
|
11295 ELINK_SUPPORTED_Pause
|
11296 ELINK_SUPPORTED_Asym_Pause
);
11298 case PORT_HW_CFG_NET_SERDES_IF_KR2
:
11299 phy
->media_type
= ELINK_ETH_PHY_KR
;
11300 phy
->flags
|= ELINK_FLAGS_WC_DUAL_MODE
;
11301 phy
->supported
&= (ELINK_SUPPORTED_20000baseKR2_Full
|
11302 ELINK_SUPPORTED_10000baseT_Full
|
11303 ELINK_SUPPORTED_1000baseT_Full
|
11304 ELINK_SUPPORTED_Autoneg
|
11305 ELINK_SUPPORTED_FIBRE
|
11306 ELINK_SUPPORTED_Pause
|
11307 ELINK_SUPPORTED_Asym_Pause
);
11308 phy
->flags
&= ~ELINK_FLAGS_TX_ERROR_CHECK
;
11311 PMD_DRV_LOG(DEBUG
, "Unknown WC interface type 0x%x",
11316 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11317 * was not set as expected. For B0, ECO will be enabled so there
11318 * won't be an issue there
11320 if (CHIP_REV(sc
) == CHIP_REV_Ax
)
11321 phy
->flags
|= ELINK_FLAGS_MDC_MDIO_WA
;
11323 phy
->flags
|= ELINK_FLAGS_MDC_MDIO_WA_B0
;
11325 switch (switch_cfg
) {
11326 case ELINK_SWITCH_CFG_1G
:
11327 phy_addr
= REG_RD(sc
,
11328 NIG_REG_SERDES0_CTRL_PHY_ADDR
+
11332 case ELINK_SWITCH_CFG_10G
:
11333 phy_addr
= REG_RD(sc
,
11334 NIG_REG_XGXS0_CTRL_PHY_ADDR
+
11339 PMD_DRV_LOG(DEBUG
, "Invalid switch_cfg");
11340 return ELINK_STATUS_ERROR
;
11343 phy
->addr
= (uint8_t) phy_addr
;
11344 phy
->mdio_ctrl
= elink_get_emac_base(sc
,
11345 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
,
11347 if (CHIP_IS_E2(sc
))
11348 phy
->def_md_devad
= ELINK_E2_DEFAULT_PHY_DEV_ADDR
;
11350 phy
->def_md_devad
= ELINK_DEFAULT_PHY_DEV_ADDR
;
11352 PMD_DRV_LOG(DEBUG
, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x",
11353 port
, phy
->addr
, phy
->mdio_ctrl
);
11355 elink_populate_preemphasis(sc
, shmem_base
, phy
, port
, ELINK_INT_PHY
);
11356 return ELINK_STATUS_OK
;
11359 static elink_status_t
elink_populate_ext_phy(struct bnx2x_softc
*sc
,
11361 uint32_t shmem_base
,
11362 uint32_t shmem2_base
,
11364 struct elink_phy
*phy
)
11366 uint32_t ext_phy_config
, phy_type
, config2
;
11367 uint32_t mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
;
11368 ext_phy_config
= elink_get_ext_phy_config(sc
, shmem_base
,
11370 phy_type
= ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config
);
11371 /* Select the phy type */
11372 switch (phy_type
) {
11373 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073
:
11374 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED
;
11377 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8705
:
11380 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8706
:
11383 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
:
11384 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
;
11387 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC
:
11388 /* BNX2X8727_NOC => BNX2X8727 no over current */
11389 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
;
11391 phy
->flags
|= ELINK_FLAGS_NOC
;
11393 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
11394 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
11395 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
;
11398 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8481
:
11401 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84823
:
11404 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
:
11407 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
:
11410 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54616
:
11411 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
:
11412 *phy
= phy_54618se
;
11413 if (phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X54618SE
)
11414 phy
->flags
|= ELINK_FLAGS_EEE
;
11416 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
11419 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
11421 return ELINK_STATUS_ERROR
;
11424 /* In case external PHY wasn't found */
11425 if ((phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
11426 (phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
11427 return ELINK_STATUS_ERROR
;
11428 return ELINK_STATUS_OK
;
11431 phy
->addr
= ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config
);
11432 elink_populate_preemphasis(sc
, shmem_base
, phy
, port
, phy_index
);
11434 /* The shmem address of the phy version is located on different
11435 * structures. In case this structure is too old, do not set
11438 config2
= REG_RD(sc
, shmem_base
+ offsetof(struct shmem_region
,
11439 dev_info
.shared_hw_config
.
11441 if (phy_index
== ELINK_EXT_PHY1
) {
11442 phy
->ver_addr
= shmem_base
+ offsetof(struct shmem_region
,
11444 ext_phy_fw_version
);
11446 /* Check specific mdc mdio settings */
11447 if (config2
& SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK
)
11448 mdc_mdio_access
= config2
&
11449 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK
;
11451 uint32_t size
= REG_RD(sc
, shmem2_base
);
11453 if (size
> offsetof(struct shmem2_region
, ext_phy_fw_version2
)) {
11454 phy
->ver_addr
= shmem2_base
+
11455 offsetof(struct shmem2_region
,
11456 ext_phy_fw_version2
[port
]);
11458 /* Check specific mdc mdio settings */
11459 if (config2
& SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK
)
11460 mdc_mdio_access
= (config2
&
11461 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK
)
11462 >> (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT
-
11463 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT
);
11465 phy
->mdio_ctrl
= elink_get_emac_base(sc
, mdc_mdio_access
, port
);
11467 if (((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
) ||
11468 (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
)) &&
11470 /* Remove 100Mb link supported for BNX2X84833/4 when phy fw
11471 * version lower than or equal to 1.39
11473 uint32_t raw_ver
= REG_RD(sc
, phy
->ver_addr
);
11474 if (((raw_ver
& 0x7F) <= 39) && (((raw_ver
& 0xF80) >> 7) <= 1))
11475 phy
->supported
&= ~(ELINK_SUPPORTED_100baseT_Half
|
11476 ELINK_SUPPORTED_100baseT_Full
);
11479 PMD_DRV_LOG(DEBUG
, "phy_type 0x%x port %d found in index %d",
11480 phy_type
, port
, phy_index
);
11481 PMD_DRV_LOG(DEBUG
, " addr=0x%x, mdio_ctl=0x%x",
11482 phy
->addr
, phy
->mdio_ctrl
);
11483 return ELINK_STATUS_OK
;
11486 static elink_status_t
elink_populate_phy(struct bnx2x_softc
*sc
,
11487 uint8_t phy_index
, uint32_t shmem_base
,
11488 uint32_t shmem2_base
, uint8_t port
,
11489 struct elink_phy
*phy
)
11491 elink_status_t status
= ELINK_STATUS_OK
;
11492 phy
->type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
;
11493 if (phy_index
== ELINK_INT_PHY
)
11494 return elink_populate_int_phy(sc
, shmem_base
, port
, phy
);
11495 status
= elink_populate_ext_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
11500 static void elink_phy_def_cfg(struct elink_params
*params
,
11501 struct elink_phy
*phy
, uint8_t phy_index
)
11503 struct bnx2x_softc
*sc
= params
->sc
;
11504 uint32_t link_config
;
11505 /* Populate the default phy configuration for MF mode */
11506 if (phy_index
== ELINK_EXT_PHY2
) {
11507 link_config
= REG_RD(sc
, params
->shmem_base
+
11508 offsetof(struct shmem_region
,
11509 dev_info
.port_feature_config
11510 [params
->port
].link_config2
));
11511 phy
->speed_cap_mask
=
11513 params
->shmem_base
+ offsetof(struct shmem_region
,
11514 dev_info
.port_hw_config
11516 speed_capability_mask2
));
11518 link_config
= REG_RD(sc
, params
->shmem_base
+
11519 offsetof(struct shmem_region
,
11520 dev_info
.port_feature_config
11521 [params
->port
].link_config
));
11522 phy
->speed_cap_mask
=
11524 params
->shmem_base
+ offsetof(struct shmem_region
,
11525 dev_info
.port_hw_config
11527 speed_capability_mask
));
11531 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x",
11532 phy_index
, link_config
, phy
->speed_cap_mask
);
11534 phy
->req_duplex
= DUPLEX_FULL
;
11535 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
11536 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
11537 phy
->req_duplex
= DUPLEX_HALF
;
11539 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
11540 phy
->req_line_speed
= ELINK_SPEED_10
;
11542 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
11543 phy
->req_duplex
= DUPLEX_HALF
;
11545 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
11546 phy
->req_line_speed
= ELINK_SPEED_100
;
11548 case PORT_FEATURE_LINK_SPEED_1G
:
11549 phy
->req_line_speed
= ELINK_SPEED_1000
;
11551 case PORT_FEATURE_LINK_SPEED_2_5G
:
11552 phy
->req_line_speed
= ELINK_SPEED_2500
;
11554 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
11555 phy
->req_line_speed
= ELINK_SPEED_10000
;
11558 phy
->req_line_speed
= ELINK_SPEED_AUTO_NEG
;
11562 switch (link_config
& PORT_FEATURE_FLOW_CONTROL_MASK
) {
11563 case PORT_FEATURE_FLOW_CONTROL_AUTO
:
11564 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_AUTO
;
11566 case PORT_FEATURE_FLOW_CONTROL_TX
:
11567 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_TX
;
11569 case PORT_FEATURE_FLOW_CONTROL_RX
:
11570 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_RX
;
11572 case PORT_FEATURE_FLOW_CONTROL_BOTH
:
11573 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_BOTH
;
11576 phy
->req_flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11581 uint32_t elink_phy_selection(struct elink_params
*params
)
11583 uint32_t phy_config_swapped
, prio_cfg
;
11584 uint32_t return_cfg
= PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
;
11586 phy_config_swapped
= params
->multi_phy_config
&
11587 PORT_HW_CFG_PHY_SWAPPED_ENABLED
;
11589 prio_cfg
= params
->multi_phy_config
& PORT_HW_CFG_PHY_SELECTION_MASK
;
11591 if (phy_config_swapped
) {
11592 switch (prio_cfg
) {
11593 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
:
11595 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
;
11597 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
:
11599 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
;
11601 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
:
11602 return_cfg
= PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
;
11604 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
:
11605 return_cfg
= PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
;
11609 return_cfg
= prio_cfg
;
11614 elink_status_t
elink_phy_probe(struct elink_params
* params
)
11616 uint8_t phy_index
, actual_phy_idx
;
11617 uint32_t phy_config_swapped
, sync_offset
, media_types
;
11618 struct bnx2x_softc
*sc
= params
->sc
;
11619 struct elink_phy
*phy
;
11620 params
->num_phys
= 0;
11621 PMD_DRV_LOG(DEBUG
, "Begin phy probe");
11623 phy_config_swapped
= params
->multi_phy_config
&
11624 PORT_HW_CFG_PHY_SWAPPED_ENABLED
;
11626 for (phy_index
= ELINK_INT_PHY
; phy_index
< ELINK_MAX_PHYS
; phy_index
++) {
11627 actual_phy_idx
= phy_index
;
11628 if (phy_config_swapped
) {
11629 if (phy_index
== ELINK_EXT_PHY1
)
11630 actual_phy_idx
= ELINK_EXT_PHY2
;
11631 else if (phy_index
== ELINK_EXT_PHY2
)
11632 actual_phy_idx
= ELINK_EXT_PHY1
;
11634 PMD_DRV_LOG(DEBUG
, "phy_config_swapped %x, phy_index %x,"
11635 " actual_phy_idx %x", phy_config_swapped
,
11636 phy_index
, actual_phy_idx
);
11637 phy
= ¶ms
->phy
[actual_phy_idx
];
11638 if (elink_populate_phy(sc
, phy_index
, params
->shmem_base
,
11639 params
->shmem2_base
, params
->port
,
11640 phy
) != ELINK_STATUS_OK
) {
11641 params
->num_phys
= 0;
11642 PMD_DRV_LOG(DEBUG
, "phy probe failed in phy index %d",
11644 for (phy_index
= ELINK_INT_PHY
;
11645 phy_index
< ELINK_MAX_PHYS
; phy_index
++)
11647 return ELINK_STATUS_ERROR
;
11649 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
)
11652 if (params
->feature_config_flags
&
11653 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET
)
11654 phy
->flags
&= ~ELINK_FLAGS_TX_ERROR_CHECK
;
11656 if (!(params
->feature_config_flags
&
11657 ELINK_FEATURE_CONFIG_MT_SUPPORT
))
11658 phy
->flags
|= ELINK_FLAGS_MDC_MDIO_WA_G
;
11660 sync_offset
= params
->shmem_base
+
11661 offsetof(struct shmem_region
,
11662 dev_info
.port_hw_config
[params
->port
].media_type
);
11663 media_types
= REG_RD(sc
, sync_offset
);
11665 /* Update media type for non-PMF sync only for the first time
11666 * In case the media type changes afterwards, it will be updated
11667 * using the update_status function
11669 if ((media_types
& (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
<<
11670 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
*
11671 actual_phy_idx
))) == 0) {
11672 media_types
|= ((phy
->media_type
&
11673 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
) <<
11674 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
*
11677 REG_WR(sc
, sync_offset
, media_types
);
11679 elink_phy_def_cfg(params
, phy
, phy_index
);
11680 params
->num_phys
++;
11683 PMD_DRV_LOG(DEBUG
, "End phy probe. #phys found %x", params
->num_phys
);
11684 return ELINK_STATUS_OK
;
11687 static void elink_init_bmac_loopback(struct elink_params
*params
,
11688 struct elink_vars
*vars
)
11690 struct bnx2x_softc
*sc
= params
->sc
;
11692 vars
->line_speed
= ELINK_SPEED_10000
;
11693 vars
->duplex
= DUPLEX_FULL
;
11694 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11695 vars
->mac_type
= ELINK_MAC_TYPE_BMAC
;
11697 vars
->phy_flags
= PHY_XGXS_FLAG
;
11699 elink_xgxs_deassert(params
);
11701 /* Set bmac loopback */
11702 elink_bmac_enable(params
, vars
, 1, 1);
11704 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11707 static void elink_init_emac_loopback(struct elink_params
*params
,
11708 struct elink_vars
*vars
)
11710 struct bnx2x_softc
*sc
= params
->sc
;
11712 vars
->line_speed
= ELINK_SPEED_1000
;
11713 vars
->duplex
= DUPLEX_FULL
;
11714 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11715 vars
->mac_type
= ELINK_MAC_TYPE_EMAC
;
11717 vars
->phy_flags
= PHY_XGXS_FLAG
;
11719 elink_xgxs_deassert(params
);
11720 /* Set bmac loopback */
11721 elink_emac_enable(params
, vars
, 1);
11722 elink_emac_program(params
, vars
);
11723 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11726 static void elink_init_xmac_loopback(struct elink_params
*params
,
11727 struct elink_vars
*vars
)
11729 struct bnx2x_softc
*sc
= params
->sc
;
11731 if (!params
->req_line_speed
[0])
11732 vars
->line_speed
= ELINK_SPEED_10000
;
11734 vars
->line_speed
= params
->req_line_speed
[0];
11735 vars
->duplex
= DUPLEX_FULL
;
11736 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11737 vars
->mac_type
= ELINK_MAC_TYPE_XMAC
;
11738 vars
->phy_flags
= PHY_XGXS_FLAG
;
11739 /* Set WC to loopback mode since link is required to provide clock
11740 * to the XMAC in 20G mode
11742 elink_set_aer_mmd(params
, ¶ms
->phy
[0]);
11743 elink_warpcore_reset_lane(sc
, ¶ms
->phy
[0], 0);
11744 params
->phy
[ELINK_INT_PHY
].config_loopback(¶ms
->phy
[ELINK_INT_PHY
],
11747 elink_xmac_enable(params
, vars
, 1);
11748 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11751 static void elink_init_umac_loopback(struct elink_params
*params
,
11752 struct elink_vars
*vars
)
11754 struct bnx2x_softc
*sc
= params
->sc
;
11756 vars
->line_speed
= ELINK_SPEED_1000
;
11757 vars
->duplex
= DUPLEX_FULL
;
11758 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11759 vars
->mac_type
= ELINK_MAC_TYPE_UMAC
;
11760 vars
->phy_flags
= PHY_XGXS_FLAG
;
11761 elink_umac_enable(params
, vars
, 1);
11763 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11766 static void elink_init_xgxs_loopback(struct elink_params
*params
,
11767 struct elink_vars
*vars
)
11769 struct bnx2x_softc
*sc
= params
->sc
;
11770 struct elink_phy
*int_phy
= ¶ms
->phy
[ELINK_INT_PHY
];
11772 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11773 vars
->duplex
= DUPLEX_FULL
;
11774 if (params
->req_line_speed
[0] == ELINK_SPEED_1000
)
11775 vars
->line_speed
= ELINK_SPEED_1000
;
11776 else if ((params
->req_line_speed
[0] == ELINK_SPEED_20000
) ||
11777 (int_phy
->flags
& ELINK_FLAGS_WC_DUAL_MODE
))
11778 vars
->line_speed
= ELINK_SPEED_20000
;
11780 vars
->line_speed
= ELINK_SPEED_10000
;
11782 if (!USES_WARPCORE(sc
))
11783 elink_xgxs_deassert(params
);
11784 elink_link_initialize(params
, vars
);
11786 if (params
->req_line_speed
[0] == ELINK_SPEED_1000
) {
11787 if (USES_WARPCORE(sc
))
11788 elink_umac_enable(params
, vars
, 0);
11790 elink_emac_program(params
, vars
);
11791 elink_emac_enable(params
, vars
, 0);
11794 if (USES_WARPCORE(sc
))
11795 elink_xmac_enable(params
, vars
, 0);
11797 elink_bmac_enable(params
, vars
, 0, 1);
11800 if (params
->loopback_mode
== ELINK_LOOPBACK_XGXS
) {
11801 /* Set 10G XGXS loopback */
11802 int_phy
->config_loopback(int_phy
, params
);
11804 /* Set external phy loopback */
11806 for (phy_index
= ELINK_EXT_PHY1
;
11807 phy_index
< params
->num_phys
; phy_index
++)
11808 if (params
->phy
[phy_index
].config_loopback
)
11809 params
->phy
[phy_index
].config_loopback(¶ms
->
11814 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11816 elink_set_led(params
, vars
, ELINK_LED_MODE_OPER
, vars
->line_speed
);
11819 void elink_set_rx_filter(struct elink_params
*params
, uint8_t en
)
11821 struct bnx2x_softc
*sc
= params
->sc
;
11822 uint8_t val
= en
* 0x1F;
11824 /* Open / close the gate between the NIG and the BRB */
11825 if (!CHIP_IS_E1x(sc
))
11827 REG_WR(sc
, NIG_REG_LLH0_BRB1_DRV_MASK
+ params
->port
* 4, val
);
11829 REG_WR(sc
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ params
->port
* 4, en
* 0x3);
11831 REG_WR(sc
, (params
->port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
11832 NIG_REG_LLH0_BRB1_NOT_MCP
), en
);
11835 static elink_status_t
elink_avoid_link_flap(struct elink_params
*params
,
11836 struct elink_vars
*vars
)
11839 uint32_t dont_clear_stat
, lfa_sts
;
11840 struct bnx2x_softc
*sc
= params
->sc
;
11842 /* Sync the link parameters */
11843 elink_link_status_update(params
, vars
);
11846 * The module verification was already done by previous link owner,
11847 * so this call is meant only to get warning message
11850 for (phy_idx
= ELINK_INT_PHY
; phy_idx
< params
->num_phys
; phy_idx
++) {
11851 struct elink_phy
*phy
= ¶ms
->phy
[phy_idx
];
11852 if (phy
->phy_specific_func
) {
11853 PMD_DRV_LOG(DEBUG
, "Calling PHY specific func");
11854 phy
->phy_specific_func(phy
, params
, ELINK_PHY_INIT
);
11856 if ((phy
->media_type
== ELINK_ETH_PHY_SFPP_10G_FIBER
) ||
11857 (phy
->media_type
== ELINK_ETH_PHY_SFP_1G_FIBER
) ||
11858 (phy
->media_type
== ELINK_ETH_PHY_DA_TWINAX
))
11859 elink_verify_sfp_module(phy
, params
);
11861 lfa_sts
= REG_RD(sc
, params
->lfa_base
+
11862 offsetof(struct shmem_lfa
, lfa_sts
));
11864 dont_clear_stat
= lfa_sts
& SHMEM_LFA_DONT_CLEAR_STAT
;
11866 /* Re-enable the NIG/MAC */
11867 if (CHIP_IS_E3(sc
)) {
11868 if (!dont_clear_stat
) {
11869 REG_WR(sc
, GRCBASE_MISC
+
11870 MISC_REGISTERS_RESET_REG_2_CLEAR
,
11871 (MISC_REGISTERS_RESET_REG_2_MSTAT0
<<
11873 REG_WR(sc
, GRCBASE_MISC
+
11874 MISC_REGISTERS_RESET_REG_2_SET
,
11875 (MISC_REGISTERS_RESET_REG_2_MSTAT0
<<
11878 if (vars
->line_speed
< ELINK_SPEED_10000
)
11879 elink_umac_enable(params
, vars
, 0);
11881 elink_xmac_enable(params
, vars
, 0);
11883 if (vars
->line_speed
< ELINK_SPEED_10000
)
11884 elink_emac_enable(params
, vars
, 0);
11886 elink_bmac_enable(params
, vars
, 0, !dont_clear_stat
);
11889 /* Increment LFA count */
11890 lfa_sts
= ((lfa_sts
& ~LINK_FLAP_AVOIDANCE_COUNT_MASK
) |
11891 (((((lfa_sts
& LINK_FLAP_AVOIDANCE_COUNT_MASK
) >>
11892 LINK_FLAP_AVOIDANCE_COUNT_OFFSET
) + 1) & 0xff)
11893 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET
));
11894 /* Clear link flap reason */
11895 lfa_sts
&= ~LFA_LINK_FLAP_REASON_MASK
;
11897 REG_WR(sc
, params
->lfa_base
+
11898 offsetof(struct shmem_lfa
, lfa_sts
), lfa_sts
);
11900 /* Disable NIG DRAIN */
11901 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
11903 /* Enable interrupts */
11904 elink_link_int_enable(params
);
11905 return ELINK_STATUS_OK
;
11908 static void elink_cannot_avoid_link_flap(struct elink_params
*params
,
11909 struct elink_vars
*vars
,
11912 uint32_t lfa_sts
, cfg_idx
, tmp_val
;
11913 struct bnx2x_softc
*sc
= params
->sc
;
11915 elink_link_reset(params
, vars
, 1);
11917 if (!params
->lfa_base
)
11919 /* Store the new link parameters */
11920 REG_WR(sc
, params
->lfa_base
+
11921 offsetof(struct shmem_lfa
, req_duplex
),
11922 params
->req_duplex
[0] | (params
->req_duplex
[1] << 16));
11924 REG_WR(sc
, params
->lfa_base
+
11925 offsetof(struct shmem_lfa
, req_flow_ctrl
),
11926 params
->req_flow_ctrl
[0] | (params
->req_flow_ctrl
[1] << 16));
11928 REG_WR(sc
, params
->lfa_base
+
11929 offsetof(struct shmem_lfa
, req_line_speed
),
11930 params
->req_line_speed
[0] | (params
->req_line_speed
[1] << 16));
11932 for (cfg_idx
= 0; cfg_idx
< SHMEM_LINK_CONFIG_SIZE
; cfg_idx
++) {
11933 REG_WR(sc
, params
->lfa_base
+
11934 offsetof(struct shmem_lfa
,
11935 speed_cap_mask
[cfg_idx
]),
11936 params
->speed_cap_mask
[cfg_idx
]);
11939 tmp_val
= REG_RD(sc
, params
->lfa_base
+
11940 offsetof(struct shmem_lfa
, additional_config
));
11941 tmp_val
&= ~REQ_FC_AUTO_ADV_MASK
;
11942 tmp_val
|= params
->req_fc_auto_adv
;
11944 REG_WR(sc
, params
->lfa_base
+
11945 offsetof(struct shmem_lfa
, additional_config
), tmp_val
);
11947 lfa_sts
= REG_RD(sc
, params
->lfa_base
+
11948 offsetof(struct shmem_lfa
, lfa_sts
));
11950 /* Clear the "Don't Clear Statistics" bit, and set reason */
11951 lfa_sts
&= ~SHMEM_LFA_DONT_CLEAR_STAT
;
11953 /* Set link flap reason */
11954 lfa_sts
&= ~LFA_LINK_FLAP_REASON_MASK
;
11955 lfa_sts
|= ((lfa_status
& LFA_LINK_FLAP_REASON_MASK
) <<
11956 LFA_LINK_FLAP_REASON_OFFSET
);
11958 /* Increment link flap counter */
11959 lfa_sts
= ((lfa_sts
& ~LINK_FLAP_COUNT_MASK
) |
11960 (((((lfa_sts
& LINK_FLAP_COUNT_MASK
) >>
11961 LINK_FLAP_COUNT_OFFSET
) + 1) & 0xff)
11962 << LINK_FLAP_COUNT_OFFSET
));
11963 REG_WR(sc
, params
->lfa_base
+
11964 offsetof(struct shmem_lfa
, lfa_sts
), lfa_sts
);
11965 /* Proceed with regular link initialization */
11968 elink_status_t
elink_phy_init(struct elink_params
*params
,
11969 struct elink_vars
*vars
)
11972 struct bnx2x_softc
*sc
= params
->sc
;
11973 PMD_DRV_LOG(DEBUG
, "Phy Initialization started");
11974 PMD_DRV_LOG(DEBUG
, "(1) req_speed %d, req_flowctrl %d",
11975 params
->req_line_speed
[0], params
->req_flow_ctrl
[0]);
11976 PMD_DRV_LOG(DEBUG
, "(2) req_speed %d, req_flowctrl %d",
11977 params
->req_line_speed
[1], params
->req_flow_ctrl
[1]);
11978 PMD_DRV_LOG(DEBUG
, "req_adv_flow_ctrl 0x%x", params
->req_fc_auto_adv
);
11979 vars
->link_status
= 0;
11980 vars
->phy_link_up
= 0;
11982 vars
->line_speed
= 0;
11983 vars
->duplex
= DUPLEX_FULL
;
11984 vars
->flow_ctrl
= ELINK_FLOW_CTRL_NONE
;
11985 vars
->mac_type
= ELINK_MAC_TYPE_NONE
;
11986 vars
->phy_flags
= 0;
11987 vars
->check_kr2_recovery_cnt
= 0;
11988 params
->link_flags
= ELINK_PHY_INITIALIZED
;
11989 /* Driver opens NIG-BRB filters */
11990 elink_set_rx_filter(params
, 1);
11991 /* Check if link flap can be avoided */
11992 lfa_status
= elink_check_lfa(params
);
11994 if (lfa_status
== 0) {
11995 PMD_DRV_LOG(DEBUG
, "Link Flap Avoidance in progress");
11996 return elink_avoid_link_flap(params
, vars
);
11999 PMD_DRV_LOG(DEBUG
, "Cannot avoid link flap lfa_sta=0x%x", lfa_status
);
12000 elink_cannot_avoid_link_flap(params
, vars
, lfa_status
);
12002 /* Disable attentions */
12003 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ params
->port
* 4,
12004 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
12005 ELINK_NIG_MASK_XGXS0_LINK10G
|
12006 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
12007 ELINK_NIG_MASK_MI_INT
));
12009 elink_emac_init(params
);
12011 if (params
->feature_config_flags
& ELINK_FEATURE_CONFIG_PFC_ENABLED
)
12012 vars
->link_status
|= LINK_STATUS_PFC_ENABLED
;
12014 if ((params
->num_phys
== 0) && !CHIP_REV_IS_SLOW(sc
)) {
12015 PMD_DRV_LOG(DEBUG
, "No phy found for initialization !!");
12016 return ELINK_STATUS_ERROR
;
12018 set_phy_vars(params
, vars
);
12020 PMD_DRV_LOG(DEBUG
, "Num of phys on board: %d", params
->num_phys
);
12022 switch (params
->loopback_mode
) {
12023 case ELINK_LOOPBACK_BMAC
:
12024 elink_init_bmac_loopback(params
, vars
);
12026 case ELINK_LOOPBACK_EMAC
:
12027 elink_init_emac_loopback(params
, vars
);
12029 case ELINK_LOOPBACK_XMAC
:
12030 elink_init_xmac_loopback(params
, vars
);
12032 case ELINK_LOOPBACK_UMAC
:
12033 elink_init_umac_loopback(params
, vars
);
12035 case ELINK_LOOPBACK_XGXS
:
12036 case ELINK_LOOPBACK_EXT_PHY
:
12037 elink_init_xgxs_loopback(params
, vars
);
12040 if (!CHIP_IS_E3(sc
)) {
12041 if (params
->switch_cfg
== ELINK_SWITCH_CFG_10G
)
12042 elink_xgxs_deassert(params
);
12044 elink_serdes_deassert(sc
, params
->port
);
12046 elink_link_initialize(params
, vars
);
12048 elink_link_int_enable(params
);
12051 elink_update_mng(params
, vars
->link_status
);
12053 elink_update_mng_eee(params
, vars
->eee_status
);
12054 return ELINK_STATUS_OK
;
12057 static elink_status_t
elink_link_reset(struct elink_params
*params
,
12058 struct elink_vars
*vars
,
12059 uint8_t reset_ext_phy
)
12061 struct bnx2x_softc
*sc
= params
->sc
;
12062 uint8_t phy_index
, port
= params
->port
, clear_latch_ind
= 0;
12063 PMD_DRV_LOG(DEBUG
, "Resetting the link of port %d", port
);
12064 /* Disable attentions */
12065 vars
->link_status
= 0;
12066 elink_update_mng(params
, vars
->link_status
);
12067 vars
->eee_status
&= ~(SHMEM_EEE_LP_ADV_STATUS_MASK
|
12068 SHMEM_EEE_ACTIVE_BIT
);
12069 elink_update_mng_eee(params
, vars
->eee_status
);
12070 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
* 4,
12071 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
12072 ELINK_NIG_MASK_XGXS0_LINK10G
|
12073 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
12074 ELINK_NIG_MASK_MI_INT
));
12076 /* Activate nig drain */
12077 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
* 4, 1);
12079 /* Disable nig egress interface */
12080 if (!CHIP_IS_E3(sc
)) {
12081 REG_WR(sc
, NIG_REG_BMAC0_OUT_EN
+ port
* 4, 0);
12082 REG_WR(sc
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
* 4, 0);
12084 if (!CHIP_IS_E3(sc
))
12085 elink_set_bmac_rx(sc
, port
, 0);
12086 if (CHIP_IS_E3(sc
) && !CHIP_REV_IS_FPGA(sc
)) {
12087 elink_set_xmac_rxtx(params
, 0);
12088 elink_set_umac_rxtx(params
, 0);
12091 if (!CHIP_IS_E3(sc
))
12092 REG_WR(sc
, NIG_REG_NIG_EMAC0_EN
+ port
* 4, 0);
12095 /* The PHY reset is controlled by GPIO 1
12096 * Hold it as vars low
12098 /* Clear link led */
12099 elink_set_mdio_emac_per_phy(sc
, params
);
12100 elink_set_led(params
, vars
, ELINK_LED_MODE_OFF
, 0);
12102 if (reset_ext_phy
&& (!CHIP_REV_IS_SLOW(sc
))) {
12103 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< params
->num_phys
;
12105 if (params
->phy
[phy_index
].link_reset
) {
12106 elink_set_aer_mmd(params
,
12107 ¶ms
->phy
[phy_index
]);
12108 params
->phy
[phy_index
].link_reset(¶ms
->
12113 if (params
->phy
[phy_index
].flags
&
12114 ELINK_FLAGS_REARM_LATCH_SIGNAL
)
12115 clear_latch_ind
= 1;
12119 if (clear_latch_ind
) {
12120 /* Clear latching indication */
12121 elink_rearm_latch_signal(sc
, port
, 0);
12122 elink_bits_dis(sc
, NIG_REG_LATCH_BC_0
+ port
* 4,
12123 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT
);
12125 if (params
->phy
[ELINK_INT_PHY
].link_reset
)
12126 params
->phy
[ELINK_INT_PHY
].link_reset(¶ms
->
12131 /* Disable nig ingress interface */
12132 if (!CHIP_IS_E3(sc
)) {
12134 REG_WR(sc
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
12135 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
12136 REG_WR(sc
, NIG_REG_BMAC0_IN_EN
+ port
* 4, 0);
12137 REG_WR(sc
, NIG_REG_EMAC0_IN_EN
+ port
* 4, 0);
12139 uint32_t xmac_base
=
12140 (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
12141 elink_set_xumac_nig(params
, 0, 0);
12142 if (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
12143 MISC_REGISTERS_RESET_REG_2_XMAC
)
12144 REG_WR(sc
, xmac_base
+ XMAC_REG_CTRL
,
12145 XMAC_CTRL_REG_SOFT_RESET
);
12148 vars
->phy_flags
= 0;
12149 return ELINK_STATUS_OK
;
12152 elink_status_t
elink_lfa_reset(struct elink_params
* params
,
12153 struct elink_vars
* vars
)
12155 struct bnx2x_softc
*sc
= params
->sc
;
12157 vars
->phy_flags
= 0;
12158 params
->link_flags
&= ~ELINK_PHY_INITIALIZED
;
12159 if (!params
->lfa_base
)
12160 return elink_link_reset(params
, vars
, 1);
12162 * Activate NIG drain so that during this time the device won't send
12163 * anything while it is unable to response.
12165 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 1);
12168 * Close gracefully the gate from BMAC to NIG such that no half packets
12171 if (!CHIP_IS_E3(sc
))
12172 elink_set_bmac_rx(sc
, params
->port
, 0);
12174 if (CHIP_IS_E3(sc
)) {
12175 elink_set_xmac_rxtx(params
, 0);
12176 elink_set_umac_rxtx(params
, 0);
12178 /* Wait 10ms for the pipe to clean up */
12181 /* Clean the NIG-BRB using the network filters in a way that will
12182 * not cut a packet in the middle.
12184 elink_set_rx_filter(params
, 0);
12187 * Re-open the gate between the BMAC and the NIG, after verifying the
12188 * gate to the BRB is closed, otherwise packets may arrive to the
12189 * firmware before driver had initialized it. The target is to achieve
12190 * minimum management protocol down time.
12192 if (!CHIP_IS_E3(sc
))
12193 elink_set_bmac_rx(sc
, params
->port
, 1);
12195 if (CHIP_IS_E3(sc
)) {
12196 elink_set_xmac_rxtx(params
, 1);
12197 elink_set_umac_rxtx(params
, 1);
12199 /* Disable NIG drain */
12200 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
12201 return ELINK_STATUS_OK
;
12204 /****************************************************************************/
12205 /* Common function */
12206 /****************************************************************************/
12207 static elink_status_t
elink_8073_common_init_phy(struct bnx2x_softc
*sc
,
12208 uint32_t shmem_base_path
[],
12209 uint32_t shmem2_base_path
[],
12211 __rte_unused
uint32_t chip_id
)
12213 struct elink_phy phy
[PORT_MAX
];
12214 struct elink_phy
*phy_blk
[PORT_MAX
];
12217 int8_t port_of_path
= 0;
12218 uint32_t swap_val
, swap_override
;
12219 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
12220 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
12221 port
^= (swap_val
&& swap_override
);
12222 elink_ext_phy_hw_reset(sc
, port
);
12223 /* PART1 - Reset both phys */
12224 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12225 uint32_t shmem_base
, shmem2_base
;
12226 /* In E2, same phy is using for port0 of the two paths */
12227 if (CHIP_IS_E1x(sc
)) {
12228 shmem_base
= shmem_base_path
[0];
12229 shmem2_base
= shmem2_base_path
[0];
12230 port_of_path
= port
;
12232 shmem_base
= shmem_base_path
[port
];
12233 shmem2_base
= shmem2_base_path
[port
];
12237 /* Extract the ext phy address for the port */
12238 if (elink_populate_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
12239 port_of_path
, &phy
[port
]) !=
12241 PMD_DRV_LOG(DEBUG
, "populate_phy failed");
12242 return ELINK_STATUS_ERROR
;
12244 /* Disable attentions */
12245 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+
12247 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
12248 ELINK_NIG_MASK_XGXS0_LINK10G
|
12249 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
12250 ELINK_NIG_MASK_MI_INT
));
12252 /* Need to take the phy out of low power mode in order
12253 * to write to access its registers
12255 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
12256 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
12258 /* Reset the phy */
12259 elink_cl45_write(sc
, &phy
[port
],
12260 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1 << 15);
12263 /* Add delay of 150ms after reset */
12266 if (phy
[PORT_0
].addr
& 0x1) {
12267 phy_blk
[PORT_0
] = &(phy
[PORT_1
]);
12268 phy_blk
[PORT_1
] = &(phy
[PORT_0
]);
12270 phy_blk
[PORT_0
] = &(phy
[PORT_0
]);
12271 phy_blk
[PORT_1
] = &(phy
[PORT_1
]);
12274 /* PART2 - Download firmware to both phys */
12275 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12276 if (CHIP_IS_E1x(sc
))
12277 port_of_path
= port
;
12281 PMD_DRV_LOG(DEBUG
, "Loading spirom for phy address 0x%x",
12282 phy_blk
[port
]->addr
);
12283 if (elink_8073_8727_external_rom_boot(sc
, phy_blk
[port
],
12285 return ELINK_STATUS_ERROR
;
12287 /* Only set bit 10 = 1 (Tx power down) */
12288 elink_cl45_read(sc
, phy_blk
[port
],
12290 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
12292 /* Phase1 of TX_POWER_DOWN reset */
12293 elink_cl45_write(sc
, phy_blk
[port
],
12295 MDIO_PMA_REG_TX_POWER_DOWN
, (val
| 1 << 10));
12298 /* Toggle Transmitter: Power down and then up with 600ms delay
12303 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12304 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12305 /* Phase2 of POWER_DOWN_RESET */
12306 /* Release bit 10 (Release Tx power down) */
12307 elink_cl45_read(sc
, phy_blk
[port
],
12309 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
12311 elink_cl45_write(sc
, phy_blk
[port
],
12313 MDIO_PMA_REG_TX_POWER_DOWN
,
12314 (val
& (~(1 << 10))));
12317 /* Read modify write the SPI-ROM version select register */
12318 elink_cl45_read(sc
, phy_blk
[port
],
12320 MDIO_PMA_REG_EDC_FFE_MAIN
, &val
);
12321 elink_cl45_write(sc
, phy_blk
[port
],
12323 MDIO_PMA_REG_EDC_FFE_MAIN
, (val
| (1 << 12)));
12325 /* set GPIO2 back to LOW */
12326 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_2
,
12327 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
12329 return ELINK_STATUS_OK
;
12332 static elink_status_t
elink_8726_common_init_phy(struct bnx2x_softc
*sc
,
12333 uint32_t shmem_base_path
[],
12334 uint32_t shmem2_base_path
[],
12336 __rte_unused
uint32_t chip_id
)
12340 struct elink_phy phy
;
12341 /* Use port1 because of the static port-swap */
12342 /* Enable the module detection interrupt */
12343 val
= REG_RD(sc
, MISC_REG_GPIO_EVENT_EN
);
12344 val
|= ((1 << MISC_REGISTERS_GPIO_3
) |
12346 (MISC_REGISTERS_GPIO_3
+ MISC_REGISTERS_GPIO_PORT_SHIFT
)));
12347 REG_WR(sc
, MISC_REG_GPIO_EVENT_EN
, val
);
12349 elink_ext_phy_hw_reset(sc
, 0);
12351 for (port
= 0; port
< PORT_MAX
; port
++) {
12352 uint32_t shmem_base
, shmem2_base
;
12354 /* In E2, same phy is using for port0 of the two paths */
12355 if (CHIP_IS_E1x(sc
)) {
12356 shmem_base
= shmem_base_path
[0];
12357 shmem2_base
= shmem2_base_path
[0];
12359 shmem_base
= shmem_base_path
[port
];
12360 shmem2_base
= shmem2_base_path
[port
];
12362 /* Extract the ext phy address for the port */
12363 if (elink_populate_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
12364 port
, &phy
) != ELINK_STATUS_OK
) {
12365 PMD_DRV_LOG(DEBUG
, "populate phy failed");
12366 return ELINK_STATUS_ERROR
;
12370 elink_cl45_write(sc
, &phy
,
12371 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x0001);
12373 /* Set fault module detected LED on */
12374 elink_cb_gpio_write(sc
, MISC_REGISTERS_GPIO_0
,
12375 MISC_REGISTERS_GPIO_HIGH
, port
);
12378 return ELINK_STATUS_OK
;
12381 static void elink_get_ext_phy_reset_gpio(struct bnx2x_softc
*sc
,
12382 uint32_t shmem_base
, uint8_t * io_gpio
,
12386 uint32_t phy_gpio_reset
= REG_RD(sc
, shmem_base
+
12387 offsetof(struct shmem_region
,
12389 port_hw_config
[PORT_0
].
12391 switch (phy_gpio_reset
) {
12392 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0
:
12396 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0
:
12400 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0
:
12404 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0
:
12408 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1
:
12412 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1
:
12416 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1
:
12420 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1
:
12425 /* Don't override the io_gpio and io_port */
12430 static elink_status_t
elink_8727_common_init_phy(struct bnx2x_softc
*sc
,
12431 uint32_t shmem_base_path
[],
12432 uint32_t shmem2_base_path
[],
12434 __rte_unused
uint32_t chip_id
)
12436 int8_t port
, reset_gpio
;
12437 uint32_t swap_val
, swap_override
;
12438 struct elink_phy phy
[PORT_MAX
];
12439 struct elink_phy
*phy_blk
[PORT_MAX
];
12440 int8_t port_of_path
;
12441 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
12442 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
12444 reset_gpio
= MISC_REGISTERS_GPIO_1
;
12447 /* Retrieve the reset gpio/port which control the reset.
12448 * Default is GPIO1, PORT1
12450 elink_get_ext_phy_reset_gpio(sc
, shmem_base_path
[0],
12451 (uint8_t *) & reset_gpio
,
12452 (uint8_t *) & port
);
12454 /* Calculate the port based on port swap */
12455 port
^= (swap_val
&& swap_override
);
12457 /* Initiate PHY reset */
12458 elink_cb_gpio_write(sc
, reset_gpio
, MISC_REGISTERS_GPIO_OUTPUT_LOW
,
12461 elink_cb_gpio_write(sc
, reset_gpio
, MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
12466 /* PART1 - Reset both phys */
12467 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12468 uint32_t shmem_base
, shmem2_base
;
12470 /* In E2, same phy is using for port0 of the two paths */
12471 if (CHIP_IS_E1x(sc
)) {
12472 shmem_base
= shmem_base_path
[0];
12473 shmem2_base
= shmem2_base_path
[0];
12474 port_of_path
= port
;
12476 shmem_base
= shmem_base_path
[port
];
12477 shmem2_base
= shmem2_base_path
[port
];
12481 /* Extract the ext phy address for the port */
12482 if (elink_populate_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
12483 port_of_path
, &phy
[port
]) !=
12485 PMD_DRV_LOG(DEBUG
, "populate phy failed");
12486 return ELINK_STATUS_ERROR
;
12488 /* disable attentions */
12489 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+
12491 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
12492 ELINK_NIG_MASK_XGXS0_LINK10G
|
12493 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
12494 ELINK_NIG_MASK_MI_INT
));
12496 /* Reset the phy */
12497 elink_cl45_write(sc
, &phy
[port
],
12498 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1 << 15);
12501 /* Add delay of 150ms after reset */
12503 if (phy
[PORT_0
].addr
& 0x1) {
12504 phy_blk
[PORT_0
] = &(phy
[PORT_1
]);
12505 phy_blk
[PORT_1
] = &(phy
[PORT_0
]);
12507 phy_blk
[PORT_0
] = &(phy
[PORT_0
]);
12508 phy_blk
[PORT_1
] = &(phy
[PORT_1
]);
12510 /* PART2 - Download firmware to both phys */
12511 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12512 if (CHIP_IS_E1x(sc
))
12513 port_of_path
= port
;
12516 PMD_DRV_LOG(DEBUG
, "Loading spirom for phy address 0x%x",
12517 phy_blk
[port
]->addr
);
12518 if (elink_8073_8727_external_rom_boot(sc
, phy_blk
[port
],
12520 return ELINK_STATUS_ERROR
;
12521 /* Disable PHY transmitter output */
12522 elink_cl45_write(sc
, phy_blk
[port
],
12523 MDIO_PMA_DEVAD
, MDIO_PMA_REG_TX_DISABLE
, 1);
12526 return ELINK_STATUS_OK
;
12529 static elink_status_t
elink_84833_common_init_phy(struct bnx2x_softc
*sc
,
12530 uint32_t shmem_base_path
[],
12531 __rte_unused
uint32_t
12532 shmem2_base_path
[],
12533 __rte_unused
uint8_t
12534 phy_index
, uint32_t chip_id
)
12536 uint8_t reset_gpios
;
12537 reset_gpios
= elink_84833_get_reset_gpios(sc
, shmem_base_path
, chip_id
);
12538 elink_cb_gpio_mult_write(sc
, reset_gpios
,
12539 MISC_REGISTERS_GPIO_OUTPUT_LOW
);
12541 elink_cb_gpio_mult_write(sc
, reset_gpios
,
12542 MISC_REGISTERS_GPIO_OUTPUT_HIGH
);
12543 PMD_DRV_LOG(DEBUG
, "84833 reset pulse on pin values 0x%x", reset_gpios
);
12544 return ELINK_STATUS_OK
;
12547 static elink_status_t
elink_ext_phy_common_init(struct bnx2x_softc
*sc
,
12548 uint32_t shmem_base_path
[],
12549 uint32_t shmem2_base_path
[],
12551 uint32_t ext_phy_type
,
12554 elink_status_t rc
= ELINK_STATUS_OK
;
12556 switch (ext_phy_type
) {
12557 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8073
:
12558 rc
= elink_8073_common_init_phy(sc
, shmem_base_path
,
12560 phy_index
, chip_id
);
12562 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8722
:
12563 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727
:
12564 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8727_NOC
:
12565 rc
= elink_8727_common_init_phy(sc
, shmem_base_path
,
12567 phy_index
, chip_id
);
12570 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
:
12571 /* GPIO1 affects both ports, so there's need to pull
12572 * it for single port alone
12574 rc
= elink_8726_common_init_phy(sc
, shmem_base_path
,
12576 phy_index
, chip_id
);
12578 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84833
:
12579 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X84834
:
12580 /* GPIO3's are linked, and so both need to be toggled
12581 * to obtain required 2us pulse.
12583 rc
= elink_84833_common_init_phy(sc
, shmem_base_path
,
12585 phy_index
, chip_id
);
12587 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
12588 rc
= ELINK_STATUS_ERROR
;
12592 "ext_phy 0x%x common init not required",
12597 if (rc
!= ELINK_STATUS_OK
)
12598 elink_cb_event_log(sc
, ELINK_LOG_ID_PHY_UNINITIALIZED
, 0); // "Warning: PHY was not initialized,"
12604 elink_status_t
elink_common_init_phy(struct bnx2x_softc
* sc
,
12605 uint32_t shmem_base_path
[],
12606 uint32_t shmem2_base_path
[],
12608 __rte_unused
uint8_t one_port_enabled
)
12610 elink_status_t rc
= ELINK_STATUS_OK
;
12611 uint32_t phy_ver
, val
;
12612 uint8_t phy_index
= 0;
12613 uint32_t ext_phy_type
, ext_phy_config
;
12615 elink_set_mdio_clk(sc
, GRCBASE_EMAC0
);
12616 elink_set_mdio_clk(sc
, GRCBASE_EMAC1
);
12617 PMD_DRV_LOG(DEBUG
, "Begin common phy init");
12618 if (CHIP_IS_E3(sc
)) {
12620 val
= REG_RD(sc
, MISC_REG_GEN_PURP_HWG
);
12621 REG_WR(sc
, MISC_REG_GEN_PURP_HWG
, val
| 1);
12623 /* Check if common init was already done */
12624 phy_ver
= REG_RD(sc
, shmem_base_path
[0] +
12625 offsetof(struct shmem_region
,
12626 port_mb
[PORT_0
].ext_phy_fw_version
));
12628 PMD_DRV_LOG(DEBUG
, "Not doing common init; phy ver is 0x%x",
12630 return ELINK_STATUS_OK
;
12633 /* Read the ext_phy_type for arbitrary port(0) */
12634 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< ELINK_MAX_PHYS
;
12636 ext_phy_config
= elink_get_ext_phy_config(sc
,
12637 shmem_base_path
[0],
12639 ext_phy_type
= ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config
);
12640 rc
|= elink_ext_phy_common_init(sc
, shmem_base_path
,
12642 phy_index
, ext_phy_type
,
12648 static void elink_check_over_curr(struct elink_params
*params
,
12649 struct elink_vars
*vars
)
12651 struct bnx2x_softc
*sc
= params
->sc
;
12653 uint8_t port
= params
->port
;
12656 cfg_pin
= (REG_RD(sc
, params
->shmem_base
+
12657 offsetof(struct shmem_region
,
12658 dev_info
.port_hw_config
[port
].
12659 e3_cmn_pin_cfg1
)) &
12660 PORT_HW_CFG_E3_OVER_CURRENT_MASK
) >>
12661 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT
;
12663 /* Ignore check if no external input PIN available */
12664 if (elink_get_cfg_pin(sc
, cfg_pin
, &pin_val
) != ELINK_STATUS_OK
)
12668 if ((vars
->phy_flags
& PHY_OVER_CURRENT_FLAG
) == 0) {
12669 elink_cb_event_log(sc
, ELINK_LOG_ID_OVER_CURRENT
, params
->port
); //"Error: Power fault on Port %d has"
12670 // " been detected and the power to "
12671 // "that SFP+ module has been removed"
12672 // " to prevent failure of the card."
12673 // " Please remove the SFP+ module and"
12674 // " restart the system to clear this"
12676 vars
->phy_flags
|= PHY_OVER_CURRENT_FLAG
;
12677 elink_warpcore_power_module(params
, 0);
12680 vars
->phy_flags
&= ~PHY_OVER_CURRENT_FLAG
;
12683 /* Returns 0 if no change occurred since last check; 1 otherwise. */
12684 static uint8_t elink_analyze_link_error(struct elink_params
*params
,
12685 struct elink_vars
*vars
,
12686 uint32_t status
, uint32_t phy_flag
,
12687 uint32_t link_flag
, uint8_t notify
)
12689 struct bnx2x_softc
*sc
= params
->sc
;
12690 /* Compare new value with previous value */
12692 uint32_t old_status
= (vars
->phy_flags
& phy_flag
) ? 1 : 0;
12694 if ((status
^ old_status
) == 0)
12697 /* If values differ */
12698 switch (phy_flag
) {
12699 case PHY_HALF_OPEN_CONN_FLAG
:
12700 PMD_DRV_LOG(DEBUG
, "Analyze Remote Fault");
12702 case PHY_SFP_TX_FAULT_FLAG
:
12703 PMD_DRV_LOG(DEBUG
, "Analyze TX Fault");
12706 PMD_DRV_LOG(DEBUG
, "Analyze UNKNOWN");
12708 PMD_DRV_LOG(DEBUG
, "Link changed:[%x %x]->%x", vars
->link_up
,
12709 old_status
, status
);
12711 /* a. Update shmem->link_status accordingly
12712 * b. Update elink_vars->link_up
12715 vars
->link_status
&= ~LINK_STATUS_LINK_UP
;
12716 vars
->link_status
|= link_flag
;
12718 vars
->phy_flags
|= phy_flag
;
12720 /* activate nig drain */
12721 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 1);
12722 /* Set LED mode to off since the PHY doesn't know about these
12725 led_mode
= ELINK_LED_MODE_OFF
;
12727 vars
->link_status
|= LINK_STATUS_LINK_UP
;
12728 vars
->link_status
&= ~link_flag
;
12730 vars
->phy_flags
&= ~phy_flag
;
12731 led_mode
= ELINK_LED_MODE_OPER
;
12733 /* Clear nig drain */
12734 REG_WR(sc
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
* 4, 0);
12736 elink_sync_link(params
, vars
);
12737 /* Update the LED according to the link state */
12738 elink_set_led(params
, vars
, led_mode
, ELINK_SPEED_10000
);
12740 /* Update link status in the shared memory */
12741 elink_update_mng(params
, vars
->link_status
);
12743 /* C. Trigger General Attention */
12744 vars
->periodic_flags
|= ELINK_PERIODIC_FLAGS_LINK_EVENT
;
12746 elink_cb_notify_link_changed(sc
);
12751 /******************************************************************************
12753 * This function checks for half opened connection change indication.
12754 * When such change occurs, it calls the elink_analyze_link_error
12755 * to check if Remote Fault is set or cleared. Reception of remote fault
12756 * status message in the MAC indicates that the peer's MAC has detected
12757 * a fault, for example, due to break in the TX side of fiber.
12759 ******************************************************************************/
12760 static elink_status_t
elink_check_half_open_conn(struct elink_params
*params
,
12761 struct elink_vars
*vars
,
12764 struct bnx2x_softc
*sc
= params
->sc
;
12765 uint32_t lss_status
= 0;
12767 /* In case link status is physically up @ 10G do */
12768 if (((vars
->phy_flags
& PHY_PHYSICAL_LINK_FLAG
) == 0) ||
12769 (REG_RD(sc
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
* 4)))
12770 return ELINK_STATUS_OK
;
12772 if (CHIP_IS_E3(sc
) &&
12773 (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
12774 (MISC_REGISTERS_RESET_REG_2_XMAC
))) {
12775 /* Check E3 XMAC */
12776 /* Note that link speed cannot be queried here, since it may be
12777 * zero while link is down. In case UMAC is active, LSS will
12778 * simply not be set
12780 mac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
12782 /* Clear stick bits (Requires rising edge) */
12783 REG_WR(sc
, mac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
, 0);
12784 REG_WR(sc
, mac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
,
12785 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS
|
12786 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS
);
12787 if (REG_RD(sc
, mac_base
+ XMAC_REG_RX_LSS_STATUS
))
12790 elink_analyze_link_error(params
, vars
, lss_status
,
12791 PHY_HALF_OPEN_CONN_FLAG
,
12792 LINK_STATUS_NONE
, notify
);
12793 } else if (REG_RD(sc
, MISC_REG_RESET_REG_2
) &
12794 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< params
->port
)) {
12795 /* Check E1X / E2 BMAC */
12796 uint32_t lss_status_reg
;
12797 uint32_t wb_data
[2];
12798 mac_base
= params
->port
? NIG_REG_INGRESS_BMAC1_MEM
:
12799 NIG_REG_INGRESS_BMAC0_MEM
;
12800 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
12801 if (CHIP_IS_E2(sc
))
12802 lss_status_reg
= BIGMAC2_REGISTER_RX_LSS_STAT
;
12804 lss_status_reg
= BIGMAC_REGISTER_RX_LSS_STATUS
;
12806 REG_RD_DMAE(sc
, mac_base
+ lss_status_reg
, wb_data
, 2);
12807 lss_status
= (wb_data
[0] > 0);
12809 elink_analyze_link_error(params
, vars
, lss_status
,
12810 PHY_HALF_OPEN_CONN_FLAG
,
12811 LINK_STATUS_NONE
, notify
);
12813 return ELINK_STATUS_OK
;
12816 static void elink_sfp_tx_fault_detection(struct elink_phy
*phy
,
12817 struct elink_params
*params
,
12818 struct elink_vars
*vars
)
12820 struct bnx2x_softc
*sc
= params
->sc
;
12821 uint32_t cfg_pin
, value
= 0;
12822 uint8_t led_change
, port
= params
->port
;
12824 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
12825 cfg_pin
= (REG_RD(sc
, params
->shmem_base
+ offsetof(struct shmem_region
,
12830 PORT_HW_CFG_E3_TX_FAULT_MASK
) >>
12831 PORT_HW_CFG_E3_TX_FAULT_SHIFT
;
12833 if (elink_get_cfg_pin(sc
, cfg_pin
, &value
)) {
12834 PMD_DRV_LOG(DEBUG
, "Failed to read pin 0x%02x", cfg_pin
);
12838 led_change
= elink_analyze_link_error(params
, vars
, value
,
12839 PHY_SFP_TX_FAULT_FLAG
,
12840 LINK_STATUS_SFP_TX_FAULT
, 1);
12843 /* Change TX_Fault led, set link status for further syncs */
12846 if (vars
->phy_flags
& PHY_SFP_TX_FAULT_FLAG
) {
12847 led_mode
= MISC_REGISTERS_GPIO_HIGH
;
12848 vars
->link_status
|= LINK_STATUS_SFP_TX_FAULT
;
12850 led_mode
= MISC_REGISTERS_GPIO_LOW
;
12851 vars
->link_status
&= ~LINK_STATUS_SFP_TX_FAULT
;
12854 /* If module is unapproved, led should be on regardless */
12855 if (!(phy
->flags
& ELINK_FLAGS_SFP_NOT_APPROVED
)) {
12856 PMD_DRV_LOG(DEBUG
, "Change TX_Fault LED: ->%x",
12858 elink_set_e3_module_fault_led(params
, led_mode
);
12863 static void elink_kr2_recovery(struct elink_params
*params
,
12864 struct elink_vars
*vars
, struct elink_phy
*phy
)
12866 PMD_DRV_LOG(DEBUG
, "KR2 recovery");
12868 elink_warpcore_enable_AN_KR2(phy
, params
, vars
);
12869 elink_warpcore_restart_AN_KR(phy
, params
);
12872 static void elink_check_kr2_wa(struct elink_params
*params
,
12873 struct elink_vars
*vars
, struct elink_phy
*phy
)
12875 struct bnx2x_softc
*sc
= params
->sc
;
12876 uint16_t base_page
, next_page
, not_kr2_device
, lane
;
12879 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
12880 * Since some switches tend to reinit the AN process and clear the
12881 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
12882 * and recovered many times
12884 if (vars
->check_kr2_recovery_cnt
> 0) {
12885 vars
->check_kr2_recovery_cnt
--;
12889 sigdet
= elink_warpcore_get_sigdet(phy
, params
);
12891 if (!(vars
->link_attr_sync
& LINK_ATTR_SYNC_KR2_ENABLE
)) {
12892 elink_kr2_recovery(params
, vars
, phy
);
12893 PMD_DRV_LOG(DEBUG
, "No sigdet");
12898 lane
= elink_get_warpcore_lane(params
);
12899 CL22_WR_OVER_CL45(sc
, phy
, MDIO_REG_BANK_AER_BLOCK
,
12900 MDIO_AER_BLOCK_AER_REG
, lane
);
12901 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
12902 MDIO_AN_REG_LP_AUTO_NEG
, &base_page
);
12903 elink_cl45_read(sc
, phy
, MDIO_AN_DEVAD
,
12904 MDIO_AN_REG_LP_AUTO_NEG2
, &next_page
);
12905 elink_set_aer_mmd(params
, phy
);
12907 /* CL73 has not begun yet */
12908 if (base_page
== 0) {
12909 if (!(vars
->link_attr_sync
& LINK_ATTR_SYNC_KR2_ENABLE
)) {
12910 elink_kr2_recovery(params
, vars
, phy
);
12911 PMD_DRV_LOG(DEBUG
, "No BP");
12916 /* In case NP bit is not set in the BasePage, or it is set,
12917 * but only KX is advertised, declare this link partner as non-KR2
12920 not_kr2_device
= (((base_page
& 0x8000) == 0) ||
12921 (((base_page
& 0x8000) &&
12922 ((next_page
& 0xe0) == 0x20))));
12924 /* In case KR2 is already disabled, check if we need to re-enable it */
12925 if (!(vars
->link_attr_sync
& LINK_ATTR_SYNC_KR2_ENABLE
)) {
12926 if (!not_kr2_device
) {
12927 PMD_DRV_LOG(DEBUG
, "BP=0x%x, NP=0x%x", base_page
,
12929 elink_kr2_recovery(params
, vars
, phy
);
12933 /* KR2 is enabled, but not KR2 device */
12934 if (not_kr2_device
) {
12935 /* Disable KR2 on both lanes */
12936 PMD_DRV_LOG(DEBUG
, "BP=0x%x, NP=0x%x", base_page
, next_page
);
12937 elink_disable_kr2(params
, vars
, phy
);
12938 /* Restart AN on leading lane */
12939 elink_warpcore_restart_AN_KR(phy
, params
);
12944 void elink_period_func(struct elink_params
*params
, struct elink_vars
*vars
)
12947 struct bnx2x_softc
*sc
= params
->sc
;
12948 for (phy_idx
= ELINK_INT_PHY
; phy_idx
< ELINK_MAX_PHYS
; phy_idx
++) {
12949 if (params
->phy
[phy_idx
].flags
& ELINK_FLAGS_TX_ERROR_CHECK
) {
12950 elink_set_aer_mmd(params
, ¶ms
->phy
[phy_idx
]);
12951 if (elink_check_half_open_conn(params
, vars
, 1) !=
12953 PMD_DRV_LOG(DEBUG
, "Fault detection failed");
12959 if (CHIP_IS_E3(sc
)) {
12960 struct elink_phy
*phy
= ¶ms
->phy
[ELINK_INT_PHY
];
12961 elink_set_aer_mmd(params
, phy
);
12962 if ((phy
->supported
& ELINK_SUPPORTED_20000baseKR2_Full
) &&
12963 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
))
12964 elink_check_kr2_wa(params
, vars
, phy
);
12965 elink_check_over_curr(params
, vars
);
12966 if (vars
->rx_tx_asic_rst
)
12967 elink_warpcore_config_runtime(phy
, params
, vars
);
12969 if ((REG_RD(sc
, params
->shmem_base
+
12970 offsetof(struct shmem_region
,
12971 dev_info
.port_hw_config
[params
->port
].
12973 & PORT_HW_CFG_NET_SERDES_IF_MASK
) ==
12974 PORT_HW_CFG_NET_SERDES_IF_SFI
) {
12975 if (elink_is_sfp_module_plugged(params
)) {
12976 elink_sfp_tx_fault_detection(phy
, params
, vars
);
12977 } else if (vars
->link_status
& LINK_STATUS_SFP_TX_FAULT
) {
12978 /* Clean trail, interrupt corrects the leds */
12979 vars
->link_status
&= ~LINK_STATUS_SFP_TX_FAULT
;
12980 vars
->phy_flags
&= ~PHY_SFP_TX_FAULT_FLAG
;
12981 /* Update link status in the shared memory */
12982 elink_update_mng(params
, vars
->link_status
);
12988 uint8_t elink_fan_failure_det_req(struct bnx2x_softc
*sc
,
12989 uint32_t shmem_base
,
12990 uint32_t shmem2_base
, uint8_t port
)
12992 uint8_t phy_index
, fan_failure_det_req
= 0;
12993 struct elink_phy phy
;
12994 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< ELINK_MAX_PHYS
;
12996 if (elink_populate_phy(sc
, phy_index
, shmem_base
, shmem2_base
,
12998 != ELINK_STATUS_OK
) {
12999 PMD_DRV_LOG(DEBUG
, "populate phy failed");
13002 fan_failure_det_req
|= (phy
.flags
&
13003 ELINK_FLAGS_FAN_FAILURE_DET_REQ
);
13005 return fan_failure_det_req
;
13008 void elink_hw_reset_phy(struct elink_params
*params
)
13011 struct bnx2x_softc
*sc
= params
->sc
;
13012 elink_update_mng(params
, 0);
13013 elink_bits_dis(sc
, NIG_REG_MASK_INTERRUPT_PORT0
+ params
->port
* 4,
13014 (ELINK_NIG_MASK_XGXS0_LINK_STATUS
|
13015 ELINK_NIG_MASK_XGXS0_LINK10G
|
13016 ELINK_NIG_MASK_SERDES0_LINK_STATUS
|
13017 ELINK_NIG_MASK_MI_INT
));
13019 for (phy_index
= ELINK_INT_PHY
; phy_index
< ELINK_MAX_PHYS
; phy_index
++) {
13020 if (params
->phy
[phy_index
].hw_reset
) {
13021 params
->phy
[phy_index
].hw_reset(¶ms
->phy
[phy_index
],
13023 params
->phy
[phy_index
] = phy_null
;
13028 void elink_init_mod_abs_int(struct bnx2x_softc
*sc
, struct elink_vars
*vars
,
13029 __rte_unused
uint32_t chip_id
, uint32_t shmem_base
,
13030 uint32_t shmem2_base
, uint8_t port
)
13032 uint8_t gpio_num
= 0xff, gpio_port
= 0xff, phy_index
;
13034 uint32_t offset
, aeu_mask
, swap_val
, swap_override
, sync_offset
;
13035 if (CHIP_IS_E3(sc
)) {
13036 if (elink_get_mod_abs_int_cfg(sc
,
13040 &gpio_port
) != ELINK_STATUS_OK
)
13043 struct elink_phy phy
;
13044 for (phy_index
= ELINK_EXT_PHY1
; phy_index
< ELINK_MAX_PHYS
;
13046 if (elink_populate_phy(sc
, phy_index
, shmem_base
,
13047 shmem2_base
, port
, &phy
)
13048 != ELINK_STATUS_OK
) {
13049 PMD_DRV_LOG(DEBUG
, "populate phy failed");
13052 if (phy
.type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BNX2X8726
) {
13053 gpio_num
= MISC_REGISTERS_GPIO_3
;
13060 if (gpio_num
== 0xff)
13063 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13064 elink_cb_gpio_write(sc
, gpio_num
, MISC_REGISTERS_GPIO_INPUT_HI_Z
,
13067 swap_val
= REG_RD(sc
, NIG_REG_PORT_SWAP
);
13068 swap_override
= REG_RD(sc
, NIG_REG_STRAP_OVERRIDE
);
13069 gpio_port
^= (swap_val
&& swap_override
);
13071 vars
->aeu_int_mask
= AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0
<<
13072 (gpio_num
+ (gpio_port
<< 2));
13074 sync_offset
= shmem_base
+
13075 offsetof(struct shmem_region
,
13076 dev_info
.port_hw_config
[port
].aeu_int_mask
);
13077 REG_WR(sc
, sync_offset
, vars
->aeu_int_mask
);
13079 PMD_DRV_LOG(DEBUG
, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x",
13080 gpio_num
, gpio_port
, vars
->aeu_int_mask
);
13083 offset
= MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
;
13085 offset
= MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
;
13087 /* Open appropriate AEU for interrupts */
13088 aeu_mask
= REG_RD(sc
, offset
);
13089 aeu_mask
|= vars
->aeu_int_mask
;
13090 REG_WR(sc
, offset
, aeu_mask
);
13092 /* Enable the GPIO to trigger interrupt */
13093 val
= REG_RD(sc
, MISC_REG_GPIO_EVENT_EN
);
13094 val
|= 1 << (gpio_num
+ (gpio_port
<< 2));
13095 REG_WR(sc
, MISC_REG_GPIO_EVENT_EN
, val
);