ceph/src/spdk/dpdk/drivers/net/bnxt/bnxt_filter.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Broadcom
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _BNXT_FILTER_H_
   7 #define _BNXT_FILTER_H_
   8
   9 #include <rte_ether.h>
  10
  11 struct bnxt;
  12 struct bnxt_filter_info {
  13         STAILQ_ENTRY(bnxt_filter_info)  next;
  14         uint64_t                fw_l2_filter_id;
  15         uint64_t                fw_em_filter_id;
  16         uint64_t                fw_ntuple_filter_id;
  17 #define INVALID_MAC_INDEX       ((uint16_t)-1)
  18         uint16_t                mac_index;
  19 #define HWRM_CFA_L2_FILTER      0
  20 #define HWRM_CFA_EM_FILTER      1
  21 #define HWRM_CFA_NTUPLE_FILTER  2
  22         uint8_t                 filter_type;    //L2 or EM or NTUPLE filter
  23         uint32_t                dst_id;
  24
  25         /* Filter Characteristics */
  26         uint32_t                flags;
  27         uint32_t                enables;
  28         uint8_t                 l2_addr[ETHER_ADDR_LEN];
  29         uint8_t                 l2_addr_mask[ETHER_ADDR_LEN];
  30         uint16_t                l2_ovlan;
  31         uint16_t                l2_ovlan_mask;
  32         uint16_t                l2_ivlan;
  33         uint16_t                l2_ivlan_mask;
  34         uint8_t                 t_l2_addr[ETHER_ADDR_LEN];
  35         uint8_t                 t_l2_addr_mask[ETHER_ADDR_LEN];
  36         uint16_t                t_l2_ovlan;
  37         uint16_t                t_l2_ovlan_mask;
  38         uint16_t                t_l2_ivlan;
  39         uint16_t                t_l2_ivlan_mask;
  40         uint8_t                 tunnel_type;
  41         uint16_t                mirror_vnic_id;
  42         uint32_t                vni;
  43         uint8_t                 pri_hint;
  44         uint64_t                l2_filter_id_hint;
  45         uint32_t                src_id;
  46         uint8_t                 src_type;
  47         uint8_t                 src_macaddr[6];
  48         uint8_t                 dst_macaddr[6];
  49         uint32_t                dst_ipaddr[4];
  50         uint32_t                dst_ipaddr_mask[4];
  51         uint32_t                src_ipaddr[4];
  52         uint32_t                src_ipaddr_mask[4];
  53         uint16_t                dst_port;
  54         uint16_t                dst_port_mask;
  55         uint16_t                src_port;
  56         uint16_t                src_port_mask;
  57         uint16_t                ip_protocol;
  58         uint16_t                ip_addr_type;
  59         uint16_t                ethertype;
  60 };
  61
  62 struct bnxt_filter_info *bnxt_alloc_filter(struct bnxt *bp);
  63 struct bnxt_filter_info *bnxt_alloc_vf_filter(struct bnxt *bp, uint16_t vf);
  64 void bnxt_init_filters(struct bnxt *bp);
  65 void bnxt_free_all_filters(struct bnxt *bp);
  66 void bnxt_free_filter_mem(struct bnxt *bp);
  67 int bnxt_alloc_filter_mem(struct bnxt *bp);
  68 struct bnxt_filter_info *bnxt_get_unused_filter(struct bnxt *bp);
  69 void bnxt_free_filter(struct bnxt *bp, struct bnxt_filter_info *filter);
  70 struct bnxt_filter_info *bnxt_get_l2_filter(struct bnxt *bp,
  71                 struct bnxt_filter_info *nf, struct bnxt_vnic_info *vnic);
  72
  73 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_MACADDR  \
  74         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR
  75 #define EM_FLOW_ALLOC_INPUT_EN_SRC_MACADDR      \
  76         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR
  77 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR  \
  78         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR
  79 #define EM_FLOW_ALLOC_INPUT_EN_DST_MACADDR      \
  80         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR
  81 #define NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE   \
  82         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE
  83 #define EM_FLOW_ALLOC_INPUT_EN_ETHERTYPE       \
  84         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE
  85 #define EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID       \
  86         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID
  87 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR  \
  88         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR
  89 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK     \
  90         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK
  91 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR  \
  92         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR
  93 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK     \
  94         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK
  95 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT    \
  96         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT
  97 #define NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK       \
  98         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK
  99 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT    \
 100         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT
 101 #define NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK       \
 102         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK
 103 #define NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO        \
 104         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL
 105 #define EM_FLOW_ALLOC_INPUT_EN_SRC_IPADDR       \
 106         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR
 107 #define EM_FLOW_ALLOC_INPUT_EN_DST_IPADDR       \
 108         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR
 109 #define EM_FLOW_ALLOC_INPUT_EN_SRC_PORT \
 110         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT
 111 #define EM_FLOW_ALLOC_INPUT_EN_DST_PORT \
 112         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT
 113 #define EM_FLOW_ALLOC_INPUT_EN_IP_PROTO \
 114         HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL
 115 #define EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6   \
 116         HWRM_CFA_EM_FLOW_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
 117 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6       \
 118         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
 119 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN   \
 120         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN
 121 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE   \
 122         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE
 123 #define L2_FILTER_ALLOC_INPUT_EN_L2_ADDR_MASK   \
 124         HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK
 125 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UDP \
 126         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
 127 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_TCP \
 128         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP
 129 #define NTUPLE_FLTR_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN     \
 130         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN
 131 #define NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4       \
 132         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4
 133 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID       \
 134         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
 135 #define NTUPLE_FLTR_ALLOC_INPUT_EN_MIRROR_VNIC_ID       \
 136         HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID
 137 #endif