]> git.proxmox.com Git - ceph.git/blob - ceph/src/spdk/dpdk/drivers/net/bnxt/bnxt_hwrm.c
projects / ceph.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
update source to Ceph Pacific 16.2.2
[ceph.git] / ceph / src / spdk / dpdk / drivers / net / bnxt / bnxt_hwrm.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Broadcom
3 * All rights reserved.
4 */
5
6 #include <unistd.h>
7
8 #include <rte_byteorder.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_malloc.h>
12 #include <rte_memzone.h>
13 #include <rte_version.h>
14 #include <rte_io.h>
15
16 #include "bnxt.h"
17 #include "bnxt_filter.h"
18 #include "bnxt_hwrm.h"
19 #include "bnxt_rxq.h"
20 #include "bnxt_rxr.h"
21 #include "bnxt_ring.h"
22 #include "bnxt_txq.h"
23 #include "bnxt_txr.h"
24 #include "bnxt_vnic.h"
25 #include "hsi_struct_def_dpdk.h"
26
27 #define HWRM_SPEC_CODE_1_8_3 0x10803
28 #define HWRM_VERSION_1_9_1 0x10901
29 #define HWRM_VERSION_1_9_2 0x10903
30
31 struct bnxt_plcmodes_cfg {
32 uint32_t flags;
33 uint16_t jumbo_thresh;
34 uint16_t hds_offset;
35 uint16_t hds_threshold;
36 };
37
38 static int page_getenum(size_t size)
39 {
40 if (size <= 1 << 4)
41 return 4;
42 if (size <= 1 << 12)
43 return 12;
44 if (size <= 1 << 13)
45 return 13;
46 if (size <= 1 << 16)
47 return 16;
48 if (size <= 1 << 21)
49 return 21;
50 if (size <= 1 << 22)
51 return 22;
52 if (size <= 1 << 30)
53 return 30;
54 PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
55 return sizeof(void *) * 8 - 1;
56 }
57
58 static int page_roundup(size_t size)
59 {
60 return 1 << page_getenum(size);
61 }
62
63 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
64 uint8_t *pg_attr,
65 uint64_t *pg_dir)
66 {
67 if (rmem->nr_pages > 1) {
68 *pg_attr = 1;
69 *pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
70 } else {
71 *pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
72 }
73 }
74
75 /*
76 * HWRM Functions (sent to HWRM)
77 * These are named bnxt_hwrm_*() and return 0 on success or -110 if the
78 * HWRM command times out, or a negative error code if the HWRM
79 * command was failed by the FW.
80 */
81
82 static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
83 uint32_t msg_len, bool use_kong_mb)
84 {
85 unsigned int i;
86 struct input *req = msg;
87 struct output *resp = bp->hwrm_cmd_resp_addr;
88 uint32_t *data = msg;
89 uint8_t *bar;
90 uint8_t *valid;
91 uint16_t max_req_len = bp->max_req_len;
92 struct hwrm_short_input short_input = { 0 };
93 uint16_t bar_offset = use_kong_mb ?
94 GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
95 uint16_t mb_trigger_offset = use_kong_mb ?
96 GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
97 uint32_t timeout;
98
99 /* Do not send HWRM commands to firmware in error state */
100 if (bp->flags & BNXT_FLAG_FATAL_ERROR)
101 return 0;
102
103 timeout = bp->hwrm_cmd_timeout;
104
105 if (bp->flags & BNXT_FLAG_SHORT_CMD ||
106 msg_len > bp->max_req_len) {
107 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
108
109 memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
110 memcpy(short_cmd_req, req, msg_len);
111
112 short_input.req_type = rte_cpu_to_le_16(req->req_type);
113 short_input.signature = rte_cpu_to_le_16(
114 HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
115 short_input.size = rte_cpu_to_le_16(msg_len);
116 short_input.req_addr =
117 rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
118
119 data = (uint32_t *)&short_input;
120 msg_len = sizeof(short_input);
121
122 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
123 }
124
125 /* Write request msg to hwrm channel */
126 for (i = 0; i < msg_len; i += 4) {
127 bar = (uint8_t *)bp->bar0 + bar_offset + i;
128 rte_write32(*data, bar);
129 data++;
130 }
131
132 /* Zero the rest of the request space */
133 for (; i < max_req_len; i += 4) {
134 bar = (uint8_t *)bp->bar0 + bar_offset + i;
135 rte_write32(0, bar);
136 }
137
138 /* Ring channel doorbell */
139 bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
140 rte_write32(1, bar);
141 /*
142 * Make sure the channel doorbell ring command complete before
143 * reading the response to avoid getting stale or invalid
144 * responses.
145 */
146 rte_io_mb();
147
148 /* Poll for the valid bit */
149 for (i = 0; i < timeout; i++) {
150 /* Sanity check on the resp->resp_len */
151 rte_cio_rmb();
152 if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
153 /* Last byte of resp contains the valid key */
154 valid = (uint8_t *)resp + resp->resp_len - 1;
155 if (*valid == HWRM_RESP_VALID_KEY)
156 break;
157 }
158 rte_delay_us(1);
159 }
160
161 if (i >= timeout) {
162 /* Suppress VER_GET timeout messages during reset recovery */
163 if (bp->flags & BNXT_FLAG_FW_RESET &&
164 rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
165 return -ETIMEDOUT;
166
167 PMD_DRV_LOG(ERR,
168 "Error(timeout) sending msg 0x%04x, seq_id %d\n",
169 req->req_type, req->seq_id);
170 return -ETIMEDOUT;
171 }
172 return 0;
173 }
174
175 /*
176 * HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
177 * spinlock, and does initial processing.
178 *
179 * HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
180 * releases the spinlock only if it returns. If the regular int return codes
181 * are not used by the function, HWRM_CHECK_RESULT() should not be used
182 * directly, rather it should be copied and modified to suit the function.
183 *
184 * HWRM_UNLOCK() must be called after all response processing is completed.
185 */
186 #define HWRM_PREP(req, type, kong) do { \
187 rte_spinlock_lock(&bp->hwrm_lock); \
188 if (bp->hwrm_cmd_resp_addr == NULL) { \
189 rte_spinlock_unlock(&bp->hwrm_lock); \
190 return -EACCES; \
191 } \
192 memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
193 (req)->req_type = rte_cpu_to_le_16(type); \
194 (req)->cmpl_ring = rte_cpu_to_le_16(-1); \
195 (req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
196 rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
197 (req)->target_id = rte_cpu_to_le_16(0xffff); \
198 (req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
199 } while (0)
200
201 #define HWRM_CHECK_RESULT_SILENT() do {\
202 if (rc) { \
203 rte_spinlock_unlock(&bp->hwrm_lock); \
204 return rc; \
205 } \
206 if (resp->error_code) { \
207 rc = rte_le_to_cpu_16(resp->error_code); \
208 rte_spinlock_unlock(&bp->hwrm_lock); \
209 return rc; \
210 } \
211 } while (0)
212
213 #define HWRM_CHECK_RESULT() do {\
214 if (rc) { \
215 PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
216 rte_spinlock_unlock(&bp->hwrm_lock); \
217 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
218 rc = -EACCES; \
219 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
220 rc = -ENOSPC; \
221 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
222 rc = -EINVAL; \
223 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
224 rc = -ENOTSUP; \
225 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
226 rc = -EAGAIN; \
227 else if (rc > 0) \
228 rc = -EIO; \
229 return rc; \
230 } \
231 if (resp->error_code) { \
232 rc = rte_le_to_cpu_16(resp->error_code); \
233 if (resp->resp_len >= 16) { \
234 struct hwrm_err_output *tmp_hwrm_err_op = \
235 (void *)resp; \
236 PMD_DRV_LOG(ERR, \
237 "error %d:%d:%08x:%04x\n", \
238 rc, tmp_hwrm_err_op->cmd_err, \
239 rte_le_to_cpu_32(\
240 tmp_hwrm_err_op->opaque_0), \
241 rte_le_to_cpu_16(\
242 tmp_hwrm_err_op->opaque_1)); \
243 } else { \
244 PMD_DRV_LOG(ERR, "error %d\n", rc); \
245 } \
246 rte_spinlock_unlock(&bp->hwrm_lock); \
247 if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
248 rc = -EACCES; \
249 else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
250 rc = -ENOSPC; \
251 else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
252 rc = -EINVAL; \
253 else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
254 rc = -ENOTSUP; \
255 else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
256 rc = -EAGAIN; \
257 else if (rc > 0) \
258 rc = -EIO; \
259 return rc; \
260 } \
261 } while (0)
262
263 #define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
264
265 int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
266 bool use_kong_mb,
267 uint16_t msg_type,
268 void *msg,
269 uint32_t msg_len,
270 void *resp_msg,
271 uint32_t resp_len)
272 {
273 int rc = 0;
274 bool mailbox = BNXT_USE_CHIMP_MB;
275 struct input *req = msg;
276 struct output *resp = bp->hwrm_cmd_resp_addr;
277
278 if (use_kong_mb)
279 mailbox = BNXT_USE_KONG(bp);
280
281 HWRM_PREP(req, msg_type, mailbox);
282
283 rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
284
285 HWRM_CHECK_RESULT();
286
287 if (resp_msg)
288 memcpy(resp_msg, resp, resp_len);
289
290 HWRM_UNLOCK();
291
292 return rc;
293 }
294
295 int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
296 bool use_kong_mb,
297 uint16_t tf_type,
298 uint16_t tf_subtype,
299 uint32_t *tf_response_code,
300 void *msg,
301 uint32_t msg_len,
302 void *response,
303 uint32_t response_len)
304 {
305 int rc = 0;
306 struct hwrm_cfa_tflib_input req = { .req_type = 0 };
307 struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
308 bool mailbox = BNXT_USE_CHIMP_MB;
309
310 if (msg_len > sizeof(req.tf_req))
311 return -ENOMEM;
312
313 if (use_kong_mb)
314 mailbox = BNXT_USE_KONG(bp);
315
316 HWRM_PREP(&req, HWRM_TF, mailbox);
317 /* Build request using the user supplied request payload.
318 * TLV request size is checked at build time against HWRM
319 * request max size, thus no checking required.
320 */
321 req.tf_type = tf_type;
322 req.tf_subtype = tf_subtype;
323 memcpy(req.tf_req, msg, msg_len);
324
325 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
326 HWRM_CHECK_RESULT();
327
328 /* Copy the resp to user provided response buffer */
329 if (response != NULL)
330 /* Post process response data. We need to copy only
331 * the 'payload' as the HWRM data structure really is
332 * HWRM header + msg header + payload and the TFLIB
333 * only provided a payload place holder.
334 */
335 if (response_len != 0) {
336 memcpy(response,
337 resp->tf_resp,
338 response_len);
339 }
340
341 /* Extract the internal tflib response code */
342 *tf_response_code = resp->tf_resp_code;
343 HWRM_UNLOCK();
344
345 return rc;
346 }
347
348 int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
349 {
350 int rc = 0;
351 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
352 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
353
354 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
355 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
356 req.mask = 0;
357
358 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
359
360 HWRM_CHECK_RESULT();
361 HWRM_UNLOCK();
362
363 return rc;
364 }
365
366 int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
367 struct bnxt_vnic_info *vnic,
368 uint16_t vlan_count,
369 struct bnxt_vlan_table_entry *vlan_table)
370 {
371 int rc = 0;
372 struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
373 struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
374 uint32_t mask = 0;
375
376 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
377 return rc;
378
379 HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
380 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
381
382 if (vnic->flags & BNXT_VNIC_INFO_BCAST)
383 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
384 if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
385 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
386
387 if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
388 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
389
390 if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
391 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
392 } else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
393 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
394 req.num_mc_entries = rte_cpu_to_le_32(vnic->mc_addr_cnt);
395 req.mc_tbl_addr = rte_cpu_to_le_64(vnic->mc_list_dma_addr);
396 }
397 if (vlan_table) {
398 if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
399 mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
400 req.vlan_tag_tbl_addr =
401 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
402 req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
403 }
404 req.mask = rte_cpu_to_le_32(mask);
405
406 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
407
408 HWRM_CHECK_RESULT();
409 HWRM_UNLOCK();
410
411 return rc;
412 }
413
414 int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
415 uint16_t vlan_count,
416 struct bnxt_vlan_antispoof_table_entry *vlan_table)
417 {
418 int rc = 0;
419 struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
420 struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
421 bp->hwrm_cmd_resp_addr;
422
423 /*
424 * Older HWRM versions did not support this command, and the set_rx_mask
425 * list was used for anti-spoof. In 1.8.0, the TX path configuration was
426 * removed from set_rx_mask call, and this command was added.
427 *
428 * This command is also present from 1.7.8.11 and higher,
429 * as well as 1.7.8.0
430 */
431 if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
432 if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
433 if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
434 (11)))
435 return 0;
436 }
437 }
438 HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
439 req.fid = rte_cpu_to_le_16(fid);
440
441 req.vlan_tag_mask_tbl_addr =
442 rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
443 req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
444
445 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
446
447 HWRM_CHECK_RESULT();
448 HWRM_UNLOCK();
449
450 return rc;
451 }
452
453 int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
454 struct bnxt_filter_info *filter)
455 {
456 int rc = 0;
457 struct bnxt_filter_info *l2_filter = filter;
458 struct bnxt_vnic_info *vnic = NULL;
459 struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
460 struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
461
462 if (filter->fw_l2_filter_id == UINT64_MAX)
463 return 0;
464
465 if (filter->matching_l2_fltr_ptr)
466 l2_filter = filter->matching_l2_fltr_ptr;
467
468 PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
469 filter, l2_filter, l2_filter->l2_ref_cnt);
470
471 if (l2_filter->l2_ref_cnt == 0)
472 return 0;
473
474 if (l2_filter->l2_ref_cnt > 0)
475 l2_filter->l2_ref_cnt--;
476
477 if (l2_filter->l2_ref_cnt > 0)
478 return 0;
479
480 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
481
482 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
483
484 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
485
486 HWRM_CHECK_RESULT();
487 HWRM_UNLOCK();
488
489 filter->fw_l2_filter_id = UINT64_MAX;
490 if (l2_filter->l2_ref_cnt == 0) {
491 vnic = l2_filter->vnic;
492 if (vnic) {
493 STAILQ_REMOVE(&vnic->filter, l2_filter,
494 bnxt_filter_info, next);
495 bnxt_free_filter(bp, l2_filter);
496 }
497 }
498
499 return 0;
500 }
501
502 int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
503 uint16_t dst_id,
504 struct bnxt_filter_info *filter)
505 {
506 int rc = 0;
507 struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
508 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
509 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
510 const struct rte_eth_vmdq_rx_conf *conf =
511 &dev_conf->rx_adv_conf.vmdq_rx_conf;
512 uint32_t enables = 0;
513 uint16_t j = dst_id - 1;
514
515 //TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
516 if ((dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) &&
517 conf->pool_map[j].pools & (1UL << j)) {
518 PMD_DRV_LOG(DEBUG,
519 "Add vlan %u to vmdq pool %u\n",
520 conf->pool_map[j].vlan_id, j);
521
522 filter->l2_ivlan = conf->pool_map[j].vlan_id;
523 filter->enables |=
524 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
525 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
526 }
527
528 if (filter->fw_l2_filter_id != UINT64_MAX)
529 bnxt_hwrm_clear_l2_filter(bp, filter);
530
531 HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
532
533 req.flags = rte_cpu_to_le_32(filter->flags);
534
535 enables = filter->enables |
536 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
537 req.dst_id = rte_cpu_to_le_16(dst_id);
538
539 if (enables &
540 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
541 memcpy(req.l2_addr, filter->l2_addr,
542 RTE_ETHER_ADDR_LEN);
543 if (enables &
544 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
545 memcpy(req.l2_addr_mask, filter->l2_addr_mask,
546 RTE_ETHER_ADDR_LEN);
547 if (enables &
548 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
549 req.l2_ovlan = filter->l2_ovlan;
550 if (enables &
551 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
552 req.l2_ivlan = filter->l2_ivlan;
553 if (enables &
554 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
555 req.l2_ovlan_mask = filter->l2_ovlan_mask;
556 if (enables &
557 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
558 req.l2_ivlan_mask = filter->l2_ivlan_mask;
559 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
560 req.src_id = rte_cpu_to_le_32(filter->src_id);
561 if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
562 req.src_type = filter->src_type;
563 if (filter->pri_hint) {
564 req.pri_hint = filter->pri_hint;
565 req.l2_filter_id_hint =
566 rte_cpu_to_le_64(filter->l2_filter_id_hint);
567 }
568
569 req.enables = rte_cpu_to_le_32(enables);
570
571 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
572
573 HWRM_CHECK_RESULT();
574
575 filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
576 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
577 HWRM_UNLOCK();
578
579 filter->l2_ref_cnt++;
580
581 return rc;
582 }
583
584 int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
585 {
586 struct hwrm_port_mac_cfg_input req = {.req_type = 0};
587 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
588 uint32_t flags = 0;
589 int rc;
590
591 if (!ptp)
592 return 0;
593
594 HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
595
596 if (ptp->rx_filter)
597 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
598 else
599 flags |=
600 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
601 if (ptp->tx_tstamp_en)
602 flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
603 else
604 flags |=
605 HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
606 req.flags = rte_cpu_to_le_32(flags);
607 req.enables = rte_cpu_to_le_32
608 (HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
609 req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
610
611 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
612 HWRM_UNLOCK();
613
614 return rc;
615 }
616
617 static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
618 {
619 int rc = 0;
620 struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
621 struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
622 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
623
624 if (ptp)
625 return 0;
626
627 HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
628
629 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
630
631 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
632
633 HWRM_CHECK_RESULT();
634
635 if (!BNXT_CHIP_THOR(bp) &&
636 !(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
637 return 0;
638
639 if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
640 bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
641
642 ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
643 if (!ptp)
644 return -ENOMEM;
645
646 if (!BNXT_CHIP_THOR(bp)) {
647 ptp->rx_regs[BNXT_PTP_RX_TS_L] =
648 rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
649 ptp->rx_regs[BNXT_PTP_RX_TS_H] =
650 rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
651 ptp->rx_regs[BNXT_PTP_RX_SEQ] =
652 rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
653 ptp->rx_regs[BNXT_PTP_RX_FIFO] =
654 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
655 ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
656 rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
657 ptp->tx_regs[BNXT_PTP_TX_TS_L] =
658 rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
659 ptp->tx_regs[BNXT_PTP_TX_TS_H] =
660 rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
661 ptp->tx_regs[BNXT_PTP_TX_SEQ] =
662 rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
663 ptp->tx_regs[BNXT_PTP_TX_FIFO] =
664 rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
665 }
666
667 ptp->bp = bp;
668 bp->ptp_cfg = ptp;
669
670 return 0;
671 }
672
673 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
674 {
675 int rc = 0;
676 struct hwrm_func_qcaps_input req = {.req_type = 0 };
677 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
678 uint16_t new_max_vfs;
679 uint32_t flags;
680 int i;
681
682 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
683
684 req.fid = rte_cpu_to_le_16(0xffff);
685
686 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
687
688 HWRM_CHECK_RESULT();
689
690 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
691 flags = rte_le_to_cpu_32(resp->flags);
692 if (BNXT_PF(bp)) {
693 bp->pf->port_id = resp->port_id;
694 bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
695 bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
696 new_max_vfs = bp->pdev->max_vfs;
697 if (new_max_vfs != bp->pf->max_vfs) {
698 if (bp->pf->vf_info)
699 rte_free(bp->pf->vf_info);
700 bp->pf->vf_info = rte_malloc("bnxt_vf_info",
701 sizeof(bp->pf->vf_info[0]) * new_max_vfs, 0);
702 bp->pf->max_vfs = new_max_vfs;
703 for (i = 0; i < new_max_vfs; i++) {
704 bp->pf->vf_info[i].fid =
705 bp->pf->first_vf_id + i;
706 bp->pf->vf_info[i].vlan_table =
707 rte_zmalloc("VF VLAN table",
708 getpagesize(),
709 getpagesize());
710 if (bp->pf->vf_info[i].vlan_table == NULL)
711 PMD_DRV_LOG(ERR,
712 "Fail to alloc VLAN table for VF %d\n",
713 i);
714 else
715 rte_mem_lock_page(
716 bp->pf->vf_info[i].vlan_table);
717 bp->pf->vf_info[i].vlan_as_table =
718 rte_zmalloc("VF VLAN AS table",
719 getpagesize(),
720 getpagesize());
721 if (bp->pf->vf_info[i].vlan_as_table == NULL)
722 PMD_DRV_LOG(ERR,
723 "Alloc VLAN AS table for VF %d fail\n",
724 i);
725 else
726 rte_mem_lock_page(
727 bp->pf->vf_info[i].vlan_as_table);
728 STAILQ_INIT(&bp->pf->vf_info[i].filter);
729 }
730 }
731 }
732
733 bp->fw_fid = rte_le_to_cpu_32(resp->fid);
734 if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
735 bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
736 memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
737 } else {
738 bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
739 }
740 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
741 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
742 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
743 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
744 bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
745 bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
746 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
747 if (!BNXT_CHIP_THOR(bp))
748 bp->max_l2_ctx += bp->max_rx_em_flows;
749 /* TODO: For now, do not support VMDq/RFS on VFs. */
750 if (BNXT_PF(bp)) {
751 if (bp->pf->max_vfs)
752 bp->max_vnics = 1;
753 else
754 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
755 } else {
756 bp->max_vnics = 1;
757 }
758 PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
759 bp->max_l2_ctx, bp->max_vnics);
760 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
761 if (BNXT_PF(bp)) {
762 bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
763 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
764 bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
765 PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
766 HWRM_UNLOCK();
767 bnxt_hwrm_ptp_qcfg(bp);
768 }
769 }
770
771 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
772 bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
773
774 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
775 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
776 PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
777 }
778
779 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
780 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
781
782 if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
783 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
784
785 HWRM_UNLOCK();
786
787 return rc;
788 }
789
790 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
791 {
792 int rc;
793
794 rc = __bnxt_hwrm_func_qcaps(bp);
795 if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
796 rc = bnxt_alloc_ctx_mem(bp);
797 if (rc)
798 return rc;
799
800 rc = bnxt_hwrm_func_resc_qcaps(bp);
801 if (!rc)
802 bp->flags |= BNXT_FLAG_NEW_RM;
803 }
804
805 /* On older FW,
806 * bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
807 * But the error can be ignored. Return success.
808 */
809
810 return 0;
811 }
812
813 /* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
814 int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
815 {
816 int rc = 0;
817 struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
818 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
819
820 HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
821
822 req.target_id = rte_cpu_to_le_16(0xffff);
823
824 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
825
826 HWRM_CHECK_RESULT();
827
828 if (rte_le_to_cpu_32(resp->flags) &
829 HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
830 bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;
831 PMD_DRV_LOG(INFO, "CoS assignment capability enabled\n");
832 }
833
834 bp->max_tpa_v2 = rte_le_to_cpu_16(resp->max_aggs_supported);
835
836 HWRM_UNLOCK();
837
838 return rc;
839 }
840
841 int bnxt_hwrm_func_reset(struct bnxt *bp)
842 {
843 int rc = 0;
844 struct hwrm_func_reset_input req = {.req_type = 0 };
845 struct hwrm_func_reset_output *resp = bp->hwrm_cmd_resp_addr;
846
847 HWRM_PREP(&req, HWRM_FUNC_RESET, BNXT_USE_CHIMP_MB);
848
849 req.enables = rte_cpu_to_le_32(0);
850
851 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
852
853 HWRM_CHECK_RESULT();
854 HWRM_UNLOCK();
855
856 return rc;
857 }
858
859 int bnxt_hwrm_func_driver_register(struct bnxt *bp)
860 {
861 int rc;
862 uint32_t flags = 0;
863 struct hwrm_func_drv_rgtr_input req = {.req_type = 0 };
864 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
865
866 if (bp->flags & BNXT_FLAG_REGISTERED)
867 return 0;
868
869 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
870 flags = HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT;
871 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
872 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT;
873
874 /* PFs and trusted VFs should indicate the support of the
875 * Master capability on non Stingray platform
876 */
877 if ((BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) && !BNXT_STINGRAY(bp))
878 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT;
879
880 HWRM_PREP(&req, HWRM_FUNC_DRV_RGTR, BNXT_USE_CHIMP_MB);
881 req.enables = rte_cpu_to_le_32(HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VER |
882 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_ASYNC_EVENT_FWD);
883 req.ver_maj = RTE_VER_YEAR;
884 req.ver_min = RTE_VER_MONTH;
885 req.ver_upd = RTE_VER_MINOR;
886
887 if (BNXT_PF(bp)) {
888 req.enables |= rte_cpu_to_le_32(
889 HWRM_FUNC_DRV_RGTR_INPUT_ENABLES_VF_REQ_FWD);
890 memcpy(req.vf_req_fwd, bp->pf->vf_req_fwd,
891 RTE_MIN(sizeof(req.vf_req_fwd),
892 sizeof(bp->pf->vf_req_fwd)));
893
894 /*
895 * PF can sniff HWRM API issued by VF. This can be set up by
896 * linux driver and inherited by the DPDK PF driver. Clear
897 * this HWRM sniffer list in FW because DPDK PF driver does
898 * not support this.
899 */
900 flags |= HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FWD_NONE_MODE;
901 }
902
903 req.flags = rte_cpu_to_le_32(flags);
904
905 req.async_event_fwd[0] |=
906 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_LINK_STATUS_CHANGE |
907 ASYNC_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED |
908 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE |
909 ASYNC_CMPL_EVENT_ID_LINK_SPEED_CHANGE |
910 ASYNC_CMPL_EVENT_ID_RESET_NOTIFY);
911 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
912 req.async_event_fwd[0] |=
913 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_ERROR_RECOVERY);
914 req.async_event_fwd[1] |=
915 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_PF_DRVR_UNLOAD |
916 ASYNC_CMPL_EVENT_ID_VF_CFG_CHANGE);
917 if (BNXT_PF(bp))
918 req.async_event_fwd[1] |=
919 rte_cpu_to_le_32(ASYNC_CMPL_EVENT_ID_DBG_NOTIFICATION);
920
921 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
922
923 HWRM_CHECK_RESULT();
924
925 flags = rte_le_to_cpu_32(resp->flags);
926 if (flags & HWRM_FUNC_DRV_RGTR_OUTPUT_FLAGS_IF_CHANGE_SUPPORTED)
927 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
928
929 HWRM_UNLOCK();
930
931 bp->flags |= BNXT_FLAG_REGISTERED;
932
933 return rc;
934 }
935
936 int bnxt_hwrm_check_vf_rings(struct bnxt *bp)
937 {
938 if (!(BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)))
939 return 0;
940
941 return bnxt_hwrm_func_reserve_vf_resc(bp, true);
942 }
943
944 int bnxt_hwrm_func_reserve_vf_resc(struct bnxt *bp, bool test)
945 {
946 int rc;
947 uint32_t flags = 0;
948 uint32_t enables;
949 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
950 struct hwrm_func_vf_cfg_input req = {0};
951
952 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
953
954 enables = HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RX_RINGS |
955 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_TX_RINGS |
956 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
957 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
958 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS;
959
960 if (BNXT_HAS_RING_GRPS(bp)) {
961 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
962 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->rx_nr_rings);
963 }
964
965 req.num_tx_rings = rte_cpu_to_le_16(bp->tx_nr_rings);
966 req.num_rx_rings = rte_cpu_to_le_16(bp->rx_nr_rings *
967 AGG_RING_MULTIPLIER);
968 req.num_stat_ctxs = rte_cpu_to_le_16(bp->rx_nr_rings + bp->tx_nr_rings);
969 req.num_cmpl_rings = rte_cpu_to_le_16(bp->rx_nr_rings +
970 bp->tx_nr_rings +
971 BNXT_NUM_ASYNC_CPR(bp));
972 req.num_vnics = rte_cpu_to_le_16(bp->rx_nr_rings);
973 if (bp->vf_resv_strategy ==
974 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC) {
975 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_VNICS |
976 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_L2_CTXS |
977 HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
978 req.num_rsscos_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_RSS_CTX);
979 req.num_l2_ctxs = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_L2_CTX);
980 req.num_vnics = rte_cpu_to_le_16(BNXT_VF_RSV_NUM_VNIC);
981 } else if (bp->vf_resv_strategy ==
982 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MAXIMAL) {
983 enables |= HWRM_FUNC_VF_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS;
984 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
985 }
986
987 if (test)
988 flags = HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST |
989 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST |
990 HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST |
991 HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST |
992 HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST |
993 HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST;
994
995 if (test && BNXT_HAS_RING_GRPS(bp))
996 flags |= HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST;
997
998 req.flags = rte_cpu_to_le_32(flags);
999 req.enables |= rte_cpu_to_le_32(enables);
1000
1001 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1002
1003 if (test)
1004 HWRM_CHECK_RESULT_SILENT();
1005 else
1006 HWRM_CHECK_RESULT();
1007
1008 HWRM_UNLOCK();
1009 return rc;
1010 }
1011
1012 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp)
1013 {
1014 int rc;
1015 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
1016 struct hwrm_func_resource_qcaps_input req = {0};
1017
1018 HWRM_PREP(&req, HWRM_FUNC_RESOURCE_QCAPS, BNXT_USE_CHIMP_MB);
1019 req.fid = rte_cpu_to_le_16(0xffff);
1020
1021 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1022
1023 HWRM_CHECK_RESULT_SILENT();
1024
1025 if (BNXT_VF(bp)) {
1026 bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
1027 bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
1028 bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
1029 bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
1030 bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
1031 /* func_resource_qcaps does not return max_rx_em_flows.
1032 * So use the value provided by func_qcaps.
1033 */
1034 bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
1035 if (!BNXT_CHIP_THOR(bp))
1036 bp->max_l2_ctx += bp->max_rx_em_flows;
1037 bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
1038 bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
1039 }
1040 bp->max_nq_rings = rte_le_to_cpu_16(resp->max_msix);
1041 bp->vf_resv_strategy = rte_le_to_cpu_16(resp->vf_reservation_strategy);
1042 if (bp->vf_resv_strategy >
1043 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESV_STRATEGY_MINIMAL_STATIC)
1044 bp->vf_resv_strategy =
1045 HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_VF_RESERVATION_STRATEGY_MAXIMAL;
1046
1047 HWRM_UNLOCK();
1048 return rc;
1049 }
1050
1051 int bnxt_hwrm_ver_get(struct bnxt *bp, uint32_t timeout)
1052 {
1053 int rc = 0;
1054 struct hwrm_ver_get_input req = {.req_type = 0 };
1055 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
1056 uint32_t fw_version;
1057 uint16_t max_resp_len;
1058 char type[RTE_MEMZONE_NAMESIZE];
1059 uint32_t dev_caps_cfg;
1060
1061 bp->max_req_len = HWRM_MAX_REQ_LEN;
1062 bp->hwrm_cmd_timeout = timeout;
1063 HWRM_PREP(&req, HWRM_VER_GET, BNXT_USE_CHIMP_MB);
1064
1065 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
1066 req.hwrm_intf_min = HWRM_VERSION_MINOR;
1067 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
1068
1069 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1070
1071 if (bp->flags & BNXT_FLAG_FW_RESET)
1072 HWRM_CHECK_RESULT_SILENT();
1073 else
1074 HWRM_CHECK_RESULT();
1075
1076 PMD_DRV_LOG(INFO, "%d.%d.%d:%d.%d.%d\n",
1077 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
1078 resp->hwrm_intf_upd_8b, resp->hwrm_fw_maj_8b,
1079 resp->hwrm_fw_min_8b, resp->hwrm_fw_bld_8b);
1080 bp->fw_ver = (resp->hwrm_fw_maj_8b << 24) |
1081 (resp->hwrm_fw_min_8b << 16) |
1082 (resp->hwrm_fw_bld_8b << 8) |
1083 resp->hwrm_fw_rsvd_8b;
1084 PMD_DRV_LOG(INFO, "Driver HWRM version: %d.%d.%d\n",
1085 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR, HWRM_VERSION_UPDATE);
1086
1087 fw_version = resp->hwrm_intf_maj_8b << 16;
1088 fw_version |= resp->hwrm_intf_min_8b << 8;
1089 fw_version |= resp->hwrm_intf_upd_8b;
1090 bp->hwrm_spec_code = fw_version;
1091
1092 /* def_req_timeout value is in milliseconds */
1093 bp->hwrm_cmd_timeout = rte_le_to_cpu_16(resp->def_req_timeout);
1094 /* convert timeout to usec */
1095 bp->hwrm_cmd_timeout *= 1000;
1096 if (!bp->hwrm_cmd_timeout)
1097 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
1098
1099 if (resp->hwrm_intf_maj_8b != HWRM_VERSION_MAJOR) {
1100 PMD_DRV_LOG(ERR, "Unsupported firmware API version\n");
1101 rc = -EINVAL;
1102 goto error;
1103 }
1104
1105 if (bp->max_req_len > resp->max_req_win_len) {
1106 PMD_DRV_LOG(ERR, "Unsupported request length\n");
1107 rc = -EINVAL;
1108 }
1109 bp->max_req_len = rte_le_to_cpu_16(resp->max_req_win_len);
1110 bp->hwrm_max_ext_req_len = rte_le_to_cpu_16(resp->max_ext_req_len);
1111 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
1112 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
1113
1114 max_resp_len = rte_le_to_cpu_16(resp->max_resp_len);
1115 dev_caps_cfg = rte_le_to_cpu_32(resp->dev_caps_cfg);
1116
1117 if (bp->max_resp_len != max_resp_len) {
1118 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT,
1119 bp->pdev->addr.domain, bp->pdev->addr.bus,
1120 bp->pdev->addr.devid, bp->pdev->addr.function);
1121
1122 rte_free(bp->hwrm_cmd_resp_addr);
1123
1124 bp->hwrm_cmd_resp_addr = rte_malloc(type, max_resp_len, 0);
1125 if (bp->hwrm_cmd_resp_addr == NULL) {
1126 rc = -ENOMEM;
1127 goto error;
1128 }
1129 bp->hwrm_cmd_resp_dma_addr =
1130 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
1131 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
1132 PMD_DRV_LOG(ERR,
1133 "Unable to map response buffer to physical memory.\n");
1134 rc = -ENOMEM;
1135 goto error;
1136 }
1137 bp->max_resp_len = max_resp_len;
1138 }
1139
1140 if ((dev_caps_cfg &
1141 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1142 (dev_caps_cfg &
1143 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) {
1144 PMD_DRV_LOG(DEBUG, "Short command supported\n");
1145 bp->flags |= BNXT_FLAG_SHORT_CMD;
1146 }
1147
1148 if (((dev_caps_cfg &
1149 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
1150 (dev_caps_cfg &
1151 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_SHORT_CMD_REQUIRED)) ||
1152 bp->hwrm_max_ext_req_len > HWRM_MAX_REQ_LEN) {
1153 sprintf(type, "bnxt_hwrm_short_" PCI_PRI_FMT,
1154 bp->pdev->addr.domain, bp->pdev->addr.bus,
1155 bp->pdev->addr.devid, bp->pdev->addr.function);
1156
1157 rte_free(bp->hwrm_short_cmd_req_addr);
1158
1159 bp->hwrm_short_cmd_req_addr =
1160 rte_malloc(type, bp->hwrm_max_ext_req_len, 0);
1161 if (bp->hwrm_short_cmd_req_addr == NULL) {
1162 rc = -ENOMEM;
1163 goto error;
1164 }
1165 bp->hwrm_short_cmd_req_dma_addr =
1166 rte_malloc_virt2iova(bp->hwrm_short_cmd_req_addr);
1167 if (bp->hwrm_short_cmd_req_dma_addr == RTE_BAD_IOVA) {
1168 rte_free(bp->hwrm_short_cmd_req_addr);
1169 PMD_DRV_LOG(ERR,
1170 "Unable to map buffer to physical memory.\n");
1171 rc = -ENOMEM;
1172 goto error;
1173 }
1174 }
1175 if (dev_caps_cfg &
1176 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED) {
1177 bp->flags |= BNXT_FLAG_KONG_MB_EN;
1178 PMD_DRV_LOG(DEBUG, "Kong mailbox channel enabled\n");
1179 }
1180 if (dev_caps_cfg &
1181 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
1182 PMD_DRV_LOG(DEBUG, "FW supports Trusted VFs\n");
1183 if (dev_caps_cfg &
1184 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED) {
1185 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_MGMT;
1186 PMD_DRV_LOG(DEBUG, "FW supports advanced flow management\n");
1187 }
1188
1189 if (dev_caps_cfg &
1190 HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED) {
1191 PMD_DRV_LOG(DEBUG, "FW supports advanced flow counters\n");
1192 bp->fw_cap |= BNXT_FW_CAP_ADV_FLOW_COUNTERS;
1193 }
1194
1195
1196 error:
1197 HWRM_UNLOCK();
1198 return rc;
1199 }
1200
1201 int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
1202 {
1203 int rc;
1204 struct hwrm_func_drv_unrgtr_input req = {.req_type = 0 };
1205 struct hwrm_func_drv_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
1206
1207 if (!(bp->flags & BNXT_FLAG_REGISTERED))
1208 return 0;
1209
1210 HWRM_PREP(&req, HWRM_FUNC_DRV_UNRGTR, BNXT_USE_CHIMP_MB);
1211 req.flags = flags;
1212
1213 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1214
1215 HWRM_CHECK_RESULT();
1216 HWRM_UNLOCK();
1217
1218 return rc;
1219 }
1220
1221 static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
1222 {
1223 int rc = 0;
1224 struct hwrm_port_phy_cfg_input req = {0};
1225 struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1226 uint32_t enables = 0;
1227
1228 HWRM_PREP(&req, HWRM_PORT_PHY_CFG, BNXT_USE_CHIMP_MB);
1229
1230 if (conf->link_up) {
1231 /* Setting Fixed Speed. But AutoNeg is ON, So disable it */
1232 if (bp->link_info->auto_mode && conf->link_speed) {
1233 req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
1234 PMD_DRV_LOG(DEBUG, "Disabling AutoNeg\n");
1235 }
1236
1237 req.flags = rte_cpu_to_le_32(conf->phy_flags);
1238 req.force_link_speed = rte_cpu_to_le_16(conf->link_speed);
1239 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
1240 /*
1241 * Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
1242 * any auto mode, even "none".
1243 */
1244 if (!conf->link_speed) {
1245 /* No speeds specified. Enable AutoNeg - all speeds */
1246 req.auto_mode =
1247 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS;
1248 }
1249 /* AutoNeg - Advertise speeds specified. */
1250 if (conf->auto_link_speed_mask &&
1251 !(conf->phy_flags & HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE)) {
1252 req.auto_mode =
1253 HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK;
1254 req.auto_link_speed_mask =
1255 conf->auto_link_speed_mask;
1256 enables |=
1257 HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
1258 }
1259
1260 req.auto_duplex = conf->duplex;
1261 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
1262 req.auto_pause = conf->auto_pause;
1263 req.force_pause = conf->force_pause;
1264 /* Set force_pause if there is no auto or if there is a force */
1265 if (req.auto_pause && !req.force_pause)
1266 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
1267 else
1268 enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
1269
1270 req.enables = rte_cpu_to_le_32(enables);
1271 } else {
1272 req.flags =
1273 rte_cpu_to_le_32(HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DWN);
1274 PMD_DRV_LOG(INFO, "Force Link Down\n");
1275 }
1276
1277 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1278
1279 HWRM_CHECK_RESULT();
1280 HWRM_UNLOCK();
1281
1282 return rc;
1283 }
1284
1285 static int bnxt_hwrm_port_phy_qcfg(struct bnxt *bp,
1286 struct bnxt_link_info *link_info)
1287 {
1288 int rc = 0;
1289 struct hwrm_port_phy_qcfg_input req = {0};
1290 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1291
1292 HWRM_PREP(&req, HWRM_PORT_PHY_QCFG, BNXT_USE_CHIMP_MB);
1293
1294 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1295
1296 HWRM_CHECK_RESULT();
1297
1298 link_info->phy_link_status = resp->link;
1299 link_info->link_up =
1300 (link_info->phy_link_status ==
1301 HWRM_PORT_PHY_QCFG_OUTPUT_LINK_LINK) ? 1 : 0;
1302 link_info->link_speed = rte_le_to_cpu_16(resp->link_speed);
1303 link_info->duplex = resp->duplex_cfg;
1304 link_info->pause = resp->pause;
1305 link_info->auto_pause = resp->auto_pause;
1306 link_info->force_pause = resp->force_pause;
1307 link_info->auto_mode = resp->auto_mode;
1308 link_info->phy_type = resp->phy_type;
1309 link_info->media_type = resp->media_type;
1310
1311 link_info->support_speeds = rte_le_to_cpu_16(resp->support_speeds);
1312 link_info->auto_link_speed = rte_le_to_cpu_16(resp->auto_link_speed);
1313 link_info->preemphasis = rte_le_to_cpu_32(resp->preemphasis);
1314 link_info->force_link_speed = rte_le_to_cpu_16(resp->force_link_speed);
1315 link_info->phy_ver[0] = resp->phy_maj;
1316 link_info->phy_ver[1] = resp->phy_min;
1317 link_info->phy_ver[2] = resp->phy_bld;
1318
1319 HWRM_UNLOCK();
1320
1321 PMD_DRV_LOG(DEBUG, "Link Speed %d\n", link_info->link_speed);
1322 PMD_DRV_LOG(DEBUG, "Auto Mode %d\n", link_info->auto_mode);
1323 PMD_DRV_LOG(DEBUG, "Support Speeds %x\n", link_info->support_speeds);
1324 PMD_DRV_LOG(DEBUG, "Auto Link Speed %x\n", link_info->auto_link_speed);
1325 PMD_DRV_LOG(DEBUG, "Auto Link Speed Mask %x\n",
1326 link_info->auto_link_speed_mask);
1327 PMD_DRV_LOG(DEBUG, "Forced Link Speed %x\n",
1328 link_info->force_link_speed);
1329
1330 return rc;
1331 }
1332
1333 static bool bnxt_find_lossy_profile(struct bnxt *bp)
1334 {
1335 int i = 0;
1336
1337 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1338 if (bp->tx_cos_queue[i].profile ==
1339 HWRM_QUEUE_SERVICE_PROFILE_LOSSY) {
1340 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1341 return true;
1342 }
1343 }
1344 return false;
1345 }
1346
1347 static void bnxt_find_first_valid_profile(struct bnxt *bp)
1348 {
1349 int i = 0;
1350
1351 for (i = BNXT_COS_QUEUE_COUNT - 1; i >= 0; i--) {
1352 if (bp->tx_cos_queue[i].profile !=
1353 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN &&
1354 bp->tx_cos_queue[i].id !=
1355 HWRM_QUEUE_SERVICE_PROFILE_UNKNOWN) {
1356 bp->tx_cosq_id[0] = bp->tx_cos_queue[i].id;
1357 break;
1358 }
1359 }
1360 }
1361
1362 int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
1363 {
1364 int rc = 0;
1365 struct hwrm_queue_qportcfg_input req = {.req_type = 0 };
1366 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
1367 uint32_t dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX;
1368 int i;
1369
1370 get_rx_info:
1371 HWRM_PREP(&req, HWRM_QUEUE_QPORTCFG, BNXT_USE_CHIMP_MB);
1372
1373 req.flags = rte_cpu_to_le_32(dir);
1374 /* HWRM Version >= 1.9.1 only if COS Classification is not required. */
1375 if (bp->hwrm_spec_code >= HWRM_VERSION_1_9_1 &&
1376 !(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
1377 req.drv_qmap_cap =
1378 HWRM_QUEUE_QPORTCFG_INPUT_DRV_QMAP_CAP_ENABLED;
1379 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1380
1381 HWRM_CHECK_RESULT();
1382
1383 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1384 GET_TX_QUEUE_INFO(0);
1385 GET_TX_QUEUE_INFO(1);
1386 GET_TX_QUEUE_INFO(2);
1387 GET_TX_QUEUE_INFO(3);
1388 GET_TX_QUEUE_INFO(4);
1389 GET_TX_QUEUE_INFO(5);
1390 GET_TX_QUEUE_INFO(6);
1391 GET_TX_QUEUE_INFO(7);
1392 } else {
1393 GET_RX_QUEUE_INFO(0);
1394 GET_RX_QUEUE_INFO(1);
1395 GET_RX_QUEUE_INFO(2);
1396 GET_RX_QUEUE_INFO(3);
1397 GET_RX_QUEUE_INFO(4);
1398 GET_RX_QUEUE_INFO(5);
1399 GET_RX_QUEUE_INFO(6);
1400 GET_RX_QUEUE_INFO(7);
1401 }
1402
1403 HWRM_UNLOCK();
1404
1405 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX)
1406 goto done;
1407
1408 if (bp->hwrm_spec_code < HWRM_VERSION_1_9_1) {
1409 bp->tx_cosq_id[0] = bp->tx_cos_queue[0].id;
1410 } else {
1411 int j;
1412
1413 /* iterate and find the COSq profile to use for Tx */
1414 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1415 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
1416 if (bp->tx_cos_queue[i].id != 0xff)
1417 bp->tx_cosq_id[j++] =
1418 bp->tx_cos_queue[i].id;
1419 }
1420 } else {
1421 /* When CoS classification is disabled, for normal NIC
1422 * operations, ideally we should look to use LOSSY.
1423 * If not found, fallback to the first valid profile
1424 */
1425 if (!bnxt_find_lossy_profile(bp))
1426 bnxt_find_first_valid_profile(bp);
1427
1428 }
1429 }
1430
1431 bp->max_tc = resp->max_configurable_queues;
1432 bp->max_lltc = resp->max_configurable_lossless_queues;
1433 if (bp->max_tc > BNXT_MAX_QUEUE)
1434 bp->max_tc = BNXT_MAX_QUEUE;
1435 bp->max_q = bp->max_tc;
1436
1437 if (dir == HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_TX) {
1438 dir = HWRM_QUEUE_QPORTCFG_INPUT_FLAGS_PATH_RX;
1439 goto get_rx_info;
1440 }
1441
1442 done:
1443 return rc;
1444 }
1445
1446 int bnxt_hwrm_ring_alloc(struct bnxt *bp,
1447 struct bnxt_ring *ring,
1448 uint32_t ring_type, uint32_t map_index,
1449 uint32_t stats_ctx_id, uint32_t cmpl_ring_id,
1450 uint16_t tx_cosq_id)
1451 {
1452 int rc = 0;
1453 uint32_t enables = 0;
1454 struct hwrm_ring_alloc_input req = {.req_type = 0 };
1455 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1456 struct rte_mempool *mb_pool;
1457 uint16_t rx_buf_size;
1458
1459 HWRM_PREP(&req, HWRM_RING_ALLOC, BNXT_USE_CHIMP_MB);
1460
1461 req.page_tbl_addr = rte_cpu_to_le_64(ring->bd_dma);
1462 req.fbo = rte_cpu_to_le_32(0);
1463 /* Association of ring index with doorbell index */
1464 req.logical_id = rte_cpu_to_le_16(map_index);
1465 req.length = rte_cpu_to_le_32(ring->ring_size);
1466
1467 switch (ring_type) {
1468 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1469 req.ring_type = ring_type;
1470 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1471 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1472 req.queue_id = rte_cpu_to_le_16(tx_cosq_id);
1473 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1474 enables |=
1475 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1476 break;
1477 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1478 req.ring_type = ring_type;
1479 req.cmpl_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1480 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1481 if (BNXT_CHIP_THOR(bp)) {
1482 mb_pool = bp->rx_queues[0]->mb_pool;
1483 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1484 RTE_PKTMBUF_HEADROOM;
1485 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1486 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1487 enables |=
1488 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID;
1489 }
1490 if (stats_ctx_id != INVALID_STATS_CTX_ID)
1491 enables |=
1492 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1493 break;
1494 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1495 req.ring_type = ring_type;
1496 if (BNXT_HAS_NQ(bp)) {
1497 /* Association of cp ring with nq */
1498 req.nq_ring_id = rte_cpu_to_le_16(cmpl_ring_id);
1499 enables |=
1500 HWRM_RING_ALLOC_INPUT_ENABLES_NQ_RING_ID_VALID;
1501 }
1502 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1503 break;
1504 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1505 req.ring_type = ring_type;
1506 req.page_size = BNXT_PAGE_SHFT;
1507 req.int_mode = HWRM_RING_ALLOC_INPUT_INT_MODE_MSIX;
1508 break;
1509 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1510 req.ring_type = ring_type;
1511 req.rx_ring_id = rte_cpu_to_le_16(ring->fw_rx_ring_id);
1512
1513 mb_pool = bp->rx_queues[0]->mb_pool;
1514 rx_buf_size = rte_pktmbuf_data_room_size(mb_pool) -
1515 RTE_PKTMBUF_HEADROOM;
1516 rx_buf_size = RTE_MIN(BNXT_MAX_PKT_LEN, rx_buf_size);
1517 req.rx_buf_size = rte_cpu_to_le_16(rx_buf_size);
1518
1519 req.stat_ctx_id = rte_cpu_to_le_32(stats_ctx_id);
1520 enables |= HWRM_RING_ALLOC_INPUT_ENABLES_RX_RING_ID_VALID |
1521 HWRM_RING_ALLOC_INPUT_ENABLES_RX_BUF_SIZE_VALID |
1522 HWRM_RING_ALLOC_INPUT_ENABLES_STAT_CTX_ID_VALID;
1523 break;
1524 default:
1525 PMD_DRV_LOG(ERR, "hwrm alloc invalid ring type %d\n",
1526 ring_type);
1527 HWRM_UNLOCK();
1528 return -EINVAL;
1529 }
1530 req.enables = rte_cpu_to_le_32(enables);
1531
1532 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1533
1534 if (rc || resp->error_code) {
1535 if (rc == 0 && resp->error_code)
1536 rc = rte_le_to_cpu_16(resp->error_code);
1537 switch (ring_type) {
1538 case HWRM_RING_ALLOC_INPUT_RING_TYPE_L2_CMPL:
1539 PMD_DRV_LOG(ERR,
1540 "hwrm_ring_alloc cp failed. rc:%d\n", rc);
1541 HWRM_UNLOCK();
1542 return rc;
1543 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX:
1544 PMD_DRV_LOG(ERR,
1545 "hwrm_ring_alloc rx failed. rc:%d\n", rc);
1546 HWRM_UNLOCK();
1547 return rc;
1548 case HWRM_RING_ALLOC_INPUT_RING_TYPE_RX_AGG:
1549 PMD_DRV_LOG(ERR,
1550 "hwrm_ring_alloc rx agg failed. rc:%d\n",
1551 rc);
1552 HWRM_UNLOCK();
1553 return rc;
1554 case HWRM_RING_ALLOC_INPUT_RING_TYPE_TX:
1555 PMD_DRV_LOG(ERR,
1556 "hwrm_ring_alloc tx failed. rc:%d\n", rc);
1557 HWRM_UNLOCK();
1558 return rc;
1559 case HWRM_RING_ALLOC_INPUT_RING_TYPE_NQ:
1560 PMD_DRV_LOG(ERR,
1561 "hwrm_ring_alloc nq failed. rc:%d\n", rc);
1562 HWRM_UNLOCK();
1563 return rc;
1564 default:
1565 PMD_DRV_LOG(ERR, "Invalid ring. rc:%d\n", rc);
1566 HWRM_UNLOCK();
1567 return rc;
1568 }
1569 }
1570
1571 ring->fw_ring_id = rte_le_to_cpu_16(resp->ring_id);
1572 HWRM_UNLOCK();
1573 return rc;
1574 }
1575
1576 int bnxt_hwrm_ring_free(struct bnxt *bp,
1577 struct bnxt_ring *ring, uint32_t ring_type)
1578 {
1579 int rc;
1580 struct hwrm_ring_free_input req = {.req_type = 0 };
1581 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
1582
1583 HWRM_PREP(&req, HWRM_RING_FREE, BNXT_USE_CHIMP_MB);
1584
1585 req.ring_type = ring_type;
1586 req.ring_id = rte_cpu_to_le_16(ring->fw_ring_id);
1587
1588 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1589
1590 if (rc || resp->error_code) {
1591 if (rc == 0 && resp->error_code)
1592 rc = rte_le_to_cpu_16(resp->error_code);
1593 HWRM_UNLOCK();
1594
1595 switch (ring_type) {
1596 case HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL:
1597 PMD_DRV_LOG(ERR, "hwrm_ring_free cp failed. rc:%d\n",
1598 rc);
1599 return rc;
1600 case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
1601 PMD_DRV_LOG(ERR, "hwrm_ring_free rx failed. rc:%d\n",
1602 rc);
1603 return rc;
1604 case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
1605 PMD_DRV_LOG(ERR, "hwrm_ring_free tx failed. rc:%d\n",
1606 rc);
1607 return rc;
1608 case HWRM_RING_FREE_INPUT_RING_TYPE_NQ:
1609 PMD_DRV_LOG(ERR,
1610 "hwrm_ring_free nq failed. rc:%d\n", rc);
1611 return rc;
1612 case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
1613 PMD_DRV_LOG(ERR,
1614 "hwrm_ring_free agg failed. rc:%d\n", rc);
1615 return rc;
1616 default:
1617 PMD_DRV_LOG(ERR, "Invalid ring, rc:%d\n", rc);
1618 return rc;
1619 }
1620 }
1621 HWRM_UNLOCK();
1622 return 0;
1623 }
1624
1625 int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp, unsigned int idx)
1626 {
1627 int rc = 0;
1628 struct hwrm_ring_grp_alloc_input req = {.req_type = 0 };
1629 struct hwrm_ring_grp_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1630
1631 HWRM_PREP(&req, HWRM_RING_GRP_ALLOC, BNXT_USE_CHIMP_MB);
1632
1633 req.cr = rte_cpu_to_le_16(bp->grp_info[idx].cp_fw_ring_id);
1634 req.rr = rte_cpu_to_le_16(bp->grp_info[idx].rx_fw_ring_id);
1635 req.ar = rte_cpu_to_le_16(bp->grp_info[idx].ag_fw_ring_id);
1636 req.sc = rte_cpu_to_le_16(bp->grp_info[idx].fw_stats_ctx);
1637
1638 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1639
1640 HWRM_CHECK_RESULT();
1641
1642 bp->grp_info[idx].fw_grp_id = rte_le_to_cpu_16(resp->ring_group_id);
1643
1644 HWRM_UNLOCK();
1645
1646 return rc;
1647 }
1648
1649 int bnxt_hwrm_ring_grp_free(struct bnxt *bp, unsigned int idx)
1650 {
1651 int rc;
1652 struct hwrm_ring_grp_free_input req = {.req_type = 0 };
1653 struct hwrm_ring_grp_free_output *resp = bp->hwrm_cmd_resp_addr;
1654
1655 HWRM_PREP(&req, HWRM_RING_GRP_FREE, BNXT_USE_CHIMP_MB);
1656
1657 req.ring_group_id = rte_cpu_to_le_16(bp->grp_info[idx].fw_grp_id);
1658
1659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1660
1661 HWRM_CHECK_RESULT();
1662 HWRM_UNLOCK();
1663
1664 bp->grp_info[idx].fw_grp_id = INVALID_HW_RING_ID;
1665 return rc;
1666 }
1667
1668 int bnxt_hwrm_stat_clear(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1669 {
1670 int rc = 0;
1671 struct hwrm_stat_ctx_clr_stats_input req = {.req_type = 0 };
1672 struct hwrm_stat_ctx_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
1673
1674 if (cpr->hw_stats_ctx_id == (uint32_t)HWRM_NA_SIGNATURE)
1675 return rc;
1676
1677 HWRM_PREP(&req, HWRM_STAT_CTX_CLR_STATS, BNXT_USE_CHIMP_MB);
1678
1679 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1680
1681 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1682
1683 HWRM_CHECK_RESULT();
1684 HWRM_UNLOCK();
1685
1686 return rc;
1687 }
1688
1689 int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1690 unsigned int idx __rte_unused)
1691 {
1692 int rc;
1693 struct hwrm_stat_ctx_alloc_input req = {.req_type = 0 };
1694 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1695
1696 HWRM_PREP(&req, HWRM_STAT_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1697
1698 req.update_period_ms = rte_cpu_to_le_32(0);
1699
1700 req.stats_dma_addr = rte_cpu_to_le_64(cpr->hw_stats_map);
1701
1702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1703
1704 HWRM_CHECK_RESULT();
1705
1706 cpr->hw_stats_ctx_id = rte_le_to_cpu_32(resp->stat_ctx_id);
1707
1708 HWRM_UNLOCK();
1709
1710 return rc;
1711 }
1712
1713 int bnxt_hwrm_stat_ctx_free(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1714 unsigned int idx __rte_unused)
1715 {
1716 int rc;
1717 struct hwrm_stat_ctx_free_input req = {.req_type = 0 };
1718 struct hwrm_stat_ctx_free_output *resp = bp->hwrm_cmd_resp_addr;
1719
1720 HWRM_PREP(&req, HWRM_STAT_CTX_FREE, BNXT_USE_CHIMP_MB);
1721
1722 req.stat_ctx_id = rte_cpu_to_le_32(cpr->hw_stats_ctx_id);
1723
1724 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1725
1726 HWRM_CHECK_RESULT();
1727 HWRM_UNLOCK();
1728
1729 return rc;
1730 }
1731
1732 int bnxt_hwrm_vnic_alloc(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1733 {
1734 int rc = 0, i, j;
1735 struct hwrm_vnic_alloc_input req = { 0 };
1736 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
1737
1738 if (!BNXT_HAS_RING_GRPS(bp))
1739 goto skip_ring_grps;
1740
1741 /* map ring groups to this vnic */
1742 PMD_DRV_LOG(DEBUG, "Alloc VNIC. Start %x, End %x\n",
1743 vnic->start_grp_id, vnic->end_grp_id);
1744 for (i = vnic->start_grp_id, j = 0; i < vnic->end_grp_id; i++, j++)
1745 vnic->fw_grp_ids[j] = bp->grp_info[i].fw_grp_id;
1746
1747 vnic->dflt_ring_grp = bp->grp_info[vnic->start_grp_id].fw_grp_id;
1748 vnic->rss_rule = (uint16_t)HWRM_NA_SIGNATURE;
1749 vnic->cos_rule = (uint16_t)HWRM_NA_SIGNATURE;
1750 vnic->lb_rule = (uint16_t)HWRM_NA_SIGNATURE;
1751
1752 skip_ring_grps:
1753 vnic->mru = BNXT_VNIC_MRU(bp->eth_dev->data->mtu);
1754 HWRM_PREP(&req, HWRM_VNIC_ALLOC, BNXT_USE_CHIMP_MB);
1755
1756 if (vnic->func_default)
1757 req.flags =
1758 rte_cpu_to_le_32(HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT);
1759 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1760
1761 HWRM_CHECK_RESULT();
1762
1763 vnic->fw_vnic_id = rte_le_to_cpu_16(resp->vnic_id);
1764 HWRM_UNLOCK();
1765 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1766 return rc;
1767 }
1768
1769 static int bnxt_hwrm_vnic_plcmodes_qcfg(struct bnxt *bp,
1770 struct bnxt_vnic_info *vnic,
1771 struct bnxt_plcmodes_cfg *pmode)
1772 {
1773 int rc = 0;
1774 struct hwrm_vnic_plcmodes_qcfg_input req = {.req_type = 0 };
1775 struct hwrm_vnic_plcmodes_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1776
1777 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_QCFG, BNXT_USE_CHIMP_MB);
1778
1779 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1780
1781 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1782
1783 HWRM_CHECK_RESULT();
1784
1785 pmode->flags = rte_le_to_cpu_32(resp->flags);
1786 /* dflt_vnic bit doesn't exist in the _cfg command */
1787 pmode->flags &= ~(HWRM_VNIC_PLCMODES_QCFG_OUTPUT_FLAGS_DFLT_VNIC);
1788 pmode->jumbo_thresh = rte_le_to_cpu_16(resp->jumbo_thresh);
1789 pmode->hds_offset = rte_le_to_cpu_16(resp->hds_offset);
1790 pmode->hds_threshold = rte_le_to_cpu_16(resp->hds_threshold);
1791
1792 HWRM_UNLOCK();
1793
1794 return rc;
1795 }
1796
1797 static int bnxt_hwrm_vnic_plcmodes_cfg(struct bnxt *bp,
1798 struct bnxt_vnic_info *vnic,
1799 struct bnxt_plcmodes_cfg *pmode)
1800 {
1801 int rc = 0;
1802 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
1803 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1804
1805 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1806 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1807 return rc;
1808 }
1809
1810 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
1811
1812 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1813 req.flags = rte_cpu_to_le_32(pmode->flags);
1814 req.jumbo_thresh = rte_cpu_to_le_16(pmode->jumbo_thresh);
1815 req.hds_offset = rte_cpu_to_le_16(pmode->hds_offset);
1816 req.hds_threshold = rte_cpu_to_le_16(pmode->hds_threshold);
1817 req.enables = rte_cpu_to_le_32(
1818 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_THRESHOLD_VALID |
1819 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_HDS_OFFSET_VALID |
1820 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID
1821 );
1822
1823 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1824
1825 HWRM_CHECK_RESULT();
1826 HWRM_UNLOCK();
1827
1828 return rc;
1829 }
1830
1831 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, struct bnxt_vnic_info *vnic)
1832 {
1833 int rc = 0;
1834 struct hwrm_vnic_cfg_input req = {.req_type = 0 };
1835 struct hwrm_vnic_cfg_output *resp = bp->hwrm_cmd_resp_addr;
1836 struct bnxt_plcmodes_cfg pmodes = { 0 };
1837 uint32_t ctx_enable_flag = 0;
1838 uint32_t enables = 0;
1839
1840 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1841 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
1842 return rc;
1843 }
1844
1845 rc = bnxt_hwrm_vnic_plcmodes_qcfg(bp, vnic, &pmodes);
1846 if (rc)
1847 return rc;
1848
1849 HWRM_PREP(&req, HWRM_VNIC_CFG, BNXT_USE_CHIMP_MB);
1850
1851 if (BNXT_CHIP_THOR(bp)) {
1852 int dflt_rxq = vnic->start_grp_id;
1853 struct bnxt_rx_ring_info *rxr;
1854 struct bnxt_cp_ring_info *cpr;
1855 struct bnxt_rx_queue *rxq;
1856 int i;
1857
1858 /*
1859 * The first active receive ring is used as the VNIC
1860 * default receive ring. If there are no active receive
1861 * rings (all corresponding receive queues are stopped),
1862 * the first receive ring is used.
1863 */
1864 for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++) {
1865 rxq = bp->eth_dev->data->rx_queues[i];
1866 if (rxq->rx_started) {
1867 dflt_rxq = i;
1868 break;
1869 }
1870 }
1871
1872 rxq = bp->eth_dev->data->rx_queues[dflt_rxq];
1873 rxr = rxq->rx_ring;
1874 cpr = rxq->cp_ring;
1875
1876 req.default_rx_ring_id =
1877 rte_cpu_to_le_16(rxr->rx_ring_struct->fw_ring_id);
1878 req.default_cmpl_ring_id =
1879 rte_cpu_to_le_16(cpr->cp_ring_struct->fw_ring_id);
1880 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_RX_RING_ID |
1881 HWRM_VNIC_CFG_INPUT_ENABLES_DEFAULT_CMPL_RING_ID;
1882 goto config_mru;
1883 }
1884
1885 /* Only RSS support for now TBD: COS & LB */
1886 enables = HWRM_VNIC_CFG_INPUT_ENABLES_DFLT_RING_GRP;
1887 if (vnic->lb_rule != 0xffff)
1888 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_LB_RULE;
1889 if (vnic->cos_rule != 0xffff)
1890 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_COS_RULE;
1891 if (vnic->rss_rule != (uint16_t)HWRM_NA_SIGNATURE) {
1892 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_MRU;
1893 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_RSS_RULE;
1894 }
1895 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY) {
1896 ctx_enable_flag |= HWRM_VNIC_CFG_INPUT_ENABLES_QUEUE_ID;
1897 req.queue_id = rte_cpu_to_le_16(vnic->cos_queue_id);
1898 }
1899
1900 enables |= ctx_enable_flag;
1901 req.dflt_ring_grp = rte_cpu_to_le_16(vnic->dflt_ring_grp);
1902 req.rss_rule = rte_cpu_to_le_16(vnic->rss_rule);
1903 req.cos_rule = rte_cpu_to_le_16(vnic->cos_rule);
1904 req.lb_rule = rte_cpu_to_le_16(vnic->lb_rule);
1905
1906 config_mru:
1907 req.enables = rte_cpu_to_le_32(enables);
1908 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1909 req.mru = rte_cpu_to_le_16(vnic->mru);
1910 /* Configure default VNIC only once. */
1911 if (vnic->func_default && !(bp->flags & BNXT_FLAG_DFLT_VNIC_SET)) {
1912 req.flags |=
1913 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_DEFAULT);
1914 bp->flags |= BNXT_FLAG_DFLT_VNIC_SET;
1915 }
1916 if (vnic->vlan_strip)
1917 req.flags |=
1918 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_VLAN_STRIP_MODE);
1919 if (vnic->bd_stall)
1920 req.flags |=
1921 rte_cpu_to_le_32(HWRM_VNIC_CFG_INPUT_FLAGS_BD_STALL_MODE);
1922 if (vnic->roce_dual)
1923 req.flags |= rte_cpu_to_le_32(
1924 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE);
1925 if (vnic->roce_only)
1926 req.flags |= rte_cpu_to_le_32(
1927 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE);
1928 if (vnic->rss_dflt_cr)
1929 req.flags |= rte_cpu_to_le_32(
1930 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE);
1931
1932 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1933
1934 HWRM_CHECK_RESULT();
1935 HWRM_UNLOCK();
1936
1937 rc = bnxt_hwrm_vnic_plcmodes_cfg(bp, vnic, &pmodes);
1938
1939 return rc;
1940 }
1941
1942 int bnxt_hwrm_vnic_qcfg(struct bnxt *bp, struct bnxt_vnic_info *vnic,
1943 int16_t fw_vf_id)
1944 {
1945 int rc = 0;
1946 struct hwrm_vnic_qcfg_input req = {.req_type = 0 };
1947 struct hwrm_vnic_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
1948
1949 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
1950 PMD_DRV_LOG(DEBUG, "VNIC QCFG ID %d\n", vnic->fw_vnic_id);
1951 return rc;
1952 }
1953 HWRM_PREP(&req, HWRM_VNIC_QCFG, BNXT_USE_CHIMP_MB);
1954
1955 req.enables =
1956 rte_cpu_to_le_32(HWRM_VNIC_QCFG_INPUT_ENABLES_VF_ID_VALID);
1957 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
1958 req.vf_id = rte_cpu_to_le_16(fw_vf_id);
1959
1960 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1961
1962 HWRM_CHECK_RESULT();
1963
1964 vnic->dflt_ring_grp = rte_le_to_cpu_16(resp->dflt_ring_grp);
1965 vnic->rss_rule = rte_le_to_cpu_16(resp->rss_rule);
1966 vnic->cos_rule = rte_le_to_cpu_16(resp->cos_rule);
1967 vnic->lb_rule = rte_le_to_cpu_16(resp->lb_rule);
1968 vnic->mru = rte_le_to_cpu_16(resp->mru);
1969 vnic->func_default = rte_le_to_cpu_32(
1970 resp->flags) & HWRM_VNIC_QCFG_OUTPUT_FLAGS_DEFAULT;
1971 vnic->vlan_strip = rte_le_to_cpu_32(resp->flags) &
1972 HWRM_VNIC_QCFG_OUTPUT_FLAGS_VLAN_STRIP_MODE;
1973 vnic->bd_stall = rte_le_to_cpu_32(resp->flags) &
1974 HWRM_VNIC_QCFG_OUTPUT_FLAGS_BD_STALL_MODE;
1975 vnic->roce_dual = rte_le_to_cpu_32(resp->flags) &
1976 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_DUAL_VNIC_MODE;
1977 vnic->roce_only = rte_le_to_cpu_32(resp->flags) &
1978 HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_ONLY_VNIC_MODE;
1979 vnic->rss_dflt_cr = rte_le_to_cpu_32(resp->flags) &
1980 HWRM_VNIC_QCFG_OUTPUT_FLAGS_RSS_DFLT_CR_MODE;
1981
1982 HWRM_UNLOCK();
1983
1984 return rc;
1985 }
1986
1987 int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp,
1988 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
1989 {
1990 int rc = 0;
1991 uint16_t ctx_id;
1992 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {.req_type = 0 };
1993 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
1994 bp->hwrm_cmd_resp_addr;
1995
1996 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, BNXT_USE_CHIMP_MB);
1997
1998 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
1999 HWRM_CHECK_RESULT();
2000
2001 ctx_id = rte_le_to_cpu_16(resp->rss_cos_lb_ctx_id);
2002 if (!BNXT_HAS_RING_GRPS(bp))
2003 vnic->fw_grp_ids[ctx_idx] = ctx_id;
2004 else if (ctx_idx == 0)
2005 vnic->rss_rule = ctx_id;
2006
2007 HWRM_UNLOCK();
2008
2009 return rc;
2010 }
2011
2012 static
2013 int _bnxt_hwrm_vnic_ctx_free(struct bnxt *bp,
2014 struct bnxt_vnic_info *vnic, uint16_t ctx_idx)
2015 {
2016 int rc = 0;
2017 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {.req_type = 0 };
2018 struct hwrm_vnic_rss_cos_lb_ctx_free_output *resp =
2019 bp->hwrm_cmd_resp_addr;
2020
2021 if (ctx_idx == (uint16_t)HWRM_NA_SIGNATURE) {
2022 PMD_DRV_LOG(DEBUG, "VNIC RSS Rule %x\n", vnic->rss_rule);
2023 return rc;
2024 }
2025 HWRM_PREP(&req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, BNXT_USE_CHIMP_MB);
2026
2027 req.rss_cos_lb_ctx_id = rte_cpu_to_le_16(ctx_idx);
2028
2029 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2030
2031 HWRM_CHECK_RESULT();
2032 HWRM_UNLOCK();
2033
2034 return rc;
2035 }
2036
2037 int bnxt_hwrm_vnic_ctx_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2038 {
2039 int rc = 0;
2040
2041 if (BNXT_CHIP_THOR(bp)) {
2042 int j;
2043
2044 for (j = 0; j < vnic->num_lb_ctxts; j++) {
2045 rc = _bnxt_hwrm_vnic_ctx_free(bp,
2046 vnic,
2047 vnic->fw_grp_ids[j]);
2048 vnic->fw_grp_ids[j] = INVALID_HW_RING_ID;
2049 }
2050 vnic->num_lb_ctxts = 0;
2051 } else {
2052 rc = _bnxt_hwrm_vnic_ctx_free(bp, vnic, vnic->rss_rule);
2053 vnic->rss_rule = INVALID_HW_RING_ID;
2054 }
2055
2056 return rc;
2057 }
2058
2059 int bnxt_hwrm_vnic_free(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2060 {
2061 int rc = 0;
2062 struct hwrm_vnic_free_input req = {.req_type = 0 };
2063 struct hwrm_vnic_free_output *resp = bp->hwrm_cmd_resp_addr;
2064
2065 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2066 PMD_DRV_LOG(DEBUG, "VNIC FREE ID %x\n", vnic->fw_vnic_id);
2067 return rc;
2068 }
2069
2070 HWRM_PREP(&req, HWRM_VNIC_FREE, BNXT_USE_CHIMP_MB);
2071
2072 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2073
2074 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2075
2076 HWRM_CHECK_RESULT();
2077 HWRM_UNLOCK();
2078
2079 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2080 /* Configure default VNIC again if necessary. */
2081 if (vnic->func_default && (bp->flags & BNXT_FLAG_DFLT_VNIC_SET))
2082 bp->flags &= ~BNXT_FLAG_DFLT_VNIC_SET;
2083
2084 return rc;
2085 }
2086
2087 static int
2088 bnxt_hwrm_vnic_rss_cfg_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2089 {
2090 int i;
2091 int rc = 0;
2092 int nr_ctxs = vnic->num_lb_ctxts;
2093 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2094 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2095
2096 for (i = 0; i < nr_ctxs; i++) {
2097 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2098
2099 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2100 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2101 req.hash_mode_flags = vnic->hash_mode;
2102
2103 req.hash_key_tbl_addr =
2104 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2105
2106 req.ring_grp_tbl_addr =
2107 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
2108 i * HW_HASH_INDEX_SIZE);
2109 req.ring_table_pair_index = i;
2110 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
2111
2112 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
2113 BNXT_USE_CHIMP_MB);
2114
2115 HWRM_CHECK_RESULT();
2116 HWRM_UNLOCK();
2117 }
2118
2119 return rc;
2120 }
2121
2122 int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
2123 struct bnxt_vnic_info *vnic)
2124 {
2125 int rc = 0;
2126 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
2127 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2128
2129 if (!vnic->rss_table)
2130 return 0;
2131
2132 if (BNXT_CHIP_THOR(bp))
2133 return bnxt_hwrm_vnic_rss_cfg_thor(bp, vnic);
2134
2135 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
2136
2137 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
2138 req.hash_mode_flags = vnic->hash_mode;
2139
2140 req.ring_grp_tbl_addr =
2141 rte_cpu_to_le_64(vnic->rss_table_dma_addr);
2142 req.hash_key_tbl_addr =
2143 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
2144 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
2145 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2146
2147 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2148
2149 HWRM_CHECK_RESULT();
2150 HWRM_UNLOCK();
2151
2152 return rc;
2153 }
2154
2155 int bnxt_hwrm_vnic_plcmode_cfg(struct bnxt *bp,
2156 struct bnxt_vnic_info *vnic)
2157 {
2158 int rc = 0;
2159 struct hwrm_vnic_plcmodes_cfg_input req = {.req_type = 0 };
2160 struct hwrm_vnic_plcmodes_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2161 uint16_t size;
2162
2163 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2164 PMD_DRV_LOG(DEBUG, "VNIC ID %x\n", vnic->fw_vnic_id);
2165 return rc;
2166 }
2167
2168 HWRM_PREP(&req, HWRM_VNIC_PLCMODES_CFG, BNXT_USE_CHIMP_MB);
2169
2170 req.flags = rte_cpu_to_le_32(
2171 HWRM_VNIC_PLCMODES_CFG_INPUT_FLAGS_JUMBO_PLACEMENT);
2172
2173 req.enables = rte_cpu_to_le_32(
2174 HWRM_VNIC_PLCMODES_CFG_INPUT_ENABLES_JUMBO_THRESH_VALID);
2175
2176 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool);
2177 size -= RTE_PKTMBUF_HEADROOM;
2178 size = RTE_MIN(BNXT_MAX_PKT_LEN, size);
2179
2180 req.jumbo_thresh = rte_cpu_to_le_16(size);
2181 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2182
2183 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2184
2185 HWRM_CHECK_RESULT();
2186 HWRM_UNLOCK();
2187
2188 return rc;
2189 }
2190
2191 int bnxt_hwrm_vnic_tpa_cfg(struct bnxt *bp,
2192 struct bnxt_vnic_info *vnic, bool enable)
2193 {
2194 int rc = 0;
2195 struct hwrm_vnic_tpa_cfg_input req = {.req_type = 0 };
2196 struct hwrm_vnic_tpa_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2197
2198 if (BNXT_CHIP_THOR(bp) && !bp->max_tpa_v2) {
2199 if (enable)
2200 PMD_DRV_LOG(ERR, "No HW support for LRO\n");
2201 return -ENOTSUP;
2202 }
2203
2204 if (vnic->fw_vnic_id == INVALID_HW_RING_ID) {
2205 PMD_DRV_LOG(DEBUG, "Invalid vNIC ID\n");
2206 return 0;
2207 }
2208
2209 HWRM_PREP(&req, HWRM_VNIC_TPA_CFG, BNXT_USE_CHIMP_MB);
2210
2211 if (enable) {
2212 req.enables = rte_cpu_to_le_32(
2213 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS |
2214 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGGS |
2215 HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN);
2216 req.flags = rte_cpu_to_le_32(
2217 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_TPA |
2218 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA |
2219 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE |
2220 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO |
2221 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN |
2222 HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ);
2223 req.max_agg_segs = rte_cpu_to_le_16(BNXT_TPA_MAX_AGGS(bp));
2224 req.max_aggs = rte_cpu_to_le_16(BNXT_TPA_MAX_SEGS(bp));
2225 req.min_agg_len = rte_cpu_to_le_32(512);
2226 }
2227 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
2228
2229 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2230
2231 HWRM_CHECK_RESULT();
2232 HWRM_UNLOCK();
2233
2234 return rc;
2235 }
2236
2237 int bnxt_hwrm_func_vf_mac(struct bnxt *bp, uint16_t vf, const uint8_t *mac_addr)
2238 {
2239 struct hwrm_func_cfg_input req = {0};
2240 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
2241 int rc;
2242
2243 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
2244 req.enables = rte_cpu_to_le_32(
2245 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
2246 memcpy(req.dflt_mac_addr, mac_addr, sizeof(req.dflt_mac_addr));
2247 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
2248
2249 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
2250
2251 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2252 HWRM_CHECK_RESULT();
2253 HWRM_UNLOCK();
2254
2255 bp->pf->vf_info[vf].random_mac = false;
2256
2257 return rc;
2258 }
2259
2260 int bnxt_hwrm_func_qstats_tx_drop(struct bnxt *bp, uint16_t fid,
2261 uint64_t *dropped)
2262 {
2263 int rc = 0;
2264 struct hwrm_func_qstats_input req = {.req_type = 0};
2265 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2266
2267 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2268
2269 req.fid = rte_cpu_to_le_16(fid);
2270
2271 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2272
2273 HWRM_CHECK_RESULT();
2274
2275 if (dropped)
2276 *dropped = rte_le_to_cpu_64(resp->tx_drop_pkts);
2277
2278 HWRM_UNLOCK();
2279
2280 return rc;
2281 }
2282
2283 int bnxt_hwrm_func_qstats(struct bnxt *bp, uint16_t fid,
2284 struct rte_eth_stats *stats,
2285 struct hwrm_func_qstats_output *func_qstats)
2286 {
2287 int rc = 0;
2288 struct hwrm_func_qstats_input req = {.req_type = 0};
2289 struct hwrm_func_qstats_output *resp = bp->hwrm_cmd_resp_addr;
2290
2291 HWRM_PREP(&req, HWRM_FUNC_QSTATS, BNXT_USE_CHIMP_MB);
2292
2293 req.fid = rte_cpu_to_le_16(fid);
2294
2295 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2296
2297 HWRM_CHECK_RESULT();
2298 if (func_qstats)
2299 memcpy(func_qstats, resp,
2300 sizeof(struct hwrm_func_qstats_output));
2301
2302 if (!stats)
2303 goto exit;
2304
2305 stats->ipackets = rte_le_to_cpu_64(resp->rx_ucast_pkts);
2306 stats->ipackets += rte_le_to_cpu_64(resp->rx_mcast_pkts);
2307 stats->ipackets += rte_le_to_cpu_64(resp->rx_bcast_pkts);
2308 stats->ibytes = rte_le_to_cpu_64(resp->rx_ucast_bytes);
2309 stats->ibytes += rte_le_to_cpu_64(resp->rx_mcast_bytes);
2310 stats->ibytes += rte_le_to_cpu_64(resp->rx_bcast_bytes);
2311
2312 stats->opackets = rte_le_to_cpu_64(resp->tx_ucast_pkts);
2313 stats->opackets += rte_le_to_cpu_64(resp->tx_mcast_pkts);
2314 stats->opackets += rte_le_to_cpu_64(resp->tx_bcast_pkts);
2315 stats->obytes = rte_le_to_cpu_64(resp->tx_ucast_bytes);
2316 stats->obytes += rte_le_to_cpu_64(resp->tx_mcast_bytes);
2317 stats->obytes += rte_le_to_cpu_64(resp->tx_bcast_bytes);
2318
2319 stats->imissed = rte_le_to_cpu_64(resp->rx_discard_pkts);
2320 stats->ierrors = rte_le_to_cpu_64(resp->rx_drop_pkts);
2321 stats->oerrors = rte_le_to_cpu_64(resp->tx_discard_pkts);
2322
2323 exit:
2324 HWRM_UNLOCK();
2325
2326 return rc;
2327 }
2328
2329 int bnxt_hwrm_func_clr_stats(struct bnxt *bp, uint16_t fid)
2330 {
2331 int rc = 0;
2332 struct hwrm_func_clr_stats_input req = {.req_type = 0};
2333 struct hwrm_func_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
2334
2335 HWRM_PREP(&req, HWRM_FUNC_CLR_STATS, BNXT_USE_CHIMP_MB);
2336
2337 req.fid = rte_cpu_to_le_16(fid);
2338
2339 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
2340
2341 HWRM_CHECK_RESULT();
2342 HWRM_UNLOCK();
2343
2344 return rc;
2345 }
2346
2347 int bnxt_clear_all_hwrm_stat_ctxs(struct bnxt *bp)
2348 {
2349 unsigned int i;
2350 int rc = 0;
2351
2352 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2353 struct bnxt_tx_queue *txq;
2354 struct bnxt_rx_queue *rxq;
2355 struct bnxt_cp_ring_info *cpr;
2356
2357 if (i >= bp->rx_cp_nr_rings) {
2358 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2359 cpr = txq->cp_ring;
2360 } else {
2361 rxq = bp->rx_queues[i];
2362 cpr = rxq->cp_ring;
2363 }
2364
2365 rc = bnxt_hwrm_stat_clear(bp, cpr);
2366 if (rc)
2367 return rc;
2368 }
2369 return 0;
2370 }
2371
2372 static int
2373 bnxt_free_all_hwrm_stat_ctxs(struct bnxt *bp)
2374 {
2375 int rc;
2376 unsigned int i;
2377 struct bnxt_cp_ring_info *cpr;
2378
2379 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2380
2381 if (i >= bp->rx_cp_nr_rings) {
2382 cpr = bp->tx_queues[i - bp->rx_cp_nr_rings]->cp_ring;
2383 } else {
2384 cpr = bp->rx_queues[i]->cp_ring;
2385 if (BNXT_HAS_RING_GRPS(bp))
2386 bp->grp_info[i].fw_stats_ctx = -1;
2387 }
2388 if (cpr->hw_stats_ctx_id != HWRM_NA_SIGNATURE) {
2389 rc = bnxt_hwrm_stat_ctx_free(bp, cpr, i);
2390 cpr->hw_stats_ctx_id = HWRM_NA_SIGNATURE;
2391 if (rc)
2392 return rc;
2393 }
2394 }
2395 return 0;
2396 }
2397
2398 int bnxt_alloc_all_hwrm_stat_ctxs(struct bnxt *bp)
2399 {
2400 unsigned int i;
2401 int rc = 0;
2402
2403 for (i = 0; i < bp->rx_cp_nr_rings + bp->tx_cp_nr_rings; i++) {
2404 struct bnxt_tx_queue *txq;
2405 struct bnxt_rx_queue *rxq;
2406 struct bnxt_cp_ring_info *cpr;
2407
2408 if (i >= bp->rx_cp_nr_rings) {
2409 txq = bp->tx_queues[i - bp->rx_cp_nr_rings];
2410 cpr = txq->cp_ring;
2411 } else {
2412 rxq = bp->rx_queues[i];
2413 cpr = rxq->cp_ring;
2414 }
2415
2416 rc = bnxt_hwrm_stat_ctx_alloc(bp, cpr, i);
2417
2418 if (rc)
2419 return rc;
2420 }
2421 return rc;
2422 }
2423
2424 static int
2425 bnxt_free_all_hwrm_ring_grps(struct bnxt *bp)
2426 {
2427 uint16_t idx;
2428 uint32_t rc = 0;
2429
2430 if (!BNXT_HAS_RING_GRPS(bp))
2431 return 0;
2432
2433 for (idx = 0; idx < bp->rx_cp_nr_rings; idx++) {
2434
2435 if (bp->grp_info[idx].fw_grp_id == INVALID_HW_RING_ID)
2436 continue;
2437
2438 rc = bnxt_hwrm_ring_grp_free(bp, idx);
2439
2440 if (rc)
2441 return rc;
2442 }
2443 return rc;
2444 }
2445
2446 void bnxt_free_nq_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2447 {
2448 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2449
2450 bnxt_hwrm_ring_free(bp, cp_ring,
2451 HWRM_RING_FREE_INPUT_RING_TYPE_NQ);
2452 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2453 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2454 sizeof(*cpr->cp_desc_ring));
2455 cpr->cp_raw_cons = 0;
2456 cpr->valid = 0;
2457 }
2458
2459 void bnxt_free_cp_ring(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2460 {
2461 struct bnxt_ring *cp_ring = cpr->cp_ring_struct;
2462
2463 bnxt_hwrm_ring_free(bp, cp_ring,
2464 HWRM_RING_FREE_INPUT_RING_TYPE_L2_CMPL);
2465 cp_ring->fw_ring_id = INVALID_HW_RING_ID;
2466 memset(cpr->cp_desc_ring, 0, cpr->cp_ring_struct->ring_size *
2467 sizeof(*cpr->cp_desc_ring));
2468 cpr->cp_raw_cons = 0;
2469 cpr->valid = 0;
2470 }
2471
2472 void bnxt_free_hwrm_rx_ring(struct bnxt *bp, int queue_index)
2473 {
2474 struct bnxt_rx_queue *rxq = bp->rx_queues[queue_index];
2475 struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
2476 struct bnxt_ring *ring = rxr->rx_ring_struct;
2477 struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
2478
2479 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2480 bnxt_hwrm_ring_free(bp, ring,
2481 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2482 ring->fw_ring_id = INVALID_HW_RING_ID;
2483 if (BNXT_HAS_RING_GRPS(bp))
2484 bp->grp_info[queue_index].rx_fw_ring_id =
2485 INVALID_HW_RING_ID;
2486 }
2487 ring = rxr->ag_ring_struct;
2488 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2489 bnxt_hwrm_ring_free(bp, ring,
2490 BNXT_CHIP_THOR(bp) ?
2491 HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG :
2492 HWRM_RING_FREE_INPUT_RING_TYPE_RX);
2493 if (BNXT_HAS_RING_GRPS(bp))
2494 bp->grp_info[queue_index].ag_fw_ring_id =
2495 INVALID_HW_RING_ID;
2496 }
2497 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID)
2498 bnxt_free_cp_ring(bp, cpr);
2499
2500 if (BNXT_HAS_RING_GRPS(bp))
2501 bp->grp_info[queue_index].cp_fw_ring_id = INVALID_HW_RING_ID;
2502 }
2503
2504 static int
2505 bnxt_free_all_hwrm_rings(struct bnxt *bp)
2506 {
2507 unsigned int i;
2508
2509 for (i = 0; i < bp->tx_cp_nr_rings; i++) {
2510 struct bnxt_tx_queue *txq = bp->tx_queues[i];
2511 struct bnxt_tx_ring_info *txr = txq->tx_ring;
2512 struct bnxt_ring *ring = txr->tx_ring_struct;
2513 struct bnxt_cp_ring_info *cpr = txq->cp_ring;
2514
2515 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
2516 bnxt_hwrm_ring_free(bp, ring,
2517 HWRM_RING_FREE_INPUT_RING_TYPE_TX);
2518 ring->fw_ring_id = INVALID_HW_RING_ID;
2519 memset(txr->tx_desc_ring, 0,
2520 txr->tx_ring_struct->ring_size *
2521 sizeof(*txr->tx_desc_ring));
2522 memset(txr->tx_buf_ring, 0,
2523 txr->tx_ring_struct->ring_size *
2524 sizeof(*txr->tx_buf_ring));
2525 txr->tx_prod = 0;
2526 txr->tx_cons = 0;
2527 }
2528 if (cpr->cp_ring_struct->fw_ring_id != INVALID_HW_RING_ID) {
2529 bnxt_free_cp_ring(bp, cpr);
2530 cpr->cp_ring_struct->fw_ring_id = INVALID_HW_RING_ID;
2531 }
2532 }
2533
2534 for (i = 0; i < bp->rx_cp_nr_rings; i++)
2535 bnxt_free_hwrm_rx_ring(bp, i);
2536
2537 return 0;
2538 }
2539
2540 int bnxt_alloc_all_hwrm_ring_grps(struct bnxt *bp)
2541 {
2542 uint16_t i;
2543 uint32_t rc = 0;
2544
2545 if (!BNXT_HAS_RING_GRPS(bp))
2546 return 0;
2547
2548 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
2549 rc = bnxt_hwrm_ring_grp_alloc(bp, i);
2550 if (rc)
2551 return rc;
2552 }
2553 return rc;
2554 }
2555
2556 /*
2557 * HWRM utility functions
2558 */
2559
2560 void bnxt_free_hwrm_resources(struct bnxt *bp)
2561 {
2562 /* Release memzone */
2563 rte_free(bp->hwrm_cmd_resp_addr);
2564 rte_free(bp->hwrm_short_cmd_req_addr);
2565 bp->hwrm_cmd_resp_addr = NULL;
2566 bp->hwrm_short_cmd_req_addr = NULL;
2567 bp->hwrm_cmd_resp_dma_addr = 0;
2568 bp->hwrm_short_cmd_req_dma_addr = 0;
2569 }
2570
2571 int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2572 {
2573 struct rte_pci_device *pdev = bp->pdev;
2574 char type[RTE_MEMZONE_NAMESIZE];
2575
2576 sprintf(type, "bnxt_hwrm_" PCI_PRI_FMT, pdev->addr.domain,
2577 pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
2578 bp->max_resp_len = HWRM_MAX_RESP_LEN;
2579 bp->hwrm_cmd_resp_addr = rte_malloc(type, bp->max_resp_len, 0);
2580 if (bp->hwrm_cmd_resp_addr == NULL)
2581 return -ENOMEM;
2582 bp->hwrm_cmd_resp_dma_addr =
2583 rte_malloc_virt2iova(bp->hwrm_cmd_resp_addr);
2584 if (bp->hwrm_cmd_resp_dma_addr == RTE_BAD_IOVA) {
2585 PMD_DRV_LOG(ERR,
2586 "unable to map response address to physical memory\n");
2587 return -ENOMEM;
2588 }
2589 rte_spinlock_init(&bp->hwrm_lock);
2590
2591 return 0;
2592 }
2593
2594 static int
2595 bnxt_clear_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2596 {
2597 struct bnxt_filter_info *filter;
2598 int rc = 0;
2599
2600 STAILQ_FOREACH(filter, &vnic->filter, next) {
2601 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2602 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2603 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2604 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2605 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2606 STAILQ_REMOVE(&vnic->filter, filter, bnxt_filter_info, next);
2607 bnxt_free_filter(bp, filter);
2608 }
2609 return rc;
2610 }
2611
2612 static int
2613 bnxt_clear_hwrm_vnic_flows(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2614 {
2615 struct bnxt_filter_info *filter;
2616 struct rte_flow *flow;
2617 int rc = 0;
2618
2619 while (!STAILQ_EMPTY(&vnic->flow_list)) {
2620 flow = STAILQ_FIRST(&vnic->flow_list);
2621 filter = flow->filter;
2622 PMD_DRV_LOG(DEBUG, "filter type %d\n", filter->filter_type);
2623 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2624 rc = bnxt_hwrm_clear_em_filter(bp, filter);
2625 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2626 rc = bnxt_hwrm_clear_ntuple_filter(bp, filter);
2627 rc = bnxt_hwrm_clear_l2_filter(bp, filter);
2628
2629 STAILQ_REMOVE(&vnic->flow_list, flow, rte_flow, next);
2630 rte_free(flow);
2631 }
2632 return rc;
2633 }
2634
2635 int bnxt_set_hwrm_vnic_filters(struct bnxt *bp, struct bnxt_vnic_info *vnic)
2636 {
2637 struct bnxt_filter_info *filter;
2638 int rc = 0;
2639
2640 STAILQ_FOREACH(filter, &vnic->filter, next) {
2641 if (filter->filter_type == HWRM_CFA_EM_FILTER)
2642 rc = bnxt_hwrm_set_em_filter(bp, filter->dst_id,
2643 filter);
2644 else if (filter->filter_type == HWRM_CFA_NTUPLE_FILTER)
2645 rc = bnxt_hwrm_set_ntuple_filter(bp, filter->dst_id,
2646 filter);
2647 else
2648 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id,
2649 filter);
2650 if (rc)
2651 break;
2652 }
2653 return rc;
2654 }
2655
2656 static void
2657 bnxt_free_tunnel_ports(struct bnxt *bp)
2658 {
2659 if (bp->vxlan_port_cnt)
2660 bnxt_hwrm_tunnel_dst_port_free(bp, bp->vxlan_fw_dst_port_id,
2661 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN);
2662 bp->vxlan_port = 0;
2663 if (bp->geneve_port_cnt)
2664 bnxt_hwrm_tunnel_dst_port_free(bp, bp->geneve_fw_dst_port_id,
2665 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE);
2666 bp->geneve_port = 0;
2667 }
2668
2669 void bnxt_free_all_hwrm_resources(struct bnxt *bp)
2670 {
2671 int i;
2672
2673 if (bp->vnic_info == NULL)
2674 return;
2675
2676 /*
2677 * Cleanup VNICs in reverse order, to make sure the L2 filter
2678 * from vnic0 is last to be cleaned up.
2679 */
2680 for (i = bp->max_vnics - 1; i >= 0; i--) {
2681 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2682
2683 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
2684 continue;
2685
2686 bnxt_clear_hwrm_vnic_flows(bp, vnic);
2687
2688 bnxt_clear_hwrm_vnic_filters(bp, vnic);
2689
2690 bnxt_hwrm_vnic_ctx_free(bp, vnic);
2691
2692 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, false);
2693
2694 bnxt_hwrm_vnic_free(bp, vnic);
2695
2696 rte_free(vnic->fw_grp_ids);
2697 }
2698 /* Ring resources */
2699 bnxt_free_all_hwrm_rings(bp);
2700 bnxt_free_all_hwrm_ring_grps(bp);
2701 bnxt_free_all_hwrm_stat_ctxs(bp);
2702 bnxt_free_tunnel_ports(bp);
2703 }
2704
2705 static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
2706 {
2707 uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2708
2709 if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
2710 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
2711
2712 switch (conf_link_speed) {
2713 case ETH_LINK_SPEED_10M_HD:
2714 case ETH_LINK_SPEED_100M_HD:
2715 /* FALLTHROUGH */
2716 return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
2717 }
2718 return hw_link_duplex;
2719 }
2720
2721 static uint16_t bnxt_check_eth_link_autoneg(uint32_t conf_link)
2722 {
2723 return (conf_link & ETH_LINK_SPEED_FIXED) ? 0 : 1;
2724 }
2725
2726 static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
2727 {
2728 uint16_t eth_link_speed = 0;
2729
2730 if (conf_link_speed == ETH_LINK_SPEED_AUTONEG)
2731 return ETH_LINK_SPEED_AUTONEG;
2732
2733 switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
2734 case ETH_LINK_SPEED_100M:
2735 case ETH_LINK_SPEED_100M_HD:
2736 /* FALLTHROUGH */
2737 eth_link_speed =
2738 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB;
2739 break;
2740 case ETH_LINK_SPEED_1G:
2741 eth_link_speed =
2742 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB;
2743 break;
2744 case ETH_LINK_SPEED_2_5G:
2745 eth_link_speed =
2746 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB;
2747 break;
2748 case ETH_LINK_SPEED_10G:
2749 eth_link_speed =
2750 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB;
2751 break;
2752 case ETH_LINK_SPEED_20G:
2753 eth_link_speed =
2754 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB;
2755 break;
2756 case ETH_LINK_SPEED_25G:
2757 eth_link_speed =
2758 HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB;
2759 break;
2760 case ETH_LINK_SPEED_40G:
2761 eth_link_speed =
2762 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB;
2763 break;
2764 case ETH_LINK_SPEED_50G:
2765 eth_link_speed =
2766 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB;
2767 break;
2768 case ETH_LINK_SPEED_100G:
2769 eth_link_speed =
2770 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB;
2771 break;
2772 case ETH_LINK_SPEED_200G:
2773 eth_link_speed =
2774 HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB;
2775 break;
2776 default:
2777 PMD_DRV_LOG(ERR,
2778 "Unsupported link speed %d; default to AUTO\n",
2779 conf_link_speed);
2780 break;
2781 }
2782 return eth_link_speed;
2783 }
2784
2785 #define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
2786 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
2787 ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
2788 ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G | \
2789 ETH_LINK_SPEED_100G | ETH_LINK_SPEED_200G)
2790
2791 static int bnxt_valid_link_speed(uint32_t link_speed, uint16_t port_id)
2792 {
2793 uint32_t one_speed;
2794
2795 if (link_speed == ETH_LINK_SPEED_AUTONEG)
2796 return 0;
2797
2798 if (link_speed & ETH_LINK_SPEED_FIXED) {
2799 one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
2800
2801 if (one_speed & (one_speed - 1)) {
2802 PMD_DRV_LOG(ERR,
2803 "Invalid advertised speeds (%u) for port %u\n",
2804 link_speed, port_id);
2805 return -EINVAL;
2806 }
2807 if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
2808 PMD_DRV_LOG(ERR,
2809 "Unsupported advertised speed (%u) for port %u\n",
2810 link_speed, port_id);
2811 return -EINVAL;
2812 }
2813 } else {
2814 if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
2815 PMD_DRV_LOG(ERR,
2816 "Unsupported advertised speeds (%u) for port %u\n",
2817 link_speed, port_id);
2818 return -EINVAL;
2819 }
2820 }
2821 return 0;
2822 }
2823
2824 static uint16_t
2825 bnxt_parse_eth_link_speed_mask(struct bnxt *bp, uint32_t link_speed)
2826 {
2827 uint16_t ret = 0;
2828
2829 if (link_speed == ETH_LINK_SPEED_AUTONEG) {
2830 if (bp->link_info->support_speeds)
2831 return bp->link_info->support_speeds;
2832 link_speed = BNXT_SUPPORTED_SPEEDS;
2833 }
2834
2835 if (link_speed & ETH_LINK_SPEED_100M)
2836 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2837 if (link_speed & ETH_LINK_SPEED_100M_HD)
2838 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
2839 if (link_speed & ETH_LINK_SPEED_1G)
2840 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
2841 if (link_speed & ETH_LINK_SPEED_2_5G)
2842 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
2843 if (link_speed & ETH_LINK_SPEED_10G)
2844 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
2845 if (link_speed & ETH_LINK_SPEED_20G)
2846 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
2847 if (link_speed & ETH_LINK_SPEED_25G)
2848 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
2849 if (link_speed & ETH_LINK_SPEED_40G)
2850 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
2851 if (link_speed & ETH_LINK_SPEED_50G)
2852 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
2853 if (link_speed & ETH_LINK_SPEED_100G)
2854 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB;
2855 if (link_speed & ETH_LINK_SPEED_200G)
2856 ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB;
2857 return ret;
2858 }
2859
2860 static uint32_t bnxt_parse_hw_link_speed(uint16_t hw_link_speed)
2861 {
2862 uint32_t eth_link_speed = ETH_SPEED_NUM_NONE;
2863
2864 switch (hw_link_speed) {
2865 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB:
2866 eth_link_speed = ETH_SPEED_NUM_100M;
2867 break;
2868 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_1GB:
2869 eth_link_speed = ETH_SPEED_NUM_1G;
2870 break;
2871 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2_5GB:
2872 eth_link_speed = ETH_SPEED_NUM_2_5G;
2873 break;
2874 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10GB:
2875 eth_link_speed = ETH_SPEED_NUM_10G;
2876 break;
2877 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_20GB:
2878 eth_link_speed = ETH_SPEED_NUM_20G;
2879 break;
2880 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_25GB:
2881 eth_link_speed = ETH_SPEED_NUM_25G;
2882 break;
2883 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_40GB:
2884 eth_link_speed = ETH_SPEED_NUM_40G;
2885 break;
2886 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB:
2887 eth_link_speed = ETH_SPEED_NUM_50G;
2888 break;
2889 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB:
2890 eth_link_speed = ETH_SPEED_NUM_100G;
2891 break;
2892 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB:
2893 eth_link_speed = ETH_SPEED_NUM_200G;
2894 break;
2895 case HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_2GB:
2896 default:
2897 PMD_DRV_LOG(ERR, "HWRM link speed %d not defined\n",
2898 hw_link_speed);
2899 break;
2900 }
2901 return eth_link_speed;
2902 }
2903
2904 static uint16_t bnxt_parse_hw_link_duplex(uint16_t hw_link_duplex)
2905 {
2906 uint16_t eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2907
2908 switch (hw_link_duplex) {
2909 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH:
2910 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL:
2911 /* FALLTHROUGH */
2912 eth_link_duplex = ETH_LINK_FULL_DUPLEX;
2913 break;
2914 case HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF:
2915 eth_link_duplex = ETH_LINK_HALF_DUPLEX;
2916 break;
2917 default:
2918 PMD_DRV_LOG(ERR, "HWRM link duplex %d not defined\n",
2919 hw_link_duplex);
2920 break;
2921 }
2922 return eth_link_duplex;
2923 }
2924
2925 int bnxt_get_hwrm_link_config(struct bnxt *bp, struct rte_eth_link *link)
2926 {
2927 int rc = 0;
2928 struct bnxt_link_info *link_info = bp->link_info;
2929
2930 rc = bnxt_hwrm_port_phy_qcfg(bp, link_info);
2931 if (rc) {
2932 PMD_DRV_LOG(ERR,
2933 "Get link config failed with rc %d\n", rc);
2934 goto exit;
2935 }
2936 if (link_info->link_speed)
2937 link->link_speed =
2938 bnxt_parse_hw_link_speed(link_info->link_speed);
2939 else
2940 link->link_speed = ETH_SPEED_NUM_NONE;
2941 link->link_duplex = bnxt_parse_hw_link_duplex(link_info->duplex);
2942 link->link_status = link_info->link_up;
2943 link->link_autoneg = link_info->auto_mode ==
2944 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE ?
2945 ETH_LINK_FIXED : ETH_LINK_AUTONEG;
2946 exit:
2947 return rc;
2948 }
2949
2950 int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
2951 {
2952 int rc = 0;
2953 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
2954 struct bnxt_link_info link_req;
2955 uint16_t speed, autoneg;
2956
2957 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp))
2958 return 0;
2959
2960 rc = bnxt_valid_link_speed(dev_conf->link_speeds,
2961 bp->eth_dev->data->port_id);
2962 if (rc)
2963 goto error;
2964
2965 memset(&link_req, 0, sizeof(link_req));
2966 link_req.link_up = link_up;
2967 if (!link_up)
2968 goto port_phy_cfg;
2969
2970 autoneg = bnxt_check_eth_link_autoneg(dev_conf->link_speeds);
2971 if (BNXT_CHIP_THOR(bp) &&
2972 dev_conf->link_speeds == ETH_LINK_SPEED_40G) {
2973 /* 40G is not supported as part of media auto detect.
2974 * The speed should be forced and autoneg disabled
2975 * to configure 40G speed.
2976 */
2977 PMD_DRV_LOG(INFO, "Disabling autoneg for 40G\n");
2978 autoneg = 0;
2979 }
2980
2981 speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
2982 link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
2983 /* Autoneg can be done only when the FW allows.
2984 * When user configures fixed speed of 40G and later changes to
2985 * any other speed, auto_link_speed/force_link_speed is still set
2986 * to 40G until link comes up at new speed.
2987 */
2988 if (autoneg == 1 &&
2989 !(!BNXT_CHIP_THOR(bp) &&
2990 (bp->link_info->auto_link_speed ||
2991 bp->link_info->force_link_speed))) {
2992 link_req.phy_flags |=
2993 HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
2994 link_req.auto_link_speed_mask =
2995 bnxt_parse_eth_link_speed_mask(bp,
2996 dev_conf->link_speeds);
2997 } else {
2998 if (bp->link_info->phy_type ==
2999 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASET ||
3000 bp->link_info->phy_type ==
3001 HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_BASETE ||
3002 bp->link_info->media_type ==
3003 HWRM_PORT_PHY_QCFG_OUTPUT_MEDIA_TYPE_TP) {
3004 PMD_DRV_LOG(ERR, "10GBase-T devices must autoneg\n");
3005 return -EINVAL;
3006 }
3007
3008 link_req.phy_flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
3009 /* If user wants a particular speed try that first. */
3010 if (speed)
3011 link_req.link_speed = speed;
3012 else if (bp->link_info->force_link_speed)
3013 link_req.link_speed = bp->link_info->force_link_speed;
3014 else
3015 link_req.link_speed = bp->link_info->auto_link_speed;
3016 }
3017 link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
3018 link_req.auto_pause = bp->link_info->auto_pause;
3019 link_req.force_pause = bp->link_info->force_pause;
3020
3021 port_phy_cfg:
3022 rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
3023 if (rc) {
3024 PMD_DRV_LOG(ERR,
3025 "Set link config failed with rc %d\n", rc);
3026 }
3027
3028 error:
3029 return rc;
3030 }
3031
3032 /* JIRA 22088 */
3033 int bnxt_hwrm_func_qcfg(struct bnxt *bp, uint16_t *mtu)
3034 {
3035 struct hwrm_func_qcfg_input req = {0};
3036 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3037 uint16_t flags;
3038 int rc = 0;
3039 bp->func_svif = BNXT_SVIF_INVALID;
3040 uint16_t svif_info;
3041
3042 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3043 req.fid = rte_cpu_to_le_16(0xffff);
3044
3045 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3046
3047 HWRM_CHECK_RESULT();
3048
3049 /* Hard Coded.. 0xfff VLAN ID mask */
3050 bp->vlan = rte_le_to_cpu_16(resp->vlan) & 0xfff;
3051
3052 svif_info = rte_le_to_cpu_16(resp->svif_info);
3053 if (svif_info & HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_VALID)
3054 bp->func_svif = svif_info &
3055 HWRM_FUNC_QCFG_OUTPUT_SVIF_INFO_SVIF_MASK;
3056
3057 flags = rte_le_to_cpu_16(resp->flags);
3058 if (BNXT_PF(bp) && (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_HOST))
3059 bp->flags |= BNXT_FLAG_MULTI_HOST;
3060
3061 if (BNXT_VF(bp) &&
3062 !BNXT_VF_IS_TRUSTED(bp) &&
3063 (flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3064 bp->flags |= BNXT_FLAG_TRUSTED_VF_EN;
3065 PMD_DRV_LOG(INFO, "Trusted VF cap enabled\n");
3066 } else if (BNXT_VF(bp) &&
3067 BNXT_VF_IS_TRUSTED(bp) &&
3068 !(flags & HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF)) {
3069 bp->flags &= ~BNXT_FLAG_TRUSTED_VF_EN;
3070 PMD_DRV_LOG(INFO, "Trusted VF cap disabled\n");
3071 }
3072
3073 if (mtu)
3074 *mtu = rte_le_to_cpu_16(resp->mtu);
3075
3076 switch (resp->port_partition_type) {
3077 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_0:
3078 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR1_5:
3079 case HWRM_FUNC_QCFG_OUTPUT_PORT_PARTITION_TYPE_NPAR2_0:
3080 /* FALLTHROUGH */
3081 bp->flags |= BNXT_FLAG_NPAR_PF;
3082 break;
3083 default:
3084 bp->flags &= ~BNXT_FLAG_NPAR_PF;
3085 break;
3086 }
3087
3088 HWRM_UNLOCK();
3089
3090 return rc;
3091 }
3092
3093 int bnxt_hwrm_port_mac_qcfg(struct bnxt *bp)
3094 {
3095 struct hwrm_port_mac_qcfg_input req = {0};
3096 struct hwrm_port_mac_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3097 uint16_t port_svif_info;
3098 int rc;
3099
3100 bp->port_svif = BNXT_SVIF_INVALID;
3101
3102 if (!BNXT_PF(bp))
3103 return 0;
3104
3105 HWRM_PREP(&req, HWRM_PORT_MAC_QCFG, BNXT_USE_CHIMP_MB);
3106
3107 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3108
3109 HWRM_CHECK_RESULT();
3110
3111 port_svif_info = rte_le_to_cpu_16(resp->port_svif_info);
3112 if (port_svif_info &
3113 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_VALID)
3114 bp->port_svif = port_svif_info &
3115 HWRM_PORT_MAC_QCFG_OUTPUT_PORT_SVIF_INFO_PORT_SVIF_MASK;
3116
3117 HWRM_UNLOCK();
3118
3119 return 0;
3120 }
3121
3122 static void copy_func_cfg_to_qcaps(struct hwrm_func_cfg_input *fcfg,
3123 struct hwrm_func_qcaps_output *qcaps)
3124 {
3125 qcaps->max_rsscos_ctx = fcfg->num_rsscos_ctxs;
3126 memcpy(qcaps->mac_address, fcfg->dflt_mac_addr,
3127 sizeof(qcaps->mac_address));
3128 qcaps->max_l2_ctxs = fcfg->num_l2_ctxs;
3129 qcaps->max_rx_rings = fcfg->num_rx_rings;
3130 qcaps->max_tx_rings = fcfg->num_tx_rings;
3131 qcaps->max_cmpl_rings = fcfg->num_cmpl_rings;
3132 qcaps->max_stat_ctx = fcfg->num_stat_ctxs;
3133 qcaps->max_vfs = 0;
3134 qcaps->first_vf_id = 0;
3135 qcaps->max_vnics = fcfg->num_vnics;
3136 qcaps->max_decap_records = 0;
3137 qcaps->max_encap_records = 0;
3138 qcaps->max_tx_wm_flows = 0;
3139 qcaps->max_tx_em_flows = 0;
3140 qcaps->max_rx_wm_flows = 0;
3141 qcaps->max_rx_em_flows = 0;
3142 qcaps->max_flow_id = 0;
3143 qcaps->max_mcast_filters = fcfg->num_mcast_filters;
3144 qcaps->max_sp_tx_rings = 0;
3145 qcaps->max_hw_ring_grps = fcfg->num_hw_ring_grps;
3146 }
3147
3148 static int bnxt_hwrm_pf_func_cfg(struct bnxt *bp, int tx_rings)
3149 {
3150 struct hwrm_func_cfg_input req = {0};
3151 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3152 uint32_t enables;
3153 int rc;
3154
3155 enables = HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3156 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3157 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3158 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3159 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3160 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3161 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3162 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3163 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS;
3164
3165 if (BNXT_HAS_RING_GRPS(bp)) {
3166 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS;
3167 req.num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps);
3168 } else if (BNXT_HAS_NQ(bp)) {
3169 enables |= HWRM_FUNC_CFG_INPUT_ENABLES_NUM_MSIX;
3170 req.num_msix = rte_cpu_to_le_16(bp->max_nq_rings);
3171 }
3172
3173 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3174 req.mtu = rte_cpu_to_le_16(BNXT_MAX_MTU);
3175 req.mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3176 req.num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx);
3177 req.num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx);
3178 req.num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings);
3179 req.num_tx_rings = rte_cpu_to_le_16(tx_rings);
3180 req.num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings);
3181 req.num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx);
3182 req.num_vnics = rte_cpu_to_le_16(bp->max_vnics);
3183 req.fid = rte_cpu_to_le_16(0xffff);
3184 req.enables = rte_cpu_to_le_32(enables);
3185
3186 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3187
3188 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3189
3190 HWRM_CHECK_RESULT();
3191 HWRM_UNLOCK();
3192
3193 return rc;
3194 }
3195
3196 static void populate_vf_func_cfg_req(struct bnxt *bp,
3197 struct hwrm_func_cfg_input *req,
3198 int num_vfs)
3199 {
3200 req->enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_MTU |
3201 HWRM_FUNC_CFG_INPUT_ENABLES_MRU |
3202 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RSSCOS_CTXS |
3203 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_STAT_CTXS |
3204 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_CMPL_RINGS |
3205 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_TX_RINGS |
3206 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_RX_RINGS |
3207 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_L2_CTXS |
3208 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_VNICS |
3209 HWRM_FUNC_CFG_INPUT_ENABLES_NUM_HW_RING_GRPS);
3210
3211 req->mtu = rte_cpu_to_le_16(bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
3212 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE *
3213 BNXT_NUM_VLANS);
3214 req->mru = rte_cpu_to_le_16(BNXT_VNIC_MRU(bp->eth_dev->data->mtu));
3215 req->num_rsscos_ctxs = rte_cpu_to_le_16(bp->max_rsscos_ctx /
3216 (num_vfs + 1));
3217 req->num_stat_ctxs = rte_cpu_to_le_16(bp->max_stat_ctx / (num_vfs + 1));
3218 req->num_cmpl_rings = rte_cpu_to_le_16(bp->max_cp_rings /
3219 (num_vfs + 1));
3220 req->num_tx_rings = rte_cpu_to_le_16(bp->max_tx_rings / (num_vfs + 1));
3221 req->num_rx_rings = rte_cpu_to_le_16(bp->max_rx_rings / (num_vfs + 1));
3222 req->num_l2_ctxs = rte_cpu_to_le_16(bp->max_l2_ctx / (num_vfs + 1));
3223 /* TODO: For now, do not support VMDq/RFS on VFs. */
3224 req->num_vnics = rte_cpu_to_le_16(1);
3225 req->num_hw_ring_grps = rte_cpu_to_le_16(bp->max_ring_grps /
3226 (num_vfs + 1));
3227 }
3228
3229 static void add_random_mac_if_needed(struct bnxt *bp,
3230 struct hwrm_func_cfg_input *cfg_req,
3231 int vf)
3232 {
3233 struct rte_ether_addr mac;
3234
3235 if (bnxt_hwrm_func_qcfg_vf_default_mac(bp, vf, &mac))
3236 return;
3237
3238 if (memcmp(mac.addr_bytes, "\x00\x00\x00\x00\x00", 6) == 0) {
3239 cfg_req->enables |=
3240 rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3241 rte_eth_random_addr(cfg_req->dflt_mac_addr);
3242 bp->pf->vf_info[vf].random_mac = true;
3243 } else {
3244 memcpy(cfg_req->dflt_mac_addr, mac.addr_bytes,
3245 RTE_ETHER_ADDR_LEN);
3246 }
3247 }
3248
3249 static int reserve_resources_from_vf(struct bnxt *bp,
3250 struct hwrm_func_cfg_input *cfg_req,
3251 int vf)
3252 {
3253 struct hwrm_func_qcaps_input req = {0};
3254 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3255 int rc;
3256
3257 /* Get the actual allocated values now */
3258 HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
3259 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3260 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3261
3262 if (rc) {
3263 PMD_DRV_LOG(ERR, "hwrm_func_qcaps failed rc:%d\n", rc);
3264 copy_func_cfg_to_qcaps(cfg_req, resp);
3265 } else if (resp->error_code) {
3266 rc = rte_le_to_cpu_16(resp->error_code);
3267 PMD_DRV_LOG(ERR, "hwrm_func_qcaps error %d\n", rc);
3268 copy_func_cfg_to_qcaps(cfg_req, resp);
3269 }
3270
3271 bp->max_rsscos_ctx -= rte_le_to_cpu_16(resp->max_rsscos_ctx);
3272 bp->max_stat_ctx -= rte_le_to_cpu_16(resp->max_stat_ctx);
3273 bp->max_cp_rings -= rte_le_to_cpu_16(resp->max_cmpl_rings);
3274 bp->max_tx_rings -= rte_le_to_cpu_16(resp->max_tx_rings);
3275 bp->max_rx_rings -= rte_le_to_cpu_16(resp->max_rx_rings);
3276 bp->max_l2_ctx -= rte_le_to_cpu_16(resp->max_l2_ctxs);
3277 /*
3278 * TODO: While not supporting VMDq with VFs, max_vnics is always
3279 * forced to 1 in this case
3280 */
3281 //bp->max_vnics -= rte_le_to_cpu_16(esp->max_vnics);
3282 bp->max_ring_grps -= rte_le_to_cpu_16(resp->max_hw_ring_grps);
3283
3284 HWRM_UNLOCK();
3285
3286 return 0;
3287 }
3288
3289 int bnxt_hwrm_func_qcfg_current_vf_vlan(struct bnxt *bp, int vf)
3290 {
3291 struct hwrm_func_qcfg_input req = {0};
3292 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3293 int rc;
3294
3295 /* Check for zero MAC address */
3296 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3297 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3298 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3299 HWRM_CHECK_RESULT();
3300 rc = rte_le_to_cpu_16(resp->vlan);
3301
3302 HWRM_UNLOCK();
3303
3304 return rc;
3305 }
3306
3307 static int update_pf_resource_max(struct bnxt *bp)
3308 {
3309 struct hwrm_func_qcfg_input req = {0};
3310 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3311 int rc;
3312
3313 /* And copy the allocated numbers into the pf struct */
3314 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3315 req.fid = rte_cpu_to_le_16(0xffff);
3316 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3317 HWRM_CHECK_RESULT();
3318
3319 /* Only TX ring value reflects actual allocation? TODO */
3320 bp->max_tx_rings = rte_le_to_cpu_16(resp->alloc_tx_rings);
3321 bp->pf->evb_mode = resp->evb_mode;
3322
3323 HWRM_UNLOCK();
3324
3325 return rc;
3326 }
3327
3328 int bnxt_hwrm_allocate_pf_only(struct bnxt *bp)
3329 {
3330 int rc;
3331
3332 if (!BNXT_PF(bp)) {
3333 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3334 return -EINVAL;
3335 }
3336
3337 rc = bnxt_hwrm_func_qcaps(bp);
3338 if (rc)
3339 return rc;
3340
3341 bp->pf->func_cfg_flags &=
3342 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3343 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3344 bp->pf->func_cfg_flags |=
3345 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE;
3346 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3347 rc = __bnxt_hwrm_func_qcaps(bp);
3348 return rc;
3349 }
3350
3351 int bnxt_hwrm_allocate_vfs(struct bnxt *bp, int num_vfs)
3352 {
3353 struct hwrm_func_cfg_input req = {0};
3354 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3355 int i;
3356 size_t sz;
3357 int rc = 0;
3358 size_t req_buf_sz;
3359
3360 if (!BNXT_PF(bp)) {
3361 PMD_DRV_LOG(ERR, "Attempt to allcoate VFs on a VF!\n");
3362 return -EINVAL;
3363 }
3364
3365 rc = bnxt_hwrm_func_qcaps(bp);
3366
3367 if (rc)
3368 return rc;
3369
3370 bp->pf->active_vfs = num_vfs;
3371
3372 /*
3373 * First, configure the PF to only use one TX ring. This ensures that
3374 * there are enough rings for all VFs.
3375 *
3376 * If we don't do this, when we call func_alloc() later, we will lock
3377 * extra rings to the PF that won't be available during func_cfg() of
3378 * the VFs.
3379 *
3380 * This has been fixed with firmware versions above 20.6.54
3381 */
3382 bp->pf->func_cfg_flags &=
3383 ~(HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE |
3384 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_DISABLE);
3385 bp->pf->func_cfg_flags |=
3386 HWRM_FUNC_CFG_INPUT_FLAGS_STD_TX_RING_MODE_ENABLE;
3387 rc = bnxt_hwrm_pf_func_cfg(bp, 1);
3388 if (rc)
3389 return rc;
3390
3391 /*
3392 * Now, create and register a buffer to hold forwarded VF requests
3393 */
3394 req_buf_sz = num_vfs * HWRM_MAX_REQ_LEN;
3395 bp->pf->vf_req_buf = rte_malloc("bnxt_vf_fwd", req_buf_sz,
3396 page_roundup(num_vfs * HWRM_MAX_REQ_LEN));
3397 if (bp->pf->vf_req_buf == NULL) {
3398 rc = -ENOMEM;
3399 goto error_free;
3400 }
3401 for (sz = 0; sz < req_buf_sz; sz += getpagesize())
3402 rte_mem_lock_page(((char *)bp->pf->vf_req_buf) + sz);
3403 for (i = 0; i < num_vfs; i++)
3404 bp->pf->vf_info[i].req_buf = ((char *)bp->pf->vf_req_buf) +
3405 (i * HWRM_MAX_REQ_LEN);
3406
3407 rc = bnxt_hwrm_func_buf_rgtr(bp);
3408 if (rc)
3409 goto error_free;
3410
3411 populate_vf_func_cfg_req(bp, &req, num_vfs);
3412
3413 bp->pf->active_vfs = 0;
3414 for (i = 0; i < num_vfs; i++) {
3415 add_random_mac_if_needed(bp, &req, i);
3416
3417 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3418 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[i].func_cfg_flags);
3419 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[i].fid);
3420 rc = bnxt_hwrm_send_message(bp,
3421 &req,
3422 sizeof(req),
3423 BNXT_USE_CHIMP_MB);
3424
3425 /* Clear enable flag for next pass */
3426 req.enables &= ~rte_cpu_to_le_32(
3427 HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
3428
3429 if (rc || resp->error_code) {
3430 PMD_DRV_LOG(ERR,
3431 "Failed to initizlie VF %d\n", i);
3432 PMD_DRV_LOG(ERR,
3433 "Not all VFs available. (%d, %d)\n",
3434 rc, resp->error_code);
3435 HWRM_UNLOCK();
3436 break;
3437 }
3438
3439 HWRM_UNLOCK();
3440
3441 reserve_resources_from_vf(bp, &req, i);
3442 bp->pf->active_vfs++;
3443 bnxt_hwrm_func_clr_stats(bp, bp->pf->vf_info[i].fid);
3444 }
3445
3446 /*
3447 * Now configure the PF to use "the rest" of the resources
3448 * We're using STD_TX_RING_MODE here though which will limit the TX
3449 * rings. This will allow QoS to function properly. Not setting this
3450 * will cause PF rings to break bandwidth settings.
3451 */
3452 rc = bnxt_hwrm_pf_func_cfg(bp, bp->max_tx_rings);
3453 if (rc)
3454 goto error_free;
3455
3456 rc = update_pf_resource_max(bp);
3457 if (rc)
3458 goto error_free;
3459
3460 return rc;
3461
3462 error_free:
3463 bnxt_hwrm_func_buf_unrgtr(bp);
3464 return rc;
3465 }
3466
3467 int bnxt_hwrm_pf_evb_mode(struct bnxt *bp)
3468 {
3469 struct hwrm_func_cfg_input req = {0};
3470 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3471 int rc;
3472
3473 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3474
3475 req.fid = rte_cpu_to_le_16(0xffff);
3476 req.enables = rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_EVB_MODE);
3477 req.evb_mode = bp->pf->evb_mode;
3478
3479 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3480 HWRM_CHECK_RESULT();
3481 HWRM_UNLOCK();
3482
3483 return rc;
3484 }
3485
3486 int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, uint16_t port,
3487 uint8_t tunnel_type)
3488 {
3489 struct hwrm_tunnel_dst_port_alloc_input req = {0};
3490 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3491 int rc = 0;
3492
3493 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_ALLOC, BNXT_USE_CHIMP_MB);
3494 req.tunnel_type = tunnel_type;
3495 req.tunnel_dst_port_val = port;
3496 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3497 HWRM_CHECK_RESULT();
3498
3499 switch (tunnel_type) {
3500 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN:
3501 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3502 bp->vxlan_port = port;
3503 break;
3504 case HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE:
3505 bp->geneve_fw_dst_port_id = resp->tunnel_dst_port_id;
3506 bp->geneve_port = port;
3507 break;
3508 default:
3509 break;
3510 }
3511
3512 HWRM_UNLOCK();
3513
3514 return rc;
3515 }
3516
3517 int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, uint16_t port,
3518 uint8_t tunnel_type)
3519 {
3520 struct hwrm_tunnel_dst_port_free_input req = {0};
3521 struct hwrm_tunnel_dst_port_free_output *resp = bp->hwrm_cmd_resp_addr;
3522 int rc = 0;
3523
3524 HWRM_PREP(&req, HWRM_TUNNEL_DST_PORT_FREE, BNXT_USE_CHIMP_MB);
3525
3526 req.tunnel_type = tunnel_type;
3527 req.tunnel_dst_port_id = rte_cpu_to_be_16(port);
3528 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3529
3530 HWRM_CHECK_RESULT();
3531 HWRM_UNLOCK();
3532
3533 return rc;
3534 }
3535
3536 int bnxt_hwrm_func_cfg_vf_set_flags(struct bnxt *bp, uint16_t vf,
3537 uint32_t flags)
3538 {
3539 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3540 struct hwrm_func_cfg_input req = {0};
3541 int rc;
3542
3543 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3544
3545 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3546 req.flags = rte_cpu_to_le_32(flags);
3547 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3548
3549 HWRM_CHECK_RESULT();
3550 HWRM_UNLOCK();
3551
3552 return rc;
3553 }
3554
3555 void vf_vnic_set_rxmask_cb(struct bnxt_vnic_info *vnic, void *flagp)
3556 {
3557 uint32_t *flag = flagp;
3558
3559 vnic->flags = *flag;
3560 }
3561
3562 int bnxt_set_rx_mask_no_vlan(struct bnxt *bp, struct bnxt_vnic_info *vnic)
3563 {
3564 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
3565 }
3566
3567 int bnxt_hwrm_func_buf_rgtr(struct bnxt *bp)
3568 {
3569 int rc = 0;
3570 struct hwrm_func_buf_rgtr_input req = {.req_type = 0 };
3571 struct hwrm_func_buf_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
3572
3573 HWRM_PREP(&req, HWRM_FUNC_BUF_RGTR, BNXT_USE_CHIMP_MB);
3574
3575 req.req_buf_num_pages = rte_cpu_to_le_16(1);
3576 req.req_buf_page_size = rte_cpu_to_le_16(
3577 page_getenum(bp->pf->active_vfs * HWRM_MAX_REQ_LEN));
3578 req.req_buf_len = rte_cpu_to_le_16(HWRM_MAX_REQ_LEN);
3579 req.req_buf_page_addr0 =
3580 rte_cpu_to_le_64(rte_malloc_virt2iova(bp->pf->vf_req_buf));
3581 if (req.req_buf_page_addr0 == RTE_BAD_IOVA) {
3582 PMD_DRV_LOG(ERR,
3583 "unable to map buffer address to physical memory\n");
3584 return -ENOMEM;
3585 }
3586
3587 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3588
3589 HWRM_CHECK_RESULT();
3590 HWRM_UNLOCK();
3591
3592 return rc;
3593 }
3594
3595 int bnxt_hwrm_func_buf_unrgtr(struct bnxt *bp)
3596 {
3597 int rc = 0;
3598 struct hwrm_func_buf_unrgtr_input req = {.req_type = 0 };
3599 struct hwrm_func_buf_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
3600
3601 if (!(BNXT_PF(bp) && bp->pdev->max_vfs))
3602 return 0;
3603
3604 HWRM_PREP(&req, HWRM_FUNC_BUF_UNRGTR, BNXT_USE_CHIMP_MB);
3605
3606 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3607
3608 HWRM_CHECK_RESULT();
3609 HWRM_UNLOCK();
3610
3611 return rc;
3612 }
3613
3614 int bnxt_hwrm_func_cfg_def_cp(struct bnxt *bp)
3615 {
3616 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3617 struct hwrm_func_cfg_input req = {0};
3618 int rc;
3619
3620 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3621
3622 req.fid = rte_cpu_to_le_16(0xffff);
3623 req.flags = rte_cpu_to_le_32(bp->pf->func_cfg_flags);
3624 req.enables = rte_cpu_to_le_32(
3625 HWRM_FUNC_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3626 req.async_event_cr = rte_cpu_to_le_16(
3627 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3628 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3629
3630 HWRM_CHECK_RESULT();
3631 HWRM_UNLOCK();
3632
3633 return rc;
3634 }
3635
3636 int bnxt_hwrm_vf_func_cfg_def_cp(struct bnxt *bp)
3637 {
3638 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3639 struct hwrm_func_vf_cfg_input req = {0};
3640 int rc;
3641
3642 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
3643
3644 req.enables = rte_cpu_to_le_32(
3645 HWRM_FUNC_VF_CFG_INPUT_ENABLES_ASYNC_EVENT_CR);
3646 req.async_event_cr = rte_cpu_to_le_16(
3647 bp->async_cp_ring->cp_ring_struct->fw_ring_id);
3648 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3649
3650 HWRM_CHECK_RESULT();
3651 HWRM_UNLOCK();
3652
3653 return rc;
3654 }
3655
3656 int bnxt_hwrm_set_default_vlan(struct bnxt *bp, int vf, uint8_t is_vf)
3657 {
3658 struct hwrm_func_cfg_input req = {0};
3659 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3660 uint16_t dflt_vlan, fid;
3661 uint32_t func_cfg_flags;
3662 int rc = 0;
3663
3664 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3665
3666 if (is_vf) {
3667 dflt_vlan = bp->pf->vf_info[vf].dflt_vlan;
3668 fid = bp->pf->vf_info[vf].fid;
3669 func_cfg_flags = bp->pf->vf_info[vf].func_cfg_flags;
3670 } else {
3671 fid = rte_cpu_to_le_16(0xffff);
3672 func_cfg_flags = bp->pf->func_cfg_flags;
3673 dflt_vlan = bp->vlan;
3674 }
3675
3676 req.flags = rte_cpu_to_le_32(func_cfg_flags);
3677 req.fid = rte_cpu_to_le_16(fid);
3678 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3679 req.dflt_vlan = rte_cpu_to_le_16(dflt_vlan);
3680
3681 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3682
3683 HWRM_CHECK_RESULT();
3684 HWRM_UNLOCK();
3685
3686 return rc;
3687 }
3688
3689 int bnxt_hwrm_func_bw_cfg(struct bnxt *bp, uint16_t vf,
3690 uint16_t max_bw, uint16_t enables)
3691 {
3692 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3693 struct hwrm_func_cfg_input req = {0};
3694 int rc;
3695
3696 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3697
3698 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3699 req.enables |= rte_cpu_to_le_32(enables);
3700 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3701 req.max_bw = rte_cpu_to_le_32(max_bw);
3702 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3703
3704 HWRM_CHECK_RESULT();
3705 HWRM_UNLOCK();
3706
3707 return rc;
3708 }
3709
3710 int bnxt_hwrm_set_vf_vlan(struct bnxt *bp, int vf)
3711 {
3712 struct hwrm_func_cfg_input req = {0};
3713 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3714 int rc = 0;
3715
3716 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
3717
3718 req.flags = rte_cpu_to_le_32(bp->pf->vf_info[vf].func_cfg_flags);
3719 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3720 req.enables |= rte_cpu_to_le_32(HWRM_FUNC_CFG_INPUT_ENABLES_DFLT_VLAN);
3721 req.dflt_vlan = rte_cpu_to_le_16(bp->pf->vf_info[vf].dflt_vlan);
3722
3723 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3724
3725 HWRM_CHECK_RESULT();
3726 HWRM_UNLOCK();
3727
3728 return rc;
3729 }
3730
3731 int bnxt_hwrm_set_async_event_cr(struct bnxt *bp)
3732 {
3733 int rc;
3734
3735 if (BNXT_PF(bp))
3736 rc = bnxt_hwrm_func_cfg_def_cp(bp);
3737 else
3738 rc = bnxt_hwrm_vf_func_cfg_def_cp(bp);
3739
3740 return rc;
3741 }
3742
3743 int bnxt_hwrm_reject_fwd_resp(struct bnxt *bp, uint16_t target_id,
3744 void *encaped, size_t ec_size)
3745 {
3746 int rc = 0;
3747 struct hwrm_reject_fwd_resp_input req = {.req_type = 0};
3748 struct hwrm_reject_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3749
3750 if (ec_size > sizeof(req.encap_request))
3751 return -1;
3752
3753 HWRM_PREP(&req, HWRM_REJECT_FWD_RESP, BNXT_USE_CHIMP_MB);
3754
3755 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3756 memcpy(req.encap_request, encaped, ec_size);
3757
3758 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3759
3760 HWRM_CHECK_RESULT();
3761 HWRM_UNLOCK();
3762
3763 return rc;
3764 }
3765
3766 int bnxt_hwrm_func_qcfg_vf_default_mac(struct bnxt *bp, uint16_t vf,
3767 struct rte_ether_addr *mac)
3768 {
3769 struct hwrm_func_qcfg_input req = {0};
3770 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3771 int rc;
3772
3773 HWRM_PREP(&req, HWRM_FUNC_QCFG, BNXT_USE_CHIMP_MB);
3774
3775 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
3776 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3777
3778 HWRM_CHECK_RESULT();
3779
3780 memcpy(mac->addr_bytes, resp->mac_address, RTE_ETHER_ADDR_LEN);
3781
3782 HWRM_UNLOCK();
3783
3784 return rc;
3785 }
3786
3787 int bnxt_hwrm_exec_fwd_resp(struct bnxt *bp, uint16_t target_id,
3788 void *encaped, size_t ec_size)
3789 {
3790 int rc = 0;
3791 struct hwrm_exec_fwd_resp_input req = {.req_type = 0};
3792 struct hwrm_exec_fwd_resp_output *resp = bp->hwrm_cmd_resp_addr;
3793
3794 if (ec_size > sizeof(req.encap_request))
3795 return -1;
3796
3797 HWRM_PREP(&req, HWRM_EXEC_FWD_RESP, BNXT_USE_CHIMP_MB);
3798
3799 req.encap_resp_target_id = rte_cpu_to_le_16(target_id);
3800 memcpy(req.encap_request, encaped, ec_size);
3801
3802 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3803
3804 HWRM_CHECK_RESULT();
3805 HWRM_UNLOCK();
3806
3807 return rc;
3808 }
3809
3810 int bnxt_hwrm_ctx_qstats(struct bnxt *bp, uint32_t cid, int idx,
3811 struct rte_eth_stats *stats, uint8_t rx)
3812 {
3813 int rc = 0;
3814 struct hwrm_stat_ctx_query_input req = {.req_type = 0};
3815 struct hwrm_stat_ctx_query_output *resp = bp->hwrm_cmd_resp_addr;
3816
3817 HWRM_PREP(&req, HWRM_STAT_CTX_QUERY, BNXT_USE_CHIMP_MB);
3818
3819 req.stat_ctx_id = rte_cpu_to_le_32(cid);
3820
3821 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3822
3823 HWRM_CHECK_RESULT();
3824
3825 if (rx) {
3826 stats->q_ipackets[idx] = rte_le_to_cpu_64(resp->rx_ucast_pkts);
3827 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_mcast_pkts);
3828 stats->q_ipackets[idx] += rte_le_to_cpu_64(resp->rx_bcast_pkts);
3829 stats->q_ibytes[idx] = rte_le_to_cpu_64(resp->rx_ucast_bytes);
3830 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_mcast_bytes);
3831 stats->q_ibytes[idx] += rte_le_to_cpu_64(resp->rx_bcast_bytes);
3832 stats->q_errors[idx] = rte_le_to_cpu_64(resp->rx_err_pkts);
3833 stats->q_errors[idx] += rte_le_to_cpu_64(resp->rx_drop_pkts);
3834 } else {
3835 stats->q_opackets[idx] = rte_le_to_cpu_64(resp->tx_ucast_pkts);
3836 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_mcast_pkts);
3837 stats->q_opackets[idx] += rte_le_to_cpu_64(resp->tx_bcast_pkts);
3838 stats->q_obytes[idx] = rte_le_to_cpu_64(resp->tx_ucast_bytes);
3839 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_mcast_bytes);
3840 stats->q_obytes[idx] += rte_le_to_cpu_64(resp->tx_bcast_bytes);
3841 }
3842
3843 HWRM_UNLOCK();
3844
3845 return rc;
3846 }
3847
3848 int bnxt_hwrm_port_qstats(struct bnxt *bp)
3849 {
3850 struct hwrm_port_qstats_input req = {0};
3851 struct hwrm_port_qstats_output *resp = bp->hwrm_cmd_resp_addr;
3852 struct bnxt_pf_info *pf = bp->pf;
3853 int rc;
3854
3855 HWRM_PREP(&req, HWRM_PORT_QSTATS, BNXT_USE_CHIMP_MB);
3856
3857 req.port_id = rte_cpu_to_le_16(pf->port_id);
3858 req.tx_stat_host_addr = rte_cpu_to_le_64(bp->hw_tx_port_stats_map);
3859 req.rx_stat_host_addr = rte_cpu_to_le_64(bp->hw_rx_port_stats_map);
3860 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3861
3862 HWRM_CHECK_RESULT();
3863 HWRM_UNLOCK();
3864
3865 return rc;
3866 }
3867
3868 int bnxt_hwrm_port_clr_stats(struct bnxt *bp)
3869 {
3870 struct hwrm_port_clr_stats_input req = {0};
3871 struct hwrm_port_clr_stats_output *resp = bp->hwrm_cmd_resp_addr;
3872 struct bnxt_pf_info *pf = bp->pf;
3873 int rc;
3874
3875 /* Not allowed on NS2 device, NPAR, MultiHost, VF */
3876 if (!(bp->flags & BNXT_FLAG_PORT_STATS) || BNXT_VF(bp) ||
3877 BNXT_NPAR(bp) || BNXT_MH(bp) || BNXT_TOTAL_VFS(bp))
3878 return 0;
3879
3880 HWRM_PREP(&req, HWRM_PORT_CLR_STATS, BNXT_USE_CHIMP_MB);
3881
3882 req.port_id = rte_cpu_to_le_16(pf->port_id);
3883 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3884
3885 HWRM_CHECK_RESULT();
3886 HWRM_UNLOCK();
3887
3888 return rc;
3889 }
3890
3891 int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
3892 {
3893 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3894 struct hwrm_port_led_qcaps_input req = {0};
3895 int rc;
3896
3897 if (BNXT_VF(bp))
3898 return 0;
3899
3900 HWRM_PREP(&req, HWRM_PORT_LED_QCAPS, BNXT_USE_CHIMP_MB);
3901 req.port_id = bp->pf->port_id;
3902 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3903
3904 HWRM_CHECK_RESULT();
3905
3906 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
3907 unsigned int i;
3908
3909 bp->leds->num_leds = resp->num_leds;
3910 memcpy(bp->leds, &resp->led0_id,
3911 sizeof(bp->leds[0]) * bp->leds->num_leds);
3912 for (i = 0; i < bp->leds->num_leds; i++) {
3913 struct bnxt_led_info *led = &bp->leds[i];
3914
3915 uint16_t caps = led->led_state_caps;
3916
3917 if (!led->led_group_id ||
3918 !BNXT_LED_ALT_BLINK_CAP(caps)) {
3919 bp->leds->num_leds = 0;
3920 break;
3921 }
3922 }
3923 }
3924
3925 HWRM_UNLOCK();
3926
3927 return rc;
3928 }
3929
3930 int bnxt_hwrm_port_led_cfg(struct bnxt *bp, bool led_on)
3931 {
3932 struct hwrm_port_led_cfg_output *resp = bp->hwrm_cmd_resp_addr;
3933 struct hwrm_port_led_cfg_input req = {0};
3934 struct bnxt_led_cfg *led_cfg;
3935 uint8_t led_state = HWRM_PORT_LED_QCFG_OUTPUT_LED0_STATE_DEFAULT;
3936 uint16_t duration = 0;
3937 int rc, i;
3938
3939 if (!bp->leds->num_leds || BNXT_VF(bp))
3940 return -EOPNOTSUPP;
3941
3942 HWRM_PREP(&req, HWRM_PORT_LED_CFG, BNXT_USE_CHIMP_MB);
3943
3944 if (led_on) {
3945 led_state = HWRM_PORT_LED_CFG_INPUT_LED0_STATE_BLINKALT;
3946 duration = rte_cpu_to_le_16(500);
3947 }
3948 req.port_id = bp->pf->port_id;
3949 req.num_leds = bp->leds->num_leds;
3950 led_cfg = (struct bnxt_led_cfg *)&req.led0_id;
3951 for (i = 0; i < bp->leds->num_leds; i++, led_cfg++) {
3952 req.enables |= BNXT_LED_DFLT_ENABLES(i);
3953 led_cfg->led_id = bp->leds[i].led_id;
3954 led_cfg->led_state = led_state;
3955 led_cfg->led_blink_on = duration;
3956 led_cfg->led_blink_off = duration;
3957 led_cfg->led_group_id = bp->leds[i].led_group_id;
3958 }
3959
3960 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3961
3962 HWRM_CHECK_RESULT();
3963 HWRM_UNLOCK();
3964
3965 return rc;
3966 }
3967
3968 int bnxt_hwrm_nvm_get_dir_info(struct bnxt *bp, uint32_t *entries,
3969 uint32_t *length)
3970 {
3971 int rc;
3972 struct hwrm_nvm_get_dir_info_input req = {0};
3973 struct hwrm_nvm_get_dir_info_output *resp = bp->hwrm_cmd_resp_addr;
3974
3975 HWRM_PREP(&req, HWRM_NVM_GET_DIR_INFO, BNXT_USE_CHIMP_MB);
3976
3977 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
3978
3979 HWRM_CHECK_RESULT();
3980
3981 *entries = rte_le_to_cpu_32(resp->entries);
3982 *length = rte_le_to_cpu_32(resp->entry_length);
3983
3984 HWRM_UNLOCK();
3985 return rc;
3986 }
3987
3988 int bnxt_get_nvram_directory(struct bnxt *bp, uint32_t len, uint8_t *data)
3989 {
3990 int rc;
3991 uint32_t dir_entries;
3992 uint32_t entry_length;
3993 uint8_t *buf;
3994 size_t buflen;
3995 rte_iova_t dma_handle;
3996 struct hwrm_nvm_get_dir_entries_input req = {0};
3997 struct hwrm_nvm_get_dir_entries_output *resp = bp->hwrm_cmd_resp_addr;
3998
3999 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length);
4000 if (rc != 0)
4001 return rc;
4002
4003 *data++ = dir_entries;
4004 *data++ = entry_length;
4005 len -= 2;
4006 memset(data, 0xff, len);
4007
4008 buflen = dir_entries * entry_length;
4009 buf = rte_malloc("nvm_dir", buflen, 0);
4010 if (buf == NULL)
4011 return -ENOMEM;
4012 dma_handle = rte_malloc_virt2iova(buf);
4013 if (dma_handle == RTE_BAD_IOVA) {
4014 PMD_DRV_LOG(ERR,
4015 "unable to map response address to physical memory\n");
4016 return -ENOMEM;
4017 }
4018 HWRM_PREP(&req, HWRM_NVM_GET_DIR_ENTRIES, BNXT_USE_CHIMP_MB);
4019 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4020 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4021
4022 if (rc == 0)
4023 memcpy(data, buf, len > buflen ? buflen : len);
4024
4025 rte_free(buf);
4026 HWRM_CHECK_RESULT();
4027 HWRM_UNLOCK();
4028
4029 return rc;
4030 }
4031
4032 int bnxt_hwrm_get_nvram_item(struct bnxt *bp, uint32_t index,
4033 uint32_t offset, uint32_t length,
4034 uint8_t *data)
4035 {
4036 int rc;
4037 uint8_t *buf;
4038 rte_iova_t dma_handle;
4039 struct hwrm_nvm_read_input req = {0};
4040 struct hwrm_nvm_read_output *resp = bp->hwrm_cmd_resp_addr;
4041
4042 buf = rte_malloc("nvm_item", length, 0);
4043 if (!buf)
4044 return -ENOMEM;
4045
4046 dma_handle = rte_malloc_virt2iova(buf);
4047 if (dma_handle == RTE_BAD_IOVA) {
4048 PMD_DRV_LOG(ERR,
4049 "unable to map response address to physical memory\n");
4050 return -ENOMEM;
4051 }
4052 HWRM_PREP(&req, HWRM_NVM_READ, BNXT_USE_CHIMP_MB);
4053 req.host_dest_addr = rte_cpu_to_le_64(dma_handle);
4054 req.dir_idx = rte_cpu_to_le_16(index);
4055 req.offset = rte_cpu_to_le_32(offset);
4056 req.len = rte_cpu_to_le_32(length);
4057 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4058 if (rc == 0)
4059 memcpy(data, buf, length);
4060
4061 rte_free(buf);
4062 HWRM_CHECK_RESULT();
4063 HWRM_UNLOCK();
4064
4065 return rc;
4066 }
4067
4068 int bnxt_hwrm_erase_nvram_directory(struct bnxt *bp, uint8_t index)
4069 {
4070 int rc;
4071 struct hwrm_nvm_erase_dir_entry_input req = {0};
4072 struct hwrm_nvm_erase_dir_entry_output *resp = bp->hwrm_cmd_resp_addr;
4073
4074 HWRM_PREP(&req, HWRM_NVM_ERASE_DIR_ENTRY, BNXT_USE_CHIMP_MB);
4075 req.dir_idx = rte_cpu_to_le_16(index);
4076 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4077 HWRM_CHECK_RESULT();
4078 HWRM_UNLOCK();
4079
4080 return rc;
4081 }
4082
4083
4084 int bnxt_hwrm_flash_nvram(struct bnxt *bp, uint16_t dir_type,
4085 uint16_t dir_ordinal, uint16_t dir_ext,
4086 uint16_t dir_attr, const uint8_t *data,
4087 size_t data_len)
4088 {
4089 int rc;
4090 struct hwrm_nvm_write_input req = {0};
4091 struct hwrm_nvm_write_output *resp = bp->hwrm_cmd_resp_addr;
4092 rte_iova_t dma_handle;
4093 uint8_t *buf;
4094
4095 buf = rte_malloc("nvm_write", data_len, 0);
4096 if (!buf)
4097 return -ENOMEM;
4098
4099 dma_handle = rte_malloc_virt2iova(buf);
4100 if (dma_handle == RTE_BAD_IOVA) {
4101 PMD_DRV_LOG(ERR,
4102 "unable to map response address to physical memory\n");
4103 return -ENOMEM;
4104 }
4105 memcpy(buf, data, data_len);
4106
4107 HWRM_PREP(&req, HWRM_NVM_WRITE, BNXT_USE_CHIMP_MB);
4108
4109 req.dir_type = rte_cpu_to_le_16(dir_type);
4110 req.dir_ordinal = rte_cpu_to_le_16(dir_ordinal);
4111 req.dir_ext = rte_cpu_to_le_16(dir_ext);
4112 req.dir_attr = rte_cpu_to_le_16(dir_attr);
4113 req.dir_data_length = rte_cpu_to_le_32(data_len);
4114 req.host_src_addr = rte_cpu_to_le_64(dma_handle);
4115
4116 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4117
4118 rte_free(buf);
4119 HWRM_CHECK_RESULT();
4120 HWRM_UNLOCK();
4121
4122 return rc;
4123 }
4124
4125 static void
4126 bnxt_vnic_count(struct bnxt_vnic_info *vnic __rte_unused, void *cbdata)
4127 {
4128 uint32_t *count = cbdata;
4129
4130 *count = *count + 1;
4131 }
4132
4133 static int bnxt_vnic_count_hwrm_stub(struct bnxt *bp __rte_unused,
4134 struct bnxt_vnic_info *vnic __rte_unused)
4135 {
4136 return 0;
4137 }
4138
4139 int bnxt_vf_vnic_count(struct bnxt *bp, uint16_t vf)
4140 {
4141 uint32_t count = 0;
4142
4143 bnxt_hwrm_func_vf_vnic_query_and_config(bp, vf, bnxt_vnic_count,
4144 &count, bnxt_vnic_count_hwrm_stub);
4145
4146 return count;
4147 }
4148
4149 static int bnxt_hwrm_func_vf_vnic_query(struct bnxt *bp, uint16_t vf,
4150 uint16_t *vnic_ids)
4151 {
4152 struct hwrm_func_vf_vnic_ids_query_input req = {0};
4153 struct hwrm_func_vf_vnic_ids_query_output *resp =
4154 bp->hwrm_cmd_resp_addr;
4155 int rc;
4156
4157 /* First query all VNIC ids */
4158 HWRM_PREP(&req, HWRM_FUNC_VF_VNIC_IDS_QUERY, BNXT_USE_CHIMP_MB);
4159
4160 req.vf_id = rte_cpu_to_le_16(bp->pf->first_vf_id + vf);
4161 req.max_vnic_id_cnt = rte_cpu_to_le_32(bp->pf->total_vnics);
4162 req.vnic_id_tbl_addr = rte_cpu_to_le_64(rte_malloc_virt2iova(vnic_ids));
4163
4164 if (req.vnic_id_tbl_addr == RTE_BAD_IOVA) {
4165 HWRM_UNLOCK();
4166 PMD_DRV_LOG(ERR,
4167 "unable to map VNIC ID table address to physical memory\n");
4168 return -ENOMEM;
4169 }
4170 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4171 HWRM_CHECK_RESULT();
4172 rc = rte_le_to_cpu_32(resp->vnic_id_cnt);
4173
4174 HWRM_UNLOCK();
4175
4176 return rc;
4177 }
4178
4179 /*
4180 * This function queries the VNIC IDs for a specified VF. It then calls
4181 * the vnic_cb to update the necessary field in vnic_info with cbdata.
4182 * Then it calls the hwrm_cb function to program this new vnic configuration.
4183 */
4184 int bnxt_hwrm_func_vf_vnic_query_and_config(struct bnxt *bp, uint16_t vf,
4185 void (*vnic_cb)(struct bnxt_vnic_info *, void *), void *cbdata,
4186 int (*hwrm_cb)(struct bnxt *bp, struct bnxt_vnic_info *vnic))
4187 {
4188 struct bnxt_vnic_info vnic;
4189 int rc = 0;
4190 int i, num_vnic_ids;
4191 uint16_t *vnic_ids;
4192 size_t vnic_id_sz;
4193 size_t sz;
4194
4195 /* First query all VNIC ids */
4196 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4197 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4198 RTE_CACHE_LINE_SIZE);
4199 if (vnic_ids == NULL)
4200 return -ENOMEM;
4201
4202 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4203 rte_mem_lock_page(((char *)vnic_ids) + sz);
4204
4205 num_vnic_ids = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4206
4207 if (num_vnic_ids < 0)
4208 return num_vnic_ids;
4209
4210 /* Retrieve VNIC, update bd_stall then update */
4211
4212 for (i = 0; i < num_vnic_ids; i++) {
4213 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4214 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4215 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic, bp->pf->first_vf_id + vf);
4216 if (rc)
4217 break;
4218 if (vnic.mru <= 4) /* Indicates unallocated */
4219 continue;
4220
4221 vnic_cb(&vnic, cbdata);
4222
4223 rc = hwrm_cb(bp, &vnic);
4224 if (rc)
4225 break;
4226 }
4227
4228 rte_free(vnic_ids);
4229
4230 return rc;
4231 }
4232
4233 int bnxt_hwrm_func_cfg_vf_set_vlan_anti_spoof(struct bnxt *bp, uint16_t vf,
4234 bool on)
4235 {
4236 struct hwrm_func_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4237 struct hwrm_func_cfg_input req = {0};
4238 int rc;
4239
4240 HWRM_PREP(&req, HWRM_FUNC_CFG, BNXT_USE_CHIMP_MB);
4241
4242 req.fid = rte_cpu_to_le_16(bp->pf->vf_info[vf].fid);
4243 req.enables |= rte_cpu_to_le_32(
4244 HWRM_FUNC_CFG_INPUT_ENABLES_VLAN_ANTISPOOF_MODE);
4245 req.vlan_antispoof_mode = on ?
4246 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN :
4247 HWRM_FUNC_CFG_INPUT_VLAN_ANTISPOOF_MODE_NOCHECK;
4248 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4249
4250 HWRM_CHECK_RESULT();
4251 HWRM_UNLOCK();
4252
4253 return rc;
4254 }
4255
4256 int bnxt_hwrm_func_qcfg_vf_dflt_vnic_id(struct bnxt *bp, int vf)
4257 {
4258 struct bnxt_vnic_info vnic;
4259 uint16_t *vnic_ids;
4260 size_t vnic_id_sz;
4261 int num_vnic_ids, i;
4262 size_t sz;
4263 int rc;
4264
4265 vnic_id_sz = bp->pf->total_vnics * sizeof(*vnic_ids);
4266 vnic_ids = rte_malloc("bnxt_hwrm_vf_vnic_ids_query", vnic_id_sz,
4267 RTE_CACHE_LINE_SIZE);
4268 if (vnic_ids == NULL)
4269 return -ENOMEM;
4270
4271 for (sz = 0; sz < vnic_id_sz; sz += getpagesize())
4272 rte_mem_lock_page(((char *)vnic_ids) + sz);
4273
4274 rc = bnxt_hwrm_func_vf_vnic_query(bp, vf, vnic_ids);
4275 if (rc <= 0)
4276 goto exit;
4277 num_vnic_ids = rc;
4278
4279 /*
4280 * Loop through to find the default VNIC ID.
4281 * TODO: The easier way would be to obtain the resp->dflt_vnic_id
4282 * by sending the hwrm_func_qcfg command to the firmware.
4283 */
4284 for (i = 0; i < num_vnic_ids; i++) {
4285 memset(&vnic, 0, sizeof(struct bnxt_vnic_info));
4286 vnic.fw_vnic_id = rte_le_to_cpu_16(vnic_ids[i]);
4287 rc = bnxt_hwrm_vnic_qcfg(bp, &vnic,
4288 bp->pf->first_vf_id + vf);
4289 if (rc)
4290 goto exit;
4291 if (vnic.func_default) {
4292 rte_free(vnic_ids);
4293 return vnic.fw_vnic_id;
4294 }
4295 }
4296 /* Could not find a default VNIC. */
4297 PMD_DRV_LOG(ERR, "No default VNIC\n");
4298 exit:
4299 rte_free(vnic_ids);
4300 return rc;
4301 }
4302
4303 int bnxt_hwrm_set_em_filter(struct bnxt *bp,
4304 uint16_t dst_id,
4305 struct bnxt_filter_info *filter)
4306 {
4307 int rc = 0;
4308 struct hwrm_cfa_em_flow_alloc_input req = {.req_type = 0 };
4309 struct hwrm_cfa_em_flow_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4310 uint32_t enables = 0;
4311
4312 if (filter->fw_em_filter_id != UINT64_MAX)
4313 bnxt_hwrm_clear_em_filter(bp, filter);
4314
4315 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_ALLOC, BNXT_USE_KONG(bp));
4316
4317 req.flags = rte_cpu_to_le_32(filter->flags);
4318
4319 enables = filter->enables |
4320 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_ID;
4321 req.dst_id = rte_cpu_to_le_16(dst_id);
4322
4323 if (filter->ip_addr_type) {
4324 req.ip_addr_type = filter->ip_addr_type;
4325 enables |= HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4326 }
4327 if (enables &
4328 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4329 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4330 if (enables &
4331 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4332 memcpy(req.src_macaddr, filter->src_macaddr,
4333 RTE_ETHER_ADDR_LEN);
4334 if (enables &
4335 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_MACADDR)
4336 memcpy(req.dst_macaddr, filter->dst_macaddr,
4337 RTE_ETHER_ADDR_LEN);
4338 if (enables &
4339 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_OVLAN_VID)
4340 req.ovlan_vid = filter->l2_ovlan;
4341 if (enables &
4342 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IVLAN_VID)
4343 req.ivlan_vid = filter->l2_ivlan;
4344 if (enables &
4345 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_ETHERTYPE)
4346 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4347 if (enables &
4348 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4349 req.ip_protocol = filter->ip_protocol;
4350 if (enables &
4351 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4352 req.src_ipaddr[0] = rte_cpu_to_be_32(filter->src_ipaddr[0]);
4353 if (enables &
4354 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_IPADDR)
4355 req.dst_ipaddr[0] = rte_cpu_to_be_32(filter->dst_ipaddr[0]);
4356 if (enables &
4357 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_SRC_PORT)
4358 req.src_port = rte_cpu_to_be_16(filter->src_port);
4359 if (enables &
4360 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_DST_PORT)
4361 req.dst_port = rte_cpu_to_be_16(filter->dst_port);
4362 if (enables &
4363 HWRM_CFA_EM_FLOW_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4364 req.mirror_vnic_id = filter->mirror_vnic_id;
4365
4366 req.enables = rte_cpu_to_le_32(enables);
4367
4368 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4369
4370 HWRM_CHECK_RESULT();
4371
4372 filter->fw_em_filter_id = rte_le_to_cpu_64(resp->em_filter_id);
4373 HWRM_UNLOCK();
4374
4375 return rc;
4376 }
4377
4378 int bnxt_hwrm_clear_em_filter(struct bnxt *bp, struct bnxt_filter_info *filter)
4379 {
4380 int rc = 0;
4381 struct hwrm_cfa_em_flow_free_input req = {.req_type = 0 };
4382 struct hwrm_cfa_em_flow_free_output *resp = bp->hwrm_cmd_resp_addr;
4383
4384 if (filter->fw_em_filter_id == UINT64_MAX)
4385 return 0;
4386
4387 HWRM_PREP(&req, HWRM_CFA_EM_FLOW_FREE, BNXT_USE_KONG(bp));
4388
4389 req.em_filter_id = rte_cpu_to_le_64(filter->fw_em_filter_id);
4390
4391 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
4392
4393 HWRM_CHECK_RESULT();
4394 HWRM_UNLOCK();
4395
4396 filter->fw_em_filter_id = UINT64_MAX;
4397 filter->fw_l2_filter_id = UINT64_MAX;
4398
4399 return 0;
4400 }
4401
4402 int bnxt_hwrm_set_ntuple_filter(struct bnxt *bp,
4403 uint16_t dst_id,
4404 struct bnxt_filter_info *filter)
4405 {
4406 int rc = 0;
4407 struct hwrm_cfa_ntuple_filter_alloc_input req = {.req_type = 0 };
4408 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
4409 bp->hwrm_cmd_resp_addr;
4410 uint32_t enables = 0;
4411
4412 if (filter->fw_ntuple_filter_id != UINT64_MAX)
4413 bnxt_hwrm_clear_ntuple_filter(bp, filter);
4414
4415 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
4416
4417 req.flags = rte_cpu_to_le_32(filter->flags);
4418
4419 enables = filter->enables |
4420 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
4421 req.dst_id = rte_cpu_to_le_16(dst_id);
4422
4423 if (filter->ip_addr_type) {
4424 req.ip_addr_type = filter->ip_addr_type;
4425 enables |=
4426 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE;
4427 }
4428 if (enables &
4429 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID)
4430 req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
4431 if (enables &
4432 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR)
4433 memcpy(req.src_macaddr, filter->src_macaddr,
4434 RTE_ETHER_ADDR_LEN);
4435 if (enables &
4436 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE)
4437 req.ethertype = rte_cpu_to_be_16(filter->ethertype);
4438 if (enables &
4439 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL)
4440 req.ip_protocol = filter->ip_protocol;
4441 if (enables &
4442 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR)
4443 req.src_ipaddr[0] = rte_cpu_to_le_32(filter->src_ipaddr[0]);
4444 if (enables &
4445 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR_MASK)
4446 req.src_ipaddr_mask[0] =
4447 rte_cpu_to_le_32(filter->src_ipaddr_mask[0]);
4448 if (enables &
4449 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR)
4450 req.dst_ipaddr[0] = rte_cpu_to_le_32(filter->dst_ipaddr[0]);
4451 if (enables &
4452 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR_MASK)
4453 req.dst_ipaddr_mask[0] =
4454 rte_cpu_to_be_32(filter->dst_ipaddr_mask[0]);
4455 if (enables &
4456 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT)
4457 req.src_port = rte_cpu_to_le_16(filter->src_port);
4458 if (enables &
4459 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT_MASK)
4460 req.src_port_mask = rte_cpu_to_le_16(filter->src_port_mask);
4461 if (enables &
4462 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT)
4463 req.dst_port = rte_cpu_to_le_16(filter->dst_port);
4464 if (enables &
4465 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_PORT_MASK)
4466 req.dst_port_mask = rte_cpu_to_le_16(filter->dst_port_mask);
4467 if (enables &
4468 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID)
4469 req.mirror_vnic_id = filter->mirror_vnic_id;
4470
4471 req.enables = rte_cpu_to_le_32(enables);
4472
4473 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4474
4475 HWRM_CHECK_RESULT();
4476
4477 filter->fw_ntuple_filter_id = rte_le_to_cpu_64(resp->ntuple_filter_id);
4478 filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
4479 HWRM_UNLOCK();
4480
4481 return rc;
4482 }
4483
4484 int bnxt_hwrm_clear_ntuple_filter(struct bnxt *bp,
4485 struct bnxt_filter_info *filter)
4486 {
4487 int rc = 0;
4488 struct hwrm_cfa_ntuple_filter_free_input req = {.req_type = 0 };
4489 struct hwrm_cfa_ntuple_filter_free_output *resp =
4490 bp->hwrm_cmd_resp_addr;
4491
4492 if (filter->fw_ntuple_filter_id == UINT64_MAX)
4493 return 0;
4494
4495 HWRM_PREP(&req, HWRM_CFA_NTUPLE_FILTER_FREE, BNXT_USE_CHIMP_MB);
4496
4497 req.ntuple_filter_id = rte_cpu_to_le_64(filter->fw_ntuple_filter_id);
4498
4499 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4500
4501 HWRM_CHECK_RESULT();
4502 HWRM_UNLOCK();
4503
4504 filter->fw_ntuple_filter_id = UINT64_MAX;
4505
4506 return 0;
4507 }
4508
4509 static int
4510 bnxt_vnic_rss_configure_thor(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4511 {
4512 struct hwrm_vnic_rss_cfg_output *resp = bp->hwrm_cmd_resp_addr;
4513 uint8_t *rx_queue_state = bp->eth_dev->data->rx_queue_state;
4514 struct hwrm_vnic_rss_cfg_input req = {.req_type = 0 };
4515 struct bnxt_rx_queue **rxqs = bp->rx_queues;
4516 uint16_t *ring_tbl = vnic->rss_table;
4517 int nr_ctxs = vnic->num_lb_ctxts;
4518 int max_rings = bp->rx_nr_rings;
4519 int i, j, k, cnt;
4520 int rc = 0;
4521
4522 for (i = 0, k = 0; i < nr_ctxs; i++) {
4523 struct bnxt_rx_ring_info *rxr;
4524 struct bnxt_cp_ring_info *cpr;
4525
4526 HWRM_PREP(&req, HWRM_VNIC_RSS_CFG, BNXT_USE_CHIMP_MB);
4527
4528 req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
4529 req.hash_type = rte_cpu_to_le_32(vnic->hash_type);
4530 req.hash_mode_flags = vnic->hash_mode;
4531
4532 req.ring_grp_tbl_addr =
4533 rte_cpu_to_le_64(vnic->rss_table_dma_addr +
4534 i * BNXT_RSS_ENTRIES_PER_CTX_THOR *
4535 2 * sizeof(*ring_tbl));
4536 req.hash_key_tbl_addr =
4537 rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
4538
4539 req.ring_table_pair_index = i;
4540 req.rss_ctx_idx = rte_cpu_to_le_16(vnic->fw_grp_ids[i]);
4541
4542 for (j = 0; j < 64; j++) {
4543 uint16_t ring_id;
4544
4545 /* Find next active ring. */
4546 for (cnt = 0; cnt < max_rings; cnt++) {
4547 if (rx_queue_state[k] !=
4548 RTE_ETH_QUEUE_STATE_STOPPED)
4549 break;
4550 if (++k == max_rings)
4551 k = 0;
4552 }
4553
4554 /* Return if no rings are active. */
4555 if (cnt == max_rings) {
4556 HWRM_UNLOCK();
4557 return 0;
4558 }
4559
4560 /* Add rx/cp ring pair to RSS table. */
4561 rxr = rxqs[k]->rx_ring;
4562 cpr = rxqs[k]->cp_ring;
4563
4564 ring_id = rxr->rx_ring_struct->fw_ring_id;
4565 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4566 ring_id = cpr->cp_ring_struct->fw_ring_id;
4567 *ring_tbl++ = rte_cpu_to_le_16(ring_id);
4568
4569 if (++k == max_rings)
4570 k = 0;
4571 }
4572 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
4573 BNXT_USE_CHIMP_MB);
4574
4575 HWRM_CHECK_RESULT();
4576 HWRM_UNLOCK();
4577 }
4578
4579 return rc;
4580 }
4581
4582 int bnxt_vnic_rss_configure(struct bnxt *bp, struct bnxt_vnic_info *vnic)
4583 {
4584 unsigned int rss_idx, fw_idx, i;
4585
4586 if (!(vnic->rss_table && vnic->hash_type))
4587 return 0;
4588
4589 if (BNXT_CHIP_THOR(bp))
4590 return bnxt_vnic_rss_configure_thor(bp, vnic);
4591
4592 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4593 return 0;
4594
4595 if (vnic->rss_table && vnic->hash_type) {
4596 /*
4597 * Fill the RSS hash & redirection table with
4598 * ring group ids for all VNICs
4599 */
4600 for (rss_idx = 0, fw_idx = 0; rss_idx < HW_HASH_INDEX_SIZE;
4601 rss_idx++, fw_idx++) {
4602 for (i = 0; i < bp->rx_cp_nr_rings; i++) {
4603 fw_idx %= bp->rx_cp_nr_rings;
4604 if (vnic->fw_grp_ids[fw_idx] !=
4605 INVALID_HW_RING_ID)
4606 break;
4607 fw_idx++;
4608 }
4609 if (i == bp->rx_cp_nr_rings)
4610 return 0;
4611 vnic->rss_table[rss_idx] = vnic->fw_grp_ids[fw_idx];
4612 }
4613 return bnxt_hwrm_vnic_rss_cfg(bp, vnic);
4614 }
4615
4616 return 0;
4617 }
4618
4619 static void bnxt_hwrm_set_coal_params(struct bnxt_coal *hw_coal,
4620 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4621 {
4622 uint16_t flags;
4623
4624 req->num_cmpl_aggr_int = rte_cpu_to_le_16(hw_coal->num_cmpl_aggr_int);
4625
4626 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4627 req->num_cmpl_dma_aggr = rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr);
4628
4629 /* This is a 6-bit value and must not be 0, or we'll get non stop IRQ */
4630 req->num_cmpl_dma_aggr_during_int =
4631 rte_cpu_to_le_16(hw_coal->num_cmpl_dma_aggr_during_int);
4632
4633 req->int_lat_tmr_max = rte_cpu_to_le_16(hw_coal->int_lat_tmr_max);
4634
4635 /* min timer set to 1/2 of interrupt timer */
4636 req->int_lat_tmr_min = rte_cpu_to_le_16(hw_coal->int_lat_tmr_min);
4637
4638 /* buf timer set to 1/4 of interrupt timer */
4639 req->cmpl_aggr_dma_tmr = rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr);
4640
4641 req->cmpl_aggr_dma_tmr_during_int =
4642 rte_cpu_to_le_16(hw_coal->cmpl_aggr_dma_tmr_during_int);
4643
4644 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4645 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4646 req->flags = rte_cpu_to_le_16(flags);
4647 }
4648
4649 static int bnxt_hwrm_set_coal_params_thor(struct bnxt *bp,
4650 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *agg_req)
4651 {
4652 struct hwrm_ring_aggint_qcaps_input req = {0};
4653 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4654 uint32_t enables;
4655 uint16_t flags;
4656 int rc;
4657
4658 HWRM_PREP(&req, HWRM_RING_AGGINT_QCAPS, BNXT_USE_CHIMP_MB);
4659 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4660 HWRM_CHECK_RESULT();
4661
4662 agg_req->num_cmpl_dma_aggr = resp->num_cmpl_dma_aggr_max;
4663 agg_req->cmpl_aggr_dma_tmr = resp->cmpl_aggr_dma_tmr_min;
4664
4665 flags = HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_TIMER_RESET |
4666 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_FLAGS_RING_IDLE;
4667 agg_req->flags = rte_cpu_to_le_16(flags);
4668 enables =
4669 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_CMPL_AGGR_DMA_TMR |
4670 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS_INPUT_ENABLES_NUM_CMPL_DMA_AGGR;
4671 agg_req->enables = rte_cpu_to_le_32(enables);
4672
4673 HWRM_UNLOCK();
4674 return rc;
4675 }
4676
4677 int bnxt_hwrm_set_ring_coal(struct bnxt *bp,
4678 struct bnxt_coal *coal, uint16_t ring_id)
4679 {
4680 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
4681 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output *resp =
4682 bp->hwrm_cmd_resp_addr;
4683 int rc;
4684
4685 /* Set ring coalesce parameters only for 100G NICs */
4686 if (BNXT_CHIP_THOR(bp)) {
4687 if (bnxt_hwrm_set_coal_params_thor(bp, &req))
4688 return -1;
4689 } else if (bnxt_stratus_device(bp)) {
4690 bnxt_hwrm_set_coal_params(coal, &req);
4691 } else {
4692 return 0;
4693 }
4694
4695 HWRM_PREP(&req,
4696 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
4697 BNXT_USE_CHIMP_MB);
4698 req.ring_id = rte_cpu_to_le_16(ring_id);
4699 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4700 HWRM_CHECK_RESULT();
4701 HWRM_UNLOCK();
4702 return 0;
4703 }
4704
4705 #define BNXT_RTE_MEMZONE_FLAG (RTE_MEMZONE_1GB | RTE_MEMZONE_IOVA_CONTIG)
4706 int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
4707 {
4708 struct hwrm_func_backing_store_qcaps_input req = {0};
4709 struct hwrm_func_backing_store_qcaps_output *resp =
4710 bp->hwrm_cmd_resp_addr;
4711 struct bnxt_ctx_pg_info *ctx_pg;
4712 struct bnxt_ctx_mem_info *ctx;
4713 int total_alloc_len;
4714 int rc, i, tqm_rings;
4715
4716 if (!BNXT_CHIP_THOR(bp) ||
4717 bp->hwrm_spec_code < HWRM_VERSION_1_9_2 ||
4718 BNXT_VF(bp) ||
4719 bp->ctx)
4720 return 0;
4721
4722 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_QCAPS, BNXT_USE_CHIMP_MB);
4723 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4724 HWRM_CHECK_RESULT_SILENT();
4725
4726 total_alloc_len = sizeof(*ctx);
4727 ctx = rte_zmalloc("bnxt_ctx_mem", total_alloc_len,
4728 RTE_CACHE_LINE_SIZE);
4729 if (!ctx) {
4730 rc = -ENOMEM;
4731 goto ctx_err;
4732 }
4733
4734 ctx->qp_max_entries = rte_le_to_cpu_32(resp->qp_max_entries);
4735 ctx->qp_min_qp1_entries =
4736 rte_le_to_cpu_16(resp->qp_min_qp1_entries);
4737 ctx->qp_max_l2_entries =
4738 rte_le_to_cpu_16(resp->qp_max_l2_entries);
4739 ctx->qp_entry_size = rte_le_to_cpu_16(resp->qp_entry_size);
4740 ctx->srq_max_l2_entries =
4741 rte_le_to_cpu_16(resp->srq_max_l2_entries);
4742 ctx->srq_max_entries = rte_le_to_cpu_32(resp->srq_max_entries);
4743 ctx->srq_entry_size = rte_le_to_cpu_16(resp->srq_entry_size);
4744 ctx->cq_max_l2_entries =
4745 rte_le_to_cpu_16(resp->cq_max_l2_entries);
4746 ctx->cq_max_entries = rte_le_to_cpu_32(resp->cq_max_entries);
4747 ctx->cq_entry_size = rte_le_to_cpu_16(resp->cq_entry_size);
4748 ctx->vnic_max_vnic_entries =
4749 rte_le_to_cpu_16(resp->vnic_max_vnic_entries);
4750 ctx->vnic_max_ring_table_entries =
4751 rte_le_to_cpu_16(resp->vnic_max_ring_table_entries);
4752 ctx->vnic_entry_size = rte_le_to_cpu_16(resp->vnic_entry_size);
4753 ctx->stat_max_entries =
4754 rte_le_to_cpu_32(resp->stat_max_entries);
4755 ctx->stat_entry_size = rte_le_to_cpu_16(resp->stat_entry_size);
4756 ctx->tqm_entry_size = rte_le_to_cpu_16(resp->tqm_entry_size);
4757 ctx->tqm_min_entries_per_ring =
4758 rte_le_to_cpu_32(resp->tqm_min_entries_per_ring);
4759 ctx->tqm_max_entries_per_ring =
4760 rte_le_to_cpu_32(resp->tqm_max_entries_per_ring);
4761 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
4762 if (!ctx->tqm_entries_multiple)
4763 ctx->tqm_entries_multiple = 1;
4764 ctx->mrav_max_entries =
4765 rte_le_to_cpu_32(resp->mrav_max_entries);
4766 ctx->mrav_entry_size = rte_le_to_cpu_16(resp->mrav_entry_size);
4767 ctx->tim_entry_size = rte_le_to_cpu_16(resp->tim_entry_size);
4768 ctx->tim_max_entries = rte_le_to_cpu_32(resp->tim_max_entries);
4769 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
4770
4771 if (!ctx->tqm_fp_rings_count)
4772 ctx->tqm_fp_rings_count = bp->max_q;
4773
4774 tqm_rings = ctx->tqm_fp_rings_count + 1;
4775
4776 ctx_pg = rte_malloc("bnxt_ctx_pg_mem",
4777 sizeof(*ctx_pg) * tqm_rings,
4778 RTE_CACHE_LINE_SIZE);
4779 if (!ctx_pg) {
4780 rc = -ENOMEM;
4781 goto ctx_err;
4782 }
4783 for (i = 0; i < tqm_rings; i++, ctx_pg++)
4784 ctx->tqm_mem[i] = ctx_pg;
4785
4786 bp->ctx = ctx;
4787 ctx_err:
4788 HWRM_UNLOCK();
4789 return rc;
4790 }
4791
4792 int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, uint32_t enables)
4793 {
4794 struct hwrm_func_backing_store_cfg_input req = {0};
4795 struct hwrm_func_backing_store_cfg_output *resp =
4796 bp->hwrm_cmd_resp_addr;
4797 struct bnxt_ctx_mem_info *ctx = bp->ctx;
4798 struct bnxt_ctx_pg_info *ctx_pg;
4799 uint32_t *num_entries;
4800 uint64_t *pg_dir;
4801 uint8_t *pg_attr;
4802 uint32_t ena;
4803 int i, rc;
4804
4805 if (!ctx)
4806 return 0;
4807
4808 HWRM_PREP(&req, HWRM_FUNC_BACKING_STORE_CFG, BNXT_USE_CHIMP_MB);
4809 req.enables = rte_cpu_to_le_32(enables);
4810
4811 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_QP) {
4812 ctx_pg = &ctx->qp_mem;
4813 req.qp_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4814 req.qp_num_qp1_entries =
4815 rte_cpu_to_le_16(ctx->qp_min_qp1_entries);
4816 req.qp_num_l2_entries =
4817 rte_cpu_to_le_16(ctx->qp_max_l2_entries);
4818 req.qp_entry_size = rte_cpu_to_le_16(ctx->qp_entry_size);
4819 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4820 &req.qpc_pg_size_qpc_lvl,
4821 &req.qpc_page_dir);
4822 }
4823
4824 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_SRQ) {
4825 ctx_pg = &ctx->srq_mem;
4826 req.srq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4827 req.srq_num_l2_entries =
4828 rte_cpu_to_le_16(ctx->srq_max_l2_entries);
4829 req.srq_entry_size = rte_cpu_to_le_16(ctx->srq_entry_size);
4830 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4831 &req.srq_pg_size_srq_lvl,
4832 &req.srq_page_dir);
4833 }
4834
4835 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_CQ) {
4836 ctx_pg = &ctx->cq_mem;
4837 req.cq_num_entries = rte_cpu_to_le_32(ctx_pg->entries);
4838 req.cq_num_l2_entries =
4839 rte_cpu_to_le_16(ctx->cq_max_l2_entries);
4840 req.cq_entry_size = rte_cpu_to_le_16(ctx->cq_entry_size);
4841 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4842 &req.cq_pg_size_cq_lvl,
4843 &req.cq_page_dir);
4844 }
4845
4846 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_VNIC) {
4847 ctx_pg = &ctx->vnic_mem;
4848 req.vnic_num_vnic_entries =
4849 rte_cpu_to_le_16(ctx->vnic_max_vnic_entries);
4850 req.vnic_num_ring_table_entries =
4851 rte_cpu_to_le_16(ctx->vnic_max_ring_table_entries);
4852 req.vnic_entry_size = rte_cpu_to_le_16(ctx->vnic_entry_size);
4853 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4854 &req.vnic_pg_size_vnic_lvl,
4855 &req.vnic_page_dir);
4856 }
4857
4858 if (enables & HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_STAT) {
4859 ctx_pg = &ctx->stat_mem;
4860 req.stat_num_entries = rte_cpu_to_le_16(ctx->stat_max_entries);
4861 req.stat_entry_size = rte_cpu_to_le_16(ctx->stat_entry_size);
4862 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
4863 &req.stat_pg_size_stat_lvl,
4864 &req.stat_page_dir);
4865 }
4866
4867 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4868 num_entries = &req.tqm_sp_num_entries;
4869 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl;
4870 pg_dir = &req.tqm_sp_page_dir;
4871 ena = HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP;
4872 for (i = 0; i < 9; i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
4873 if (!(enables & ena))
4874 continue;
4875
4876 req.tqm_entry_size = rte_cpu_to_le_16(ctx->tqm_entry_size);
4877
4878 ctx_pg = ctx->tqm_mem[i];
4879 *num_entries = rte_cpu_to_le_16(ctx_pg->entries);
4880 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
4881 }
4882
4883 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4884 HWRM_CHECK_RESULT();
4885 HWRM_UNLOCK();
4886
4887 return rc;
4888 }
4889
4890 int bnxt_hwrm_ext_port_qstats(struct bnxt *bp)
4891 {
4892 struct hwrm_port_qstats_ext_input req = {0};
4893 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
4894 struct bnxt_pf_info *pf = bp->pf;
4895 int rc;
4896
4897 if (!(bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS ||
4898 bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS))
4899 return 0;
4900
4901 HWRM_PREP(&req, HWRM_PORT_QSTATS_EXT, BNXT_USE_CHIMP_MB);
4902
4903 req.port_id = rte_cpu_to_le_16(pf->port_id);
4904 if (bp->flags & BNXT_FLAG_EXT_TX_PORT_STATS) {
4905 req.tx_stat_host_addr =
4906 rte_cpu_to_le_64(bp->hw_tx_port_stats_ext_map);
4907 req.tx_stat_size =
4908 rte_cpu_to_le_16(sizeof(struct tx_port_stats_ext));
4909 }
4910 if (bp->flags & BNXT_FLAG_EXT_RX_PORT_STATS) {
4911 req.rx_stat_host_addr =
4912 rte_cpu_to_le_64(bp->hw_rx_port_stats_ext_map);
4913 req.rx_stat_size =
4914 rte_cpu_to_le_16(sizeof(struct rx_port_stats_ext));
4915 }
4916 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4917
4918 if (rc) {
4919 bp->fw_rx_port_stats_ext_size = 0;
4920 bp->fw_tx_port_stats_ext_size = 0;
4921 } else {
4922 bp->fw_rx_port_stats_ext_size =
4923 rte_le_to_cpu_16(resp->rx_stat_size);
4924 bp->fw_tx_port_stats_ext_size =
4925 rte_le_to_cpu_16(resp->tx_stat_size);
4926 }
4927
4928 HWRM_CHECK_RESULT();
4929 HWRM_UNLOCK();
4930
4931 return rc;
4932 }
4933
4934 int
4935 bnxt_hwrm_tunnel_redirect(struct bnxt *bp, uint8_t type)
4936 {
4937 struct hwrm_cfa_redirect_tunnel_type_alloc_input req = {0};
4938 struct hwrm_cfa_redirect_tunnel_type_alloc_output *resp =
4939 bp->hwrm_cmd_resp_addr;
4940 int rc = 0;
4941
4942 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC, BNXT_USE_CHIMP_MB);
4943 req.tunnel_type = type;
4944 req.dest_fid = bp->fw_fid;
4945 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4946 HWRM_CHECK_RESULT();
4947
4948 HWRM_UNLOCK();
4949
4950 return rc;
4951 }
4952
4953 int
4954 bnxt_hwrm_tunnel_redirect_free(struct bnxt *bp, uint8_t type)
4955 {
4956 struct hwrm_cfa_redirect_tunnel_type_free_input req = {0};
4957 struct hwrm_cfa_redirect_tunnel_type_free_output *resp =
4958 bp->hwrm_cmd_resp_addr;
4959 int rc = 0;
4960
4961 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE, BNXT_USE_CHIMP_MB);
4962 req.tunnel_type = type;
4963 req.dest_fid = bp->fw_fid;
4964 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4965 HWRM_CHECK_RESULT();
4966
4967 HWRM_UNLOCK();
4968
4969 return rc;
4970 }
4971
4972 int bnxt_hwrm_tunnel_redirect_query(struct bnxt *bp, uint32_t *type)
4973 {
4974 struct hwrm_cfa_redirect_query_tunnel_type_input req = {0};
4975 struct hwrm_cfa_redirect_query_tunnel_type_output *resp =
4976 bp->hwrm_cmd_resp_addr;
4977 int rc = 0;
4978
4979 HWRM_PREP(&req, HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE, BNXT_USE_CHIMP_MB);
4980 req.src_fid = bp->fw_fid;
4981 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
4982 HWRM_CHECK_RESULT();
4983
4984 if (type)
4985 *type = rte_le_to_cpu_32(resp->tunnel_mask);
4986
4987 HWRM_UNLOCK();
4988
4989 return rc;
4990 }
4991
4992 int bnxt_hwrm_tunnel_redirect_info(struct bnxt *bp, uint8_t tun_type,
4993 uint16_t *dst_fid)
4994 {
4995 struct hwrm_cfa_redirect_tunnel_type_info_input req = {0};
4996 struct hwrm_cfa_redirect_tunnel_type_info_output *resp =
4997 bp->hwrm_cmd_resp_addr;
4998 int rc = 0;
4999
5000 HWRM_PREP(&req, HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO, BNXT_USE_CHIMP_MB);
5001 req.src_fid = bp->fw_fid;
5002 req.tunnel_type = tun_type;
5003 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5004 HWRM_CHECK_RESULT();
5005
5006 if (dst_fid)
5007 *dst_fid = rte_le_to_cpu_16(resp->dest_fid);
5008
5009 PMD_DRV_LOG(DEBUG, "dst_fid: %x\n", resp->dest_fid);
5010
5011 HWRM_UNLOCK();
5012
5013 return rc;
5014 }
5015
5016 int bnxt_hwrm_set_mac(struct bnxt *bp)
5017 {
5018 struct hwrm_func_vf_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5019 struct hwrm_func_vf_cfg_input req = {0};
5020 int rc = 0;
5021
5022 if (!BNXT_VF(bp))
5023 return 0;
5024
5025 HWRM_PREP(&req, HWRM_FUNC_VF_CFG, BNXT_USE_CHIMP_MB);
5026
5027 req.enables =
5028 rte_cpu_to_le_32(HWRM_FUNC_VF_CFG_INPUT_ENABLES_DFLT_MAC_ADDR);
5029 memcpy(req.dflt_mac_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
5030
5031 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5032
5033 HWRM_CHECK_RESULT();
5034
5035 HWRM_UNLOCK();
5036
5037 return rc;
5038 }
5039
5040 int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
5041 {
5042 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
5043 struct hwrm_func_drv_if_change_input req = {0};
5044 uint32_t flags;
5045 int rc;
5046
5047 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
5048 return 0;
5049
5050 /* Do not issue FUNC_DRV_IF_CHANGE during reset recovery.
5051 * If we issue FUNC_DRV_IF_CHANGE with flags down before
5052 * FUNC_DRV_UNRGTR, FW resets before FUNC_DRV_UNRGTR
5053 */
5054 if (!up && (bp->flags & BNXT_FLAG_FW_RESET))
5055 return 0;
5056
5057 HWRM_PREP(&req, HWRM_FUNC_DRV_IF_CHANGE, BNXT_USE_CHIMP_MB);
5058
5059 if (up)
5060 req.flags =
5061 rte_cpu_to_le_32(HWRM_FUNC_DRV_IF_CHANGE_INPUT_FLAGS_UP);
5062
5063 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5064
5065 HWRM_CHECK_RESULT();
5066 flags = rte_le_to_cpu_32(resp->flags);
5067 HWRM_UNLOCK();
5068
5069 if (!up)
5070 return 0;
5071
5072 if (flags & HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE) {
5073 PMD_DRV_LOG(INFO, "FW reset happened while port was down\n");
5074 bp->flags |= BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE;
5075 }
5076
5077 return 0;
5078 }
5079
5080 int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
5081 {
5082 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5083 struct bnxt_error_recovery_info *info = bp->recovery_info;
5084 struct hwrm_error_recovery_qcfg_input req = {0};
5085 uint32_t flags = 0;
5086 unsigned int i;
5087 int rc;
5088
5089 /* Older FW does not have error recovery support */
5090 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
5091 return 0;
5092
5093 HWRM_PREP(&req, HWRM_ERROR_RECOVERY_QCFG, BNXT_USE_CHIMP_MB);
5094
5095 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5096
5097 HWRM_CHECK_RESULT();
5098
5099 flags = rte_le_to_cpu_32(resp->flags);
5100 if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST)
5101 info->flags |= BNXT_FLAG_ERROR_RECOVERY_HOST;
5102 else if (flags & HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU)
5103 info->flags |= BNXT_FLAG_ERROR_RECOVERY_CO_CPU;
5104
5105 if ((info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) &&
5106 !(bp->flags & BNXT_FLAG_KONG_MB_EN)) {
5107 rc = -EINVAL;
5108 goto err;
5109 }
5110
5111 /* FW returned values are in units of 100msec */
5112 info->driver_polling_freq =
5113 rte_le_to_cpu_32(resp->driver_polling_freq) * 100;
5114 info->master_func_wait_period =
5115 rte_le_to_cpu_32(resp->master_func_wait_period) * 100;
5116 info->normal_func_wait_period =
5117 rte_le_to_cpu_32(resp->normal_func_wait_period) * 100;
5118 info->master_func_wait_period_after_reset =
5119 rte_le_to_cpu_32(resp->master_func_wait_period_after_reset) * 100;
5120 info->max_bailout_time_after_reset =
5121 rte_le_to_cpu_32(resp->max_bailout_time_after_reset) * 100;
5122 info->status_regs[BNXT_FW_STATUS_REG] =
5123 rte_le_to_cpu_32(resp->fw_health_status_reg);
5124 info->status_regs[BNXT_FW_HEARTBEAT_CNT_REG] =
5125 rte_le_to_cpu_32(resp->fw_heartbeat_reg);
5126 info->status_regs[BNXT_FW_RECOVERY_CNT_REG] =
5127 rte_le_to_cpu_32(resp->fw_reset_cnt_reg);
5128 info->status_regs[BNXT_FW_RESET_INPROG_REG] =
5129 rte_le_to_cpu_32(resp->reset_inprogress_reg);
5130 info->reg_array_cnt =
5131 rte_le_to_cpu_32(resp->reg_array_cnt);
5132
5133 if (info->reg_array_cnt >= BNXT_NUM_RESET_REG) {
5134 rc = -EINVAL;
5135 goto err;
5136 }
5137
5138 for (i = 0; i < info->reg_array_cnt; i++) {
5139 info->reset_reg[i] =
5140 rte_le_to_cpu_32(resp->reset_reg[i]);
5141 info->reset_reg_val[i] =
5142 rte_le_to_cpu_32(resp->reset_reg_val[i]);
5143 info->delay_after_reset[i] =
5144 resp->delay_after_reset[i];
5145 }
5146 err:
5147 HWRM_UNLOCK();
5148
5149 /* Map the FW status registers */
5150 if (!rc)
5151 rc = bnxt_map_fw_health_status_regs(bp);
5152
5153 if (rc) {
5154 rte_free(bp->recovery_info);
5155 bp->recovery_info = NULL;
5156 }
5157 return rc;
5158 }
5159
5160 int bnxt_hwrm_fw_reset(struct bnxt *bp)
5161 {
5162 struct hwrm_fw_reset_output *resp = bp->hwrm_cmd_resp_addr;
5163 struct hwrm_fw_reset_input req = {0};
5164 int rc;
5165
5166 if (!BNXT_PF(bp))
5167 return -EOPNOTSUPP;
5168
5169 HWRM_PREP(&req, HWRM_FW_RESET, BNXT_USE_KONG(bp));
5170
5171 req.embedded_proc_type =
5172 HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_CHIP;
5173 req.selfrst_status =
5174 HWRM_FW_RESET_INPUT_SELFRST_STATUS_SELFRSTASAP;
5175 req.flags = HWRM_FW_RESET_INPUT_FLAGS_RESET_GRACEFUL;
5176
5177 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req),
5178 BNXT_USE_KONG(bp));
5179
5180 HWRM_CHECK_RESULT();
5181 HWRM_UNLOCK();
5182
5183 return rc;
5184 }
5185
5186 int bnxt_hwrm_port_ts_query(struct bnxt *bp, uint8_t path, uint64_t *timestamp)
5187 {
5188 struct hwrm_port_ts_query_output *resp = bp->hwrm_cmd_resp_addr;
5189 struct hwrm_port_ts_query_input req = {0};
5190 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
5191 uint32_t flags = 0;
5192 int rc;
5193
5194 if (!ptp)
5195 return 0;
5196
5197 HWRM_PREP(&req, HWRM_PORT_TS_QUERY, BNXT_USE_CHIMP_MB);
5198
5199 switch (path) {
5200 case BNXT_PTP_FLAGS_PATH_TX:
5201 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_TX;
5202 break;
5203 case BNXT_PTP_FLAGS_PATH_RX:
5204 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_PATH_RX;
5205 break;
5206 case BNXT_PTP_FLAGS_CURRENT_TIME:
5207 flags |= HWRM_PORT_TS_QUERY_INPUT_FLAGS_CURRENT_TIME;
5208 break;
5209 }
5210
5211 req.flags = rte_cpu_to_le_32(flags);
5212 req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
5213
5214 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
5215
5216 HWRM_CHECK_RESULT();
5217
5218 if (timestamp) {
5219 *timestamp = rte_le_to_cpu_32(resp->ptp_msg_ts[0]);
5220 *timestamp |=
5221 (uint64_t)(rte_le_to_cpu_32(resp->ptp_msg_ts[1])) << 32;
5222 }
5223 HWRM_UNLOCK();
5224
5225 return rc;
5226 }
5227
5228 int bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(struct bnxt *bp)
5229 {
5230 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp =
5231 bp->hwrm_cmd_resp_addr;
5232 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
5233 uint32_t flags = 0;
5234 int rc = 0;
5235
5236 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_MGMT))
5237 return rc;
5238
5239 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5240 PMD_DRV_LOG(DEBUG,
5241 "Not a PF or trusted VF. Command not supported\n");
5242 return 0;
5243 }
5244
5245 HWRM_PREP(&req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, BNXT_USE_KONG(bp));
5246 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5247
5248 HWRM_CHECK_RESULT();
5249 flags = rte_le_to_cpu_32(resp->flags);
5250 HWRM_UNLOCK();
5251
5252 if (flags & HWRM_CFA_ADV_FLOW_MGNT_QCAPS_L2_HDR_SRC_FILTER_EN) {
5253 bp->flow_flags |= BNXT_FLOW_FLAG_L2_HDR_SRC_FILTER_EN;
5254 PMD_DRV_LOG(INFO, "Source L2 header filtering enabled\n");
5255 }
5256
5257 return rc;
5258 }
5259
5260 int bnxt_hwrm_cfa_counter_qcaps(struct bnxt *bp, uint16_t *max_fc)
5261 {
5262 int rc = 0;
5263
5264 struct hwrm_cfa_counter_qcaps_input req = {0};
5265 struct hwrm_cfa_counter_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5266
5267 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5268 PMD_DRV_LOG(DEBUG,
5269 "Not a PF or trusted VF. Command not supported\n");
5270 return 0;
5271 }
5272
5273 HWRM_PREP(&req, HWRM_CFA_COUNTER_QCAPS, BNXT_USE_KONG(bp));
5274 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5275 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5276
5277 HWRM_CHECK_RESULT();
5278 if (max_fc)
5279 *max_fc = rte_le_to_cpu_16(resp->max_rx_fc);
5280 HWRM_UNLOCK();
5281
5282 return 0;
5283 }
5284
5285 int bnxt_hwrm_ctx_rgtr(struct bnxt *bp, rte_iova_t dma_addr, uint16_t *ctx_id)
5286 {
5287 int rc = 0;
5288 struct hwrm_cfa_ctx_mem_rgtr_input req = {.req_type = 0 };
5289 struct hwrm_cfa_ctx_mem_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
5290
5291 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5292 PMD_DRV_LOG(DEBUG,
5293 "Not a PF or trusted VF. Command not supported\n");
5294 return 0;
5295 }
5296
5297 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_RGTR, BNXT_USE_KONG(bp));
5298
5299 req.page_level = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0;
5300 req.page_size = HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M;
5301 req.page_dir = rte_cpu_to_le_64(dma_addr);
5302
5303 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5304
5305 HWRM_CHECK_RESULT();
5306 if (ctx_id) {
5307 *ctx_id = rte_le_to_cpu_16(resp->ctx_id);
5308 PMD_DRV_LOG(DEBUG, "ctx_id = %d\n", *ctx_id);
5309 }
5310 HWRM_UNLOCK();
5311
5312 return 0;
5313 }
5314
5315 int bnxt_hwrm_ctx_unrgtr(struct bnxt *bp, uint16_t ctx_id)
5316 {
5317 int rc = 0;
5318 struct hwrm_cfa_ctx_mem_unrgtr_input req = {.req_type = 0 };
5319 struct hwrm_cfa_ctx_mem_unrgtr_output *resp = bp->hwrm_cmd_resp_addr;
5320
5321 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5322 PMD_DRV_LOG(DEBUG,
5323 "Not a PF or trusted VF. Command not supported\n");
5324 return 0;
5325 }
5326
5327 HWRM_PREP(&req, HWRM_CFA_CTX_MEM_UNRGTR, BNXT_USE_KONG(bp));
5328
5329 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5330
5331 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5332
5333 HWRM_CHECK_RESULT();
5334 HWRM_UNLOCK();
5335
5336 return rc;
5337 }
5338
5339 int bnxt_hwrm_cfa_counter_cfg(struct bnxt *bp, enum bnxt_flow_dir dir,
5340 uint16_t cntr, uint16_t ctx_id,
5341 uint32_t num_entries, bool enable)
5342 {
5343 struct hwrm_cfa_counter_cfg_input req = {0};
5344 struct hwrm_cfa_counter_cfg_output *resp = bp->hwrm_cmd_resp_addr;
5345 uint16_t flags = 0;
5346 int rc;
5347
5348 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5349 PMD_DRV_LOG(DEBUG,
5350 "Not a PF or trusted VF. Command not supported\n");
5351 return 0;
5352 }
5353
5354 HWRM_PREP(&req, HWRM_CFA_COUNTER_CFG, BNXT_USE_KONG(bp));
5355
5356 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5357 req.counter_type = rte_cpu_to_le_16(cntr);
5358 flags = enable ? HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_ENABLE :
5359 HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_CFG_MODE_DISABLE;
5360 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_DATA_TRANSFER_MODE_PULL;
5361 if (dir == BNXT_DIR_RX)
5362 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_RX;
5363 else if (dir == BNXT_DIR_TX)
5364 flags |= HWRM_CFA_COUNTER_CFG_INPUT_FLAGS_PATH_TX;
5365 req.flags = rte_cpu_to_le_16(flags);
5366 req.ctx_id = rte_cpu_to_le_16(ctx_id);
5367 req.num_entries = rte_cpu_to_le_32(num_entries);
5368
5369 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5370 HWRM_CHECK_RESULT();
5371 HWRM_UNLOCK();
5372
5373 return 0;
5374 }
5375
5376 int bnxt_hwrm_cfa_counter_qstats(struct bnxt *bp,
5377 enum bnxt_flow_dir dir,
5378 uint16_t cntr,
5379 uint16_t num_entries)
5380 {
5381 struct hwrm_cfa_counter_qstats_output *resp = bp->hwrm_cmd_resp_addr;
5382 struct hwrm_cfa_counter_qstats_input req = {0};
5383 uint16_t flow_ctx_id = 0;
5384 uint16_t flags = 0;
5385 int rc = 0;
5386
5387 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) {
5388 PMD_DRV_LOG(DEBUG,
5389 "Not a PF or trusted VF. Command not supported\n");
5390 return 0;
5391 }
5392
5393 if (dir == BNXT_DIR_RX) {
5394 flow_ctx_id = bp->flow_stat->rx_fc_in_tbl.ctx_id;
5395 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_RX;
5396 } else if (dir == BNXT_DIR_TX) {
5397 flow_ctx_id = bp->flow_stat->tx_fc_in_tbl.ctx_id;
5398 flags = HWRM_CFA_COUNTER_QSTATS_INPUT_FLAGS_PATH_TX;
5399 }
5400
5401 HWRM_PREP(&req, HWRM_CFA_COUNTER_QSTATS, BNXT_USE_KONG(bp));
5402 req.target_id = rte_cpu_to_le_16(bp->fw_fid);
5403 req.counter_type = rte_cpu_to_le_16(cntr);
5404 req.input_flow_ctx_id = rte_cpu_to_le_16(flow_ctx_id);
5405 req.num_entries = rte_cpu_to_le_16(num_entries);
5406 req.flags = rte_cpu_to_le_16(flags);
5407 rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_KONG(bp));
5408
5409 HWRM_CHECK_RESULT();
5410 HWRM_UNLOCK();
5411
5412 return 0;
5413 }
Ceph