ceph/src/spdk/dpdk/drivers/net/cxgbe/base/common.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #ifndef __CHELSIO_COMMON_H
   7 #define __CHELSIO_COMMON_H
   8
   9 #include "cxgbe_compat.h"
  10 #include "t4_hw.h"
  11 #include "t4vf_hw.h"
  12 #include "t4_chip_type.h"
  13 #include "t4fw_interface.h"
  14
  15 #ifdef __cplusplus
  16 extern "C" {
  17 #endif
  18
  19 #define CXGBE_PAGE_SIZE RTE_PGSIZE_4K
  20
  21 #define T4_MEMORY_WRITE 0
  22 #define T4_MEMORY_READ  1
  23
  24 enum {
  25         MAX_NPORTS     = 4,     /* max # of ports */
  26 };
  27
  28 enum {
  29         T5_REGMAP_SIZE = (332 * 1024),
  30 };
  31
  32 enum {
  33         MEMWIN0_APERTURE = 2048,
  34         MEMWIN0_BASE     = 0x1b800,
  35 };
  36
  37 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
  38
  39 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
  40
  41 enum cc_pause {
  42         PAUSE_RX      = 1 << 0,
  43         PAUSE_TX      = 1 << 1,
  44         PAUSE_AUTONEG = 1 << 2
  45 };
  46
  47 enum cc_fec {
  48         FEC_AUTO     = 1 << 0,    /* IEEE 802.3 "automatic" */
  49         FEC_RS       = 1 << 1,    /* Reed-Solomon */
  50         FEC_BASER_RS = 1 << 2,    /* BaseR/Reed-Solomon */
  51 };
  52
  53 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
  54
  55 struct port_stats {
  56         u64 tx_octets;            /* total # of octets in good frames */
  57         u64 tx_frames;            /* all good frames */
  58         u64 tx_bcast_frames;      /* all broadcast frames */
  59         u64 tx_mcast_frames;      /* all multicast frames */
  60         u64 tx_ucast_frames;      /* all unicast frames */
  61         u64 tx_error_frames;      /* all error frames */
  62
  63         u64 tx_frames_64;         /* # of Tx frames in a particular range */
  64         u64 tx_frames_65_127;
  65         u64 tx_frames_128_255;
  66         u64 tx_frames_256_511;
  67         u64 tx_frames_512_1023;
  68         u64 tx_frames_1024_1518;
  69         u64 tx_frames_1519_max;
  70
  71         u64 tx_drop;              /* # of dropped Tx frames */
  72         u64 tx_pause;             /* # of transmitted pause frames */
  73         u64 tx_ppp0;              /* # of transmitted PPP prio 0 frames */
  74         u64 tx_ppp1;              /* # of transmitted PPP prio 1 frames */
  75         u64 tx_ppp2;              /* # of transmitted PPP prio 2 frames */
  76         u64 tx_ppp3;              /* # of transmitted PPP prio 3 frames */
  77         u64 tx_ppp4;              /* # of transmitted PPP prio 4 frames */
  78         u64 tx_ppp5;              /* # of transmitted PPP prio 5 frames */
  79         u64 tx_ppp6;              /* # of transmitted PPP prio 6 frames */
  80         u64 tx_ppp7;              /* # of transmitted PPP prio 7 frames */
  81
  82         u64 rx_octets;            /* total # of octets in good frames */
  83         u64 rx_frames;            /* all good frames */
  84         u64 rx_bcast_frames;      /* all broadcast frames */
  85         u64 rx_mcast_frames;      /* all multicast frames */
  86         u64 rx_ucast_frames;      /* all unicast frames */
  87         u64 rx_too_long;          /* # of frames exceeding MTU */
  88         u64 rx_jabber;            /* # of jabber frames */
  89         u64 rx_fcs_err;           /* # of received frames with bad FCS */
  90         u64 rx_len_err;           /* # of received frames with length error */
  91         u64 rx_symbol_err;        /* symbol errors */
  92         u64 rx_runt;              /* # of short frames */
  93
  94         u64 rx_frames_64;         /* # of Rx frames in a particular range */
  95         u64 rx_frames_65_127;
  96         u64 rx_frames_128_255;
  97         u64 rx_frames_256_511;
  98         u64 rx_frames_512_1023;
  99         u64 rx_frames_1024_1518;
 100         u64 rx_frames_1519_max;
 101
 102         u64 rx_pause;             /* # of received pause frames */
 103         u64 rx_ppp0;              /* # of received PPP prio 0 frames */
 104         u64 rx_ppp1;              /* # of received PPP prio 1 frames */
 105         u64 rx_ppp2;              /* # of received PPP prio 2 frames */
 106         u64 rx_ppp3;              /* # of received PPP prio 3 frames */
 107         u64 rx_ppp4;              /* # of received PPP prio 4 frames */
 108         u64 rx_ppp5;              /* # of received PPP prio 5 frames */
 109         u64 rx_ppp6;              /* # of received PPP prio 6 frames */
 110         u64 rx_ppp7;              /* # of received PPP prio 7 frames */
 111
 112         u64 rx_ovflow0;           /* drops due to buffer-group 0 overflows */
 113         u64 rx_ovflow1;           /* drops due to buffer-group 1 overflows */
 114         u64 rx_ovflow2;           /* drops due to buffer-group 2 overflows */
 115         u64 rx_ovflow3;           /* drops due to buffer-group 3 overflows */
 116         u64 rx_trunc0;            /* buffer-group 0 truncated packets */
 117         u64 rx_trunc1;            /* buffer-group 1 truncated packets */
 118         u64 rx_trunc2;            /* buffer-group 2 truncated packets */
 119         u64 rx_trunc3;            /* buffer-group 3 truncated packets */
 120 };
 121
 122 struct sge_params {
 123         u32 hps;                        /* host page size for our PF/VF */
 124         u32 eq_qpp;                     /* egress queues/page for our PF/VF */
 125         u32 iq_qpp;                     /* egress queues/page for our PF/VF */
 126 };
 127
 128 struct tp_params {
 129         unsigned int ntxchan;        /* # of Tx channels */
 130         unsigned int tre;            /* log2 of core clocks per TP tick */
 131         unsigned int dack_re;        /* DACK timer resolution */
 132         unsigned int la_mask;        /* what events are recorded by TP LA */
 133         unsigned short tx_modq[NCHAN];  /* channel to modulation queue map */
 134
 135         u32 vlan_pri_map;               /* cached TP_VLAN_PRI_MAP */
 136         u32 ingress_config;             /* cached TP_INGRESS_CONFIG */
 137
 138         /* cached TP_OUT_CONFIG compressed error vector
 139          * and passing outer header info for encapsulated packets.
 140          */
 141         int rx_pkt_encap;
 142
 143         /*
 144          * TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets.  This is a
 145          * subset of the set of fields which may be present in the Compressed
 146          * Filter Tuple portion of filters and TCP TCB connections.  The
 147          * fields which are present are controlled by the TP_VLAN_PRI_MAP.
 148          * Since a variable number of fields may or may not be present, their
 149          * shifted field positions within the Compressed Filter Tuple may
 150          * vary, or not even be present if the field isn't selected in
 151          * TP_VLAN_PRI_MAP.  Since some of these fields are needed in various
 152          * places we store their offsets here, or a -1 if the field isn't
 153          * present.
 154          */
 155         int vlan_shift;
 156         int vnic_shift;
 157         int port_shift;
 158         int protocol_shift;
 159         int ethertype_shift;
 160
 161         u64 hash_filter_mask;
 162 };
 163
 164 struct vpd_params {
 165         unsigned int cclk;
 166 };
 167
 168 struct pci_params {
 169         uint16_t        vendor_id;
 170         uint16_t        device_id;
 171         uint32_t        vpd_cap_addr;
 172         uint16_t        speed;
 173         uint8_t         width;
 174 };
 175
 176 /*
 177  * Firmware device log.
 178  */
 179 struct devlog_params {
 180         u32 memtype;                    /* which memory (EDC0, EDC1, MC) */
 181         u32 start;                      /* start of log in firmware memory */
 182         u32 size;                       /* size of log */
 183 };
 184
 185 struct arch_specific_params {
 186         u8 nchan;
 187         u16 mps_rplc_size;
 188         u16 vfcount;
 189         u32 sge_fl_db;
 190         u16 mps_tcam_size;
 191 };
 192
 193 /*
 194  * Global Receive Side Scaling (RSS) parameters in host-native format.
 195  */
 196 struct rss_params {
 197         unsigned int mode;                      /* RSS mode */
 198         union {
 199                 struct {
 200                         uint synmapen:1;        /* SYN Map Enable */
 201                         uint syn4tupenipv6:1;   /* en 4-tuple IPv6 SYNs hash */
 202                         uint syn2tupenipv6:1;   /* en 2-tuple IPv6 SYNs hash */
 203                         uint syn4tupenipv4:1;   /* en 4-tuple IPv4 SYNs hash */
 204                         uint syn2tupenipv4:1;   /* en 2-tuple IPv4 SYNs hash */
 205                         uint ofdmapen:1;        /* Offload Map Enable */
 206                         uint tnlmapen:1;        /* Tunnel Map Enable */
 207                         uint tnlalllookup:1;    /* Tunnel All Lookup */
 208                         uint hashtoeplitz:1;    /* use Toeplitz hash */
 209                 } basicvirtual;
 210         } u;
 211 };
 212
 213 /*
 214  * Maximum resources provisioned for a PCI PF.
 215  */
 216 struct pf_resources {
 217         unsigned int neq;      /* N egress Qs */
 218         unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
 219 };
 220
 221 /*
 222  * Maximum resources provisioned for a PCI VF.
 223  */
 224 struct vf_resources {
 225         unsigned int nvi;               /* N virtual interfaces */
 226         unsigned int neq;               /* N egress Qs */
 227         unsigned int nethctrl;          /* N egress ETH or CTRL Qs */
 228         unsigned int niqflint;          /* N ingress Qs/w free list(s) & intr */
 229         unsigned int niq;               /* N ingress Qs */
 230         unsigned int tc;                /* PCI-E traffic class */
 231         unsigned int pmask;             /* port access rights mask */
 232         unsigned int nexactf;           /* N exact MPS filters */
 233         unsigned int r_caps;            /* read capabilities */
 234         unsigned int wx_caps;           /* write/execute capabilities */
 235 };
 236
 237 struct adapter_params {
 238         struct sge_params sge;
 239         struct tp_params  tp;
 240         struct vpd_params vpd;
 241         struct pci_params pci;
 242         struct devlog_params devlog;
 243         struct rss_params rss;
 244         struct pf_resources pfres;
 245         struct vf_resources vfres;
 246         enum pcie_memwin drv_memwin;
 247
 248         unsigned int sf_size;             /* serial flash size in bytes */
 249         unsigned int sf_nsec;             /* # of flash sectors */
 250
 251         unsigned int fw_vers;
 252         unsigned int bs_vers;
 253         unsigned int tp_vers;
 254         unsigned int er_vers;
 255
 256         unsigned short mtus[NMTUS];
 257         unsigned short a_wnd[NCCTRL_WIN];
 258         unsigned short b_wnd[NCCTRL_WIN];
 259
 260         unsigned int mc_size;             /* MC memory size */
 261         unsigned int cim_la_size;
 262
 263         unsigned char nports;             /* # of ethernet ports */
 264         unsigned char portvec;
 265
 266         unsigned char hash_filter;
 267
 268         enum chip_type chip;              /* chip code */
 269         struct arch_specific_params arch; /* chip specific params */
 270
 271         bool ulptx_memwrite_dsgl;          /* use of T5 DSGL allowed */
 272         u8 fw_caps_support;               /* 32-bit Port Capabilities */
 273 };
 274
 275 /* Firmware Port Capabilities types.
 276  */
 277 typedef u16 fw_port_cap16_t;    /* 16-bit Port Capabilities integral value */
 278 typedef u32 fw_port_cap32_t;    /* 32-bit Port Capabilities integral value */
 279
 280 enum fw_caps {
 281         FW_CAPS_UNKNOWN = 0,    /* 0'ed out initial state */
 282         FW_CAPS16       = 1,    /* old Firmware: 16-bit Port Capabilities */
 283         FW_CAPS32       = 2,    /* new Firmware: 32-bit Port Capabilities */
 284 };
 285
 286 struct link_config {
 287         fw_port_cap32_t pcaps;          /* link capabilities */
 288         fw_port_cap32_t acaps;          /* advertised capabilities */
 289
 290         u32 requested_speed;            /* speed (Mb/s) user has requested */
 291         u32 speed;                      /* actual link speed (Mb/s) */
 292
 293         enum cc_pause requested_fc;     /* flow control user has requested */
 294         enum cc_pause fc;               /* actual link flow control */
 295
 296         enum cc_fec auto_fec;           /* Forward Error Correction
 297                                          * "automatic" (IEEE 802.3)
 298                                          */
 299         enum cc_fec requested_fec;      /* Forward Error Correction requested */
 300         enum cc_fec fec;                /* Forward Error Correction actual */
 301
 302         unsigned char autoneg;          /* autonegotiating? */
 303
 304         unsigned char link_ok;          /* link up? */
 305         unsigned char link_down_rc;     /* link down reason */
 306 };
 307
 308 #include "adapter.h"
 309
 310 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
 311                       u32 val);
 312 int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
 313                         int polarity,
 314                         int attempts, int delay, u32 *valp);
 315
 316 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
 317                                   int polarity, int attempts, int delay)
 318 {
 319         return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
 320                                    delay, NULL);
 321 }
 322
 323 static inline int is_pf4(struct adapter *adap)
 324 {
 325         return adap->pf == 4;
 326 }
 327
 328 #define for_each_port(adapter, iter) \
 329         for (iter = 0; iter < (adapter)->params.nports; ++iter)
 330
 331 static inline int is_hashfilter(const struct adapter *adap)
 332 {
 333         return adap->params.hash_filter;
 334 }
 335
 336 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
 337 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
 338                             unsigned int mask, unsigned int val);
 339 void t4_intr_enable(struct adapter *adapter);
 340 void t4_intr_disable(struct adapter *adapter);
 341 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
 342                   struct link_config *lc);
 343 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
 344                   const unsigned short *alpha, const unsigned short *beta);
 345 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
 346                 enum dev_master master, enum dev_state *state);
 347 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
 348 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
 349 int t4vf_fw_reset(struct adapter *adap);
 350 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
 351 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
 352 int t4_fl_pkt_align(struct adapter *adap);
 353 int t4vf_fl_pkt_align(struct adapter *adap, u32 sge_control, u32 sge_control2);
 354 int t4vf_get_vfres(struct adapter *adap);
 355 int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
 356                                 unsigned int cache_line_size,
 357                                 enum chip_type chip_compat);
 358 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
 359                          unsigned int cache_line_size);
 360 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
 361 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
 362                     unsigned int vf, unsigned int nparams, const u32 *params,
 363                     u32 *val);
 364 int t4vf_query_params(struct adapter *adap, unsigned int nparams,
 365                       const u32 *params, u32 *vals);
 366 int t4vf_get_dev_params(struct adapter *adap);
 367 int t4vf_get_vpd_params(struct adapter *adap);
 368 int t4vf_get_rss_glb_config(struct adapter *adap);
 369 int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
 370                     const u32 *params, const u32 *vals);
 371 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
 372                           unsigned int pf, unsigned int vf,
 373                           unsigned int nparams, const u32 *params,
 374                           const u32 *val, int timeout);
 375 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
 376                   unsigned int vf, unsigned int nparams, const u32 *params,
 377                   const u32 *val);
 378 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
 379                      unsigned int port, unsigned int pf, unsigned int vf,
 380                      unsigned int nmac, u8 *mac, unsigned int *rss_size,
 381                      unsigned int portfunc, unsigned int idstype);
 382 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
 383                 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
 384                 unsigned int *rss_size);
 385 int t4_free_vi(struct adapter *adap, unsigned int mbox,
 386                unsigned int pf, unsigned int vf,
 387                unsigned int viid);
 388 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
 389                   int mtu, int promisc, int all_multi, int bcast, int vlanex,
 390                   bool sleep_ok);
 391 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
 392                   int idx, const u8 *addr, bool persist, bool add_smt);
 393 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
 394                         unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
 395 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
 396                  bool rx_en, bool tx_en);
 397 int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
 398                      unsigned int pf, unsigned int vf, unsigned int iqid,
 399                      unsigned int fl0id, unsigned int fl1id);
 400 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
 401                unsigned int vf, unsigned int iqtype, unsigned int iqid,
 402                unsigned int fl0id, unsigned int fl1id);
 403 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
 404                    unsigned int vf, unsigned int eqid);
 405 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
 406                     unsigned int vf, unsigned int eqid);
 407
 408 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
 409 {
 410         return adap->params.vpd.cclk / 1000;
 411 }
 412
 413 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
 414                                             unsigned int us)
 415 {
 416         return (us * adap->params.vpd.cclk) / 1000;
 417 }
 418
 419 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
 420                                             unsigned int ticks)
 421 {
 422         /* add Core Clock / 2 to round ticks to nearest uS */
 423         return ((ticks * 1000 + adapter->params.vpd.cclk / 2) /
 424                 adapter->params.vpd.cclk);
 425 }
 426
 427 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 428                             int size, void *rpl, bool sleep_ok, int timeout);
 429 int t4_wr_mbox_meat(struct adapter *adap, int mbox,
 430                     const void __attribute__((__may_alias__)) *cmd, int size,
 431                     void *rpl, bool sleep_ok);
 432
 433 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
 434                                      const void *cmd, int size, void *rpl,
 435                                      int timeout)
 436 {
 437         return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
 438                                        timeout);
 439 }
 440
 441 int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);
 442
 443 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
 444                              int size, void *rpl)
 445 {
 446         return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
 447 }
 448
 449 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
 450                                 int size, void *rpl)
 451 {
 452         return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
 453 }
 454
 455 int t4vf_wr_mbox_core(struct adapter *, const void *, int, void *, bool);
 456
 457 static inline int t4vf_wr_mbox(struct adapter *adapter, const void *cmd,
 458                                int size, void *rpl)
 459 {
 460         return t4vf_wr_mbox_core(adapter, cmd, size, rpl, true);
 461 }
 462
 463 static inline int t4vf_wr_mbox_ns(struct adapter *adapter, const void *cmd,
 464                                   int size, void *rpl)
 465 {
 466         return t4vf_wr_mbox_core(adapter, cmd, size, rpl, false);
 467 }
 468
 469
 470 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 471                       unsigned int data_reg, u32 *vals, unsigned int nregs,
 472                       unsigned int start_idx);
 473 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 474                        unsigned int data_reg, const u32 *vals,
 475                        unsigned int nregs, unsigned int start_idx);
 476
 477 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
 478 int t4_get_pfres(struct adapter *adapter);
 479 int t4_read_flash(struct adapter *adapter, unsigned int addr,
 480                   unsigned int nwords, u32 *data, int byte_oriented);
 481 int t4_flash_cfg_addr(struct adapter *adapter);
 482 unsigned int t4_get_mps_bg_map(struct adapter *adapter, unsigned int pidx);
 483 unsigned int t4_get_tp_ch_map(struct adapter *adapter, unsigned int pidx);
 484 const char *t4_get_port_type_description(enum fw_port_type port_type);
 485 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
 486 void t4vf_get_port_stats(struct adapter *adapter, int pidx,
 487                          struct port_stats *p);
 488 void t4_get_port_stats_offset(struct adapter *adap, int idx,
 489                               struct port_stats *stats,
 490                               struct port_stats *offset);
 491 void t4_clr_port_stats(struct adapter *adap, int idx);
 492 void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
 493                       fw_port_cap32_t acaps);
 494 void t4_reset_link_config(struct adapter *adap, int idx);
 495 int t4_get_version_info(struct adapter *adapter);
 496 void t4_dump_version_info(struct adapter *adapter);
 497 int t4_get_flash_params(struct adapter *adapter);
 498 int t4_get_chip_type(struct adapter *adap, int ver);
 499 int t4_prep_adapter(struct adapter *adapter);
 500 int t4vf_prep_adapter(struct adapter *adapter);
 501 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
 502 int t4vf_port_init(struct adapter *adap);
 503 int t4_init_rss_mode(struct adapter *adap, int mbox);
 504 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
 505                         int start, int n, const u16 *rspq, unsigned int nrspq);
 506 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
 507                      unsigned int flags, unsigned int defq);
 508 int t4_read_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
 509                           u64 *flags, unsigned int *defq);
 510 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
 511                      unsigned int start_index, unsigned int rw);
 512 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx);
 513 void t4_read_rss_key(struct adapter *adap, u32 *key);
 514
 515 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
 516 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
 517                       unsigned int qtype, u64 *pbar2_qoffset,
 518                       unsigned int *pbar2_qid);
 519
 520 int t4_init_sge_params(struct adapter *adapter);
 521 int t4_init_tp_params(struct adapter *adap);
 522 int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
 523 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
 524 unsigned int t4_get_regs_len(struct adapter *adap);
 525 unsigned int t4vf_get_pf_from_vf(struct adapter *adap);
 526 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
 527 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
 528 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
 529 int t4_seeprom_wp(struct adapter *adapter, int enable);
 530 int t4_memory_rw_addr(struct adapter *adap, int win,
 531                       u32 addr, u32 len, void *hbuf, int dir);
 532 int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr,
 533                        u32 len, void *hbuf, int dir);
 534 static inline int t4_memory_rw(struct adapter *adap, int win,
 535                                int mtype, u32 maddr, u32 len,
 536                                void *hbuf, int dir)
 537 {
 538         return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir);
 539 }
 540 fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
 541 #endif /* __CHELSIO_COMMON_H */