ceph/src/spdk/dpdk/drivers/net/cxgbe/cxgbe_filter.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #ifndef _CXGBE_FILTER_H_
   7 #define _CXGBE_FILTER_H_
   8
   9 #include "t4_msg.h"
  10 /*
  11  * Defined bit width of user definable filter tuples
  12  */
  13 #define ETHTYPE_BITWIDTH 16
  14 #define FRAG_BITWIDTH 1
  15 #define MACIDX_BITWIDTH 9
  16 #define FCOE_BITWIDTH 1
  17 #define IPORT_BITWIDTH 3
  18 #define MATCHTYPE_BITWIDTH 3
  19 #define PROTO_BITWIDTH 8
  20 #define TOS_BITWIDTH 8
  21 #define PF_BITWIDTH 8
  22 #define VF_BITWIDTH 8
  23 #define IVLAN_BITWIDTH 16
  24 #define OVLAN_BITWIDTH 16
  25
  26 /*
  27  * Filter matching rules.  These consist of a set of ingress packet field
  28  * (value, mask) tuples.  The associated ingress packet field matches the
  29  * tuple when ((field & mask) == value).  (Thus a wildcard "don't care" field
  30  * rule can be constructed by specifying a tuple of (0, 0).)  A filter rule
  31  * matches an ingress packet when all of the individual individual field
  32  * matching rules are true.
  33  *
  34  * Partial field masks are always valid, however, while it may be easy to
  35  * understand their meanings for some fields (e.g. IP address to match a
  36  * subnet), for others making sensible partial masks is less intuitive (e.g.
  37  * MPS match type) ...
  38  */
  39 struct ch_filter_tuple {
  40         /*
  41          * Compressed header matching field rules.  The TP_VLAN_PRI_MAP
  42          * register selects which of these fields will participate in the
  43          * filter match rules -- up to a maximum of 36 bits.  Because
  44          * TP_VLAN_PRI_MAP is a global register, all filters must use the same
  45          * set of fields.
  46          */
  47         uint32_t ethtype:ETHTYPE_BITWIDTH;      /* Ethernet type */
  48         uint32_t frag:FRAG_BITWIDTH;            /* IP fragmentation header */
  49         uint32_t ivlan_vld:1;                   /* inner VLAN valid */
  50         uint32_t ovlan_vld:1;                   /* outer VLAN valid */
  51         uint32_t pfvf_vld:1;                    /* PF/VF valid */
  52         uint32_t macidx:MACIDX_BITWIDTH;        /* exact match MAC index */
  53         uint32_t fcoe:FCOE_BITWIDTH;            /* FCoE packet */
  54         uint32_t iport:IPORT_BITWIDTH;          /* ingress port */
  55         uint32_t matchtype:MATCHTYPE_BITWIDTH;  /* MPS match type */
  56         uint32_t proto:PROTO_BITWIDTH;          /* protocol type */
  57         uint32_t tos:TOS_BITWIDTH;              /* TOS/Traffic Type */
  58         uint32_t pf:PF_BITWIDTH;                /* PCI-E PF ID */
  59         uint32_t vf:VF_BITWIDTH;                /* PCI-E VF ID */
  60         uint32_t ivlan:IVLAN_BITWIDTH;          /* inner VLAN */
  61         uint32_t ovlan:OVLAN_BITWIDTH;          /* outer VLAN */
  62
  63         /*
  64          * Uncompressed header matching field rules.  These are always
  65          * available for field rules.
  66          */
  67         uint8_t lip[16];        /* local IP address (IPv4 in [3:0]) */
  68         uint8_t fip[16];        /* foreign IP address (IPv4 in [3:0]) */
  69         uint16_t lport;         /* local port */
  70         uint16_t fport;         /* foreign port */
  71
  72         /* reservations for future additions */
  73         uint8_t rsvd[12];
  74 };
  75
  76 /*
  77  * Filter specification
  78  */
  79 struct ch_filter_specification {
  80         /* Administrative fields for filter. */
  81         uint32_t hitcnts:1;     /* count filter hits in TCB */
  82         uint32_t prio:1;        /* filter has priority over active/server */
  83
  84         /*
  85          * Fundamental filter typing.  This is the one element of filter
  86          * matching that doesn't exist as a (value, mask) tuple.
  87          */
  88         uint32_t type:1;        /* 0 => IPv4, 1 => IPv6 */
  89         uint32_t cap:1;         /* 0 => LE-TCAM, 1 => Hash */
  90
  91         /*
  92          * Packet dispatch information.  Ingress packets which match the
  93          * filter rules will be dropped, passed to the host or switched back
  94          * out as egress packets.
  95          */
  96         uint32_t action:2;      /* drop, pass, switch */
  97
  98         uint32_t dirsteer:1;    /* 0 => RSS, 1 => steer to iq */
  99         uint32_t iq:10;         /* ingress queue */
 100
 101         uint32_t eport:2;       /* egress port to switch packet out */
 102
 103         /* Filter rule value/mask pairs. */
 104         struct ch_filter_tuple val;
 105         struct ch_filter_tuple mask;
 106 };
 107
 108 enum {
 109         FILTER_PASS = 0,        /* default */
 110         FILTER_DROP,
 111         FILTER_SWITCH
 112 };
 113
 114 enum filter_type {
 115         FILTER_TYPE_IPV4 = 0,
 116         FILTER_TYPE_IPV6,
 117 };
 118
 119 struct t4_completion {
 120         unsigned int done;       /* completion done (0 - No, 1 - Yes) */
 121         rte_spinlock_t lock;     /* completion lock */
 122 };
 123
 124 /*
 125  * Filter operation context to allow callers to wait for
 126  * an asynchronous completion.
 127  */
 128 struct filter_ctx {
 129         struct t4_completion completion; /* completion rendezvous */
 130         int result;                      /* result of operation */
 131         u32 tid;                         /* to store tid of hash filter */
 132 };
 133
 134 /*
 135  * Host shadow copy of ingress filter entry.  This is in host native format
 136  * and doesn't match the ordering or bit order, etc. of the hardware or the
 137  * firmware command.
 138  */
 139 struct filter_entry {
 140         /*
 141          * Administrative fields for filter.
 142          */
 143         u32 valid:1;                /* filter allocated and valid */
 144         u32 locked:1;               /* filter is administratively locked */
 145         u32 pending:1;              /* filter action is pending FW reply */
 146         struct filter_ctx *ctx;     /* caller's completion hook */
 147         struct clip_entry *clipt;   /* CLIP Table entry for IPv6 */
 148         struct rte_eth_dev *dev;    /* Port's rte eth device */
 149         void *private;              /* For use by apps using filter_entry */
 150
 151         /* This will store the actual tid */
 152         u32 tid;
 153
 154         /*
 155          * The filter itself.
 156          */
 157         struct ch_filter_specification fs;
 158 };
 159
 160 #define FILTER_ID_MAX   (~0U)
 161
 162 struct tid_info;
 163 struct adapter;
 164
 165 /**
 166  * Find first clear bit in the bitmap.
 167  */
 168 static inline unsigned int cxgbe_find_first_zero_bit(struct rte_bitmap *bmap,
 169                                                      unsigned int size)
 170 {
 171         unsigned int idx;
 172
 173         for (idx = 0; idx < size; idx++)
 174                 if (!rte_bitmap_get(bmap, idx))
 175                         break;
 176
 177         return idx;
 178 }
 179
 180 /**
 181  * Find a free region of 'num' consecutive entries.
 182  */
 183 static inline unsigned int
 184 cxgbe_bitmap_find_free_region(struct rte_bitmap *bmap, unsigned int size,
 185                               unsigned int num)
 186 {
 187         unsigned int idx, j, free = 0;
 188
 189         if (num > size)
 190                 return size;
 191
 192         for (idx = 0; idx < size; idx += num) {
 193                 for (j = 0; j < num; j++) {
 194                         if (!rte_bitmap_get(bmap, idx + j)) {
 195                                 free++;
 196                         } else {
 197                                 free = 0;
 198                                 break;
 199                         }
 200                 }
 201
 202                 /* Found the Region */
 203                 if (free == num)
 204                         break;
 205
 206                 /* Reached the end and still no region found */
 207                 if ((idx + num) > size) {
 208                         idx = size;
 209                         break;
 210                 }
 211         }
 212
 213         return idx;
 214 }
 215
 216 bool is_filter_set(struct tid_info *, int fidx, int family);
 217 void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl);
 218 void clear_filter(struct filter_entry *f);
 219 int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx);
 220 int writable_filter(struct filter_entry *f);
 221 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 222                      struct ch_filter_specification *fs,
 223                      struct filter_ctx *ctx);
 224 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 225                      struct ch_filter_specification *fs,
 226                      struct filter_ctx *ctx);
 227 int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family);
 228 int init_hash_filter(struct adapter *adap);
 229 void hash_filter_rpl(struct adapter *adap, const struct cpl_act_open_rpl *rpl);
 230 void hash_del_filter_rpl(struct adapter *adap,
 231                          const struct cpl_abort_rpl_rss *rpl);
 232 int validate_filter(struct adapter *adap, struct ch_filter_specification *fs);
 233 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
 234                            u64 *c, int hash, bool get_byte);
 235 #endif /* _CXGBE_FILTER_H_ */