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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / dpaa / dpaa_ethdev.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2017 NXP
5 *
6 */
7 /* System headers */
8 #include <stdio.h>
9 #include <inttypes.h>
10 #include <unistd.h>
11 #include <limits.h>
12 #include <sched.h>
13 #include <signal.h>
14 #include <pthread.h>
15 #include <sys/types.h>
16 #include <sys/syscall.h>
17
18 #include <rte_byteorder.h>
19 #include <rte_common.h>
20 #include <rte_interrupts.h>
21 #include <rte_log.h>
22 #include <rte_debug.h>
23 #include <rte_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
28 #include <rte_eal.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_malloc.h>
33 #include <rte_ring.h>
34
35 #include <rte_dpaa_bus.h>
36 #include <rte_dpaa_logs.h>
37 #include <dpaa_mempool.h>
38
39 #include <dpaa_ethdev.h>
40 #include <dpaa_rxtx.h>
41 #include <rte_pmd_dpaa.h>
42
43 #include <fsl_usd.h>
44 #include <fsl_qman.h>
45 #include <fsl_bman.h>
46 #include <fsl_fman.h>
47
48 /* Supported Rx offloads */
49 static uint64_t dev_rx_offloads_sup =
50 DEV_RX_OFFLOAD_JUMBO_FRAME;
51
52 /* Rx offloads which cannot be disabled */
53 static uint64_t dev_rx_offloads_nodis =
54 DEV_RX_OFFLOAD_IPV4_CKSUM |
55 DEV_RX_OFFLOAD_UDP_CKSUM |
56 DEV_RX_OFFLOAD_TCP_CKSUM |
57 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
58 DEV_RX_OFFLOAD_CRC_STRIP |
59 DEV_RX_OFFLOAD_SCATTER;
60
61 /* Supported Tx offloads */
62 static uint64_t dev_tx_offloads_sup;
63
64 /* Tx offloads which cannot be disabled */
65 static uint64_t dev_tx_offloads_nodis =
66 DEV_TX_OFFLOAD_IPV4_CKSUM |
67 DEV_TX_OFFLOAD_UDP_CKSUM |
68 DEV_TX_OFFLOAD_TCP_CKSUM |
69 DEV_TX_OFFLOAD_SCTP_CKSUM |
70 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
71 DEV_TX_OFFLOAD_MULTI_SEGS |
72 DEV_TX_OFFLOAD_MT_LOCKFREE |
73 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
74
75 /* Keep track of whether QMAN and BMAN have been globally initialized */
76 static int is_global_init;
77 static int default_q; /* use default queue - FMC is not executed*/
78 /* At present we only allow up to 4 push mode queues as default - as each of
79 * this queue need dedicated portal and we are short of portals.
80 */
81 #define DPAA_MAX_PUSH_MODE_QUEUE 8
82 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
83
84 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
85 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
86
87
88 /* Per FQ Taildrop in frame count */
89 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
90
91 struct rte_dpaa_xstats_name_off {
92 char name[RTE_ETH_XSTATS_NAME_SIZE];
93 uint32_t offset;
94 };
95
96 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
97 {"rx_align_err",
98 offsetof(struct dpaa_if_stats, raln)},
99 {"rx_valid_pause",
100 offsetof(struct dpaa_if_stats, rxpf)},
101 {"rx_fcs_err",
102 offsetof(struct dpaa_if_stats, rfcs)},
103 {"rx_vlan_frame",
104 offsetof(struct dpaa_if_stats, rvlan)},
105 {"rx_frame_err",
106 offsetof(struct dpaa_if_stats, rerr)},
107 {"rx_drop_err",
108 offsetof(struct dpaa_if_stats, rdrp)},
109 {"rx_undersized",
110 offsetof(struct dpaa_if_stats, rund)},
111 {"rx_oversize_err",
112 offsetof(struct dpaa_if_stats, rovr)},
113 {"rx_fragment_pkt",
114 offsetof(struct dpaa_if_stats, rfrg)},
115 {"tx_valid_pause",
116 offsetof(struct dpaa_if_stats, txpf)},
117 {"tx_fcs_err",
118 offsetof(struct dpaa_if_stats, terr)},
119 {"tx_vlan_frame",
120 offsetof(struct dpaa_if_stats, tvlan)},
121 {"rx_undersized",
122 offsetof(struct dpaa_if_stats, tund)},
123 };
124
125 static struct rte_dpaa_driver rte_dpaa_pmd;
126
127 static void
128 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
129
130 static inline void
131 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
132 {
133 memset(opts, 0, sizeof(struct qm_mcc_initfq));
134 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
135 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
136 QM_FQCTRL_PREFERINCACHE;
137 opts->fqd.context_a.stashing.exclusive = 0;
138 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
139 opts->fqd.context_a.stashing.annotation_cl =
140 DPAA_IF_RX_ANNOTATION_STASH;
141 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
142 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
143 }
144
145 static int
146 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
147 {
148 struct dpaa_if *dpaa_intf = dev->data->dev_private;
149 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
150 + VLAN_TAG_SIZE;
151
152 PMD_INIT_FUNC_TRACE();
153
154 if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
155 return -EINVAL;
156 if (frame_size > ETHER_MAX_LEN)
157 dev->data->dev_conf.rxmode.offloads &=
158 DEV_RX_OFFLOAD_JUMBO_FRAME;
159 else
160 dev->data->dev_conf.rxmode.offloads &=
161 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
162
163 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
164
165 fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
166
167 return 0;
168 }
169
170 static int
171 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
172 {
173 struct dpaa_if *dpaa_intf = dev->data->dev_private;
174 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
175 uint64_t rx_offloads = eth_conf->rxmode.offloads;
176 uint64_t tx_offloads = eth_conf->txmode.offloads;
177
178 PMD_INIT_FUNC_TRACE();
179
180 /* Rx offloads validation */
181 if (dev_rx_offloads_nodis & ~rx_offloads) {
182 DPAA_PMD_WARN(
183 "Rx offloads non configurable - requested 0x%" PRIx64
184 " ignored 0x%" PRIx64,
185 rx_offloads, dev_rx_offloads_nodis);
186 }
187
188 /* Tx offloads validation */
189 if (dev_tx_offloads_nodis & ~tx_offloads) {
190 DPAA_PMD_WARN(
191 "Tx offloads non configurable - requested 0x%" PRIx64
192 " ignored 0x%" PRIx64,
193 tx_offloads, dev_tx_offloads_nodis);
194 }
195
196 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
197 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
198 DPAA_MAX_RX_PKT_LEN) {
199 fman_if_set_maxfrm(dpaa_intf->fif,
200 dev->data->dev_conf.rxmode.max_rx_pkt_len);
201 return 0;
202 } else {
203 return -1;
204 }
205 }
206 return 0;
207 }
208
209 static const uint32_t *
210 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
211 {
212 static const uint32_t ptypes[] = {
213 /*todo -= add more types */
214 RTE_PTYPE_L2_ETHER,
215 RTE_PTYPE_L3_IPV4,
216 RTE_PTYPE_L3_IPV4_EXT,
217 RTE_PTYPE_L3_IPV6,
218 RTE_PTYPE_L3_IPV6_EXT,
219 RTE_PTYPE_L4_TCP,
220 RTE_PTYPE_L4_UDP,
221 RTE_PTYPE_L4_SCTP
222 };
223
224 PMD_INIT_FUNC_TRACE();
225
226 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
227 return ptypes;
228 return NULL;
229 }
230
231 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
232 {
233 struct dpaa_if *dpaa_intf = dev->data->dev_private;
234
235 PMD_INIT_FUNC_TRACE();
236
237 /* Change tx callback to the real one */
238 dev->tx_pkt_burst = dpaa_eth_queue_tx;
239 fman_if_enable_rx(dpaa_intf->fif);
240
241 return 0;
242 }
243
244 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
245 {
246 struct dpaa_if *dpaa_intf = dev->data->dev_private;
247
248 PMD_INIT_FUNC_TRACE();
249
250 fman_if_disable_rx(dpaa_intf->fif);
251 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
252 }
253
254 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
255 {
256 PMD_INIT_FUNC_TRACE();
257
258 dpaa_eth_dev_stop(dev);
259 }
260
261 static int
262 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
263 char *fw_version,
264 size_t fw_size)
265 {
266 int ret;
267 FILE *svr_file = NULL;
268 unsigned int svr_ver = 0;
269
270 PMD_INIT_FUNC_TRACE();
271
272 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
273 if (!svr_file) {
274 DPAA_PMD_ERR("Unable to open SoC device");
275 return -ENOTSUP; /* Not supported on this infra */
276 }
277 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
278 dpaa_svr_family = svr_ver & SVR_MASK;
279 else
280 DPAA_PMD_ERR("Unable to read SoC device");
281
282 fclose(svr_file);
283
284 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
285 svr_ver, fman_ip_rev);
286 ret += 1; /* add the size of '\0' */
287
288 if (fw_size < (uint32_t)ret)
289 return ret;
290 else
291 return 0;
292 }
293
294 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
295 struct rte_eth_dev_info *dev_info)
296 {
297 struct dpaa_if *dpaa_intf = dev->data->dev_private;
298
299 PMD_INIT_FUNC_TRACE();
300
301 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
302 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
303 dev_info->min_rx_bufsize = DPAA_MIN_RX_BUF_SIZE;
304 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
305 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
306 dev_info->max_hash_mac_addrs = 0;
307 dev_info->max_vfs = 0;
308 dev_info->max_vmdq_pools = ETH_16_POOLS;
309 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
310 dev_info->speed_capa = (ETH_LINK_SPEED_1G |
311 ETH_LINK_SPEED_10G);
312 dev_info->rx_offload_capa = dev_rx_offloads_sup |
313 dev_rx_offloads_nodis;
314 dev_info->tx_offload_capa = dev_tx_offloads_sup |
315 dev_tx_offloads_nodis;
316 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
317 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
318 }
319
320 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
321 int wait_to_complete __rte_unused)
322 {
323 struct dpaa_if *dpaa_intf = dev->data->dev_private;
324 struct rte_eth_link *link = &dev->data->dev_link;
325
326 PMD_INIT_FUNC_TRACE();
327
328 if (dpaa_intf->fif->mac_type == fman_mac_1g)
329 link->link_speed = ETH_SPEED_NUM_1G;
330 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
331 link->link_speed = ETH_SPEED_NUM_10G;
332 else
333 DPAA_PMD_ERR("invalid link_speed: %s, %d",
334 dpaa_intf->name, dpaa_intf->fif->mac_type);
335
336 link->link_status = dpaa_intf->valid;
337 link->link_duplex = ETH_LINK_FULL_DUPLEX;
338 link->link_autoneg = ETH_LINK_AUTONEG;
339 return 0;
340 }
341
342 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
343 struct rte_eth_stats *stats)
344 {
345 struct dpaa_if *dpaa_intf = dev->data->dev_private;
346
347 PMD_INIT_FUNC_TRACE();
348
349 fman_if_stats_get(dpaa_intf->fif, stats);
350 return 0;
351 }
352
353 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
354 {
355 struct dpaa_if *dpaa_intf = dev->data->dev_private;
356
357 PMD_INIT_FUNC_TRACE();
358
359 fman_if_stats_reset(dpaa_intf->fif);
360 }
361
362 static int
363 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
364 unsigned int n)
365 {
366 struct dpaa_if *dpaa_intf = dev->data->dev_private;
367 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
368 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
369
370 if (n < num)
371 return num;
372
373 if (xstats == NULL)
374 return 0;
375
376 fman_if_stats_get_all(dpaa_intf->fif, values,
377 sizeof(struct dpaa_if_stats) / 8);
378
379 for (i = 0; i < num; i++) {
380 xstats[i].id = i;
381 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
382 }
383 return i;
384 }
385
386 static int
387 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
388 struct rte_eth_xstat_name *xstats_names,
389 unsigned int limit)
390 {
391 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
392
393 if (limit < stat_cnt)
394 return stat_cnt;
395
396 if (xstats_names != NULL)
397 for (i = 0; i < stat_cnt; i++)
398 snprintf(xstats_names[i].name,
399 sizeof(xstats_names[i].name),
400 "%s",
401 dpaa_xstats_strings[i].name);
402
403 return stat_cnt;
404 }
405
406 static int
407 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
408 uint64_t *values, unsigned int n)
409 {
410 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
411 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
412
413 if (!ids) {
414 struct dpaa_if *dpaa_intf = dev->data->dev_private;
415
416 if (n < stat_cnt)
417 return stat_cnt;
418
419 if (!values)
420 return 0;
421
422 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
423 sizeof(struct dpaa_if_stats) / 8);
424
425 for (i = 0; i < stat_cnt; i++)
426 values[i] =
427 values_copy[dpaa_xstats_strings[i].offset / 8];
428
429 return stat_cnt;
430 }
431
432 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
433
434 for (i = 0; i < n; i++) {
435 if (ids[i] >= stat_cnt) {
436 DPAA_PMD_ERR("id value isn't valid");
437 return -1;
438 }
439 values[i] = values_copy[ids[i]];
440 }
441 return n;
442 }
443
444 static int
445 dpaa_xstats_get_names_by_id(
446 struct rte_eth_dev *dev,
447 struct rte_eth_xstat_name *xstats_names,
448 const uint64_t *ids,
449 unsigned int limit)
450 {
451 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
452 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
453
454 if (!ids)
455 return dpaa_xstats_get_names(dev, xstats_names, limit);
456
457 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
458
459 for (i = 0; i < limit; i++) {
460 if (ids[i] >= stat_cnt) {
461 DPAA_PMD_ERR("id value isn't valid");
462 return -1;
463 }
464 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
465 }
466 return limit;
467 }
468
469 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
470 {
471 struct dpaa_if *dpaa_intf = dev->data->dev_private;
472
473 PMD_INIT_FUNC_TRACE();
474
475 fman_if_promiscuous_enable(dpaa_intf->fif);
476 }
477
478 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
479 {
480 struct dpaa_if *dpaa_intf = dev->data->dev_private;
481
482 PMD_INIT_FUNC_TRACE();
483
484 fman_if_promiscuous_disable(dpaa_intf->fif);
485 }
486
487 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
488 {
489 struct dpaa_if *dpaa_intf = dev->data->dev_private;
490
491 PMD_INIT_FUNC_TRACE();
492
493 fman_if_set_mcast_filter_table(dpaa_intf->fif);
494 }
495
496 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
497 {
498 struct dpaa_if *dpaa_intf = dev->data->dev_private;
499
500 PMD_INIT_FUNC_TRACE();
501
502 fman_if_reset_mcast_filter_table(dpaa_intf->fif);
503 }
504
505 static
506 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
507 uint16_t nb_desc,
508 unsigned int socket_id __rte_unused,
509 const struct rte_eth_rxconf *rx_conf __rte_unused,
510 struct rte_mempool *mp)
511 {
512 struct dpaa_if *dpaa_intf = dev->data->dev_private;
513 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
514 struct qm_mcc_initfq opts = {0};
515 u32 flags = 0;
516 int ret;
517
518 PMD_INIT_FUNC_TRACE();
519
520 if (queue_idx >= dev->data->nb_rx_queues) {
521 rte_errno = EOVERFLOW;
522 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
523 (void *)dev, queue_idx, dev->data->nb_rx_queues);
524 return -rte_errno;
525 }
526
527 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
528 queue_idx, rxq->fqid);
529
530 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
531 struct fman_if_ic_params icp;
532 uint32_t fd_offset;
533 uint32_t bp_size;
534
535 if (!mp->pool_data) {
536 DPAA_PMD_ERR("Not an offloaded buffer pool!");
537 return -1;
538 }
539 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
540
541 memset(&icp, 0, sizeof(icp));
542 /* set ICEOF for to the default value , which is 0*/
543 icp.iciof = DEFAULT_ICIOF;
544 icp.iceof = DEFAULT_RX_ICEOF;
545 icp.icsz = DEFAULT_ICSZ;
546 fman_if_set_ic_params(dpaa_intf->fif, &icp);
547
548 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
549 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
550
551 /* Buffer pool size should be equal to Dataroom Size*/
552 bp_size = rte_pktmbuf_data_room_size(mp);
553 fman_if_set_bp(dpaa_intf->fif, mp->size,
554 dpaa_intf->bp_info->bpid, bp_size);
555 dpaa_intf->valid = 1;
556 DPAA_PMD_INFO("if =%s - fd_offset = %d offset = %d",
557 dpaa_intf->name, fd_offset,
558 fman_if_get_fdoff(dpaa_intf->fif));
559 }
560 /* checking if push mode only, no error check for now */
561 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
562 dpaa_push_queue_idx++;
563 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
564 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
565 QM_FQCTRL_CTXASTASHING |
566 QM_FQCTRL_PREFERINCACHE;
567 opts.fqd.context_a.stashing.exclusive = 0;
568 /* In muticore scenario stashing becomes a bottleneck on LS1046.
569 * So do not enable stashing in this case
570 */
571 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
572 opts.fqd.context_a.stashing.annotation_cl =
573 DPAA_IF_RX_ANNOTATION_STASH;
574 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
575 opts.fqd.context_a.stashing.context_cl =
576 DPAA_IF_RX_CONTEXT_STASH;
577
578 /*Create a channel and associate given queue with the channel*/
579 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
580 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
581 opts.fqd.dest.channel = rxq->ch_id;
582 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
583 flags = QMAN_INITFQ_FLAG_SCHED;
584
585 /* Configure tail drop */
586 if (dpaa_intf->cgr_rx) {
587 opts.we_mask |= QM_INITFQ_WE_CGID;
588 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
589 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
590 }
591 ret = qman_init_fq(rxq, flags, &opts);
592 if (ret) {
593 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
594 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
595 return ret;
596 }
597 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
598 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
599 rxq->is_static = true;
600 }
601 dev->data->rx_queues[queue_idx] = rxq;
602
603 /* configure the CGR size as per the desc size */
604 if (dpaa_intf->cgr_rx) {
605 struct qm_mcc_initcgr cgr_opts = {0};
606
607 /* Enable tail drop with cgr on this queue */
608 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
609 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
610 if (ret) {
611 DPAA_PMD_WARN(
612 "rx taildrop modify fail on fqid %d (ret=%d)",
613 rxq->fqid, ret);
614 }
615 }
616
617 return 0;
618 }
619
620 int
621 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
622 int eth_rx_queue_id,
623 u16 ch_id,
624 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
625 {
626 int ret;
627 u32 flags = 0;
628 struct dpaa_if *dpaa_intf = dev->data->dev_private;
629 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
630 struct qm_mcc_initfq opts = {0};
631
632 if (dpaa_push_mode_max_queue)
633 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.\n"
634 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
635 dpaa_push_mode_max_queue);
636
637 dpaa_poll_queue_default_config(&opts);
638
639 switch (queue_conf->ev.sched_type) {
640 case RTE_SCHED_TYPE_ATOMIC:
641 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
642 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
643 * configuration with HOLD_ACTIVE setting
644 */
645 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
646 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
647 break;
648 case RTE_SCHED_TYPE_ORDERED:
649 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
650 return -1;
651 default:
652 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
653 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
654 break;
655 }
656
657 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
658 opts.fqd.dest.channel = ch_id;
659 opts.fqd.dest.wq = queue_conf->ev.priority;
660
661 if (dpaa_intf->cgr_rx) {
662 opts.we_mask |= QM_INITFQ_WE_CGID;
663 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
664 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
665 }
666
667 flags = QMAN_INITFQ_FLAG_SCHED;
668
669 ret = qman_init_fq(rxq, flags, &opts);
670 if (ret) {
671 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
672 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
673 return ret;
674 }
675
676 /* copy configuration which needs to be filled during dequeue */
677 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
678 dev->data->rx_queues[eth_rx_queue_id] = rxq;
679
680 return ret;
681 }
682
683 int
684 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
685 int eth_rx_queue_id)
686 {
687 struct qm_mcc_initfq opts;
688 int ret;
689 u32 flags = 0;
690 struct dpaa_if *dpaa_intf = dev->data->dev_private;
691 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
692
693 dpaa_poll_queue_default_config(&opts);
694
695 if (dpaa_intf->cgr_rx) {
696 opts.we_mask |= QM_INITFQ_WE_CGID;
697 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
698 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
699 }
700
701 ret = qman_init_fq(rxq, flags, &opts);
702 if (ret) {
703 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
704 rxq->fqid, ret);
705 }
706
707 rxq->cb.dqrr_dpdk_cb = NULL;
708 dev->data->rx_queues[eth_rx_queue_id] = NULL;
709
710 return 0;
711 }
712
713 static
714 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
715 {
716 PMD_INIT_FUNC_TRACE();
717 }
718
719 static
720 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
721 uint16_t nb_desc __rte_unused,
722 unsigned int socket_id __rte_unused,
723 const struct rte_eth_txconf *tx_conf __rte_unused)
724 {
725 struct dpaa_if *dpaa_intf = dev->data->dev_private;
726
727 PMD_INIT_FUNC_TRACE();
728
729 if (queue_idx >= dev->data->nb_tx_queues) {
730 rte_errno = EOVERFLOW;
731 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
732 (void *)dev, queue_idx, dev->data->nb_tx_queues);
733 return -rte_errno;
734 }
735
736 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
737 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
738 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
739 return 0;
740 }
741
742 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
743 {
744 PMD_INIT_FUNC_TRACE();
745 }
746
747 static uint32_t
748 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
749 {
750 struct dpaa_if *dpaa_intf = dev->data->dev_private;
751 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
752 u32 frm_cnt = 0;
753
754 PMD_INIT_FUNC_TRACE();
755
756 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
757 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
758 rx_queue_id, frm_cnt);
759 }
760 return frm_cnt;
761 }
762
763 static int dpaa_link_down(struct rte_eth_dev *dev)
764 {
765 PMD_INIT_FUNC_TRACE();
766
767 dpaa_eth_dev_stop(dev);
768 return 0;
769 }
770
771 static int dpaa_link_up(struct rte_eth_dev *dev)
772 {
773 PMD_INIT_FUNC_TRACE();
774
775 dpaa_eth_dev_start(dev);
776 return 0;
777 }
778
779 static int
780 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
781 struct rte_eth_fc_conf *fc_conf)
782 {
783 struct dpaa_if *dpaa_intf = dev->data->dev_private;
784 struct rte_eth_fc_conf *net_fc;
785
786 PMD_INIT_FUNC_TRACE();
787
788 if (!(dpaa_intf->fc_conf)) {
789 dpaa_intf->fc_conf = rte_zmalloc(NULL,
790 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
791 if (!dpaa_intf->fc_conf) {
792 DPAA_PMD_ERR("unable to save flow control info");
793 return -ENOMEM;
794 }
795 }
796 net_fc = dpaa_intf->fc_conf;
797
798 if (fc_conf->high_water < fc_conf->low_water) {
799 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
800 return -EINVAL;
801 }
802
803 if (fc_conf->mode == RTE_FC_NONE) {
804 return 0;
805 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
806 fc_conf->mode == RTE_FC_FULL) {
807 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
808 fc_conf->low_water,
809 dpaa_intf->bp_info->bpid);
810 if (fc_conf->pause_time)
811 fman_if_set_fc_quanta(dpaa_intf->fif,
812 fc_conf->pause_time);
813 }
814
815 /* Save the information in dpaa device */
816 net_fc->pause_time = fc_conf->pause_time;
817 net_fc->high_water = fc_conf->high_water;
818 net_fc->low_water = fc_conf->low_water;
819 net_fc->send_xon = fc_conf->send_xon;
820 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
821 net_fc->mode = fc_conf->mode;
822 net_fc->autoneg = fc_conf->autoneg;
823
824 return 0;
825 }
826
827 static int
828 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
829 struct rte_eth_fc_conf *fc_conf)
830 {
831 struct dpaa_if *dpaa_intf = dev->data->dev_private;
832 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
833 int ret;
834
835 PMD_INIT_FUNC_TRACE();
836
837 if (net_fc) {
838 fc_conf->pause_time = net_fc->pause_time;
839 fc_conf->high_water = net_fc->high_water;
840 fc_conf->low_water = net_fc->low_water;
841 fc_conf->send_xon = net_fc->send_xon;
842 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
843 fc_conf->mode = net_fc->mode;
844 fc_conf->autoneg = net_fc->autoneg;
845 return 0;
846 }
847 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
848 if (ret) {
849 fc_conf->mode = RTE_FC_TX_PAUSE;
850 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
851 } else {
852 fc_conf->mode = RTE_FC_NONE;
853 }
854
855 return 0;
856 }
857
858 static int
859 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
860 struct ether_addr *addr,
861 uint32_t index,
862 __rte_unused uint32_t pool)
863 {
864 int ret;
865 struct dpaa_if *dpaa_intf = dev->data->dev_private;
866
867 PMD_INIT_FUNC_TRACE();
868
869 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
870
871 if (ret)
872 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
873 " err = %d", ret);
874 return 0;
875 }
876
877 static void
878 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
879 uint32_t index)
880 {
881 struct dpaa_if *dpaa_intf = dev->data->dev_private;
882
883 PMD_INIT_FUNC_TRACE();
884
885 fman_if_clear_mac_addr(dpaa_intf->fif, index);
886 }
887
888 static int
889 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
890 struct ether_addr *addr)
891 {
892 int ret;
893 struct dpaa_if *dpaa_intf = dev->data->dev_private;
894
895 PMD_INIT_FUNC_TRACE();
896
897 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
898 if (ret)
899 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
900
901 return ret;
902 }
903
904 static struct eth_dev_ops dpaa_devops = {
905 .dev_configure = dpaa_eth_dev_configure,
906 .dev_start = dpaa_eth_dev_start,
907 .dev_stop = dpaa_eth_dev_stop,
908 .dev_close = dpaa_eth_dev_close,
909 .dev_infos_get = dpaa_eth_dev_info,
910 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
911
912 .rx_queue_setup = dpaa_eth_rx_queue_setup,
913 .tx_queue_setup = dpaa_eth_tx_queue_setup,
914 .rx_queue_release = dpaa_eth_rx_queue_release,
915 .tx_queue_release = dpaa_eth_tx_queue_release,
916 .rx_queue_count = dpaa_dev_rx_queue_count,
917
918 .flow_ctrl_get = dpaa_flow_ctrl_get,
919 .flow_ctrl_set = dpaa_flow_ctrl_set,
920
921 .link_update = dpaa_eth_link_update,
922 .stats_get = dpaa_eth_stats_get,
923 .xstats_get = dpaa_dev_xstats_get,
924 .xstats_get_by_id = dpaa_xstats_get_by_id,
925 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
926 .xstats_get_names = dpaa_xstats_get_names,
927 .xstats_reset = dpaa_eth_stats_reset,
928 .stats_reset = dpaa_eth_stats_reset,
929 .promiscuous_enable = dpaa_eth_promiscuous_enable,
930 .promiscuous_disable = dpaa_eth_promiscuous_disable,
931 .allmulticast_enable = dpaa_eth_multicast_enable,
932 .allmulticast_disable = dpaa_eth_multicast_disable,
933 .mtu_set = dpaa_mtu_set,
934 .dev_set_link_down = dpaa_link_down,
935 .dev_set_link_up = dpaa_link_up,
936 .mac_addr_add = dpaa_dev_add_mac_addr,
937 .mac_addr_remove = dpaa_dev_remove_mac_addr,
938 .mac_addr_set = dpaa_dev_set_mac_addr,
939
940 .fw_version_get = dpaa_fw_version_get,
941 };
942
943 static bool
944 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
945 {
946 if (strcmp(dev->device->driver->name,
947 drv->driver.name))
948 return false;
949
950 return true;
951 }
952
953 static bool
954 is_dpaa_supported(struct rte_eth_dev *dev)
955 {
956 return is_device_supported(dev, &rte_dpaa_pmd);
957 }
958
959 int
960 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
961 {
962 struct rte_eth_dev *dev;
963 struct dpaa_if *dpaa_intf;
964
965 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
966
967 dev = &rte_eth_devices[port];
968
969 if (!is_dpaa_supported(dev))
970 return -ENOTSUP;
971
972 dpaa_intf = dev->data->dev_private;
973
974 if (on)
975 fman_if_loopback_enable(dpaa_intf->fif);
976 else
977 fman_if_loopback_disable(dpaa_intf->fif);
978
979 return 0;
980 }
981
982 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
983 {
984 struct rte_eth_fc_conf *fc_conf;
985 int ret;
986
987 PMD_INIT_FUNC_TRACE();
988
989 if (!(dpaa_intf->fc_conf)) {
990 dpaa_intf->fc_conf = rte_zmalloc(NULL,
991 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
992 if (!dpaa_intf->fc_conf) {
993 DPAA_PMD_ERR("unable to save flow control info");
994 return -ENOMEM;
995 }
996 }
997 fc_conf = dpaa_intf->fc_conf;
998 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
999 if (ret) {
1000 fc_conf->mode = RTE_FC_TX_PAUSE;
1001 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1002 } else {
1003 fc_conf->mode = RTE_FC_NONE;
1004 }
1005
1006 return 0;
1007 }
1008
1009 /* Initialise an Rx FQ */
1010 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1011 uint32_t fqid)
1012 {
1013 struct qm_mcc_initfq opts = {0};
1014 int ret;
1015 u32 flags = 0;
1016 struct qm_mcc_initcgr cgr_opts = {
1017 .we_mask = QM_CGR_WE_CS_THRES |
1018 QM_CGR_WE_CSTD_EN |
1019 QM_CGR_WE_MODE,
1020 .cgr = {
1021 .cstd_en = QM_CGR_EN,
1022 .mode = QMAN_CGR_MODE_FRAME
1023 }
1024 };
1025
1026 PMD_INIT_FUNC_TRACE();
1027
1028 ret = qman_reserve_fqid(fqid);
1029 if (ret) {
1030 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1031 fqid, ret);
1032 return -EINVAL;
1033 }
1034
1035 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1036 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1037 if (ret) {
1038 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1039 fqid, ret);
1040 return ret;
1041 }
1042 fq->is_static = false;
1043
1044 dpaa_poll_queue_default_config(&opts);
1045
1046 if (cgr_rx) {
1047 /* Enable tail drop with cgr on this queue */
1048 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1049 cgr_rx->cb = NULL;
1050 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1051 &cgr_opts);
1052 if (ret) {
1053 DPAA_PMD_WARN(
1054 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1055 fqid, ret);
1056 goto without_cgr;
1057 }
1058 opts.we_mask |= QM_INITFQ_WE_CGID;
1059 opts.fqd.cgid = cgr_rx->cgrid;
1060 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1061 }
1062 without_cgr:
1063 ret = qman_init_fq(fq, flags, &opts);
1064 if (ret)
1065 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1066 return ret;
1067 }
1068
1069 /* Initialise a Tx FQ */
1070 static int dpaa_tx_queue_init(struct qman_fq *fq,
1071 struct fman_if *fman_intf)
1072 {
1073 struct qm_mcc_initfq opts = {0};
1074 int ret;
1075
1076 PMD_INIT_FUNC_TRACE();
1077
1078 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1079 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1080 if (ret) {
1081 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1082 return ret;
1083 }
1084 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1085 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1086 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1087 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1088 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1089 opts.fqd.context_b = 0;
1090 /* no tx-confirmation */
1091 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1092 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1093 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1094 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1095 if (ret)
1096 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1097 return ret;
1098 }
1099
1100 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1101 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1102 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1103 {
1104 struct qm_mcc_initfq opts = {0};
1105 int ret;
1106
1107 PMD_INIT_FUNC_TRACE();
1108
1109 ret = qman_reserve_fqid(fqid);
1110 if (ret) {
1111 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1112 fqid, ret);
1113 return -EINVAL;
1114 }
1115 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1116 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1117 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1118 if (ret) {
1119 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1120 fqid, ret);
1121 return ret;
1122 }
1123 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1124 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1125 ret = qman_init_fq(fq, 0, &opts);
1126 if (ret)
1127 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1128 fqid, ret);
1129 return ret;
1130 }
1131 #endif
1132
1133 /* Initialise a network interface */
1134 static int
1135 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1136 {
1137 int num_cores, num_rx_fqs, fqid;
1138 int loop, ret = 0;
1139 int dev_id;
1140 struct rte_dpaa_device *dpaa_device;
1141 struct dpaa_if *dpaa_intf;
1142 struct fm_eth_port_cfg *cfg;
1143 struct fman_if *fman_intf;
1144 struct fman_if_bpool *bp, *tmp_bp;
1145 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1146
1147 PMD_INIT_FUNC_TRACE();
1148
1149 /* For secondary processes, the primary has done all the work */
1150 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1151 return 0;
1152
1153 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1154 dev_id = dpaa_device->id.dev_id;
1155 dpaa_intf = eth_dev->data->dev_private;
1156 cfg = &dpaa_netcfg->port_cfg[dev_id];
1157 fman_intf = cfg->fman_if;
1158
1159 dpaa_intf->name = dpaa_device->name;
1160
1161 /* save fman_if & cfg in the interface struture */
1162 dpaa_intf->fif = fman_intf;
1163 dpaa_intf->ifid = dev_id;
1164 dpaa_intf->cfg = cfg;
1165
1166 /* Initialize Rx FQ's */
1167 if (default_q) {
1168 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1169 } else {
1170 if (getenv("DPAA_NUM_RX_QUEUES"))
1171 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1172 else
1173 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1174 }
1175
1176
1177 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1178 * queues.
1179 */
1180 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1181 DPAA_PMD_ERR("Invalid number of RX queues\n");
1182 return -EINVAL;
1183 }
1184
1185 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1186 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1187 if (!dpaa_intf->rx_queues) {
1188 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1189 return -ENOMEM;
1190 }
1191
1192 /* If congestion control is enabled globally*/
1193 if (td_threshold) {
1194 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1195 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1196 if (!dpaa_intf->cgr_rx) {
1197 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1198 ret = -ENOMEM;
1199 goto free_rx;
1200 }
1201
1202 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1203 if (ret != num_rx_fqs) {
1204 DPAA_PMD_WARN("insufficient CGRIDs available");
1205 ret = -EINVAL;
1206 goto free_rx;
1207 }
1208 } else {
1209 dpaa_intf->cgr_rx = NULL;
1210 }
1211
1212 for (loop = 0; loop < num_rx_fqs; loop++) {
1213 if (default_q)
1214 fqid = cfg->rx_def;
1215 else
1216 fqid = DPAA_PCD_FQID_START + dpaa_intf->ifid *
1217 DPAA_PCD_FQID_MULTIPLIER + loop;
1218
1219 if (dpaa_intf->cgr_rx)
1220 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1221
1222 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1223 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1224 fqid);
1225 if (ret)
1226 goto free_rx;
1227 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1228 }
1229 dpaa_intf->nb_rx_queues = num_rx_fqs;
1230
1231 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1232 num_cores = rte_lcore_count();
1233 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1234 num_cores, MAX_CACHELINE);
1235 if (!dpaa_intf->tx_queues) {
1236 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1237 ret = -ENOMEM;
1238 goto free_rx;
1239 }
1240
1241 for (loop = 0; loop < num_cores; loop++) {
1242 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1243 fman_intf);
1244 if (ret)
1245 goto free_tx;
1246 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1247 }
1248 dpaa_intf->nb_tx_queues = num_cores;
1249
1250 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1251 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1252 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1253 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1254 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1255 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1256 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1257 #endif
1258
1259 DPAA_PMD_DEBUG("All frame queues created");
1260
1261 /* Get the initial configuration for flow control */
1262 dpaa_fc_set_default(dpaa_intf);
1263
1264 /* reset bpool list, initialize bpool dynamically */
1265 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1266 list_del(&bp->node);
1267 free(bp);
1268 }
1269
1270 /* Populate ethdev structure */
1271 eth_dev->dev_ops = &dpaa_devops;
1272 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1273 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1274
1275 /* Allocate memory for storing MAC addresses */
1276 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1277 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1278 if (eth_dev->data->mac_addrs == NULL) {
1279 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1280 "store MAC addresses",
1281 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1282 ret = -ENOMEM;
1283 goto free_tx;
1284 }
1285
1286 /* copy the primary mac address */
1287 ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1288
1289 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1290 dpaa_device->name,
1291 fman_intf->mac_addr.addr_bytes[0],
1292 fman_intf->mac_addr.addr_bytes[1],
1293 fman_intf->mac_addr.addr_bytes[2],
1294 fman_intf->mac_addr.addr_bytes[3],
1295 fman_intf->mac_addr.addr_bytes[4],
1296 fman_intf->mac_addr.addr_bytes[5]);
1297
1298 /* Disable RX mode */
1299 fman_if_discard_rx_errors(fman_intf);
1300 fman_if_disable_rx(fman_intf);
1301 /* Disable promiscuous mode */
1302 fman_if_promiscuous_disable(fman_intf);
1303 /* Disable multicast */
1304 fman_if_reset_mcast_filter_table(fman_intf);
1305 /* Reset interface statistics */
1306 fman_if_stats_reset(fman_intf);
1307
1308 return 0;
1309
1310 free_tx:
1311 rte_free(dpaa_intf->tx_queues);
1312 dpaa_intf->tx_queues = NULL;
1313 dpaa_intf->nb_tx_queues = 0;
1314
1315 free_rx:
1316 rte_free(dpaa_intf->cgr_rx);
1317 rte_free(dpaa_intf->rx_queues);
1318 dpaa_intf->rx_queues = NULL;
1319 dpaa_intf->nb_rx_queues = 0;
1320 return ret;
1321 }
1322
1323 static int
1324 dpaa_dev_uninit(struct rte_eth_dev *dev)
1325 {
1326 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1327 int loop;
1328
1329 PMD_INIT_FUNC_TRACE();
1330
1331 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1332 return -EPERM;
1333
1334 if (!dpaa_intf) {
1335 DPAA_PMD_WARN("Already closed or not started");
1336 return -1;
1337 }
1338
1339 dpaa_eth_dev_close(dev);
1340
1341 /* release configuration memory */
1342 if (dpaa_intf->fc_conf)
1343 rte_free(dpaa_intf->fc_conf);
1344
1345 /* Release RX congestion Groups */
1346 if (dpaa_intf->cgr_rx) {
1347 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1348 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1349
1350 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1351 dpaa_intf->nb_rx_queues);
1352 }
1353
1354 rte_free(dpaa_intf->cgr_rx);
1355 dpaa_intf->cgr_rx = NULL;
1356
1357 rte_free(dpaa_intf->rx_queues);
1358 dpaa_intf->rx_queues = NULL;
1359
1360 rte_free(dpaa_intf->tx_queues);
1361 dpaa_intf->tx_queues = NULL;
1362
1363 /* free memory for storing MAC addresses */
1364 rte_free(dev->data->mac_addrs);
1365 dev->data->mac_addrs = NULL;
1366
1367 dev->dev_ops = NULL;
1368 dev->rx_pkt_burst = NULL;
1369 dev->tx_pkt_burst = NULL;
1370
1371 return 0;
1372 }
1373
1374 static int
1375 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
1376 struct rte_dpaa_device *dpaa_dev)
1377 {
1378 int diag;
1379 int ret;
1380 struct rte_eth_dev *eth_dev;
1381
1382 PMD_INIT_FUNC_TRACE();
1383
1384 /* In case of secondary process, the device is already configured
1385 * and no further action is required, except portal initialization
1386 * and verifying secondary attachment to port name.
1387 */
1388 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1389 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1390 if (!eth_dev)
1391 return -ENOMEM;
1392 eth_dev->device = &dpaa_dev->device;
1393 eth_dev->dev_ops = &dpaa_devops;
1394 rte_eth_dev_probing_finish(eth_dev);
1395 return 0;
1396 }
1397
1398 if (!is_global_init) {
1399 /* One time load of Qman/Bman drivers */
1400 ret = qman_global_init();
1401 if (ret) {
1402 DPAA_PMD_ERR("QMAN initialization failed: %d",
1403 ret);
1404 return ret;
1405 }
1406 ret = bman_global_init();
1407 if (ret) {
1408 DPAA_PMD_ERR("BMAN initialization failed: %d",
1409 ret);
1410 return ret;
1411 }
1412
1413 if (access("/tmp/fmc.bin", F_OK) == -1) {
1414 RTE_LOG(INFO, PMD,
1415 "* FMC not configured.Enabling default mode\n");
1416 default_q = 1;
1417 }
1418
1419 /* disabling the default push mode for LS1043 */
1420 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1421 dpaa_push_mode_max_queue = 0;
1422
1423 /* if push mode queues to be enabled. Currenly we are allowing
1424 * only one queue per thread.
1425 */
1426 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1427 dpaa_push_mode_max_queue =
1428 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1429 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1430 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1431 }
1432
1433 is_global_init = 1;
1434 }
1435
1436 if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1437 ret = rte_dpaa_portal_init((void *)1);
1438 if (ret) {
1439 DPAA_PMD_ERR("Unable to initialize portal");
1440 return ret;
1441 }
1442 }
1443
1444 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1445 if (eth_dev == NULL)
1446 return -ENOMEM;
1447
1448 eth_dev->data->dev_private = rte_zmalloc(
1449 "ethdev private structure",
1450 sizeof(struct dpaa_if),
1451 RTE_CACHE_LINE_SIZE);
1452 if (!eth_dev->data->dev_private) {
1453 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1454 rte_eth_dev_release_port(eth_dev);
1455 return -ENOMEM;
1456 }
1457
1458 eth_dev->device = &dpaa_dev->device;
1459 eth_dev->device->driver = &dpaa_drv->driver;
1460 dpaa_dev->eth_dev = eth_dev;
1461
1462 /* Invoke PMD device initialization function */
1463 diag = dpaa_dev_init(eth_dev);
1464 if (diag == 0) {
1465 rte_eth_dev_probing_finish(eth_dev);
1466 return 0;
1467 }
1468
1469 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1470 rte_free(eth_dev->data->dev_private);
1471
1472 rte_eth_dev_release_port(eth_dev);
1473 return diag;
1474 }
1475
1476 static int
1477 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1478 {
1479 struct rte_eth_dev *eth_dev;
1480
1481 PMD_INIT_FUNC_TRACE();
1482
1483 eth_dev = dpaa_dev->eth_dev;
1484 dpaa_dev_uninit(eth_dev);
1485
1486 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1487 rte_free(eth_dev->data->dev_private);
1488
1489 rte_eth_dev_release_port(eth_dev);
1490
1491 return 0;
1492 }
1493
1494 static struct rte_dpaa_driver rte_dpaa_pmd = {
1495 .drv_type = FSL_DPAA_ETH,
1496 .probe = rte_dpaa_probe,
1497 .remove = rte_dpaa_remove,
1498 };
1499
1500 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
Ceph