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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / e1000 / base / e1000_82571.c
1 /*******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ***************************************************************************/
33
34 /* 82571EB Gigabit Ethernet Controller
35 * 82571EB Gigabit Ethernet Controller (Copper)
36 * 82571EB Gigabit Ethernet Controller (Fiber)
37 * 82571EB Dual Port Gigabit Mezzanine Adapter
38 * 82571EB Quad Port Gigabit Mezzanine Adapter
39 * 82571PT Gigabit PT Quad Port Server ExpressModule
40 * 82572EI Gigabit Ethernet Controller (Copper)
41 * 82572EI Gigabit Ethernet Controller (Fiber)
42 * 82572EI Gigabit Ethernet Controller
43 * 82573V Gigabit Ethernet Controller (Copper)
44 * 82573E Gigabit Ethernet Controller (Copper)
45 * 82573L Gigabit Ethernet Controller
46 * 82574L Gigabit Network Connection
47 * 82583V Gigabit Network Connection
48 */
49
50 #include "e1000_api.h"
51
52 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
53 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw);
54 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
57 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
58 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
59 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
60 bool active);
61 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw);
62 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw);
63 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw);
64 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
65 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw);
66 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw);
67 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
68 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
69 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
70 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
71 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
72 STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
73 STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
74 STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
75 STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
76 STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
77 STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
78 STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
79 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
80 bool active);
81 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
82 bool active);
83 STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
84 STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
85 u16 words, u16 *data);
86 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
87 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
88
89 /**
90 * e1000_init_phy_params_82571 - Init PHY func ptrs.
91 * @hw: pointer to the HW structure
92 **/
93 STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
94 {
95 struct e1000_phy_info *phy = &hw->phy;
96 s32 ret_val;
97
98 DEBUGFUNC("e1000_init_phy_params_82571");
99
100 if (hw->phy.media_type != e1000_media_type_copper) {
101 phy->type = e1000_phy_none;
102 return E1000_SUCCESS;
103 }
104
105 phy->addr = 1;
106 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
107 phy->reset_delay_us = 100;
108
109 phy->ops.check_reset_block = e1000_check_reset_block_generic;
110 phy->ops.reset = e1000_phy_hw_reset_generic;
111 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
112 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
113 phy->ops.power_up = e1000_power_up_phy_copper;
114 phy->ops.power_down = e1000_power_down_phy_copper_82571;
115
116 switch (hw->mac.type) {
117 case e1000_82571:
118 case e1000_82572:
119 phy->type = e1000_phy_igp_2;
120 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
121 phy->ops.get_info = e1000_get_phy_info_igp;
122 phy->ops.check_polarity = e1000_check_polarity_igp;
123 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
124 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
125 phy->ops.read_reg = e1000_read_phy_reg_igp;
126 phy->ops.write_reg = e1000_write_phy_reg_igp;
127 phy->ops.acquire = e1000_get_hw_semaphore_82571;
128 phy->ops.release = e1000_put_hw_semaphore_82571;
129 break;
130 case e1000_82573:
131 phy->type = e1000_phy_m88;
132 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
133 phy->ops.get_info = e1000_get_phy_info_m88;
134 phy->ops.check_polarity = e1000_check_polarity_m88;
135 phy->ops.commit = e1000_phy_sw_reset_generic;
136 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
137 phy->ops.get_cable_length = e1000_get_cable_length_m88;
138 phy->ops.read_reg = e1000_read_phy_reg_m88;
139 phy->ops.write_reg = e1000_write_phy_reg_m88;
140 phy->ops.acquire = e1000_get_hw_semaphore_82571;
141 phy->ops.release = e1000_put_hw_semaphore_82571;
142 break;
143 case e1000_82574:
144 case e1000_82583:
145 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
146
147 phy->type = e1000_phy_bm;
148 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
149 phy->ops.get_info = e1000_get_phy_info_m88;
150 phy->ops.check_polarity = e1000_check_polarity_m88;
151 phy->ops.commit = e1000_phy_sw_reset_generic;
152 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
153 phy->ops.get_cable_length = e1000_get_cable_length_m88;
154 phy->ops.read_reg = e1000_read_phy_reg_bm2;
155 phy->ops.write_reg = e1000_write_phy_reg_bm2;
156 phy->ops.acquire = e1000_get_hw_semaphore_82574;
157 phy->ops.release = e1000_put_hw_semaphore_82574;
158 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
159 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
160 break;
161 default:
162 return -E1000_ERR_PHY;
163 break;
164 }
165
166 /* This can only be done after all function pointers are setup. */
167 ret_val = e1000_get_phy_id_82571(hw);
168 if (ret_val) {
169 DEBUGOUT("Error getting PHY ID\n");
170 return ret_val;
171 }
172
173 /* Verify phy id */
174 switch (hw->mac.type) {
175 case e1000_82571:
176 case e1000_82572:
177 if (phy->id != IGP01E1000_I_PHY_ID)
178 ret_val = -E1000_ERR_PHY;
179 break;
180 case e1000_82573:
181 if (phy->id != M88E1111_I_PHY_ID)
182 ret_val = -E1000_ERR_PHY;
183 break;
184 case e1000_82574:
185 case e1000_82583:
186 if (phy->id != BME1000_E_PHY_ID_R2)
187 ret_val = -E1000_ERR_PHY;
188 break;
189 default:
190 ret_val = -E1000_ERR_PHY;
191 break;
192 }
193
194 if (ret_val)
195 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
196
197 return ret_val;
198 }
199
200 /**
201 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
202 * @hw: pointer to the HW structure
203 **/
204 STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
205 {
206 struct e1000_nvm_info *nvm = &hw->nvm;
207 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
208 u16 size;
209
210 DEBUGFUNC("e1000_init_nvm_params_82571");
211
212 nvm->opcode_bits = 8;
213 nvm->delay_usec = 1;
214 switch (nvm->override) {
215 case e1000_nvm_override_spi_large:
216 nvm->page_size = 32;
217 nvm->address_bits = 16;
218 break;
219 case e1000_nvm_override_spi_small:
220 nvm->page_size = 8;
221 nvm->address_bits = 8;
222 break;
223 default:
224 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
225 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
226 break;
227 }
228
229 switch (hw->mac.type) {
230 case e1000_82573:
231 case e1000_82574:
232 case e1000_82583:
233 if (((eecd >> 15) & 0x3) == 0x3) {
234 nvm->type = e1000_nvm_flash_hw;
235 nvm->word_size = 2048;
236 /* Autonomous Flash update bit must be cleared due
237 * to Flash update issue.
238 */
239 eecd &= ~E1000_EECD_AUPDEN;
240 E1000_WRITE_REG(hw, E1000_EECD, eecd);
241 break;
242 }
243 /* Fall Through */
244 default:
245 nvm->type = e1000_nvm_eeprom_spi;
246 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
247 E1000_EECD_SIZE_EX_SHIFT);
248 /* Added to a constant, "size" becomes the left-shift value
249 * for setting word_size.
250 */
251 size += NVM_WORD_SIZE_BASE_SHIFT;
252
253 /* EEPROM access above 16k is unsupported */
254 if (size > 14)
255 size = 14;
256 nvm->word_size = 1 << size;
257 break;
258 }
259
260 /* Function Pointers */
261 switch (hw->mac.type) {
262 case e1000_82574:
263 case e1000_82583:
264 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
265 nvm->ops.release = e1000_put_hw_semaphore_82574;
266 break;
267 default:
268 nvm->ops.acquire = e1000_acquire_nvm_82571;
269 nvm->ops.release = e1000_release_nvm_82571;
270 break;
271 }
272 nvm->ops.read = e1000_read_nvm_eerd;
273 nvm->ops.update = e1000_update_nvm_checksum_82571;
274 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
275 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
276 nvm->ops.write = e1000_write_nvm_82571;
277
278 return E1000_SUCCESS;
279 }
280
281 /**
282 * e1000_init_mac_params_82571 - Init MAC func ptrs.
283 * @hw: pointer to the HW structure
284 **/
285 STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
286 {
287 struct e1000_mac_info *mac = &hw->mac;
288 u32 swsm = 0;
289 u32 swsm2 = 0;
290 bool force_clear_smbi = false;
291
292 DEBUGFUNC("e1000_init_mac_params_82571");
293
294 /* Set media type and media-dependent function pointers */
295 switch (hw->device_id) {
296 case E1000_DEV_ID_82571EB_FIBER:
297 case E1000_DEV_ID_82572EI_FIBER:
298 case E1000_DEV_ID_82571EB_QUAD_FIBER:
299 hw->phy.media_type = e1000_media_type_fiber;
300 mac->ops.setup_physical_interface =
301 e1000_setup_fiber_serdes_link_82571;
302 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
303 mac->ops.get_link_up_info =
304 e1000_get_speed_and_duplex_fiber_serdes_generic;
305 break;
306 case E1000_DEV_ID_82571EB_SERDES:
307 case E1000_DEV_ID_82571EB_SERDES_DUAL:
308 case E1000_DEV_ID_82571EB_SERDES_QUAD:
309 case E1000_DEV_ID_82572EI_SERDES:
310 hw->phy.media_type = e1000_media_type_internal_serdes;
311 mac->ops.setup_physical_interface =
312 e1000_setup_fiber_serdes_link_82571;
313 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
314 mac->ops.get_link_up_info =
315 e1000_get_speed_and_duplex_fiber_serdes_generic;
316 break;
317 default:
318 hw->phy.media_type = e1000_media_type_copper;
319 mac->ops.setup_physical_interface =
320 e1000_setup_copper_link_82571;
321 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
322 mac->ops.get_link_up_info =
323 e1000_get_speed_and_duplex_copper_generic;
324 break;
325 }
326
327 /* Set mta register count */
328 mac->mta_reg_count = 128;
329 /* Set rar entry count */
330 mac->rar_entry_count = E1000_RAR_ENTRIES;
331 /* Set if part includes ASF firmware */
332 mac->asf_firmware_present = true;
333 /* Adaptive IFS supported */
334 mac->adaptive_ifs = true;
335
336 /* Function pointers */
337
338 /* bus type/speed/width */
339 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
340 /* reset */
341 mac->ops.reset_hw = e1000_reset_hw_82571;
342 /* hw initialization */
343 mac->ops.init_hw = e1000_init_hw_82571;
344 /* link setup */
345 mac->ops.setup_link = e1000_setup_link_82571;
346 /* multicast address update */
347 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
348 /* writing VFTA */
349 mac->ops.write_vfta = e1000_write_vfta_generic;
350 /* clearing VFTA */
351 mac->ops.clear_vfta = e1000_clear_vfta_82571;
352 /* read mac address */
353 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
354 /* ID LED init */
355 mac->ops.id_led_init = e1000_id_led_init_generic;
356 /* setup LED */
357 mac->ops.setup_led = e1000_setup_led_generic;
358 /* cleanup LED */
359 mac->ops.cleanup_led = e1000_cleanup_led_generic;
360 /* turn off LED */
361 mac->ops.led_off = e1000_led_off_generic;
362 /* clear hardware counters */
363 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
364
365 /* MAC-specific function pointers */
366 switch (hw->mac.type) {
367 case e1000_82573:
368 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
369 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
370 mac->ops.led_on = e1000_led_on_generic;
371 mac->ops.blink_led = e1000_blink_led_generic;
372
373 /* FWSM register */
374 mac->has_fwsm = true;
375 /* ARC supported; valid only if manageability features are
376 * enabled.
377 */
378 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
379 E1000_FWSM_MODE_MASK);
380 break;
381 case e1000_82574:
382 case e1000_82583:
383 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
384 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
385 mac->ops.led_on = e1000_led_on_82574;
386 break;
387 default:
388 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
389 mac->ops.led_on = e1000_led_on_generic;
390 mac->ops.blink_led = e1000_blink_led_generic;
391
392 /* FWSM register */
393 mac->has_fwsm = true;
394 break;
395 }
396
397 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
398 * first NVM or PHY access. This should be done for single-port
399 * devices, and for one port only on dual-port devices so that
400 * for those devices we can still use the SMBI lock to synchronize
401 * inter-port accesses to the PHY & NVM.
402 */
403 switch (hw->mac.type) {
404 case e1000_82571:
405 case e1000_82572:
406 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
407
408 if (!(swsm2 & E1000_SWSM2_LOCK)) {
409 /* Only do this for the first interface on this card */
410 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
411 E1000_SWSM2_LOCK);
412 force_clear_smbi = true;
413 } else {
414 force_clear_smbi = false;
415 }
416 break;
417 default:
418 force_clear_smbi = true;
419 break;
420 }
421
422 if (force_clear_smbi) {
423 /* Make sure SWSM.SMBI is clear */
424 swsm = E1000_READ_REG(hw, E1000_SWSM);
425 if (swsm & E1000_SWSM_SMBI) {
426 /* This bit should not be set on a first interface, and
427 * indicates that the bootagent or EFI code has
428 * improperly left this bit enabled
429 */
430 DEBUGOUT("Please update your 82571 Bootagent\n");
431 }
432 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
433 }
434
435 /* Initialze device specific counter of SMBI acquisition timeouts. */
436 hw->dev_spec._82571.smb_counter = 0;
437
438 return E1000_SUCCESS;
439 }
440
441 /**
442 * e1000_init_function_pointers_82571 - Init func ptrs.
443 * @hw: pointer to the HW structure
444 *
445 * Called to initialize all function pointers and parameters.
446 **/
447 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
448 {
449 DEBUGFUNC("e1000_init_function_pointers_82571");
450
451 hw->mac.ops.init_params = e1000_init_mac_params_82571;
452 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
453 hw->phy.ops.init_params = e1000_init_phy_params_82571;
454 }
455
456 /**
457 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
458 * @hw: pointer to the HW structure
459 *
460 * Reads the PHY registers and stores the PHY ID and possibly the PHY
461 * revision in the hardware structure.
462 **/
463 STATIC s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
464 {
465 struct e1000_phy_info *phy = &hw->phy;
466 s32 ret_val;
467 u16 phy_id = 0;
468
469 DEBUGFUNC("e1000_get_phy_id_82571");
470
471 switch (hw->mac.type) {
472 case e1000_82571:
473 case e1000_82572:
474 /* The 82571 firmware may still be configuring the PHY.
475 * In this case, we cannot access the PHY until the
476 * configuration is done. So we explicitly set the
477 * PHY ID.
478 */
479 phy->id = IGP01E1000_I_PHY_ID;
480 break;
481 case e1000_82573:
482 return e1000_get_phy_id(hw);
483 break;
484 case e1000_82574:
485 case e1000_82583:
486 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
487 if (ret_val)
488 return ret_val;
489
490 phy->id = (u32)(phy_id << 16);
491 usec_delay(20);
492 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
493 if (ret_val)
494 return ret_val;
495
496 phy->id |= (u32)(phy_id);
497 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
498 break;
499 default:
500 return -E1000_ERR_PHY;
501 break;
502 }
503
504 return E1000_SUCCESS;
505 }
506
507 /**
508 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
509 * @hw: pointer to the HW structure
510 *
511 * Acquire the HW semaphore to access the PHY or NVM
512 **/
513 STATIC s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
514 {
515 u32 swsm;
516 s32 sw_timeout = hw->nvm.word_size + 1;
517 s32 fw_timeout = hw->nvm.word_size + 1;
518 s32 i = 0;
519
520 DEBUGFUNC("e1000_get_hw_semaphore_82571");
521
522 /* If we have timedout 3 times on trying to acquire
523 * the inter-port SMBI semaphore, there is old code
524 * operating on the other port, and it is not
525 * releasing SMBI. Modify the number of times that
526 * we try for the semaphore to interwork with this
527 * older code.
528 */
529 if (hw->dev_spec._82571.smb_counter > 2)
530 sw_timeout = 1;
531
532 /* Get the SW semaphore */
533 while (i < sw_timeout) {
534 swsm = E1000_READ_REG(hw, E1000_SWSM);
535 if (!(swsm & E1000_SWSM_SMBI))
536 break;
537
538 usec_delay(50);
539 i++;
540 }
541
542 if (i == sw_timeout) {
543 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
544 hw->dev_spec._82571.smb_counter++;
545 }
546 /* Get the FW semaphore. */
547 for (i = 0; i < fw_timeout; i++) {
548 swsm = E1000_READ_REG(hw, E1000_SWSM);
549 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
550
551 /* Semaphore acquired if bit latched */
552 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
553 break;
554
555 usec_delay(50);
556 }
557
558 if (i == fw_timeout) {
559 /* Release semaphores */
560 e1000_put_hw_semaphore_82571(hw);
561 DEBUGOUT("Driver can't access the NVM\n");
562 return -E1000_ERR_NVM;
563 }
564
565 return E1000_SUCCESS;
566 }
567
568 /**
569 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
570 * @hw: pointer to the HW structure
571 *
572 * Release hardware semaphore used to access the PHY or NVM
573 **/
574 STATIC void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
575 {
576 u32 swsm;
577
578 DEBUGFUNC("e1000_put_hw_semaphore_generic");
579
580 swsm = E1000_READ_REG(hw, E1000_SWSM);
581
582 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
583
584 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
585 }
586
587 /**
588 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
589 * @hw: pointer to the HW structure
590 *
591 * Acquire the HW semaphore during reset.
592 *
593 **/
594 STATIC s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
595 {
596 u32 extcnf_ctrl;
597 s32 i = 0;
598
599 DEBUGFUNC("e1000_get_hw_semaphore_82573");
600
601 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
602 do {
603 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
604 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
605 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
606
607 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
608 break;
609
610 msec_delay(2);
611 i++;
612 } while (i < MDIO_OWNERSHIP_TIMEOUT);
613
614 if (i == MDIO_OWNERSHIP_TIMEOUT) {
615 /* Release semaphores */
616 e1000_put_hw_semaphore_82573(hw);
617 DEBUGOUT("Driver can't access the PHY\n");
618 return -E1000_ERR_PHY;
619 }
620
621 return E1000_SUCCESS;
622 }
623
624 /**
625 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
626 * @hw: pointer to the HW structure
627 *
628 * Release hardware semaphore used during reset.
629 *
630 **/
631 STATIC void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
632 {
633 u32 extcnf_ctrl;
634
635 DEBUGFUNC("e1000_put_hw_semaphore_82573");
636
637 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
638 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
639 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
640 }
641
642 /**
643 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
644 * @hw: pointer to the HW structure
645 *
646 * Acquire the HW semaphore to access the PHY or NVM.
647 *
648 **/
649 STATIC s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
650 {
651 s32 ret_val;
652
653 DEBUGFUNC("e1000_get_hw_semaphore_82574");
654
655 E1000_MUTEX_LOCK(&hw->dev_spec._82571.swflag_mutex);
656 ret_val = e1000_get_hw_semaphore_82573(hw);
657 if (ret_val)
658 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
659 return ret_val;
660 }
661
662 /**
663 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
664 * @hw: pointer to the HW structure
665 *
666 * Release hardware semaphore used to access the PHY or NVM
667 *
668 **/
669 STATIC void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
670 {
671 DEBUGFUNC("e1000_put_hw_semaphore_82574");
672
673 e1000_put_hw_semaphore_82573(hw);
674 E1000_MUTEX_UNLOCK(&hw->dev_spec._82571.swflag_mutex);
675 }
676
677 /**
678 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
679 * @hw: pointer to the HW structure
680 * @active: true to enable LPLU, false to disable
681 *
682 * Sets the LPLU D0 state according to the active flag.
683 * LPLU will not be activated unless the
684 * device autonegotiation advertisement meets standards of
685 * either 10 or 10/100 or 10/100/1000 at all duplexes.
686 * This is a function pointer entry point only called by
687 * PHY setup routines.
688 **/
689 STATIC s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
690 {
691 u32 data = E1000_READ_REG(hw, E1000_POEMB);
692
693 DEBUGFUNC("e1000_set_d0_lplu_state_82574");
694
695 if (active)
696 data |= E1000_PHY_CTRL_D0A_LPLU;
697 else
698 data &= ~E1000_PHY_CTRL_D0A_LPLU;
699
700 E1000_WRITE_REG(hw, E1000_POEMB, data);
701 return E1000_SUCCESS;
702 }
703
704 /**
705 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
706 * @hw: pointer to the HW structure
707 * @active: boolean used to enable/disable lplu
708 *
709 * The low power link up (lplu) state is set to the power management level D3
710 * when active is true, else clear lplu for D3. LPLU
711 * is used during Dx states where the power conservation is most important.
712 * During driver activity, SmartSpeed should be enabled so performance is
713 * maintained.
714 **/
715 STATIC s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
716 {
717 u32 data = E1000_READ_REG(hw, E1000_POEMB);
718
719 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
720
721 if (!active) {
722 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
723 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
724 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
725 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
726 data |= E1000_PHY_CTRL_NOND0A_LPLU;
727 }
728
729 E1000_WRITE_REG(hw, E1000_POEMB, data);
730 return E1000_SUCCESS;
731 }
732
733 /**
734 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
735 * @hw: pointer to the HW structure
736 *
737 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
738 * Then for non-82573 hardware, set the EEPROM access request bit and wait
739 * for EEPROM access grant bit. If the access grant bit is not set, release
740 * hardware semaphore.
741 **/
742 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
743 {
744 s32 ret_val;
745
746 DEBUGFUNC("e1000_acquire_nvm_82571");
747
748 ret_val = e1000_get_hw_semaphore_82571(hw);
749 if (ret_val)
750 return ret_val;
751
752 switch (hw->mac.type) {
753 case e1000_82573:
754 break;
755 default:
756 ret_val = e1000_acquire_nvm_generic(hw);
757 break;
758 }
759
760 if (ret_val)
761 e1000_put_hw_semaphore_82571(hw);
762
763 return ret_val;
764 }
765
766 /**
767 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
768 * @hw: pointer to the HW structure
769 *
770 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
771 **/
772 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw)
773 {
774 DEBUGFUNC("e1000_release_nvm_82571");
775
776 e1000_release_nvm_generic(hw);
777 e1000_put_hw_semaphore_82571(hw);
778 }
779
780 /**
781 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
782 * @hw: pointer to the HW structure
783 * @offset: offset within the EEPROM to be written to
784 * @words: number of words to write
785 * @data: 16 bit word(s) to be written to the EEPROM
786 *
787 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
788 *
789 * If e1000_update_nvm_checksum is not called after this function, the
790 * EEPROM will most likely contain an invalid checksum.
791 **/
792 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
793 u16 *data)
794 {
795 s32 ret_val;
796
797 DEBUGFUNC("e1000_write_nvm_82571");
798
799 switch (hw->mac.type) {
800 case e1000_82573:
801 case e1000_82574:
802 case e1000_82583:
803 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
804 break;
805 case e1000_82571:
806 case e1000_82572:
807 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
808 break;
809 default:
810 ret_val = -E1000_ERR_NVM;
811 break;
812 }
813
814 return ret_val;
815 }
816
817 /**
818 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
819 * @hw: pointer to the HW structure
820 *
821 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
822 * up to the checksum. Then calculates the EEPROM checksum and writes the
823 * value to the EEPROM.
824 **/
825 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
826 {
827 u32 eecd;
828 s32 ret_val;
829 u16 i;
830
831 DEBUGFUNC("e1000_update_nvm_checksum_82571");
832
833 ret_val = e1000_update_nvm_checksum_generic(hw);
834 if (ret_val)
835 return ret_val;
836
837 /* If our nvm is an EEPROM, then we're done
838 * otherwise, commit the checksum to the flash NVM.
839 */
840 if (hw->nvm.type != e1000_nvm_flash_hw)
841 return E1000_SUCCESS;
842
843 /* Check for pending operations. */
844 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
845 msec_delay(1);
846 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
847 break;
848 }
849
850 if (i == E1000_FLASH_UPDATES)
851 return -E1000_ERR_NVM;
852
853 /* Reset the firmware if using STM opcode. */
854 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
855 /* The enabling of and the actual reset must be done
856 * in two write cycles.
857 */
858 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
859 E1000_WRITE_FLUSH(hw);
860 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
861 }
862
863 /* Commit the write to flash */
864 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
865 E1000_WRITE_REG(hw, E1000_EECD, eecd);
866
867 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
868 msec_delay(1);
869 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
870 break;
871 }
872
873 if (i == E1000_FLASH_UPDATES)
874 return -E1000_ERR_NVM;
875
876 return E1000_SUCCESS;
877 }
878
879 /**
880 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
881 * @hw: pointer to the HW structure
882 *
883 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
884 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
885 **/
886 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
887 {
888 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
889
890 if (hw->nvm.type == e1000_nvm_flash_hw)
891 e1000_fix_nvm_checksum_82571(hw);
892
893 return e1000_validate_nvm_checksum_generic(hw);
894 }
895
896 /**
897 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
898 * @hw: pointer to the HW structure
899 * @offset: offset within the EEPROM to be written to
900 * @words: number of words to write
901 * @data: 16 bit word(s) to be written to the EEPROM
902 *
903 * After checking for invalid values, poll the EEPROM to ensure the previous
904 * command has completed before trying to write the next word. After write
905 * poll for completion.
906 *
907 * If e1000_update_nvm_checksum is not called after this function, the
908 * EEPROM will most likely contain an invalid checksum.
909 **/
910 STATIC s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
911 u16 words, u16 *data)
912 {
913 struct e1000_nvm_info *nvm = &hw->nvm;
914 u32 i, eewr = 0;
915 s32 ret_val = E1000_SUCCESS;
916
917 DEBUGFUNC("e1000_write_nvm_eewr_82571");
918
919 /* A check for invalid values: offset too large, too many words,
920 * and not enough words.
921 */
922 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
923 (words == 0)) {
924 DEBUGOUT("nvm parameter(s) out of bounds\n");
925 return -E1000_ERR_NVM;
926 }
927
928 for (i = 0; i < words; i++) {
929 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
930 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
931 E1000_NVM_RW_REG_START);
932
933 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
934 if (ret_val)
935 break;
936
937 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
938
939 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
940 if (ret_val)
941 break;
942 }
943
944 return ret_val;
945 }
946
947 /**
948 * e1000_get_cfg_done_82571 - Poll for configuration done
949 * @hw: pointer to the HW structure
950 *
951 * Reads the management control register for the config done bit to be set.
952 **/
953 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
954 {
955 s32 timeout = PHY_CFG_TIMEOUT;
956
957 DEBUGFUNC("e1000_get_cfg_done_82571");
958
959 while (timeout) {
960 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
961 E1000_NVM_CFG_DONE_PORT_0)
962 break;
963 msec_delay(1);
964 timeout--;
965 }
966 if (!timeout) {
967 DEBUGOUT("MNG configuration cycle has not completed.\n");
968 return -E1000_ERR_RESET;
969 }
970
971 return E1000_SUCCESS;
972 }
973
974 /**
975 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
976 * @hw: pointer to the HW structure
977 * @active: true to enable LPLU, false to disable
978 *
979 * Sets the LPLU D0 state according to the active flag. When activating LPLU
980 * this function also disables smart speed and vice versa. LPLU will not be
981 * activated unless the device autonegotiation advertisement meets standards
982 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
983 * pointer entry point only called by PHY setup routines.
984 **/
985 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
986 {
987 struct e1000_phy_info *phy = &hw->phy;
988 s32 ret_val;
989 u16 data;
990
991 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
992
993 if (!(phy->ops.read_reg))
994 return E1000_SUCCESS;
995
996 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
997 if (ret_val)
998 return ret_val;
999
1000 if (active) {
1001 data |= IGP02E1000_PM_D0_LPLU;
1002 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1003 data);
1004 if (ret_val)
1005 return ret_val;
1006
1007 /* When LPLU is enabled, we should disable SmartSpeed */
1008 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1009 &data);
1010 if (ret_val)
1011 return ret_val;
1012 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1013 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1014 data);
1015 if (ret_val)
1016 return ret_val;
1017 } else {
1018 data &= ~IGP02E1000_PM_D0_LPLU;
1019 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1020 data);
1021 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1022 * during Dx states where the power conservation is most
1023 * important. During driver activity we should enable
1024 * SmartSpeed, so performance is maintained.
1025 */
1026 if (phy->smart_speed == e1000_smart_speed_on) {
1027 ret_val = phy->ops.read_reg(hw,
1028 IGP01E1000_PHY_PORT_CONFIG,
1029 &data);
1030 if (ret_val)
1031 return ret_val;
1032
1033 data |= IGP01E1000_PSCFR_SMART_SPEED;
1034 ret_val = phy->ops.write_reg(hw,
1035 IGP01E1000_PHY_PORT_CONFIG,
1036 data);
1037 if (ret_val)
1038 return ret_val;
1039 } else if (phy->smart_speed == e1000_smart_speed_off) {
1040 ret_val = phy->ops.read_reg(hw,
1041 IGP01E1000_PHY_PORT_CONFIG,
1042 &data);
1043 if (ret_val)
1044 return ret_val;
1045
1046 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1047 ret_val = phy->ops.write_reg(hw,
1048 IGP01E1000_PHY_PORT_CONFIG,
1049 data);
1050 if (ret_val)
1051 return ret_val;
1052 }
1053 }
1054
1055 return E1000_SUCCESS;
1056 }
1057
1058 /**
1059 * e1000_reset_hw_82571 - Reset hardware
1060 * @hw: pointer to the HW structure
1061 *
1062 * This resets the hardware into a known state.
1063 **/
1064 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1065 {
1066 u32 ctrl, ctrl_ext, eecd, tctl;
1067 s32 ret_val;
1068
1069 DEBUGFUNC("e1000_reset_hw_82571");
1070
1071 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1072 * on the last TLP read/write transaction when MAC is reset.
1073 */
1074 ret_val = e1000_disable_pcie_master_generic(hw);
1075 if (ret_val)
1076 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1077
1078 DEBUGOUT("Masking off all interrupts\n");
1079 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1080
1081 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1082 tctl = E1000_READ_REG(hw, E1000_TCTL);
1083 tctl &= ~E1000_TCTL_EN;
1084 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1085 E1000_WRITE_FLUSH(hw);
1086
1087 msec_delay(10);
1088
1089 /* Must acquire the MDIO ownership before MAC reset.
1090 * Ownership defaults to firmware after a reset.
1091 */
1092 switch (hw->mac.type) {
1093 case e1000_82573:
1094 ret_val = e1000_get_hw_semaphore_82573(hw);
1095 break;
1096 case e1000_82574:
1097 case e1000_82583:
1098 ret_val = e1000_get_hw_semaphore_82574(hw);
1099 break;
1100 default:
1101 break;
1102 }
1103
1104 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1105
1106 DEBUGOUT("Issuing a global reset to MAC\n");
1107 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1108
1109 /* Must release MDIO ownership and mutex after MAC reset. */
1110 switch (hw->mac.type) {
1111 case e1000_82573:
1112 /* Release mutex only if the hw semaphore is acquired */
1113 if (!ret_val)
1114 e1000_put_hw_semaphore_82573(hw);
1115 break;
1116 case e1000_82574:
1117 case e1000_82583:
1118 /* Release mutex only if the hw semaphore is acquired */
1119 if (!ret_val)
1120 e1000_put_hw_semaphore_82574(hw);
1121 break;
1122 default:
1123 break;
1124 }
1125
1126 if (hw->nvm.type == e1000_nvm_flash_hw) {
1127 usec_delay(10);
1128 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1129 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1130 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1131 E1000_WRITE_FLUSH(hw);
1132 }
1133
1134 ret_val = e1000_get_auto_rd_done_generic(hw);
1135 if (ret_val)
1136 /* We don't want to continue accessing MAC registers. */
1137 return ret_val;
1138
1139 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1140 * Need to wait for Phy configuration completion before accessing
1141 * NVM and Phy.
1142 */
1143
1144 switch (hw->mac.type) {
1145 case e1000_82571:
1146 case e1000_82572:
1147 /* REQ and GNT bits need to be cleared when using AUTO_RD
1148 * to access the EEPROM.
1149 */
1150 eecd = E1000_READ_REG(hw, E1000_EECD);
1151 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1152 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1153 break;
1154 case e1000_82573:
1155 case e1000_82574:
1156 case e1000_82583:
1157 msec_delay(25);
1158 break;
1159 default:
1160 break;
1161 }
1162
1163 /* Clear any pending interrupt events. */
1164 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1165 E1000_READ_REG(hw, E1000_ICR);
1166
1167 if (hw->mac.type == e1000_82571) {
1168 /* Install any alternate MAC address into RAR0 */
1169 ret_val = e1000_check_alt_mac_addr_generic(hw);
1170 if (ret_val)
1171 return ret_val;
1172
1173 e1000_set_laa_state_82571(hw, true);
1174 }
1175
1176 /* Reinitialize the 82571 serdes link state machine */
1177 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1178 hw->mac.serdes_link_state = e1000_serdes_link_down;
1179
1180 return E1000_SUCCESS;
1181 }
1182
1183 /**
1184 * e1000_init_hw_82571 - Initialize hardware
1185 * @hw: pointer to the HW structure
1186 *
1187 * This inits the hardware readying it for operation.
1188 **/
1189 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
1190 {
1191 struct e1000_mac_info *mac = &hw->mac;
1192 u32 reg_data;
1193 s32 ret_val;
1194 u16 i, rar_count = mac->rar_entry_count;
1195
1196 DEBUGFUNC("e1000_init_hw_82571");
1197
1198 e1000_initialize_hw_bits_82571(hw);
1199
1200 /* Initialize identification LED */
1201 ret_val = mac->ops.id_led_init(hw);
1202 /* An error is not fatal and we should not stop init due to this */
1203 if (ret_val)
1204 DEBUGOUT("Error initializing identification LED\n");
1205
1206 /* Disabling VLAN filtering */
1207 DEBUGOUT("Initializing the IEEE VLAN\n");
1208 mac->ops.clear_vfta(hw);
1209
1210 /* Setup the receive address.
1211 * If, however, a locally administered address was assigned to the
1212 * 82571, we must reserve a RAR for it to work around an issue where
1213 * resetting one port will reload the MAC on the other port.
1214 */
1215 if (e1000_get_laa_state_82571(hw))
1216 rar_count--;
1217 e1000_init_rx_addrs_generic(hw, rar_count);
1218
1219 /* Zero out the Multicast HASH table */
1220 DEBUGOUT("Zeroing the MTA\n");
1221 for (i = 0; i < mac->mta_reg_count; i++)
1222 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1223
1224 /* Setup link and flow control */
1225 ret_val = mac->ops.setup_link(hw);
1226
1227 /* Set the transmit descriptor write-back policy */
1228 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1229 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1230 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1231 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1232
1233 /* ...for both queues. */
1234 switch (mac->type) {
1235 case e1000_82573:
1236 e1000_enable_tx_pkt_filtering_generic(hw);
1237 /* fall through */
1238 case e1000_82574:
1239 case e1000_82583:
1240 reg_data = E1000_READ_REG(hw, E1000_GCR);
1241 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1242 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1243 break;
1244 default:
1245 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1246 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1247 E1000_TXDCTL_FULL_TX_DESC_WB |
1248 E1000_TXDCTL_COUNT_DESC);
1249 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1250 break;
1251 }
1252
1253 /* Clear all of the statistics registers (clear on read). It is
1254 * important that we do this after we have tried to establish link
1255 * because the symbol error count will increment wildly if there
1256 * is no link.
1257 */
1258 e1000_clear_hw_cntrs_82571(hw);
1259
1260 return ret_val;
1261 }
1262
1263 /**
1264 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1265 * @hw: pointer to the HW structure
1266 *
1267 * Initializes required hardware-dependent bits needed for normal operation.
1268 **/
1269 STATIC void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1270 {
1271 u32 reg;
1272
1273 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1274
1275 /* Transmit Descriptor Control 0 */
1276 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1277 reg |= (1 << 22);
1278 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1279
1280 /* Transmit Descriptor Control 1 */
1281 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1282 reg |= (1 << 22);
1283 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1284
1285 /* Transmit Arbitration Control 0 */
1286 reg = E1000_READ_REG(hw, E1000_TARC(0));
1287 reg &= ~(0xF << 27); /* 30:27 */
1288 switch (hw->mac.type) {
1289 case e1000_82571:
1290 case e1000_82572:
1291 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1292 break;
1293 case e1000_82574:
1294 case e1000_82583:
1295 reg |= (1 << 26);
1296 break;
1297 default:
1298 break;
1299 }
1300 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1301
1302 /* Transmit Arbitration Control 1 */
1303 reg = E1000_READ_REG(hw, E1000_TARC(1));
1304 switch (hw->mac.type) {
1305 case e1000_82571:
1306 case e1000_82572:
1307 reg &= ~((1 << 29) | (1 << 30));
1308 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1309 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1310 reg &= ~(1 << 28);
1311 else
1312 reg |= (1 << 28);
1313 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1314 break;
1315 default:
1316 break;
1317 }
1318
1319 /* Device Control */
1320 switch (hw->mac.type) {
1321 case e1000_82573:
1322 case e1000_82574:
1323 case e1000_82583:
1324 reg = E1000_READ_REG(hw, E1000_CTRL);
1325 reg &= ~(1 << 29);
1326 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1327 break;
1328 default:
1329 break;
1330 }
1331
1332 /* Extended Device Control */
1333 switch (hw->mac.type) {
1334 case e1000_82573:
1335 case e1000_82574:
1336 case e1000_82583:
1337 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1338 reg &= ~(1 << 23);
1339 reg |= (1 << 22);
1340 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1341 break;
1342 default:
1343 break;
1344 }
1345
1346 if (hw->mac.type == e1000_82571) {
1347 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1348 reg |= E1000_PBA_ECC_CORR_EN;
1349 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1350 }
1351
1352 /* Workaround for hardware errata.
1353 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1354 */
1355 if ((hw->mac.type == e1000_82571) ||
1356 (hw->mac.type == e1000_82572)) {
1357 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1358 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1359 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1360 }
1361
1362 /* Disable IPv6 extension header parsing because some malformed
1363 * IPv6 headers can hang the Rx.
1364 */
1365 if (hw->mac.type <= e1000_82573) {
1366 reg = E1000_READ_REG(hw, E1000_RFCTL);
1367 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1368 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1369 }
1370
1371 /* PCI-Ex Control Registers */
1372 switch (hw->mac.type) {
1373 case e1000_82574:
1374 case e1000_82583:
1375 reg = E1000_READ_REG(hw, E1000_GCR);
1376 reg |= (1 << 22);
1377 E1000_WRITE_REG(hw, E1000_GCR, reg);
1378
1379 /* Workaround for hardware errata.
1380 * apply workaround for hardware errata documented in errata
1381 * docs Fixes issue where some error prone or unreliable PCIe
1382 * completions are occurring, particularly with ASPM enabled.
1383 * Without fix, issue can cause Tx timeouts.
1384 */
1385 reg = E1000_READ_REG(hw, E1000_GCR2);
1386 reg |= 1;
1387 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1388 break;
1389 default:
1390 break;
1391 }
1392
1393 return;
1394 }
1395
1396 /**
1397 * e1000_clear_vfta_82571 - Clear VLAN filter table
1398 * @hw: pointer to the HW structure
1399 *
1400 * Clears the register array which contains the VLAN filter table by
1401 * setting all the values to 0.
1402 **/
1403 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw)
1404 {
1405 u32 offset;
1406 u32 vfta_value = 0;
1407 u32 vfta_offset = 0;
1408 u32 vfta_bit_in_reg = 0;
1409
1410 DEBUGFUNC("e1000_clear_vfta_82571");
1411
1412 switch (hw->mac.type) {
1413 case e1000_82573:
1414 case e1000_82574:
1415 case e1000_82583:
1416 if (hw->mng_cookie.vlan_id != 0) {
1417 /* The VFTA is a 4096b bit-field, each identifying
1418 * a single VLAN ID. The following operations
1419 * determine which 32b entry (i.e. offset) into the
1420 * array we want to set the VLAN ID (i.e. bit) of
1421 * the manageability unit.
1422 */
1423 vfta_offset = (hw->mng_cookie.vlan_id >>
1424 E1000_VFTA_ENTRY_SHIFT) &
1425 E1000_VFTA_ENTRY_MASK;
1426 vfta_bit_in_reg =
1427 1 << (hw->mng_cookie.vlan_id &
1428 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1429 }
1430 break;
1431 default:
1432 break;
1433 }
1434 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1435 /* If the offset we want to clear is the same offset of the
1436 * manageability VLAN ID, then clear all bits except that of
1437 * the manageability unit.
1438 */
1439 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1440 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1441 E1000_WRITE_FLUSH(hw);
1442 }
1443 }
1444
1445 /**
1446 * e1000_check_mng_mode_82574 - Check manageability is enabled
1447 * @hw: pointer to the HW structure
1448 *
1449 * Reads the NVM Initialization Control Word 2 and returns true
1450 * (>0) if any manageability is enabled, else false (0).
1451 **/
1452 STATIC bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1453 {
1454 u16 data;
1455 s32 ret_val;
1456
1457 DEBUGFUNC("e1000_check_mng_mode_82574");
1458
1459 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1460 if (ret_val)
1461 return false;
1462
1463 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1464 }
1465
1466 /**
1467 * e1000_led_on_82574 - Turn LED on
1468 * @hw: pointer to the HW structure
1469 *
1470 * Turn LED on.
1471 **/
1472 STATIC s32 e1000_led_on_82574(struct e1000_hw *hw)
1473 {
1474 u32 ctrl;
1475 u32 i;
1476
1477 DEBUGFUNC("e1000_led_on_82574");
1478
1479 ctrl = hw->mac.ledctl_mode2;
1480 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1481 /* If no link, then turn LED on by setting the invert bit
1482 * for each LED that's "on" (0x0E) in ledctl_mode2.
1483 */
1484 for (i = 0; i < 4; i++)
1485 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1486 E1000_LEDCTL_MODE_LED_ON)
1487 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1488 }
1489 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1490
1491 return E1000_SUCCESS;
1492 }
1493
1494 /**
1495 * e1000_check_phy_82574 - check 82574 phy hung state
1496 * @hw: pointer to the HW structure
1497 *
1498 * Returns whether phy is hung or not
1499 **/
1500 bool e1000_check_phy_82574(struct e1000_hw *hw)
1501 {
1502 u16 status_1kbt = 0;
1503 u16 receive_errors = 0;
1504 s32 ret_val;
1505
1506 DEBUGFUNC("e1000_check_phy_82574");
1507
1508 /* Read PHY Receive Error counter first, if its is max - all F's then
1509 * read the Base1000T status register If both are max then PHY is hung.
1510 */
1511 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1512 &receive_errors);
1513 if (ret_val)
1514 return false;
1515 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1516 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1517 &status_1kbt);
1518 if (ret_val)
1519 return false;
1520 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1521 E1000_IDLE_ERROR_COUNT_MASK)
1522 return true;
1523 }
1524
1525 return false;
1526 }
1527
1528
1529 /**
1530 * e1000_setup_link_82571 - Setup flow control and link settings
1531 * @hw: pointer to the HW structure
1532 *
1533 * Determines which flow control settings to use, then configures flow
1534 * control. Calls the appropriate media-specific link configuration
1535 * function. Assuming the adapter has a valid link partner, a valid link
1536 * should be established. Assumes the hardware has previously been reset
1537 * and the transmitter and receiver are not enabled.
1538 **/
1539 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw)
1540 {
1541 DEBUGFUNC("e1000_setup_link_82571");
1542
1543 /* 82573 does not have a word in the NVM to determine
1544 * the default flow control setting, so we explicitly
1545 * set it to full.
1546 */
1547 switch (hw->mac.type) {
1548 case e1000_82573:
1549 case e1000_82574:
1550 case e1000_82583:
1551 if (hw->fc.requested_mode == e1000_fc_default)
1552 hw->fc.requested_mode = e1000_fc_full;
1553 break;
1554 default:
1555 break;
1556 }
1557
1558 return e1000_setup_link_generic(hw);
1559 }
1560
1561 /**
1562 * e1000_setup_copper_link_82571 - Configure copper link settings
1563 * @hw: pointer to the HW structure
1564 *
1565 * Configures the link for auto-neg or forced speed and duplex. Then we check
1566 * for link, once link is established calls to configure collision distance
1567 * and flow control are called.
1568 **/
1569 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1570 {
1571 u32 ctrl;
1572 s32 ret_val;
1573
1574 DEBUGFUNC("e1000_setup_copper_link_82571");
1575
1576 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1577 ctrl |= E1000_CTRL_SLU;
1578 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1579 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1580
1581 switch (hw->phy.type) {
1582 case e1000_phy_m88:
1583 case e1000_phy_bm:
1584 ret_val = e1000_copper_link_setup_m88(hw);
1585 break;
1586 case e1000_phy_igp_2:
1587 ret_val = e1000_copper_link_setup_igp(hw);
1588 break;
1589 default:
1590 return -E1000_ERR_PHY;
1591 break;
1592 }
1593
1594 if (ret_val)
1595 return ret_val;
1596
1597 return e1000_setup_copper_link_generic(hw);
1598 }
1599
1600 /**
1601 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1602 * @hw: pointer to the HW structure
1603 *
1604 * Configures collision distance and flow control for fiber and serdes links.
1605 * Upon successful setup, poll for link.
1606 **/
1607 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1608 {
1609 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1610
1611 switch (hw->mac.type) {
1612 case e1000_82571:
1613 case e1000_82572:
1614 /* If SerDes loopback mode is entered, there is no form
1615 * of reset to take the adapter out of that mode. So we
1616 * have to explicitly take the adapter out of loopback
1617 * mode. This prevents drivers from twiddling their thumbs
1618 * if another tool failed to take it out of loopback mode.
1619 */
1620 E1000_WRITE_REG(hw, E1000_SCTL,
1621 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1622 break;
1623 default:
1624 break;
1625 }
1626
1627 return e1000_setup_fiber_serdes_link_generic(hw);
1628 }
1629
1630 /**
1631 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1632 * @hw: pointer to the HW structure
1633 *
1634 * Reports the link state as up or down.
1635 *
1636 * If autonegotiation is supported by the link partner, the link state is
1637 * determined by the result of autonegotiation. This is the most likely case.
1638 * If autonegotiation is not supported by the link partner, and the link
1639 * has a valid signal, force the link up.
1640 *
1641 * The link state is represented internally here by 4 states:
1642 *
1643 * 1) down
1644 * 2) autoneg_progress
1645 * 3) autoneg_complete (the link successfully autonegotiated)
1646 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1647 *
1648 **/
1649 STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1650 {
1651 struct e1000_mac_info *mac = &hw->mac;
1652 u32 rxcw;
1653 u32 ctrl;
1654 u32 status;
1655 u32 txcw;
1656 u32 i;
1657 s32 ret_val = E1000_SUCCESS;
1658
1659 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1660
1661 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1662 status = E1000_READ_REG(hw, E1000_STATUS);
1663 E1000_READ_REG(hw, E1000_RXCW);
1664 /* SYNCH bit and IV bit are sticky */
1665 usec_delay(10);
1666 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1667
1668 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1669 /* Receiver is synchronized with no invalid bits. */
1670 switch (mac->serdes_link_state) {
1671 case e1000_serdes_link_autoneg_complete:
1672 if (!(status & E1000_STATUS_LU)) {
1673 /* We have lost link, retry autoneg before
1674 * reporting link failure
1675 */
1676 mac->serdes_link_state =
1677 e1000_serdes_link_autoneg_progress;
1678 mac->serdes_has_link = false;
1679 DEBUGOUT("AN_UP -> AN_PROG\n");
1680 } else {
1681 mac->serdes_has_link = true;
1682 }
1683 break;
1684
1685 case e1000_serdes_link_forced_up:
1686 /* If we are receiving /C/ ordered sets, re-enable
1687 * auto-negotiation in the TXCW register and disable
1688 * forced link in the Device Control register in an
1689 * attempt to auto-negotiate with our link partner.
1690 */
1691 if (rxcw & E1000_RXCW_C) {
1692 /* Enable autoneg, and unforce link up */
1693 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1694 E1000_WRITE_REG(hw, E1000_CTRL,
1695 (ctrl & ~E1000_CTRL_SLU));
1696 mac->serdes_link_state =
1697 e1000_serdes_link_autoneg_progress;
1698 mac->serdes_has_link = false;
1699 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1700 } else {
1701 mac->serdes_has_link = true;
1702 }
1703 break;
1704
1705 case e1000_serdes_link_autoneg_progress:
1706 if (rxcw & E1000_RXCW_C) {
1707 /* We received /C/ ordered sets, meaning the
1708 * link partner has autonegotiated, and we can
1709 * trust the Link Up (LU) status bit.
1710 */
1711 if (status & E1000_STATUS_LU) {
1712 mac->serdes_link_state =
1713 e1000_serdes_link_autoneg_complete;
1714 DEBUGOUT("AN_PROG -> AN_UP\n");
1715 mac->serdes_has_link = true;
1716 } else {
1717 /* Autoneg completed, but failed. */
1718 mac->serdes_link_state =
1719 e1000_serdes_link_down;
1720 DEBUGOUT("AN_PROG -> DOWN\n");
1721 }
1722 } else {
1723 /* The link partner did not autoneg.
1724 * Force link up and full duplex, and change
1725 * state to forced.
1726 */
1727 E1000_WRITE_REG(hw, E1000_TXCW,
1728 (mac->txcw & ~E1000_TXCW_ANE));
1729 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1730 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1731
1732 /* Configure Flow Control after link up. */
1733 ret_val =
1734 e1000_config_fc_after_link_up_generic(hw);
1735 if (ret_val) {
1736 DEBUGOUT("Error config flow control\n");
1737 break;
1738 }
1739 mac->serdes_link_state =
1740 e1000_serdes_link_forced_up;
1741 mac->serdes_has_link = true;
1742 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1743 }
1744 break;
1745
1746 case e1000_serdes_link_down:
1747 default:
1748 /* The link was down but the receiver has now gained
1749 * valid sync, so lets see if we can bring the link
1750 * up.
1751 */
1752 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1753 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1754 ~E1000_CTRL_SLU));
1755 mac->serdes_link_state =
1756 e1000_serdes_link_autoneg_progress;
1757 mac->serdes_has_link = false;
1758 DEBUGOUT("DOWN -> AN_PROG\n");
1759 break;
1760 }
1761 } else {
1762 if (!(rxcw & E1000_RXCW_SYNCH)) {
1763 mac->serdes_has_link = false;
1764 mac->serdes_link_state = e1000_serdes_link_down;
1765 DEBUGOUT("ANYSTATE -> DOWN\n");
1766 } else {
1767 /* Check several times, if SYNCH bit and CONFIG
1768 * bit both are consistently 1 then simply ignore
1769 * the IV bit and restart Autoneg
1770 */
1771 for (i = 0; i < AN_RETRY_COUNT; i++) {
1772 usec_delay(10);
1773 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1774 if ((rxcw & E1000_RXCW_SYNCH) &&
1775 (rxcw & E1000_RXCW_C))
1776 continue;
1777
1778 if (rxcw & E1000_RXCW_IV) {
1779 mac->serdes_has_link = false;
1780 mac->serdes_link_state =
1781 e1000_serdes_link_down;
1782 DEBUGOUT("ANYSTATE -> DOWN\n");
1783 break;
1784 }
1785 }
1786
1787 if (i == AN_RETRY_COUNT) {
1788 txcw = E1000_READ_REG(hw, E1000_TXCW);
1789 txcw |= E1000_TXCW_ANE;
1790 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1791 mac->serdes_link_state =
1792 e1000_serdes_link_autoneg_progress;
1793 mac->serdes_has_link = false;
1794 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1795 }
1796 }
1797 }
1798
1799 return ret_val;
1800 }
1801
1802 /**
1803 * e1000_valid_led_default_82571 - Verify a valid default LED config
1804 * @hw: pointer to the HW structure
1805 * @data: pointer to the NVM (EEPROM)
1806 *
1807 * Read the EEPROM for the current default LED configuration. If the
1808 * LED configuration is not valid, set to a valid LED configuration.
1809 **/
1810 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1811 {
1812 s32 ret_val;
1813
1814 DEBUGFUNC("e1000_valid_led_default_82571");
1815
1816 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1817 if (ret_val) {
1818 DEBUGOUT("NVM Read Error\n");
1819 return ret_val;
1820 }
1821
1822 switch (hw->mac.type) {
1823 case e1000_82573:
1824 case e1000_82574:
1825 case e1000_82583:
1826 if (*data == ID_LED_RESERVED_F746)
1827 *data = ID_LED_DEFAULT_82573;
1828 break;
1829 default:
1830 if (*data == ID_LED_RESERVED_0000 ||
1831 *data == ID_LED_RESERVED_FFFF)
1832 *data = ID_LED_DEFAULT;
1833 break;
1834 }
1835
1836 return E1000_SUCCESS;
1837 }
1838
1839 /**
1840 * e1000_get_laa_state_82571 - Get locally administered address state
1841 * @hw: pointer to the HW structure
1842 *
1843 * Retrieve and return the current locally administered address state.
1844 **/
1845 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1846 {
1847 DEBUGFUNC("e1000_get_laa_state_82571");
1848
1849 if (hw->mac.type != e1000_82571)
1850 return false;
1851
1852 return hw->dev_spec._82571.laa_is_present;
1853 }
1854
1855 /**
1856 * e1000_set_laa_state_82571 - Set locally administered address state
1857 * @hw: pointer to the HW structure
1858 * @state: enable/disable locally administered address
1859 *
1860 * Enable/Disable the current locally administered address state.
1861 **/
1862 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1863 {
1864 DEBUGFUNC("e1000_set_laa_state_82571");
1865
1866 if (hw->mac.type != e1000_82571)
1867 return;
1868
1869 hw->dev_spec._82571.laa_is_present = state;
1870
1871 /* If workaround is activated... */
1872 if (state)
1873 /* Hold a copy of the LAA in RAR[14] This is done so that
1874 * between the time RAR[0] gets clobbered and the time it
1875 * gets fixed, the actual LAA is in one of the RARs and no
1876 * incoming packets directed to this port are dropped.
1877 * Eventually the LAA will be in RAR[0] and RAR[14].
1878 */
1879 hw->mac.ops.rar_set(hw, hw->mac.addr,
1880 hw->mac.rar_entry_count - 1);
1881 return;
1882 }
1883
1884 /**
1885 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1886 * @hw: pointer to the HW structure
1887 *
1888 * Verifies that the EEPROM has completed the update. After updating the
1889 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1890 * the checksum fix is not implemented, we need to set the bit and update
1891 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1892 * we need to return bad checksum.
1893 **/
1894 STATIC s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1895 {
1896 struct e1000_nvm_info *nvm = &hw->nvm;
1897 s32 ret_val;
1898 u16 data;
1899
1900 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1901
1902 if (nvm->type != e1000_nvm_flash_hw)
1903 return E1000_SUCCESS;
1904
1905 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1906 * 10h-12h. Checksum may need to be fixed.
1907 */
1908 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1909 if (ret_val)
1910 return ret_val;
1911
1912 if (!(data & 0x10)) {
1913 /* Read 0x23 and check bit 15. This bit is a 1
1914 * when the checksum has already been fixed. If
1915 * the checksum is still wrong and this bit is a
1916 * 1, we need to return bad checksum. Otherwise,
1917 * we need to set this bit to a 1 and update the
1918 * checksum.
1919 */
1920 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1921 if (ret_val)
1922 return ret_val;
1923
1924 if (!(data & 0x8000)) {
1925 data |= 0x8000;
1926 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1927 if (ret_val)
1928 return ret_val;
1929 ret_val = nvm->ops.update(hw);
1930 if (ret_val)
1931 return ret_val;
1932 }
1933 }
1934
1935 return E1000_SUCCESS;
1936 }
1937
1938
1939 /**
1940 * e1000_read_mac_addr_82571 - Read device MAC address
1941 * @hw: pointer to the HW structure
1942 **/
1943 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1944 {
1945 DEBUGFUNC("e1000_read_mac_addr_82571");
1946
1947 if (hw->mac.type == e1000_82571) {
1948 s32 ret_val;
1949
1950 /* If there's an alternate MAC address place it in RAR0
1951 * so that it will override the Si installed default perm
1952 * address.
1953 */
1954 ret_val = e1000_check_alt_mac_addr_generic(hw);
1955 if (ret_val)
1956 return ret_val;
1957 }
1958
1959 return e1000_read_mac_addr_generic(hw);
1960 }
1961
1962 /**
1963 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1964 * @hw: pointer to the HW structure
1965 *
1966 * In the case of a PHY power down to save power, or to turn off link during a
1967 * driver unload, or wake on lan is not enabled, remove the link.
1968 **/
1969 STATIC void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1970 {
1971 struct e1000_phy_info *phy = &hw->phy;
1972 struct e1000_mac_info *mac = &hw->mac;
1973
1974 if (!phy->ops.check_reset_block)
1975 return;
1976
1977 /* If the management interface is not enabled, then power down */
1978 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1979 e1000_power_down_phy_copper(hw);
1980
1981 return;
1982 }
1983
1984 /**
1985 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1986 * @hw: pointer to the HW structure
1987 *
1988 * Clears the hardware counters by reading the counter registers.
1989 **/
1990 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1991 {
1992 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1993
1994 e1000_clear_hw_cntrs_base_generic(hw);
1995
1996 E1000_READ_REG(hw, E1000_PRC64);
1997 E1000_READ_REG(hw, E1000_PRC127);
1998 E1000_READ_REG(hw, E1000_PRC255);
1999 E1000_READ_REG(hw, E1000_PRC511);
2000 E1000_READ_REG(hw, E1000_PRC1023);
2001 E1000_READ_REG(hw, E1000_PRC1522);
2002 E1000_READ_REG(hw, E1000_PTC64);
2003 E1000_READ_REG(hw, E1000_PTC127);
2004 E1000_READ_REG(hw, E1000_PTC255);
2005 E1000_READ_REG(hw, E1000_PTC511);
2006 E1000_READ_REG(hw, E1000_PTC1023);
2007 E1000_READ_REG(hw, E1000_PTC1522);
2008
2009 E1000_READ_REG(hw, E1000_ALGNERRC);
2010 E1000_READ_REG(hw, E1000_RXERRC);
2011 E1000_READ_REG(hw, E1000_TNCRS);
2012 E1000_READ_REG(hw, E1000_CEXTERR);
2013 E1000_READ_REG(hw, E1000_TSCTC);
2014 E1000_READ_REG(hw, E1000_TSCTFC);
2015
2016 E1000_READ_REG(hw, E1000_MGTPRC);
2017 E1000_READ_REG(hw, E1000_MGTPDC);
2018 E1000_READ_REG(hw, E1000_MGTPTC);
2019
2020 E1000_READ_REG(hw, E1000_IAC);
2021 E1000_READ_REG(hw, E1000_ICRXOC);
2022
2023 E1000_READ_REG(hw, E1000_ICRXPTC);
2024 E1000_READ_REG(hw, E1000_ICRXATC);
2025 E1000_READ_REG(hw, E1000_ICTXPTC);
2026 E1000_READ_REG(hw, E1000_ICTXATC);
2027 E1000_READ_REG(hw, E1000_ICTXQEC);
2028 E1000_READ_REG(hw, E1000_ICTXQMTC);
2029 E1000_READ_REG(hw, E1000_ICRXDMTC);
2030 }
Ceph