1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001 - 2015 Intel Corporation
8 STATIC s32
e1000_acquire_nvm_i210(struct e1000_hw
*hw
);
9 STATIC
void e1000_release_nvm_i210(struct e1000_hw
*hw
);
10 STATIC s32
e1000_get_hw_semaphore_i210(struct e1000_hw
*hw
);
11 STATIC s32
e1000_write_nvm_srwr(struct e1000_hw
*hw
, u16 offset
, u16 words
,
13 STATIC s32
e1000_pool_flash_update_done_i210(struct e1000_hw
*hw
);
14 STATIC s32
e1000_valid_led_default_i210(struct e1000_hw
*hw
, u16
*data
);
17 * e1000_acquire_nvm_i210 - Request for access to EEPROM
18 * @hw: pointer to the HW structure
20 * Acquire the necessary semaphores for exclusive access to the EEPROM.
21 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
22 * Return successful if access grant bit set, else clear the request for
23 * EEPROM access and return -E1000_ERR_NVM (-1).
25 STATIC s32
e1000_acquire_nvm_i210(struct e1000_hw
*hw
)
29 DEBUGFUNC("e1000_acquire_nvm_i210");
31 ret_val
= e1000_acquire_swfw_sync_i210(hw
, E1000_SWFW_EEP_SM
);
37 * e1000_release_nvm_i210 - Release exclusive access to EEPROM
38 * @hw: pointer to the HW structure
40 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
41 * then release the semaphores acquired.
43 STATIC
void e1000_release_nvm_i210(struct e1000_hw
*hw
)
45 DEBUGFUNC("e1000_release_nvm_i210");
47 e1000_release_swfw_sync_i210(hw
, E1000_SWFW_EEP_SM
);
51 * e1000_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
52 * @hw: pointer to the HW structure
53 * @mask: specifies which semaphore to acquire
55 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
56 * will also specify which port we're acquiring the lock for.
58 s32
e1000_acquire_swfw_sync_i210(struct e1000_hw
*hw
, u16 mask
)
62 u32 fwmask
= mask
<< 16;
63 s32 ret_val
= E1000_SUCCESS
;
64 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
66 DEBUGFUNC("e1000_acquire_swfw_sync_i210");
69 if (e1000_get_hw_semaphore_i210(hw
)) {
70 ret_val
= -E1000_ERR_SWFW_SYNC
;
74 swfw_sync
= E1000_READ_REG(hw
, E1000_SW_FW_SYNC
);
75 if (!(swfw_sync
& (fwmask
| swmask
)))
79 * Firmware currently using resource (fwmask)
80 * or other software thread using resource (swmask)
82 e1000_put_hw_semaphore_generic(hw
);
88 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
89 ret_val
= -E1000_ERR_SWFW_SYNC
;
94 E1000_WRITE_REG(hw
, E1000_SW_FW_SYNC
, swfw_sync
);
96 e1000_put_hw_semaphore_generic(hw
);
103 * e1000_release_swfw_sync_i210 - Release SW/FW semaphore
104 * @hw: pointer to the HW structure
105 * @mask: specifies which semaphore to acquire
107 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
108 * will also specify which port we're releasing the lock for.
110 void e1000_release_swfw_sync_i210(struct e1000_hw
*hw
, u16 mask
)
114 DEBUGFUNC("e1000_release_swfw_sync_i210");
116 while (e1000_get_hw_semaphore_i210(hw
) != E1000_SUCCESS
)
119 swfw_sync
= E1000_READ_REG(hw
, E1000_SW_FW_SYNC
);
121 E1000_WRITE_REG(hw
, E1000_SW_FW_SYNC
, swfw_sync
);
123 e1000_put_hw_semaphore_generic(hw
);
127 * e1000_get_hw_semaphore_i210 - Acquire hardware semaphore
128 * @hw: pointer to the HW structure
130 * Acquire the HW semaphore to access the PHY or NVM
132 STATIC s32
e1000_get_hw_semaphore_i210(struct e1000_hw
*hw
)
135 s32 timeout
= hw
->nvm
.word_size
+ 1;
138 DEBUGFUNC("e1000_get_hw_semaphore_i210");
140 /* Get the SW semaphore */
141 while (i
< timeout
) {
142 swsm
= E1000_READ_REG(hw
, E1000_SWSM
);
143 if (!(swsm
& E1000_SWSM_SMBI
))
151 /* In rare circumstances, the SW semaphore may already be held
152 * unintentionally. Clear the semaphore once before giving up.
154 if (hw
->dev_spec
._82575
.clear_semaphore_once
) {
155 hw
->dev_spec
._82575
.clear_semaphore_once
= false;
156 e1000_put_hw_semaphore_generic(hw
);
157 for (i
= 0; i
< timeout
; i
++) {
158 swsm
= E1000_READ_REG(hw
, E1000_SWSM
);
159 if (!(swsm
& E1000_SWSM_SMBI
))
166 /* If we do not have the semaphore here, we have to give up. */
168 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
169 return -E1000_ERR_NVM
;
173 /* Get the FW semaphore. */
174 for (i
= 0; i
< timeout
; i
++) {
175 swsm
= E1000_READ_REG(hw
, E1000_SWSM
);
176 E1000_WRITE_REG(hw
, E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
178 /* Semaphore acquired if bit latched */
179 if (E1000_READ_REG(hw
, E1000_SWSM
) & E1000_SWSM_SWESMBI
)
186 /* Release semaphores */
187 e1000_put_hw_semaphore_generic(hw
);
188 DEBUGOUT("Driver can't access the NVM\n");
189 return -E1000_ERR_NVM
;
192 return E1000_SUCCESS
;
196 * e1000_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
197 * @hw: pointer to the HW structure
198 * @offset: offset of word in the Shadow Ram to read
199 * @words: number of words to read
200 * @data: word read from the Shadow Ram
202 * Reads a 16 bit word from the Shadow Ram using the EERD register.
203 * Uses necessary synchronization semaphores.
205 s32
e1000_read_nvm_srrd_i210(struct e1000_hw
*hw
, u16 offset
, u16 words
,
208 s32 status
= E1000_SUCCESS
;
211 DEBUGFUNC("e1000_read_nvm_srrd_i210");
213 /* We cannot hold synchronization semaphores for too long,
214 * because of forceful takeover procedure. However it is more efficient
215 * to read in bursts than synchronizing access for each word. */
216 for (i
= 0; i
< words
; i
+= E1000_EERD_EEWR_MAX_COUNT
) {
217 count
= (words
- i
) / E1000_EERD_EEWR_MAX_COUNT
> 0 ?
218 E1000_EERD_EEWR_MAX_COUNT
: (words
- i
);
219 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
220 status
= e1000_read_nvm_eerd(hw
, offset
, count
,
222 hw
->nvm
.ops
.release(hw
);
224 status
= E1000_ERR_SWFW_SYNC
;
227 if (status
!= E1000_SUCCESS
)
235 * e1000_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
236 * @hw: pointer to the HW structure
237 * @offset: offset within the Shadow RAM to be written to
238 * @words: number of words to write
239 * @data: 16 bit word(s) to be written to the Shadow RAM
241 * Writes data to Shadow RAM at offset using EEWR register.
243 * If e1000_update_nvm_checksum is not called after this function , the
244 * data will not be committed to FLASH and also Shadow RAM will most likely
245 * contain an invalid checksum.
247 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
250 s32
e1000_write_nvm_srwr_i210(struct e1000_hw
*hw
, u16 offset
, u16 words
,
253 s32 status
= E1000_SUCCESS
;
256 DEBUGFUNC("e1000_write_nvm_srwr_i210");
258 /* We cannot hold synchronization semaphores for too long,
259 * because of forceful takeover procedure. However it is more efficient
260 * to write in bursts than synchronizing access for each word. */
261 for (i
= 0; i
< words
; i
+= E1000_EERD_EEWR_MAX_COUNT
) {
262 count
= (words
- i
) / E1000_EERD_EEWR_MAX_COUNT
> 0 ?
263 E1000_EERD_EEWR_MAX_COUNT
: (words
- i
);
264 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
265 status
= e1000_write_nvm_srwr(hw
, offset
, count
,
267 hw
->nvm
.ops
.release(hw
);
269 status
= E1000_ERR_SWFW_SYNC
;
272 if (status
!= E1000_SUCCESS
)
280 * e1000_write_nvm_srwr - Write to Shadow Ram using EEWR
281 * @hw: pointer to the HW structure
282 * @offset: offset within the Shadow Ram to be written to
283 * @words: number of words to write
284 * @data: 16 bit word(s) to be written to the Shadow Ram
286 * Writes data to Shadow Ram at offset using EEWR register.
288 * If e1000_update_nvm_checksum is not called after this function , the
289 * Shadow Ram will most likely contain an invalid checksum.
291 STATIC s32
e1000_write_nvm_srwr(struct e1000_hw
*hw
, u16 offset
, u16 words
,
294 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
296 u32 attempts
= 100000;
297 s32 ret_val
= E1000_SUCCESS
;
299 DEBUGFUNC("e1000_write_nvm_srwr");
302 * A check for invalid values: offset too large, too many words,
303 * too many words for the offset, and not enough words.
305 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
307 DEBUGOUT("nvm parameter(s) out of bounds\n");
308 ret_val
= -E1000_ERR_NVM
;
312 for (i
= 0; i
< words
; i
++) {
313 eewr
= ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) |
314 (data
[i
] << E1000_NVM_RW_REG_DATA
) |
315 E1000_NVM_RW_REG_START
;
317 E1000_WRITE_REG(hw
, E1000_SRWR
, eewr
);
319 for (k
= 0; k
< attempts
; k
++) {
320 if (E1000_NVM_RW_REG_DONE
&
321 E1000_READ_REG(hw
, E1000_SRWR
)) {
322 ret_val
= E1000_SUCCESS
;
328 if (ret_val
!= E1000_SUCCESS
) {
329 DEBUGOUT("Shadow RAM write EEWR timed out\n");
338 /** e1000_read_invm_word_i210 - Reads OTP
339 * @hw: pointer to the HW structure
340 * @address: the word address (aka eeprom offset) to read
341 * @data: pointer to the data read
343 * Reads 16-bit words from the OTP. Return error when the word is not
346 STATIC s32
e1000_read_invm_word_i210(struct e1000_hw
*hw
, u8 address
, u16
*data
)
348 s32 status
= -E1000_ERR_INVM_VALUE_NOT_FOUND
;
351 u8 record_type
, word_address
;
353 DEBUGFUNC("e1000_read_invm_word_i210");
355 for (i
= 0; i
< E1000_INVM_SIZE
; i
++) {
356 invm_dword
= E1000_READ_REG(hw
, E1000_INVM_DATA_REG(i
));
357 /* Get record type */
358 record_type
= INVM_DWORD_TO_RECORD_TYPE(invm_dword
);
359 if (record_type
== E1000_INVM_UNINITIALIZED_STRUCTURE
)
361 if (record_type
== E1000_INVM_CSR_AUTOLOAD_STRUCTURE
)
362 i
+= E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS
;
363 if (record_type
== E1000_INVM_RSA_KEY_SHA256_STRUCTURE
)
364 i
+= E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS
;
365 if (record_type
== E1000_INVM_WORD_AUTOLOAD_STRUCTURE
) {
366 word_address
= INVM_DWORD_TO_WORD_ADDRESS(invm_dword
);
367 if (word_address
== address
) {
368 *data
= INVM_DWORD_TO_WORD_DATA(invm_dword
);
369 DEBUGOUT2("Read INVM Word 0x%02x = %x",
371 status
= E1000_SUCCESS
;
376 if (status
!= E1000_SUCCESS
)
377 DEBUGOUT1("Requested word 0x%02x not found in OTP\n", address
);
381 /** e1000_read_invm_i210 - Read invm wrapper function for I210/I211
382 * @hw: pointer to the HW structure
383 * @address: the word address (aka eeprom offset) to read
384 * @data: pointer to the data read
386 * Wrapper function to return data formerly found in the NVM.
388 STATIC s32
e1000_read_invm_i210(struct e1000_hw
*hw
, u16 offset
,
389 u16 E1000_UNUSEDARG words
, u16
*data
)
391 s32 ret_val
= E1000_SUCCESS
;
392 UNREFERENCED_1PARAMETER(words
);
394 DEBUGFUNC("e1000_read_invm_i210");
396 /* Only the MAC addr is required to be present in the iNVM */
399 ret_val
= e1000_read_invm_word_i210(hw
, (u8
)offset
, &data
[0]);
400 ret_val
|= e1000_read_invm_word_i210(hw
, (u8
)offset
+1,
402 ret_val
|= e1000_read_invm_word_i210(hw
, (u8
)offset
+2,
404 if (ret_val
!= E1000_SUCCESS
)
405 DEBUGOUT("MAC Addr not found in iNVM\n");
407 case NVM_INIT_CTRL_2
:
408 ret_val
= e1000_read_invm_word_i210(hw
, (u8
)offset
, data
);
409 if (ret_val
!= E1000_SUCCESS
) {
410 *data
= NVM_INIT_CTRL_2_DEFAULT_I211
;
411 ret_val
= E1000_SUCCESS
;
414 case NVM_INIT_CTRL_4
:
415 ret_val
= e1000_read_invm_word_i210(hw
, (u8
)offset
, data
);
416 if (ret_val
!= E1000_SUCCESS
) {
417 *data
= NVM_INIT_CTRL_4_DEFAULT_I211
;
418 ret_val
= E1000_SUCCESS
;
422 ret_val
= e1000_read_invm_word_i210(hw
, (u8
)offset
, data
);
423 if (ret_val
!= E1000_SUCCESS
) {
424 *data
= NVM_LED_1_CFG_DEFAULT_I211
;
425 ret_val
= E1000_SUCCESS
;
428 case NVM_LED_0_2_CFG
:
429 ret_val
= e1000_read_invm_word_i210(hw
, (u8
)offset
, data
);
430 if (ret_val
!= E1000_SUCCESS
) {
431 *data
= NVM_LED_0_2_CFG_DEFAULT_I211
;
432 ret_val
= E1000_SUCCESS
;
435 case NVM_ID_LED_SETTINGS
:
436 ret_val
= e1000_read_invm_word_i210(hw
, (u8
)offset
, data
);
437 if (ret_val
!= E1000_SUCCESS
) {
438 *data
= ID_LED_RESERVED_FFFF
;
439 ret_val
= E1000_SUCCESS
;
443 *data
= hw
->subsystem_device_id
;
446 *data
= hw
->subsystem_vendor_id
;
449 *data
= hw
->device_id
;
452 *data
= hw
->vendor_id
;
455 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset
);
456 *data
= NVM_RESERVED_WORD
;
463 * e1000_read_invm_version - Reads iNVM version and image type
464 * @hw: pointer to the HW structure
465 * @invm_ver: version structure for the version read
467 * Reads iNVM version and image type.
469 s32
e1000_read_invm_version(struct e1000_hw
*hw
,
470 struct e1000_fw_version
*invm_ver
)
473 u32
*next_record
= NULL
;
476 u32 invm_blocks
= E1000_INVM_SIZE
- (E1000_INVM_ULT_BYTES_SIZE
/
477 E1000_INVM_RECORD_SIZE_IN_BYTES
);
478 u32 buffer
[E1000_INVM_SIZE
];
479 s32 status
= -E1000_ERR_INVM_VALUE_NOT_FOUND
;
482 DEBUGFUNC("e1000_read_invm_version");
484 /* Read iNVM memory */
485 for (i
= 0; i
< E1000_INVM_SIZE
; i
++) {
486 invm_dword
= E1000_READ_REG(hw
, E1000_INVM_DATA_REG(i
));
487 buffer
[i
] = invm_dword
;
490 /* Read version number */
491 for (i
= 1; i
< invm_blocks
; i
++) {
492 record
= &buffer
[invm_blocks
- i
];
493 next_record
= &buffer
[invm_blocks
- i
+ 1];
495 /* Check if we have first version location used */
496 if ((i
== 1) && ((*record
& E1000_INVM_VER_FIELD_ONE
) == 0)) {
498 status
= E1000_SUCCESS
;
501 /* Check if we have second version location used */
503 ((*record
& E1000_INVM_VER_FIELD_TWO
) == 0)) {
504 version
= (*record
& E1000_INVM_VER_FIELD_ONE
) >> 3;
505 status
= E1000_SUCCESS
;
509 * Check if we have odd version location
510 * used and it is the last one used
512 else if ((((*record
& E1000_INVM_VER_FIELD_ONE
) == 0) &&
513 ((*record
& 0x3) == 0)) || (((*record
& 0x3) != 0) &&
515 version
= (*next_record
& E1000_INVM_VER_FIELD_TWO
)
517 status
= E1000_SUCCESS
;
521 * Check if we have even version location
522 * used and it is the last one used
524 else if (((*record
& E1000_INVM_VER_FIELD_TWO
) == 0) &&
525 ((*record
& 0x3) == 0)) {
526 version
= (*record
& E1000_INVM_VER_FIELD_ONE
) >> 3;
527 status
= E1000_SUCCESS
;
532 if (status
== E1000_SUCCESS
) {
533 invm_ver
->invm_major
= (version
& E1000_INVM_MAJOR_MASK
)
534 >> E1000_INVM_MAJOR_SHIFT
;
535 invm_ver
->invm_minor
= version
& E1000_INVM_MINOR_MASK
;
537 /* Read Image Type */
538 for (i
= 1; i
< invm_blocks
; i
++) {
539 record
= &buffer
[invm_blocks
- i
];
540 next_record
= &buffer
[invm_blocks
- i
+ 1];
542 /* Check if we have image type in first location used */
543 if ((i
== 1) && ((*record
& E1000_INVM_IMGTYPE_FIELD
) == 0)) {
544 invm_ver
->invm_img_type
= 0;
545 status
= E1000_SUCCESS
;
548 /* Check if we have image type in first location used */
549 else if ((((*record
& 0x3) == 0) &&
550 ((*record
& E1000_INVM_IMGTYPE_FIELD
) == 0)) ||
551 ((((*record
& 0x3) != 0) && (i
!= 1)))) {
552 invm_ver
->invm_img_type
=
553 (*next_record
& E1000_INVM_IMGTYPE_FIELD
) >> 23;
554 status
= E1000_SUCCESS
;
562 * e1000_validate_nvm_checksum_i210 - Validate EEPROM checksum
563 * @hw: pointer to the HW structure
565 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
566 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
568 s32
e1000_validate_nvm_checksum_i210(struct e1000_hw
*hw
)
570 s32 status
= E1000_SUCCESS
;
571 s32 (*read_op_ptr
)(struct e1000_hw
*, u16
, u16
, u16
*);
573 DEBUGFUNC("e1000_validate_nvm_checksum_i210");
575 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
578 * Replace the read function with semaphore grabbing with
579 * the one that skips this for a while.
580 * We have semaphore taken already here.
582 read_op_ptr
= hw
->nvm
.ops
.read
;
583 hw
->nvm
.ops
.read
= e1000_read_nvm_eerd
;
585 status
= e1000_validate_nvm_checksum_generic(hw
);
587 /* Revert original read operation. */
588 hw
->nvm
.ops
.read
= read_op_ptr
;
590 hw
->nvm
.ops
.release(hw
);
592 status
= E1000_ERR_SWFW_SYNC
;
600 * e1000_update_nvm_checksum_i210 - Update EEPROM checksum
601 * @hw: pointer to the HW structure
603 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
604 * up to the checksum. Then calculates the EEPROM checksum and writes the
605 * value to the EEPROM. Next commit EEPROM data onto the Flash.
607 s32
e1000_update_nvm_checksum_i210(struct e1000_hw
*hw
)
613 DEBUGFUNC("e1000_update_nvm_checksum_i210");
616 * Read the first word from the EEPROM. If this times out or fails, do
617 * not continue or we could be in for a very long wait while every
620 ret_val
= e1000_read_nvm_eerd(hw
, 0, 1, &nvm_data
);
621 if (ret_val
!= E1000_SUCCESS
) {
622 DEBUGOUT("EEPROM read failed\n");
626 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
628 * Do not use hw->nvm.ops.write, hw->nvm.ops.read
629 * because we do not want to take the synchronization
630 * semaphores twice here.
633 for (i
= 0; i
< NVM_CHECKSUM_REG
; i
++) {
634 ret_val
= e1000_read_nvm_eerd(hw
, i
, 1, &nvm_data
);
636 hw
->nvm
.ops
.release(hw
);
637 DEBUGOUT("NVM Read Error while updating checksum.\n");
640 checksum
+= nvm_data
;
642 checksum
= (u16
) NVM_SUM
- checksum
;
643 ret_val
= e1000_write_nvm_srwr(hw
, NVM_CHECKSUM_REG
, 1,
645 if (ret_val
!= E1000_SUCCESS
) {
646 hw
->nvm
.ops
.release(hw
);
647 DEBUGOUT("NVM Write Error while updating checksum.\n");
651 hw
->nvm
.ops
.release(hw
);
653 ret_val
= e1000_update_flash_i210(hw
);
655 ret_val
= E1000_ERR_SWFW_SYNC
;
662 * e1000_get_flash_presence_i210 - Check if flash device is detected.
663 * @hw: pointer to the HW structure
666 bool e1000_get_flash_presence_i210(struct e1000_hw
*hw
)
669 bool ret_val
= false;
671 DEBUGFUNC("e1000_get_flash_presence_i210");
673 eec
= E1000_READ_REG(hw
, E1000_EECD
);
675 if (eec
& E1000_EECD_FLASH_DETECTED_I210
)
682 * e1000_update_flash_i210 - Commit EEPROM to the flash
683 * @hw: pointer to the HW structure
686 s32
e1000_update_flash_i210(struct e1000_hw
*hw
)
691 DEBUGFUNC("e1000_update_flash_i210");
693 ret_val
= e1000_pool_flash_update_done_i210(hw
);
694 if (ret_val
== -E1000_ERR_NVM
) {
695 DEBUGOUT("Flash update time out\n");
699 flup
= E1000_READ_REG(hw
, E1000_EECD
) | E1000_EECD_FLUPD_I210
;
700 E1000_WRITE_REG(hw
, E1000_EECD
, flup
);
702 ret_val
= e1000_pool_flash_update_done_i210(hw
);
703 if (ret_val
== E1000_SUCCESS
)
704 DEBUGOUT("Flash update complete\n");
706 DEBUGOUT("Flash update time out\n");
713 * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
714 * @hw: pointer to the HW structure
717 s32
e1000_pool_flash_update_done_i210(struct e1000_hw
*hw
)
719 s32 ret_val
= -E1000_ERR_NVM
;
722 DEBUGFUNC("e1000_pool_flash_update_done_i210");
724 for (i
= 0; i
< E1000_FLUDONE_ATTEMPTS
; i
++) {
725 reg
= E1000_READ_REG(hw
, E1000_EECD
);
726 if (reg
& E1000_EECD_FLUDONE_I210
) {
727 ret_val
= E1000_SUCCESS
;
737 * e1000_init_nvm_params_i210 - Initialize i210 NVM function pointers
738 * @hw: pointer to the HW structure
740 * Initialize the i210/i211 NVM parameters and function pointers.
742 STATIC s32
e1000_init_nvm_params_i210(struct e1000_hw
*hw
)
745 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
747 DEBUGFUNC("e1000_init_nvm_params_i210");
749 ret_val
= e1000_init_nvm_params_82575(hw
);
750 nvm
->ops
.acquire
= e1000_acquire_nvm_i210
;
751 nvm
->ops
.release
= e1000_release_nvm_i210
;
752 nvm
->ops
.valid_led_default
= e1000_valid_led_default_i210
;
753 if (e1000_get_flash_presence_i210(hw
)) {
754 hw
->nvm
.type
= e1000_nvm_flash_hw
;
755 nvm
->ops
.read
= e1000_read_nvm_srrd_i210
;
756 nvm
->ops
.write
= e1000_write_nvm_srwr_i210
;
757 nvm
->ops
.validate
= e1000_validate_nvm_checksum_i210
;
758 nvm
->ops
.update
= e1000_update_nvm_checksum_i210
;
760 hw
->nvm
.type
= e1000_nvm_invm
;
761 nvm
->ops
.read
= e1000_read_invm_i210
;
762 nvm
->ops
.write
= e1000_null_write_nvm
;
763 nvm
->ops
.validate
= e1000_null_ops_generic
;
764 nvm
->ops
.update
= e1000_null_ops_generic
;
770 * e1000_init_function_pointers_i210 - Init func ptrs.
771 * @hw: pointer to the HW structure
773 * Called to initialize all function pointers and parameters.
775 void e1000_init_function_pointers_i210(struct e1000_hw
*hw
)
777 e1000_init_function_pointers_82575(hw
);
778 hw
->nvm
.ops
.init_params
= e1000_init_nvm_params_i210
;
784 * e1000_valid_led_default_i210 - Verify a valid default LED config
785 * @hw: pointer to the HW structure
786 * @data: pointer to the NVM (EEPROM)
788 * Read the EEPROM for the current default LED configuration. If the
789 * LED configuration is not valid, set to a valid LED configuration.
791 STATIC s32
e1000_valid_led_default_i210(struct e1000_hw
*hw
, u16
*data
)
795 DEBUGFUNC("e1000_valid_led_default_i210");
797 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
799 DEBUGOUT("NVM Read Error\n");
803 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
) {
804 switch (hw
->phy
.media_type
) {
805 case e1000_media_type_internal_serdes
:
806 *data
= ID_LED_DEFAULT_I210_SERDES
;
808 case e1000_media_type_copper
:
810 *data
= ID_LED_DEFAULT_I210
;
819 * __e1000_access_xmdio_reg - Read/write XMDIO register
820 * @hw: pointer to the HW structure
821 * @address: XMDIO address to program
822 * @dev_addr: device address to program
823 * @data: pointer to value to read/write from/to the XMDIO address
824 * @read: boolean flag to indicate read or write
826 STATIC s32
__e1000_access_xmdio_reg(struct e1000_hw
*hw
, u16 address
,
827 u8 dev_addr
, u16
*data
, bool read
)
831 DEBUGFUNC("__e1000_access_xmdio_reg");
833 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAC
, dev_addr
);
837 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAAD
, address
);
841 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAC
, E1000_MMDAC_FUNC_DATA
|
847 ret_val
= hw
->phy
.ops
.read_reg(hw
, E1000_MMDAAD
, data
);
849 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAAD
, *data
);
853 /* Recalibrate the device back to 0 */
854 ret_val
= hw
->phy
.ops
.write_reg(hw
, E1000_MMDAC
, 0);
862 * e1000_read_xmdio_reg - Read XMDIO register
863 * @hw: pointer to the HW structure
864 * @addr: XMDIO address to program
865 * @dev_addr: device address to program
866 * @data: value to be read from the EMI address
868 s32
e1000_read_xmdio_reg(struct e1000_hw
*hw
, u16 addr
, u8 dev_addr
, u16
*data
)
870 DEBUGFUNC("e1000_read_xmdio_reg");
872 return __e1000_access_xmdio_reg(hw
, addr
, dev_addr
, data
, true);
876 * e1000_write_xmdio_reg - Write XMDIO register
877 * @hw: pointer to the HW structure
878 * @addr: XMDIO address to program
879 * @dev_addr: device address to program
880 * @data: value to be written to the XMDIO address
882 s32
e1000_write_xmdio_reg(struct e1000_hw
*hw
, u16 addr
, u8 dev_addr
, u16 data
)
884 DEBUGFUNC("e1000_read_xmdio_reg");
886 return __e1000_access_xmdio_reg(hw
, addr
, dev_addr
, &data
, false);
890 * e1000_pll_workaround_i210
891 * @hw: pointer to the HW structure
893 * Works around an errata in the PLL circuit where it occasionally
894 * provides the wrong clock frequency after power up.
896 STATIC s32
e1000_pll_workaround_i210(struct e1000_hw
*hw
)
899 u32 wuc
, mdicnfg
, ctrl
, ctrl_ext
, reg_val
;
900 u16 nvm_word
, phy_word
, pci_word
, tmp_nvm
;
903 /* Get and set needed register values */
904 wuc
= E1000_READ_REG(hw
, E1000_WUC
);
905 mdicnfg
= E1000_READ_REG(hw
, E1000_MDICNFG
);
906 reg_val
= mdicnfg
& ~E1000_MDICNFG_EXT_MDIO
;
907 E1000_WRITE_REG(hw
, E1000_MDICNFG
, reg_val
);
909 /* Get data from NVM, or set default */
910 ret_val
= e1000_read_invm_word_i210(hw
, E1000_INVM_AUTOLOAD
,
912 if (ret_val
!= E1000_SUCCESS
)
913 nvm_word
= E1000_INVM_DEFAULT_AL
;
914 tmp_nvm
= nvm_word
| E1000_INVM_PLL_WO_VAL
;
915 phy_word
= E1000_PHY_PLL_UNCONF
;
916 for (i
= 0; i
< E1000_MAX_PLL_TRIES
; i
++) {
917 /* check current state directly from internal PHY */
918 e1000_read_phy_reg_gs40g(hw
, (E1000_PHY_PLL_FREQ_PAGE
|
919 E1000_PHY_PLL_FREQ_REG
), &phy_word
);
920 if ((phy_word
& E1000_PHY_PLL_UNCONF
)
921 != E1000_PHY_PLL_UNCONF
) {
922 ret_val
= E1000_SUCCESS
;
925 ret_val
= -E1000_ERR_PHY
;
927 /* directly reset the internal PHY */
928 ctrl
= E1000_READ_REG(hw
, E1000_CTRL
);
929 E1000_WRITE_REG(hw
, E1000_CTRL
, ctrl
|E1000_CTRL_PHY_RST
);
931 ctrl_ext
= E1000_READ_REG(hw
, E1000_CTRL_EXT
);
932 ctrl_ext
|= (E1000_CTRL_EXT_PHYPDEN
| E1000_CTRL_EXT_SDLPE
);
933 E1000_WRITE_REG(hw
, E1000_CTRL_EXT
, ctrl_ext
);
935 E1000_WRITE_REG(hw
, E1000_WUC
, 0);
936 reg_val
= (E1000_INVM_AUTOLOAD
<< 4) | (tmp_nvm
<< 16);
937 E1000_WRITE_REG(hw
, E1000_EEARBC_I210
, reg_val
);
939 e1000_read_pci_cfg(hw
, E1000_PCI_PMCSR
, &pci_word
);
940 pci_word
|= E1000_PCI_PMCSR_D3
;
941 e1000_write_pci_cfg(hw
, E1000_PCI_PMCSR
, &pci_word
);
943 pci_word
&= ~E1000_PCI_PMCSR_D3
;
944 e1000_write_pci_cfg(hw
, E1000_PCI_PMCSR
, &pci_word
);
945 reg_val
= (E1000_INVM_AUTOLOAD
<< 4) | (nvm_word
<< 16);
946 E1000_WRITE_REG(hw
, E1000_EEARBC_I210
, reg_val
);
948 /* restore WUC register */
949 E1000_WRITE_REG(hw
, E1000_WUC
, wuc
);
951 /* restore MDICNFG setting */
952 E1000_WRITE_REG(hw
, E1000_MDICNFG
, mdicnfg
);
957 * e1000_get_cfg_done_i210 - Read config done bit
958 * @hw: pointer to the HW structure
960 * Read the management control register for the config done bit for
961 * completion status. NOTE: silicon which is EEPROM-less will fail trying
962 * to read the config done bit, so an error is *ONLY* logged and returns
963 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
964 * would not be able to be reset or change link.
966 STATIC s32
e1000_get_cfg_done_i210(struct e1000_hw
*hw
)
968 s32 timeout
= PHY_CFG_TIMEOUT
;
969 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
971 DEBUGFUNC("e1000_get_cfg_done_i210");
974 if (E1000_READ_REG(hw
, E1000_EEMNGCTL_I210
) & mask
)
980 DEBUGOUT("MNG configuration cycle has not completed.\n");
982 return E1000_SUCCESS
;
986 * e1000_init_hw_i210 - Init hw for I210/I211
987 * @hw: pointer to the HW structure
989 * Called to initialize hw for i210 hw family.
991 s32
e1000_init_hw_i210(struct e1000_hw
*hw
)
995 DEBUGFUNC("e1000_init_hw_i210");
996 if ((hw
->mac
.type
>= e1000_i210
) &&
997 !(e1000_get_flash_presence_i210(hw
))) {
998 ret_val
= e1000_pll_workaround_i210(hw
);
999 if (ret_val
!= E1000_SUCCESS
)
1002 hw
->phy
.ops
.get_cfg_done
= e1000_get_cfg_done_i210
;
1003 ret_val
= e1000_init_hw_82575(hw
);