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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / fm10k / base / fm10k_type.h
1 /*******************************************************************************
2
3 Copyright (c) 2013 - 2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ***************************************************************************/
33
34 #ifndef _FM10K_TYPE_H_
35 #define _FM10K_TYPE_H_
36
37 /* forward declaration */
38 struct fm10k_hw;
39
40 #include "fm10k_osdep.h"
41 #include "fm10k_mbx.h"
42
43 #define FM10K_INTEL_VENDOR_ID 0x8086
44 #define FM10K_DEV_ID_PF 0x15A4
45 #define FM10K_DEV_ID_VF 0x15A5
46 #ifdef BOULDER_RAPIDS_HW
47 #define FM10K_DEV_ID_SDI_FM10420_QDA2 0x15D0
48 #endif /* BOULDER_RAPIDS_HW */
49 #ifdef ATWOOD_CHANNEL_HW
50 #define FM10K_DEV_ID_SDI_FM10420_DA2 0x15D5
51 #endif /* ATWOOD_CHANNEL_HW */
52
53 #ifndef LINUX_MACROS
54 #ifndef BIT
55 #define BIT(a) (1UL << (a))
56 #endif
57 #endif /* LINUX_MACROS */
58
59 #define FM10K_MAX_QUEUES 256
60 #define FM10K_MAX_QUEUES_PF 128
61 #define FM10K_MAX_QUEUES_POOL 16
62
63 #define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
64 #define FM10K_STAT_VALID 0x80000000
65
66 /* PCI Bus Info */
67 #define FM10K_PCIE_LINK_CAP 0x7C
68 #define FM10K_PCIE_LINK_STATUS 0x82
69 #define FM10K_PCIE_LINK_WIDTH 0x3F0
70 #define FM10K_PCIE_LINK_WIDTH_1 0x10
71 #define FM10K_PCIE_LINK_WIDTH_2 0x20
72 #define FM10K_PCIE_LINK_WIDTH_4 0x40
73 #define FM10K_PCIE_LINK_WIDTH_8 0x80
74 #define FM10K_PCIE_LINK_SPEED 0xF
75 #define FM10K_PCIE_LINK_SPEED_2500 0x1
76 #define FM10K_PCIE_LINK_SPEED_5000 0x2
77 #define FM10K_PCIE_LINK_SPEED_8000 0x3
78
79 /* PCIe payload size */
80 #define FM10K_PCIE_DEV_CAP 0x74
81 #define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07
82 #define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00
83 #define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01
84 #define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02
85 #define FM10K_PCIE_DEV_CTRL 0x78
86 #define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0
87 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00
88 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20
89 #define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40
90
91 /* PCIe MSI-X Capability info */
92 #define FM10K_PCI_MSIX_MSG_CTRL 0xB2
93 #define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF
94 #define FM10K_MAX_MSIX_VECTORS 256
95 #define FM10K_MAX_VECTORS_PF 256
96 #define FM10K_MAX_VECTORS_POOL 32
97
98 /* PCIe SR-IOV Info */
99 #define FM10K_PCIE_SRIOV_CTRL 0x190
100 #define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10
101
102 #define FM10K_SUCCESS 0
103 #define FM10K_ERR_DEVICE_NOT_SUPPORTED -1
104 #define FM10K_ERR_PARAM -2
105 #define FM10K_ERR_NO_RESOURCES -3
106 #define FM10K_ERR_REQUESTS_PENDING -4
107 #define FM10K_ERR_RESET_REQUESTED -5
108 #define FM10K_ERR_DMA_PENDING -6
109 #define FM10K_ERR_RESET_FAILED -7
110 #define FM10K_ERR_INVALID_MAC_ADDR -8
111 #define FM10K_ERR_INVALID_VALUE -9
112 #define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF
113
114 #define UNREFERENCED_XPARAMETER
115 #define UNREFERENCED_1PARAMETER(_p) (_p)
116 #define UNREFERENCED_2PARAMETER(_p, _q) do { (_p); (_q); } while (0)
117 #define UNREFERENCED_3PARAMETER(_p, _q, _r) do { (_p); (_q); (_r); } while (0)
118
119 /* Start of PF registers */
120 #define FM10K_CTRL 0x0000
121 #define FM10K_CTRL_BAR4_ALLOWED 0x00000004
122
123 #define FM10K_CTRL_EXT 0x0001
124 #define FM10K_GCR 0x0003
125 #define FM10K_GCR_EXT 0x0005
126
127 /* Interrupt control registers */
128 #define FM10K_EICR 0x0006
129 #define FM10K_EICR_PCA_FAULT 0x00000001
130 #define FM10K_EICR_THI_FAULT 0x00000004
131 #define FM10K_EICR_FUM_FAULT 0x00000020
132 #define FM10K_EICR_FAULT_MASK 0x0000003F
133 #define FM10K_EICR_MAILBOX 0x00000040
134 #define FM10K_EICR_SWITCHREADY 0x00000080
135 #define FM10K_EICR_SWITCHNOTREADY 0x00000100
136 #define FM10K_EICR_SWITCHINTERRUPT 0x00000200
137 #define FM10K_EICR_SRAMERROR 0x00000400
138 #define FM10K_EICR_VFLR 0x00000800
139 #define FM10K_EICR_MAXHOLDTIME 0x00001000
140 #define FM10K_EIMR 0x0007
141 #define FM10K_EIMR_PCA_FAULT 0x00000001
142 #define FM10K_EIMR_THI_FAULT 0x00000010
143 #define FM10K_EIMR_FUM_FAULT 0x00000400
144 #define FM10K_EIMR_MAILBOX 0x00001000
145 #define FM10K_EIMR_SWITCHREADY 0x00004000
146 #define FM10K_EIMR_SWITCHNOTREADY 0x00010000
147 #define FM10K_EIMR_SWITCHINTERRUPT 0x00040000
148 #define FM10K_EIMR_SRAMERROR 0x00100000
149 #define FM10K_EIMR_VFLR 0x00400000
150 #define FM10K_EIMR_MAXHOLDTIME 0x01000000
151 #define FM10K_EIMR_ALL 0x55555555
152 #define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0)
153 #define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1)
154 #define FM10K_FAULT_ADDR_LO 0x0
155 #define FM10K_FAULT_ADDR_HI 0x1
156 #define FM10K_FAULT_SPECINFO 0x2
157 #define FM10K_FAULT_FUNC 0x3
158 #define FM10K_FAULT_SIZE 0x4
159 #define FM10K_FAULT_FUNC_VALID 0x00008000
160 #define FM10K_FAULT_FUNC_PF 0x00004000
161 #define FM10K_FAULT_FUNC_VF_MASK 0x00003F00
162 #define FM10K_FAULT_FUNC_VF_SHIFT 8
163 #define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF
164
165 #define FM10K_PCA_FAULT 0x0008
166 #define FM10K_THI_FAULT 0x0010
167 #define FM10K_FUM_FAULT 0x001C
168
169 /* Rx queue timeout indicator */
170 #define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020)
171
172 /* Switch Manager info */
173 #define FM10K_SM_AREA(_n) ((_n) + 0x0028)
174
175 /* GLORT mapping registers */
176 #define FM10K_DGLORTMAP(_n) ((_n) + 0x0030)
177 #define FM10K_DGLORT_COUNT 8
178 #define FM10K_DGLORTMAP_MASK_SHIFT 16
179 #define FM10K_DGLORTMAP_ANY 0x00000000
180 #define FM10K_DGLORTMAP_NONE 0x0000FFFF
181 #define FM10K_DGLORTMAP_ZERO 0xFFFF0000
182 #define FM10K_DGLORTDEC(_n) ((_n) + 0x0038)
183 #define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4
184 #define FM10K_DGLORTDEC_VSIBASE_SHIFT 7
185 #define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14
186 #define FM10K_DGLORTDEC_QBASE_SHIFT 16
187 #define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24
188 #define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000
189 #define FM10K_TUNNEL_CFG 0x0040
190 #define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16
191 #define FM10K_TUNNEL_CFG_GENEVE 0x0041
192 #define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050)
193 #define FM10K_SWPRI_MAX 16
194 #define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)
195 #define FM10K_RSSRK_SIZE 10
196 #define FM10K_RSSRK_ENTRIES_PER_REG 4
197 #define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000)
198 #define FM10K_RETA_SIZE 32
199 #define FM10K_RETA_ENTRIES_PER_REG 4
200 #define FM10K_MAX_RSS_INDICES 128
201
202 /* Rate limiting registers */
203 #define FM10K_TC_CREDIT(_n) ((_n) + 0x2000)
204 #define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF
205 #define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040)
206 #define FM10K_TC_MAXCREDIT_64K 0x00010000
207 #define FM10K_TC_RATE(_n) ((_n) + 0x2080)
208 #define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF
209 #define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000
210 #define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000
211 #define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000
212
213 /* DMA control registers */
214 #define FM10K_DMA_CTRL 0x20C3
215 #define FM10K_DMA_CTRL_TX_ENABLE 0x00000001
216 #define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008
217 #define FM10K_DMA_CTRL_RX_ENABLE 0x00000010
218 #define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080
219 #define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100
220 #define FM10K_DMA_CTRL_MINMSS_SHIFT 9
221 #define FM10K_DMA_CTRL_MINMSS_64 0x00008000
222 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000
223 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000
224 #define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000
225 #define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000
226 #define FM10K_DMA_CTRL_32_DESC 0x00000000
227
228 #define FM10K_DMA_CTRL2 0x20C4
229 #define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000
230
231 /* TSO flags configuration
232 * First packet contains all flags except for fin and psh
233 * Middle packet contains only urg and ack
234 * Last packet contains urg, ack, fin, and psh
235 */
236 #define FM10K_TSO_FLAGS_LOW 0x00300FF6
237 #define FM10K_TSO_FLAGS_HI 0x00000039
238 #define FM10K_DTXTCPFLGL 0x20C5
239 #define FM10K_DTXTCPFLGH 0x20C6
240
241 #define FM10K_TPH_CTRL 0x20C7
242 #define FM10K_MRQC(_n) ((_n) + 0x2100)
243 #define FM10K_MRQC_TCP_IPV4 0x00000001
244 #define FM10K_MRQC_IPV4 0x00000002
245 #define FM10K_MRQC_IPV6 0x00000010
246 #define FM10K_MRQC_TCP_IPV6 0x00000020
247 #define FM10K_MRQC_UDP_IPV4 0x00000040
248 #define FM10K_MRQC_UDP_IPV6 0x00000080
249
250 #define FM10K_TQMAP(_n) ((_n) + 0x2800)
251 #define FM10K_TQMAP_TABLE_SIZE 2048
252 #define FM10K_RQMAP(_n) ((_n) + 0x3000)
253
254 /* Hardware Statistics */
255 #define FM10K_STATS_TIMEOUT 0x3800
256 #define FM10K_STATS_UR 0x3801
257 #define FM10K_STATS_CA 0x3802
258 #define FM10K_STATS_UM 0x3803
259 #define FM10K_STATS_XEC 0x3804
260 #define FM10K_STATS_VLAN_DROP 0x3805
261 #define FM10K_STATS_LOOPBACK_DROP 0x3806
262 #define FM10K_STATS_NODESC_DROP 0x3807
263
264 /* Timesync registers */
265 #define FM10K_SYSTIME 0x3814
266 #define FM10K_SYSTIME_CFG 0x3818
267 #define FM10K_SYSTIME_CFG_STEP_MASK 0x0000000F
268
269 /* PCIe state registers */
270 #define FM10K_PHYADDR 0x381C
271
272 /* Rx ring registers */
273 #define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000)
274 #define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001)
275 #define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002)
276 #define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003)
277 #define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020
278 #define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200
279 #define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000
280 #define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000
281 #define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004)
282 #define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005)
283 #define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006)
284 #define FM10K_RXQCTL_ENABLE 0x00000001
285 #define FM10K_RXQCTL_PF 0x000000FC
286 #define FM10K_RXQCTL_VF_SHIFT 2
287 #define FM10K_RXQCTL_VF 0x00000100
288 #define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
289 #define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007)
290 #define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001
291 #define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200
292 #define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008)
293 #define FM10K_RXINT_TIMER_SHIFT 8
294 #define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009)
295 #define FM10K_SRRCTL_BSIZEPKT_SHIFT 8 /* shift _right_ */
296 #define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000
297 #define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000
298
299 /* Rx Statistics */
300 #define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A)
301 #define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B)
302 #define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C)
303 #define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D)
304
305 /* Rx GLORT register */
306 #define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E)
307
308 /* Tx ring registers */
309 #define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000)
310 #define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001)
311 #define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002)
312 /* When fist initialized, VFs need to know the Interrupt Throttle Rate (ITR)
313 * scale which is based on the PCIe speed but the speed information in the PCI
314 * configuration space may not be accurate. The PF already knows the ITR scale
315 * but there is no defined method to pass that information from the PF to the
316 * VF. This is accomplished during VF initialization by temporarily co-opting
317 * the yet-to-be-used TDLEN register to have the PF store the ITR shift for
318 * the VF to retrieve before the VF needs to use the TDLEN register for its
319 * intended purpose, i.e. before the Tx resources are allocated.
320 */
321 #define FM10K_TDLEN_ITR_SCALE_SHIFT 9
322 #define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00
323 #define FM10K_TDLEN_ITR_SCALE_GEN1 2
324 #define FM10K_TDLEN_ITR_SCALE_GEN2 1
325 #define FM10K_TDLEN_ITR_SCALE_GEN3 0
326 #define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003)
327 #define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020
328 #define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200
329 #define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800
330 #define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000
331 #define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004)
332 #define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005)
333 #define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006)
334 #define FM10K_TXDCTL_ENABLE 0x00004000
335 #define FM10K_TXDCTL_MAX_TIME_SHIFT 16
336 #define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007)
337 #define FM10K_TXQCTL_PF 0x0000003F
338 #define FM10K_TXQCTL_VF 0x00000040
339 #define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)
340 #define FM10K_TXQCTL_PC_SHIFT 7
341 #define FM10K_TXQCTL_PC_MASK 0x00000380
342 #define FM10K_TXQCTL_TC_SHIFT 10
343 #define FM10K_TXQCTL_VID_SHIFT 16
344 #define FM10K_TXQCTL_VID_MASK 0x0FFF0000
345 #define FM10K_TXQCTL_UNLIMITED_BW 0x10000000
346 #define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008)
347 #define FM10K_TXINT_TIMER_SHIFT 8
348
349 /* Tx Statistics */
350 #define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009)
351 #define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A)
352 #define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B)
353
354 /* Tx Push registers */
355 #define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C)
356 #define FM10K_TQDLOC_BASE_32_DESC 0x08
357 #define FM10K_TQDLOC_SIZE_32_DESC 0x00050000
358
359 /* Tx GLORT registers */
360 #define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D)
361 #define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E)
362 #define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001
363
364 /* Interrupt moderation and control registers */
365 #define FM10K_INT_MAP(_n) ((_n) + 0x10080)
366 #define FM10K_INT_MAP_TIMER0 0x00000000
367 #define FM10K_INT_MAP_TIMER1 0x00000100
368 #define FM10K_INT_MAP_IMMEDIATE 0x00000200
369 #define FM10K_INT_MAP_DISABLE 0x00000300
370 #define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003)
371 #define FM10K_INT_CTRL 0x12000
372 #define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400
373 #define FM10K_ITR(_n) ((_n) + 0x12400)
374 #define FM10K_ITR_INTERVAL1_SHIFT 12
375 #define FM10K_ITR_PENDING2 0x10000000
376 #define FM10K_ITR_AUTOMASK 0x20000000
377 #define FM10K_ITR_MASK_SET 0x40000000
378 #define FM10K_ITR_MASK_CLEAR 0x80000000
379 #define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800)
380 #define FM10K_ITR_REG_COUNT 768
381 #define FM10K_ITR_REG_COUNT_PF 256
382
383 /* Switch manager interrupt registers */
384 #define FM10K_IP 0x13000
385 #define FM10K_IP_NOTINRESET 0x00000100
386 #define FM10K_SRAM_IP 0x13003
387
388 /* VLAN registers */
389 #define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000)
390 #define FM10K_VLAN_TABLE_SIZE 128
391
392 /* VLAN specific message offsets */
393 #define FM10K_VLAN_TABLE_VID_MAX 4096
394 #define FM10K_VLAN_TABLE_VSI_MAX 64
395 #define FM10K_VLAN_LENGTH_SHIFT 16
396 #define FM10K_VLAN_CLEAR BIT(15)
397 #define FM10K_VLAN_OVERRIDE FM10K_VLAN_CLEAR
398 #define FM10K_VLAN_ALL \
399 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)
400
401 /* VF FLR event notification registers */
402 #define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844)
403 #define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846)
404
405 /* Defines for size of uncacheable and write-combining memories */
406 #define FM10K_UC_ADDR_START 0x000000 /* start of standard regs */
407 #define FM10K_WC_ADDR_START 0x100000 /* start of Tx Desc Cache */
408 #define FM10K_DBI_ADDR_START 0x200000 /* start of debug registers */
409 #define FM10K_UC_ADDR_SIZE (FM10K_WC_ADDR_START - FM10K_UC_ADDR_START)
410 #define FM10K_WC_ADDR_SIZE (FM10K_DBI_ADDR_START - FM10K_WC_ADDR_START)
411
412 /* Define timeouts for resets and disables */
413 #define FM10K_QUEUE_DISABLE_TIMEOUT 100
414 #define FM10K_RESET_TIMEOUT 150
415
416 /* Maximum supported combined inner and outer header length for encapsulation */
417 #define FM10K_TUNNEL_HEADER_LENGTH 184
418
419 /* VF registers */
420 #define FM10K_VFCTRL 0x00000
421 #define FM10K_VFCTRL_RST 0x00000008
422 #define FM10K_VFINT_MAP 0x00030
423 #define FM10K_VFSYSTIME 0x00040
424 #define FM10K_VFITR(_n) ((_n) + 0x00060)
425
426 /* Registers contained in BAR 4 for Switch management */
427 #define FM10K_SW_SYSTIME_ADJUST 0x0224D
428 #define FM10K_SW_SYSTIME_ADJUST_MASK 0x3FFFFFFF
429 #define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE 0x80000000
430 #define FM10K_SW_SYSTIME_PULSE(_n) ((_n) + 0x02252)
431
432 #ifndef ETH_ALEN
433 #define ETH_ALEN 6
434 #endif /* ETH_ALEN */
435
436 #ifndef IS_ZERO_ETHER_ADDR
437 /* make certain address is not 0 */
438 #define IS_ZERO_ETHER_ADDR(addr) \
439 (!((addr)[0] | (addr)[1] | (addr)[2] | (addr)[3] | (addr)[4] | (addr)[5]))
440 #endif
441
442 #ifndef IS_MULTICAST_ETHER_ADDR
443 #define IS_MULTICAST_ETHER_ADDR(addr) ((addr)[0] & 0x1)
444 #endif
445
446 #ifndef IS_VALID_ETHER_ADDR
447 /* make certain address is not multicast or 0 */
448 #define IS_VALID_ETHER_ADDR(addr) \
449 (!IS_MULTICAST_ETHER_ADDR(addr) && !IS_ZERO_ETHER_ADDR(addr))
450 #endif
451
452 enum fm10k_int_source {
453 fm10k_int_mailbox = 0,
454 fm10k_int_pcie_fault = 1,
455 fm10k_int_switch_up_down = 2,
456 fm10k_int_switch_event = 3,
457 fm10k_int_sram = 4,
458 fm10k_int_vflr = 5,
459 fm10k_int_max_hold_time = 6,
460 fm10k_int_sources_max_pf
461 };
462
463 /* PCIe bus speeds */
464 enum fm10k_bus_speed {
465 fm10k_bus_speed_unknown = 0,
466 fm10k_bus_speed_2500 = 2500,
467 fm10k_bus_speed_5000 = 5000,
468 fm10k_bus_speed_8000 = 8000,
469 fm10k_bus_speed_reserved
470 };
471
472 /* PCIe bus widths */
473 enum fm10k_bus_width {
474 fm10k_bus_width_unknown = 0,
475 fm10k_bus_width_pcie_x1 = 1,
476 fm10k_bus_width_pcie_x2 = 2,
477 fm10k_bus_width_pcie_x4 = 4,
478 fm10k_bus_width_pcie_x8 = 8,
479 fm10k_bus_width_reserved
480 };
481
482 /* PCIe payload sizes */
483 enum fm10k_bus_payload {
484 fm10k_bus_payload_unknown = 0,
485 fm10k_bus_payload_128 = 1,
486 fm10k_bus_payload_256 = 2,
487 fm10k_bus_payload_512 = 3,
488 fm10k_bus_payload_reserved
489 };
490
491 /* Bus parameters */
492 struct fm10k_bus_info {
493 enum fm10k_bus_speed speed;
494 enum fm10k_bus_width width;
495 enum fm10k_bus_payload payload;
496 };
497
498 /* Statistics related declarations */
499 struct fm10k_hw_stat {
500 u64 count;
501 u32 base_l;
502 u32 base_h;
503 };
504
505 struct fm10k_hw_stats_q {
506 struct fm10k_hw_stat tx_bytes;
507 struct fm10k_hw_stat tx_packets;
508 #define tx_stats_idx tx_packets.base_h
509 struct fm10k_hw_stat rx_bytes;
510 struct fm10k_hw_stat rx_packets;
511 #define rx_stats_idx rx_packets.base_h
512 struct fm10k_hw_stat rx_drops;
513 };
514
515 struct fm10k_hw_stats {
516 struct fm10k_hw_stat timeout;
517 #define stats_idx timeout.base_h
518 struct fm10k_hw_stat ur;
519 struct fm10k_hw_stat ca;
520 struct fm10k_hw_stat um;
521 struct fm10k_hw_stat xec;
522 struct fm10k_hw_stat vlan_drop;
523 struct fm10k_hw_stat loopback_drop;
524 struct fm10k_hw_stat nodesc_drop;
525 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF];
526 };
527
528 /* Establish DGLORT feature priority */
529 enum fm10k_dglortdec_idx {
530 fm10k_dglort_default = 0,
531 fm10k_dglort_vf_rsvd0 = 1,
532 fm10k_dglort_vf_rss = 2,
533 fm10k_dglort_pf_rsvd0 = 3,
534 fm10k_dglort_pf_queue = 4,
535 fm10k_dglort_pf_vsi = 5,
536 fm10k_dglort_pf_rsvd1 = 6,
537 fm10k_dglort_pf_rss = 7
538 };
539
540 struct fm10k_dglort_cfg {
541 u16 glort; /* GLORT base */
542 u16 queue_b; /* Base value for queue */
543 u8 vsi_b; /* Base value for VSI */
544 u8 idx; /* index of DGLORTDEC entry */
545 u8 rss_l; /* RSS indices */
546 u8 pc_l; /* Priority Class indices */
547 u8 vsi_l; /* Number of bits from GLORT used to determine VSI */
548 u8 queue_l; /* Number of bits from GLORT used to determine queue */
549 u8 shared_l; /* Ignored bits from GLORT resulting in shared VSI */
550 u8 inner_rss; /* Boolean value if inner header is used for RSS */
551 };
552
553 enum fm10k_pca_fault {
554 PCA_NO_FAULT,
555 PCA_UNMAPPED_ADDR,
556 PCA_BAD_QACCESS_PF,
557 PCA_BAD_QACCESS_VF,
558 PCA_MALICIOUS_REQ,
559 PCA_POISONED_TLP,
560 PCA_TLP_ABORT,
561 __PCA_MAX
562 };
563
564 enum fm10k_thi_fault {
565 THI_NO_FAULT,
566 THI_MAL_DIS_Q_FAULT,
567 __THI_MAX
568 };
569
570 enum fm10k_fum_fault {
571 FUM_NO_FAULT,
572 FUM_UNMAPPED_ADDR,
573 FUM_POISONED_TLP,
574 FUM_BAD_VF_QACCESS,
575 FUM_ADD_DECODE_ERR,
576 FUM_RO_ERROR,
577 FUM_QPRC_CRC_ERROR,
578 FUM_CSR_TIMEOUT,
579 FUM_INVALID_TYPE,
580 FUM_INVALID_LENGTH,
581 FUM_INVALID_BE,
582 FUM_INVALID_ALIGN,
583 __FUM_MAX
584 };
585
586 struct fm10k_fault {
587 u64 address; /* Address at the time fault was detected */
588 u32 specinfo; /* Extra info on this fault (fault dependent) */
589 u8 type; /* Fault value dependent on subunit */
590 u8 func; /* Function number of the fault */
591 };
592
593 struct fm10k_mac_ops {
594 /* basic bring-up and tear-down */
595 s32 (*reset_hw)(struct fm10k_hw *);
596 s32 (*init_hw)(struct fm10k_hw *);
597 s32 (*start_hw)(struct fm10k_hw *);
598 s32 (*stop_hw)(struct fm10k_hw *);
599 s32 (*get_bus_info)(struct fm10k_hw *);
600 s32 (*get_host_state)(struct fm10k_hw *, bool *);
601 s32 (*request_lport_map)(struct fm10k_hw *);
602 #ifndef NO_IS_SLOT_APPROPRIATE_CHECK
603 bool (*is_slot_appropriate)(struct fm10k_hw *);
604 #endif
605 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool);
606 s32 (*read_mac_addr)(struct fm10k_hw *);
607 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *,
608 u16, bool, u8);
609 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool);
610 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8);
611 void (*update_int_moderator)(struct fm10k_hw *);
612 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool);
613 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
614 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
615 s32 (*configure_dglort_map)(struct fm10k_hw *,
616 struct fm10k_dglort_cfg *);
617 void (*set_dma_mask)(struct fm10k_hw *, u64);
618 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *);
619 s32 (*adjust_systime)(struct fm10k_hw *, s32 ppb);
620 s32 (*notify_offset)(struct fm10k_hw *, u64 offset);
621 u64 (*read_systime)(struct fm10k_hw *);
622 };
623
624 enum fm10k_mac_type {
625 fm10k_mac_unknown = 0,
626 fm10k_mac_pf,
627 fm10k_mac_vf,
628 fm10k_num_macs
629 };
630
631 struct fm10k_mac_info {
632 struct fm10k_mac_ops ops;
633 enum fm10k_mac_type type;
634 u8 addr[ETH_ALEN];
635 u8 perm_addr[ETH_ALEN];
636 u16 default_vid;
637 u16 max_msix_vectors;
638 u16 max_queues;
639 bool vlan_override;
640 bool get_host_state;
641 bool tx_ready;
642 u32 dglort_map;
643 u8 itr_scale;
644 u64 reset_while_pending;
645 };
646
647 struct fm10k_swapi_table_info {
648 u32 used;
649 u32 avail;
650 };
651
652 struct fm10k_swapi_info {
653 u32 status;
654 struct fm10k_swapi_table_info mac;
655 struct fm10k_swapi_table_info nexthop;
656 struct fm10k_swapi_table_info ffu;
657 };
658
659 enum fm10k_xcast_modes {
660 FM10K_XCAST_MODE_ALLMULTI = 0,
661 FM10K_XCAST_MODE_MULTI = 1,
662 FM10K_XCAST_MODE_PROMISC = 2,
663 FM10K_XCAST_MODE_NONE = 3,
664 FM10K_XCAST_MODE_DISABLE = 4
665 };
666
667 enum fm10k_timestamp_modes {
668 FM10K_TIMESTAMP_MODE_NONE = 0,
669 FM10K_TIMESTAMP_MODE_PEP_TO_PEP = 1,
670 FM10K_TIMESTAMP_MODE_PEP_TO_ANY = 2,
671 };
672
673 #define FM10K_VF_TC_MAX 100000 /* 100,000 Mb/s aka 100Gb/s */
674 #define FM10K_VF_TC_MIN 1 /* 1 Mb/s is the slowest rate */
675
676 struct fm10k_vf_info {
677 /* mbx must be first field in struct unless all default IOV message
678 * handlers are redone as the assumption is that vf_info starts
679 * at the same offset as the mailbox
680 */
681 struct fm10k_mbx_info mbx; /* PF side of VF mailbox */
682 int rate; /* Tx BW cap as defined by OS */
683 u16 glort; /* resource tag for this VF */
684 u16 sw_vid; /* Switch API assigned VLAN */
685 u16 pf_vid; /* PF assigned Default VLAN */
686 u8 mac[ETH_ALEN]; /* PF Default MAC address */
687 u8 vsi; /* VSI identifier */
688 u8 vf_idx; /* which VF this is */
689 u8 vf_flags; /* flags indicating what modes
690 * are supported for the port
691 */
692 #ifndef NO_FM10K_VF_TRUSTED_MODE
693 bool trusted; /* VF trust mode */
694 #endif
695 };
696
697 #define FM10K_VF_FLAG_ALLMULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_ALLMULTI))
698 #define FM10K_VF_FLAG_MULTI_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_MULTI))
699 #define FM10K_VF_FLAG_PROMISC_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_PROMISC))
700 #define FM10K_VF_FLAG_NONE_CAPABLE (u8)(BIT(FM10K_XCAST_MODE_NONE))
701 #define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF)
702 #define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4)
703 #define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode))
704 #define FM10K_VF_FLAG_SET_MODE_NONE \
705 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)
706 #define FM10K_VF_FLAG_MULTI_ENABLED \
707 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \
708 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \
709 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC))
710
711 struct fm10k_iov_ops {
712 /* IOV related bring-up and tear-down */
713 s32 (*assign_resources)(struct fm10k_hw *, u16, u16);
714 s32 (*configure_tc)(struct fm10k_hw *, u16, int);
715 s32 (*assign_int_moderator)(struct fm10k_hw *, u16);
716 s32 (*assign_default_mac_vlan)(struct fm10k_hw *,
717 struct fm10k_vf_info *);
718 s32 (*reset_resources)(struct fm10k_hw *,
719 struct fm10k_vf_info *);
720 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8);
721 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *);
722 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16);
723 void (*notify_offset)(struct fm10k_hw *, struct fm10k_vf_info*, u64);
724 };
725
726 struct fm10k_iov_info {
727 struct fm10k_iov_ops ops;
728 u16 total_vfs;
729 u16 num_vfs;
730 u16 num_pools;
731 };
732
733 struct fm10k_hw {
734 u32 *hw_addr;
735 u32 *sw_addr;
736 void *back;
737 struct fm10k_mac_info mac;
738 struct fm10k_bus_info bus;
739 struct fm10k_bus_info bus_caps;
740 struct fm10k_iov_info iov;
741 struct fm10k_mbx_info mbx;
742 struct fm10k_swapi_info swapi;
743 u16 device_id;
744 u16 vendor_id;
745 u16 subsystem_device_id;
746 u16 subsystem_vendor_id;
747 u8 revision_id;
748 u32 flags;
749 #define FM10K_HW_FLAG_CLOCK_OWNER BIT(0)
750 };
751
752 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
753 #define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8
754 #define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8
755
756 /* Transmit Descriptor */
757 struct fm10k_tx_desc {
758 __le64 buffer_addr; /* Address of the descriptor's data buffer */
759 __le16 buflen; /* Length of data to be DMAed */
760 __le16 vlan; /* VLAN_ID and VPRI to be inserted in FTAG */
761 __le16 mss; /* MSS for segmentation offload */
762 u8 hdrlen; /* Header size for segmentation offload */
763 u8 flags; /* Status and offload request flags */
764 };
765
766 /* Transmit Descriptor Cache Structure */
767 struct fm10k_tx_desc_cache {
768 struct fm10k_tx_desc tx_desc[256];
769 };
770
771 #define FM10K_TXD_FLAG_INT 0x01
772 #define FM10K_TXD_FLAG_TIME 0x02
773 #define FM10K_TXD_FLAG_CSUM 0x04
774 #define FM10K_TXD_FLAG_FTAG 0x10
775 #define FM10K_TXD_FLAG_RS 0x20
776 #define FM10K_TXD_FLAG_LAST 0x40
777 #define FM10K_TXD_FLAG_DONE 0x80
778
779
780 /* These macros are meant to enable optimal placement of the RS and INT
781 * bits. It will point us to the last descriptor in the cache for either the
782 * start of the packet, or the end of the packet. If the index is actually
783 * at the start of the FIFO it will point to the offset for the last index
784 * in the FIFO to prevent an unnecessary write.
785 */
786 #define FM10K_TXD_WB_FIFO_SIZE 4
787
788 /* Receive Descriptor - 32B */
789 union fm10k_rx_desc {
790 struct {
791 __le64 pkt_addr; /* Packet buffer address */
792 __le64 hdr_addr; /* Header buffer address */
793 __le64 reserved; /* Empty space, RSS hash */
794 __le64 timestamp;
795 } q; /* Read, Writeback, 64b quad-words */
796 struct {
797 __le32 data; /* RSS and header data */
798 __le32 rss; /* RSS Hash */
799 __le32 staterr;
800 __le32 vlan_len;
801 __le32 glort; /* sglort/dglort */
802 } d; /* Writeback, 32b double-words */
803 struct {
804 __le16 pkt_info; /* RSS, Pkt type */
805 __le16 hdr_info; /* Splithdr, hdrlen, xC */
806 __le16 rss_lower;
807 __le16 rss_upper;
808 __le16 status; /* status/error */
809 __le16 csum_err; /* checksum or extended error value */
810 __le16 length; /* Packet length */
811 __le16 vlan; /* VLAN tag */
812 __le16 dglort;
813 __le16 sglort;
814 } w; /* Writeback, 16b words */
815 };
816
817 #define FM10K_RXD_RSSTYPE_MASK 0x000F
818 enum fm10k_rdesc_rss_type {
819 FM10K_RSSTYPE_NONE = 0x0,
820 FM10K_RSSTYPE_IPV4_TCP = 0x1,
821 FM10K_RSSTYPE_IPV4 = 0x2,
822 FM10K_RSSTYPE_IPV6_TCP = 0x3,
823 /* Reserved 0x4 */
824 FM10K_RSSTYPE_IPV6 = 0x5,
825 /* Reserved 0x6 */
826 FM10K_RSSTYPE_IPV4_UDP = 0x7,
827 FM10K_RSSTYPE_IPV6_UDP = 0x8
828 /* Reserved 0x9 - 0xF */
829 };
830
831 #define FM10K_RXD_PKTTYPE_MASK 0x03F0
832 #define FM10K_RXD_PKTTYPE_SHIFT 4
833 enum fm10k_rdesc_pkt_type {
834 /* L3 type */
835 FM10K_PKTTYPE_OTHER = 0x00,
836 FM10K_PKTTYPE_IPV4 = 0x01,
837 FM10K_PKTTYPE_IPV4_EX = 0x02,
838 FM10K_PKTTYPE_IPV6 = 0x03,
839 FM10K_PKTTYPE_IPV6_EX = 0x04,
840
841 /* L4 type */
842 FM10K_PKTTYPE_TCP = 0x08,
843 FM10K_PKTTYPE_UDP = 0x10,
844 FM10K_PKTTYPE_GRE = 0x18,
845 FM10K_PKTTYPE_VXLAN = 0x20,
846 FM10K_PKTTYPE_NVGRE = 0x28,
847 FM10K_PKTTYPE_GENEVE = 0x30
848 };
849
850 #define FM10K_RXD_HDR_INFO_XC_MASK 0x0006
851 enum fm10k_rxdesc_xc {
852 FM10K_XC_UNICAST = 0x0,
853 FM10K_XC_MULTICAST = 0x4,
854 FM10K_XC_BROADCAST = 0x6
855 };
856
857
858 #define FM10K_RXD_STATUS_DD 0x0001 /* Descriptor done */
859 #define FM10K_RXD_STATUS_EOP 0x0002 /* End of packet */
860 #define FM10K_RXD_STATUS_IPCS 0x0008 /* Indicates IPv4 csum */
861 #define FM10K_RXD_STATUS_L4CS 0x0010 /* Indicates an L4 csum */
862 #define FM10K_RXD_STATUS_L4CS2 0x0040 /* Inner header L4 csum */
863 #define FM10K_RXD_STATUS_L4E2 0x0800 /* Inner header L4 csum err */
864 #define FM10K_RXD_STATUS_IPE2 0x1000 /* Inner header IPv4 csum err */
865 #define FM10K_RXD_STATUS_RXE 0x2000 /* Generic Rx error */
866 #define FM10K_RXD_STATUS_L4E 0x4000 /* L4 csum error */
867 #define FM10K_RXD_STATUS_IPE 0x8000 /* IPv4 csum error */
868
869 #define FM10K_RXD_ERR_SWITCH_ERROR 0x0001 /* Switch found bad packet */
870 #define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002 /* No descriptor available */
871 #define FM10K_RXD_ERR_PP_ERROR 0x0004 /* RAM error during processing */
872 #define FM10K_RXD_ERR_SWITCH_READY 0x0008 /* Link transition mid-packet */
873 #define FM10K_RXD_ERR_TOO_BIG 0x0010 /* Pkt too big for single buf */
874
875
876 struct fm10k_ftag {
877 __be16 swpri_type_user;
878 __be16 vlan;
879 __be16 sglort;
880 __be16 dglort;
881 };
882
883 #endif /* _FM10K_TYPE_H */
Ceph