ceph/src/spdk/dpdk/drivers/net/fm10k/fm10k.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2013-2015 Intel Corporation
   3  */
   4
   5 #ifndef _FM10K_H_
   6 #define _FM10K_H_
   7
   8 #include <stdint.h>
   9 #include <rte_mbuf.h>
  10 #include <rte_mempool.h>
  11 #include <rte_malloc.h>
  12 #include <rte_spinlock.h>
  13 #include "fm10k_logs.h"
  14 #include "base/fm10k_type.h"
  15
  16 /* descriptor ring base addresses must be aligned to the following */
  17 #define FM10K_ALIGN_RX_DESC  128
  18 #define FM10K_ALIGN_TX_DESC  128
  19
  20 /* The maximum packet size that FM10K supports */
  21 #define FM10K_MAX_PKT_SIZE  (15 * 1024)
  22
  23 /* Minimum size of RX buffer FM10K supported */
  24 #define FM10K_MIN_RX_BUF_SIZE  256
  25
  26 /* The maximum of SRIOV VFs per port supported */
  27 #define FM10K_MAX_VF_NUM    64
  28
  29 /* number of descriptors must be a multiple of the following */
  30 #define FM10K_MULT_RX_DESC  FM10K_REQ_RX_DESCRIPTOR_MULTIPLE
  31 #define FM10K_MULT_TX_DESC  FM10K_REQ_TX_DESCRIPTOR_MULTIPLE
  32
  33 /* maximum size of descriptor rings */
  34 #define FM10K_MAX_RX_RING_SZ  (512 * 1024)
  35 #define FM10K_MAX_TX_RING_SZ  (512 * 1024)
  36
  37 /* minimum and maximum number of descriptors in a ring */
  38 #define FM10K_MIN_RX_DESC  32
  39 #define FM10K_MIN_TX_DESC  32
  40 #define FM10K_MAX_RX_DESC  (FM10K_MAX_RX_RING_SZ / sizeof(union fm10k_rx_desc))
  41 #define FM10K_MAX_TX_DESC  (FM10K_MAX_TX_RING_SZ / sizeof(struct fm10k_tx_desc))
  42
  43 #define FM10K_TX_MAX_SEG     UINT8_MAX
  44 #define FM10K_TX_MAX_MTU_SEG UINT8_MAX
  45
  46 /*
  47  * byte aligment for HW RX data buffer
  48  * Datasheet requires RX buffer addresses shall either be 512-byte aligned or
  49  * be 8-byte aligned but without crossing host memory pages (4KB alignment
  50  * boundaries). Satisfy first option.
  51  */
  52 #define FM10K_RX_DATABUF_ALIGN 512
  53
  54 /*
  55  * threshold default, min, max, and divisor constraints
  56  * the configured values must satisfy the following:
  57  *   MIN <= value <= MAX
  58  *   DIV % value == 0
  59  */
  60 #define FM10K_RX_FREE_THRESH_DEFAULT(rxq)  32
  61 #define FM10K_RX_FREE_THRESH_MIN(rxq)      1
  62 #define FM10K_RX_FREE_THRESH_MAX(rxq)      ((rxq)->nb_desc - 1)
  63 #define FM10K_RX_FREE_THRESH_DIV(rxq)      ((rxq)->nb_desc)
  64
  65 #define FM10K_TX_FREE_THRESH_DEFAULT(txq)  32
  66 #define FM10K_TX_FREE_THRESH_MIN(txq)      1
  67 #define FM10K_TX_FREE_THRESH_MAX(txq)      ((txq)->nb_desc - 3)
  68 #define FM10K_TX_FREE_THRESH_DIV(txq)      0
  69
  70 #define FM10K_DEFAULT_RX_PTHRESH      8
  71 #define FM10K_DEFAULT_RX_HTHRESH      8
  72 #define FM10K_DEFAULT_RX_WTHRESH      0
  73
  74 #define FM10K_DEFAULT_TX_PTHRESH      32
  75 #define FM10K_DEFAULT_TX_HTHRESH      0
  76 #define FM10K_DEFAULT_TX_WTHRESH      0
  77
  78 #define FM10K_TX_RS_THRESH_DEFAULT(txq)    32
  79 #define FM10K_TX_RS_THRESH_MIN(txq)        1
  80 #define FM10K_TX_RS_THRESH_MAX(txq)        \
  81         RTE_MIN(((txq)->nb_desc - 2), (txq)->free_thresh)
  82 #define FM10K_TX_RS_THRESH_DIV(txq)        ((txq)->nb_desc)
  83
  84 #define FM10K_VLAN_TAG_SIZE 4
  85
  86 /* Maximum number of MAC addresses per PF/VF */
  87 #define FM10K_MAX_MACADDR_NUM       64
  88
  89 #define FM10K_UINT32_BIT_SIZE      (CHAR_BIT * sizeof(uint32_t))
  90 #define FM10K_VFTA_SIZE            (4096 / FM10K_UINT32_BIT_SIZE)
  91
  92 /* vlan_id is a 12 bit number.
  93  * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
  94  * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
  95  * The higher 7 bit val specifies VFTA array index.
  96  */
  97 #define FM10K_VFTA_BIT(vlan_id)    (1 << ((vlan_id) & 0x1F))
  98 #define FM10K_VFTA_IDX(vlan_id)    ((vlan_id) >> 5)
  99
 100 #define RTE_FM10K_RXQ_REARM_THRESH      32
 101 #define RTE_FM10K_VPMD_TX_BURST         32
 102 #define RTE_FM10K_MAX_RX_BURST          RTE_FM10K_RXQ_REARM_THRESH
 103 #define RTE_FM10K_TX_MAX_FREE_BUF_SZ    64
 104 #define RTE_FM10K_DESCS_PER_LOOP    4
 105
 106 #define FM10K_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 107 #define FM10K_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 108
 109 struct fm10k_macvlan_filter_info {
 110         uint16_t vlan_num;       /* Total VLAN number */
 111         uint16_t mac_num;        /* Total mac number */
 112         uint16_t nb_queue_pools; /* Active queue pools number */
 113         /* VMDQ ID for each MAC address */
 114         uint8_t  mac_vmdq_id[FM10K_MAX_MACADDR_NUM];
 115         uint32_t vfta[FM10K_VFTA_SIZE];        /* VLAN bitmap */
 116 };
 117
 118 struct fm10k_dev_info {
 119         volatile uint32_t enable;
 120         volatile uint32_t glort;
 121         /* Protect the mailbox to avoid race condition */
 122         rte_spinlock_t    mbx_lock;
 123         struct fm10k_macvlan_filter_info    macvlan;
 124         /* Flag to indicate if RX vector conditions satisfied */
 125         bool rx_vec_allowed;
 126         bool sm_down;
 127 };
 128
 129 /*
 130  * Structure to store private data for each driver instance.
 131  */
 132 struct fm10k_adapter {
 133         struct fm10k_hw             hw;
 134         struct fm10k_hw_stats       stats;
 135         struct fm10k_dev_info       info;
 136 };
 137
 138 #define FM10K_DEV_PRIVATE_TO_HW(adapter) \
 139         (&((struct fm10k_adapter *)adapter)->hw)
 140
 141 #define FM10K_DEV_PRIVATE_TO_STATS(adapter) \
 142         (&((struct fm10k_adapter *)adapter)->stats)
 143
 144 #define FM10K_DEV_PRIVATE_TO_INFO(adapter) \
 145         (&((struct fm10k_adapter *)adapter)->info)
 146
 147 #define FM10K_DEV_PRIVATE_TO_MBXLOCK(adapter) \
 148         (&(((struct fm10k_adapter *)adapter)->info.mbx_lock))
 149
 150 #define FM10K_DEV_PRIVATE_TO_MACVLAN(adapter) \
 151                 (&(((struct fm10k_adapter *)adapter)->info.macvlan))
 152
 153 struct fm10k_rx_queue {
 154         struct rte_mempool *mp;
 155         struct rte_mbuf **sw_ring;
 156         volatile union fm10k_rx_desc *hw_ring;
 157         struct rte_mbuf *pkt_first_seg; /* First segment of current packet. */
 158         struct rte_mbuf *pkt_last_seg;  /* Last segment of current packet. */
 159         uint64_t hw_ring_phys_addr;
 160         uint64_t mbuf_initializer; /* value to init mbufs */
 161         /* need to alloc dummy mbuf, for wraparound when scanning hw ring */
 162         struct rte_mbuf fake_mbuf;
 163         uint16_t next_dd;
 164         uint16_t next_alloc;
 165         uint16_t next_trigger;
 166         uint16_t alloc_thresh;
 167         volatile uint32_t *tail_ptr;
 168         uint16_t nb_desc;
 169         /* Number of faked desc added at the tail for Vector RX function */
 170         uint16_t nb_fake_desc;
 171         uint16_t queue_id;
 172         /* Below 2 fields only valid in case vPMD is applied. */
 173         uint16_t rxrearm_nb;     /* number of remaining to be re-armed */
 174         uint16_t rxrearm_start;  /* the idx we start the re-arming from */
 175         uint16_t rx_using_sse; /* indicates that vector RX is in use */
 176         uint16_t port_id;
 177         uint8_t drop_en;
 178         uint8_t rx_deferred_start; /* don't start this queue in dev start. */
 179         uint16_t rx_ftag_en; /* indicates FTAG RX supported */
 180         uint64_t offloads; /* offloads of DEV_RX_OFFLOAD_* */
 181 };
 182
 183 /*
 184  * a FIFO is used to track which descriptors have their RS bit set for Tx
 185  * queues which are configured to allow multiple descriptors per packet
 186  */
 187 struct fifo {
 188         uint16_t *list;
 189         uint16_t *head;
 190         uint16_t *tail;
 191         uint16_t *endp;
 192 };
 193
 194 struct fm10k_txq_ops;
 195
 196 struct fm10k_tx_queue {
 197         struct rte_mbuf **sw_ring;
 198         struct fm10k_tx_desc *hw_ring;
 199         uint64_t hw_ring_phys_addr;
 200         struct fifo rs_tracker;
 201         const struct fm10k_txq_ops *ops; /* txq ops */
 202         uint16_t last_free;
 203         uint16_t next_free;
 204         uint16_t nb_free;
 205         uint16_t nb_used;
 206         uint16_t free_thresh;
 207         uint16_t rs_thresh;
 208         /* Below 2 fields only valid in case vPMD is applied. */
 209         uint16_t next_rs; /* Next pos to set RS flag */
 210         uint16_t next_dd; /* Next pos to check DD flag */
 211         volatile uint32_t *tail_ptr;
 212         uint64_t offloads; /* Offloads of DEV_TX_OFFLOAD_* */
 213         uint16_t nb_desc;
 214         uint16_t port_id;
 215         uint8_t tx_deferred_start; /** don't start this queue in dev start. */
 216         uint16_t queue_id;
 217         uint16_t tx_ftag_en; /* indicates FTAG TX supported */
 218 };
 219
 220 struct fm10k_txq_ops {
 221         void (*reset)(struct fm10k_tx_queue *txq);
 222 };
 223
 224 #define MBUF_DMA_ADDR(mb) \
 225         ((uint64_t) ((mb)->buf_iova + (mb)->data_off))
 226
 227 /* enforce 512B alignment on default Rx DMA addresses */
 228 #define MBUF_DMA_ADDR_DEFAULT(mb) \
 229         ((uint64_t) RTE_ALIGN(((mb)->buf_iova + RTE_PKTMBUF_HEADROOM),\
 230                         FM10K_RX_DATABUF_ALIGN))
 231
 232 static inline void fifo_reset(struct fifo *fifo, uint32_t len)
 233 {
 234         fifo->head = fifo->tail = fifo->list;
 235         fifo->endp = fifo->list + len;
 236 }
 237
 238 static inline void fifo_insert(struct fifo *fifo, uint16_t val)
 239 {
 240         *fifo->head = val;
 241         if (++fifo->head == fifo->endp)
 242                 fifo->head = fifo->list;
 243 }
 244
 245 /* do not worry about list being empty since we only check it once we know
 246  * we have used enough descriptors to set the RS bit at least once */
 247 static inline uint16_t fifo_peek(struct fifo *fifo)
 248 {
 249         return *fifo->tail;
 250 }
 251
 252 static inline uint16_t fifo_remove(struct fifo *fifo)
 253 {
 254         uint16_t val;
 255         val = *fifo->tail;
 256         if (++fifo->tail == fifo->endp)
 257                 fifo->tail = fifo->list;
 258         return val;
 259 }
 260
 261 static inline void
 262 fm10k_pktmbuf_reset(struct rte_mbuf *mb, uint16_t in_port)
 263 {
 264         rte_mbuf_refcnt_set(mb, 1);
 265         mb->next = NULL;
 266         mb->nb_segs = 1;
 267
 268         /* enforce 512B alignment on default Rx virtual addresses */
 269         mb->data_off = (uint16_t)(RTE_PTR_ALIGN((char *)mb->buf_addr +
 270                         RTE_PKTMBUF_HEADROOM, FM10K_RX_DATABUF_ALIGN)
 271                         - (char *)mb->buf_addr);
 272         mb->port = in_port;
 273 }
 274
 275 /*
 276  * Verify Rx packet buffer alignment is valid.
 277  *
 278  * Hardware requires specific alignment for Rx packet buffers. At
 279  * least one of the following two conditions must be satisfied.
 280  *  1. Address is 512B aligned
 281  *  2. Address is 8B aligned and buffer does not cross 4K boundary.
 282  *
 283  * Return 1 if buffer alignment satisfies at least one condition,
 284  * otherwise return 0.
 285  *
 286  * Note: Alignment is checked by the driver when the Rx queue is reset. It
 287  *       is assumed that if an entire descriptor ring can be filled with
 288  *       buffers containing valid alignment, then all buffers in that mempool
 289  *       have valid address alignment. It is the responsibility of the user
 290  *       to ensure all buffers have valid alignment, as it is the user who
 291  *       creates the mempool.
 292  * Note: It is assumed the buffer needs only to store a maximum size Ethernet
 293  *       frame.
 294  */
 295 static inline int
 296 fm10k_addr_alignment_valid(struct rte_mbuf *mb)
 297 {
 298         uint64_t addr = MBUF_DMA_ADDR_DEFAULT(mb);
 299         uint64_t boundary1, boundary2;
 300
 301         /* 512B aligned? */
 302         if (RTE_ALIGN(addr, FM10K_RX_DATABUF_ALIGN) == addr)
 303                 return 1;
 304
 305         /* 8B aligned, and max Ethernet frame would not cross a 4KB boundary? */
 306         if (RTE_ALIGN(addr, 8) == addr) {
 307                 boundary1 = RTE_ALIGN_FLOOR(addr, 4096);
 308                 boundary2 = RTE_ALIGN_FLOOR(addr + RTE_ETHER_MAX_VLAN_FRAME_LEN,
 309                                                 4096);
 310                 if (boundary1 == boundary2)
 311                         return 1;
 312         }
 313
 314         PMD_INIT_LOG(ERR, "Error: Invalid buffer alignment!");
 315
 316         return 0;
 317 }
 318
 319 /* Rx and Tx prototypes */
 320 uint16_t fm10k_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 321         uint16_t nb_pkts);
 322
 323 uint16_t fm10k_recv_scattered_pkts(void *rx_queue,
 324                 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 325
 326 uint32_t
 327 fm10k_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 328
 329 int
 330 fm10k_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
 331
 332 int
 333 fm10k_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
 334
 335 int
 336 fm10k_dev_tx_descriptor_status(void *rx_queue, uint16_t offset);
 337
 338
 339 uint16_t fm10k_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 340         uint16_t nb_pkts);
 341
 342 uint16_t fm10k_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 343         uint16_t nb_pkts);
 344
 345 int fm10k_rxq_vec_setup(struct fm10k_rx_queue *rxq);
 346 int fm10k_rx_vec_condition_check(struct rte_eth_dev *);
 347 void fm10k_rx_queue_release_mbufs_vec(struct fm10k_rx_queue *rxq);
 348 uint16_t fm10k_recv_pkts_vec(void *, struct rte_mbuf **, uint16_t);
 349 uint16_t fm10k_recv_scattered_pkts_vec(void *, struct rte_mbuf **,
 350                                         uint16_t);
 351 uint16_t fm10k_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 352                                     uint16_t nb_pkts);
 353 void fm10k_txq_vec_setup(struct fm10k_tx_queue *txq);
 354 int fm10k_tx_vec_condition_check(struct fm10k_tx_queue *txq);
 355
 356 #endif