1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 #ifndef _HINIC_PORT_CMD_H_
6 #define _HINIC_PORT_CMD_H_
10 enum hinic_resp_aeq_num
{
18 HINIC_MOD_COMM
= 0, /* HW communication module */
19 HINIC_MOD_L2NIC
= 1, /* L2NIC module */
20 HINIC_MOD_CFGM
= 7, /* Configuration module */
21 HINIC_MOD_HILINK
= 14,
25 /* only used by VFD communicating with PFD to register or unregister,
26 * command mode type is HINIC_MOD_L2NIC
28 #define HINIC_PORT_CMD_VF_REGISTER 0x0
29 #define HINIC_PORT_CMD_VF_UNREGISTER 0x1
31 /* cmd of mgmt CPU message for NIC module */
33 HINIC_PORT_CMD_MGMT_RESET
= 0x0,
35 HINIC_PORT_CMD_CHANGE_MTU
= 0x2,
37 HINIC_PORT_CMD_ADD_VLAN
= 0x3,
38 HINIC_PORT_CMD_DEL_VLAN
,
40 HINIC_PORT_CMD_SET_ETS
= 0x7,
41 HINIC_PORT_CMD_GET_ETS
,
43 HINIC_PORT_CMD_SET_MAC
= 0x9,
44 HINIC_PORT_CMD_GET_MAC
,
45 HINIC_PORT_CMD_DEL_MAC
,
47 HINIC_PORT_CMD_SET_RX_MODE
= 0xc,
48 HINIC_PORT_CMD_SET_ANTI_ATTACK_RATE
= 0xd,
50 HINIC_PORT_CMD_GET_PAUSE_INFO
= 0x14,
51 HINIC_PORT_CMD_SET_PAUSE_INFO
,
53 HINIC_PORT_CMD_GET_LINK_STATE
= 0x18,
54 HINIC_PORT_CMD_SET_LRO
= 0x19,
55 HINIC_PORT_CMD_SET_RX_CSUM
= 0x1a,
56 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD
= 0x1b,
58 HINIC_PORT_CMD_GET_PORT_STATISTICS
= 0x1c,
59 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS
,
60 HINIC_PORT_CMD_GET_VPORT_STAT
,
61 HINIC_PORT_CMD_CLEAN_VPORT_STAT
,
63 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL
= 0x25,
64 HINIC_PORT_CMD_SET_RSS_TEMPLATE_INDIR_TBL
,
66 HINIC_PORT_CMD_SET_PORT_ENABLE
= 0x29,
67 HINIC_PORT_CMD_GET_PORT_ENABLE
,
69 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL
= 0x2b,
70 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL
,
71 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE
,
72 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE
,
73 HINIC_PORT_CMD_GET_RSS_CTX_TBL
,
74 HINIC_PORT_CMD_SET_RSS_CTX_TBL
,
75 HINIC_PORT_CMD_RSS_TEMP_MGR
,
77 HINIC_PORT_CMD_RSS_CFG
= 0x42,
79 HINIC_PORT_CMD_GET_PHY_TYPE
= 0x44,
80 HINIC_PORT_CMD_INIT_FUNC
= 0x45,
82 HINIC_PORT_CMD_GET_JUMBO_FRAME_SIZE
= 0x4a,
83 HINIC_PORT_CMD_SET_JUMBO_FRAME_SIZE
,
85 HINIC_PORT_CMD_GET_MGMT_VERSION
= 0x58,
87 HINIC_PORT_CMD_GET_PORT_TYPE
= 0x5b,
89 HINIC_PORT_CMD_GET_VPORT_ENABLE
= 0x5c,
90 HINIC_PORT_CMD_SET_VPORT_ENABLE
,
92 HINIC_PORT_CMD_GET_PORT_ID_BY_FUNC_ID
= 0x5e,
94 HINIC_PORT_CMD_GET_LRO
= 0x63,
96 HINIC_PORT_CMD_GET_DMA_CS
= 0x64,
97 HINIC_PORT_CMD_SET_DMA_CS
,
99 HINIC_PORT_CMD_GET_GLOBAL_QPN
= 0x66,
101 HINIC_PORT_CMD_SET_PFC_MISC
= 0x67,
102 HINIC_PORT_CMD_GET_PFC_MISC
,
104 HINIC_PORT_CMD_SET_VF_RATE
= 0x69,
105 HINIC_PORT_CMD_SET_VF_VLAN
,
106 HINIC_PORT_CMD_CLR_VF_VLAN
,
108 HINIC_PORT_CMD_SET_RQ_IQ_MAP
= 0x73,
109 HINIC_PORT_CMD_SET_PFC_THD
= 0x75,
111 HINIC_PORT_CMD_LINK_STATUS_REPORT
= 0xa0,
113 HINIC_PORT_CMD_SET_LOSSLESS_ETH
= 0xa3,
114 HINIC_PORT_CMD_UPDATE_MAC
= 0xa4,
116 HINIC_PORT_CMD_GET_PORT_INFO
= 0xaa,
118 HINIC_PORT_CMD_UP_TC_ADD_FLOW
= 0xaf,
119 HINIC_PORT_CMD_UP_TC_DEL_FLOW
= 0xb0,
120 HINIC_PORT_CMD_UP_TC_GET_FLOW
= 0xb1,
121 HINIC_PORT_CMD_UP_TC_FLUSH_TCAM
= 0xb2,
122 HINIC_PORT_CMD_UP_TC_CTRL_TCAM_BLOCK
= 0xb3,
124 HINIC_PORT_CMD_SET_IPSU_MAC
= 0xcb,
125 HINIC_PORT_CMD_GET_IPSU_MAC
= 0xcc,
127 HINIC_PORT_CMD_SET_XSFP_STATUS
= 0xD4,
129 HINIC_PORT_CMD_GET_LINK_MODE
= 0xD9,
130 HINIC_PORT_CMD_SET_SPEED
= 0xDA,
131 HINIC_PORT_CMD_SET_AUTONEG
= 0xDB,
133 HINIC_PORT_CMD_CLEAR_QP_RES
= 0xDD,
134 HINIC_PORT_CMD_SET_SUPER_CQE
= 0xDE,
135 HINIC_PORT_CMD_SET_VF_COS
= 0xDF,
136 HINIC_PORT_CMD_GET_VF_COS
= 0xE1,
138 HINIC_PORT_CMD_CABLE_PLUG_EVENT
= 0xE5,
139 HINIC_PORT_CMD_LINK_ERR_EVENT
= 0xE6,
141 HINIC_PORT_CMD_SET_COS_UP_MAP
= 0xE8,
143 HINIC_PORT_CMD_RESET_LINK_CFG
= 0xEB,
145 HINIC_PORT_CMD_FORCE_PKT_DROP
= 0xF3,
146 HINIC_PORT_CMD_SET_LRO_TIMER
= 0xF4,
148 HINIC_PORT_CMD_SET_VHD_CFG
= 0xF7,
149 HINIC_PORT_CMD_SET_LINK_FOLLOW
= 0xF8,
150 HINIC_PORT_CMD_Q_FILTER
= 0xFC,
151 HINIC_PORT_CMD_TCAM_FILTER
= 0xFE,
152 HINIC_PORT_CMD_SET_VLAN_FILTER
= 0xFF
155 /* cmd of mgmt CPU message for HW module */
156 enum hinic_mgmt_cmd
{
157 HINIC_MGMT_CMD_RESET_MGMT
= 0x0,
158 HINIC_MGMT_CMD_START_FLR
= 0x1,
159 HINIC_MGMT_CMD_FLUSH_DOORBELL
= 0x2,
160 HINIC_MGMT_CMD_GET_IO_STATUS
= 0x3,
161 HINIC_MGMT_CMD_DMA_ATTR_SET
= 0x4,
163 HINIC_MGMT_CMD_CMDQ_CTXT_SET
= 0x10,
164 HINIC_MGMT_CMD_CMDQ_CTXT_GET
,
166 HINIC_MGMT_CMD_VAT_SET
= 0x12,
167 HINIC_MGMT_CMD_VAT_GET
,
169 HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_SET
= 0x14,
170 HINIC_MGMT_CMD_L2NIC_SQ_CI_ATTR_GET
,
172 HINIC_MGMT_CMD_PPF_HT_GPA_SET
= 0x23,
173 HINIC_MGMT_CMD_RES_STATE_SET
= 0x24,
174 HINIC_MGMT_CMD_FUNC_CACHE_OUT
= 0x25,
175 HINIC_MGMT_CMD_FFM_SET
= 0x26,
177 HINIC_MGMT_CMD_FUNC_RES_CLEAR
= 0x29,
179 HINIC_MGMT_CMD_CEQ_CTRL_REG_WR_BY_UP
= 0x33,
180 HINIC_MGMT_CMD_MSI_CTRL_REG_WR_BY_UP
,
181 HINIC_MGMT_CMD_MSI_CTRL_REG_RD_BY_UP
,
183 HINIC_MGMT_CMD_VF_RANDOM_ID_SET
= 0x36,
184 HINIC_MGMT_CMD_FAULT_REPORT
= 0x37,
186 HINIC_MGMT_CMD_VPD_SET
= 0x40,
187 HINIC_MGMT_CMD_VPD_GET
,
188 HINIC_MGMT_CMD_LABEL_SET
,
189 HINIC_MGMT_CMD_LABEL_GET
,
190 HINIC_MGMT_CMD_SATIC_MAC_SET
,
191 HINIC_MGMT_CMD_SATIC_MAC_GET
,
192 HINIC_MGMT_CMD_SYNC_TIME
= 0x46,
193 HINIC_MGMT_CMD_SET_LED_STATUS
= 0x4A,
194 HINIC_MGMT_CMD_L2NIC_RESET
= 0x4b,
195 HINIC_MGMT_CMD_FAST_RECYCLE_MODE_SET
= 0x4d,
196 HINIC_MGMT_CMD_BIOS_NV_DATA_MGMT
= 0x4E,
197 HINIC_MGMT_CMD_ACTIVATE_FW
= 0x4F,
198 HINIC_MGMT_CMD_PAGESIZE_SET
= 0x50,
199 HINIC_MGMT_CMD_PAGESIZE_GET
= 0x51,
200 HINIC_MGMT_CMD_GET_BOARD_INFO
= 0x52,
201 HINIC_MGMT_CMD_WATCHDOG_INFO
= 0x56,
202 HINIC_MGMT_CMD_FMW_ACT_NTC
= 0x57,
203 HINIC_MGMT_CMD_SET_VF_RANDOM_ID
= 0x61,
204 HINIC_MGMT_CMD_GET_PPF_STATE
= 0x63,
205 HINIC_MGMT_CMD_PCIE_DFX_NTC
= 0x65,
206 HINIC_MGMT_CMD_PCIE_DFX_GET
= 0x66,
209 /* cmd of mgmt CPU message for HILINK module */
210 enum hinic_hilink_cmd
{
211 HINIC_HILINK_CMD_GET_LINK_INFO
= 0x3,
212 HINIC_HILINK_CMD_SET_LINK_SETTINGS
= 0x8,
215 /* uCode related commands */
216 enum hinic_ucode_cmd
{
217 HINIC_UCODE_CMD_MDY_QUEUE_CONTEXT
= 0,
218 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT
,
219 HINIC_UCODE_CMD_ARM_SQ
,
220 HINIC_UCODE_CMD_ARM_RQ
,
221 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE
,
222 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE
,
223 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE
,
224 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE
,
225 HINIC_UCODE_CMD_SET_IQ_ENABLE
,
226 HINIC_UCODE_CMD_SET_RQ_FLUSH
= 10
231 HINIC_CFG_NIC_CAP
= 0,
234 HINIC_CFG_MBOX_CAP
= 6
237 enum hinic_ack_type
{
239 HINIC_ACK_TYPE_SHARE_CQN
,
240 HINIC_ACK_TYPE_APP_CQN
,
242 HINIC_MOD_ACK_MAX
= 15,
245 enum sq_l4offload_type
{
247 TCP_OFFLOAD_ENABLE
= 1,
248 SCTP_OFFLOAD_ENABLE
= 2,
249 UDP_OFFLOAD_ENABLE
= 3,
252 enum sq_vlan_offload_flag
{
253 VLAN_OFFLOAD_DISABLE
= 0,
254 VLAN_OFFLOAD_ENABLE
= 1,
257 enum sq_pkt_parsed_flag
{
265 IPV4_PKT_NO_CHKSUM_OFFLOAD
= 2,
266 IPV4_PKT_WITH_CHKSUM_OFFLOAD
= 3,
277 enum sq_tunnel_l4_type
{
283 #define NIC_RSS_CMD_TEMP_ALLOC 0x01
284 #define NIC_RSS_CMD_TEMP_FREE 0x02
286 #define HINIC_RSS_TYPE_VALID_SHIFT 23
287 #define HINIC_RSS_TYPE_TCP_IPV6_EXT_SHIFT 24
288 #define HINIC_RSS_TYPE_IPV6_EXT_SHIFT 25
289 #define HINIC_RSS_TYPE_TCP_IPV6_SHIFT 26
290 #define HINIC_RSS_TYPE_IPV6_SHIFT 27
291 #define HINIC_RSS_TYPE_TCP_IPV4_SHIFT 28
292 #define HINIC_RSS_TYPE_IPV4_SHIFT 29
293 #define HINIC_RSS_TYPE_UDP_IPV6_SHIFT 30
294 #define HINIC_RSS_TYPE_UDP_IPV4_SHIFT 31
296 #define HINIC_RSS_TYPE_SET(val, member) \
297 (((u32)(val) & 0x1) << HINIC_RSS_TYPE_##member##_SHIFT)
299 #define HINIC_RSS_TYPE_GET(val, member) \
300 (((u32)(val) >> HINIC_RSS_TYPE_##member##_SHIFT) & 0x1)
303 HINIC_SPEED_10MB_LINK
= 0,
304 HINIC_SPEED_100MB_LINK
,
305 HINIC_SPEED_1000MB_LINK
,
306 HINIC_SPEED_10GB_LINK
,
307 HINIC_SPEED_25GB_LINK
,
308 HINIC_SPEED_40GB_LINK
,
309 HINIC_SPEED_100GB_LINK
,
310 HINIC_SPEED_UNKNOWN
= 0xFF,
314 HINIC_IFLA_VF_LINK_STATE_AUTO
, /* link state of the uplink */
315 HINIC_IFLA_VF_LINK_STATE_ENABLE
, /* link always up */
316 HINIC_IFLA_VF_LINK_STATE_DISABLE
, /* link always down */
319 #define HINIC_AF0_FUNC_GLOBAL_IDX_SHIFT 0
320 #define HINIC_AF0_P2P_IDX_SHIFT 10
321 #define HINIC_AF0_PCI_INTF_IDX_SHIFT 14
322 #define HINIC_AF0_VF_IN_PF_SHIFT 16
323 #define HINIC_AF0_FUNC_TYPE_SHIFT 24
325 #define HINIC_AF0_FUNC_GLOBAL_IDX_MASK 0x3FF
326 #define HINIC_AF0_P2P_IDX_MASK 0xF
327 #define HINIC_AF0_PCI_INTF_IDX_MASK 0x3
328 #define HINIC_AF0_VF_IN_PF_MASK 0xFF
329 #define HINIC_AF0_FUNC_TYPE_MASK 0x1
331 #define HINIC_AF0_GET(val, member) \
332 (((val) >> HINIC_AF0_##member##_SHIFT) & HINIC_AF0_##member##_MASK)
334 #define HINIC_AF1_PPF_IDX_SHIFT 0
335 #define HINIC_AF1_AEQS_PER_FUNC_SHIFT 8
336 #define HINIC_AF1_CEQS_PER_FUNC_SHIFT 12
337 #define HINIC_AF1_IRQS_PER_FUNC_SHIFT 20
338 #define HINIC_AF1_DMA_ATTR_PER_FUNC_SHIFT 24
339 #define HINIC_AF1_MGMT_INIT_STATUS_SHIFT 30
340 #define HINIC_AF1_PF_INIT_STATUS_SHIFT 31
342 #define HINIC_AF1_PPF_IDX_MASK 0x1F
343 #define HINIC_AF1_AEQS_PER_FUNC_MASK 0x3
344 #define HINIC_AF1_CEQS_PER_FUNC_MASK 0x7
345 #define HINIC_AF1_IRQS_PER_FUNC_MASK 0xF
346 #define HINIC_AF1_DMA_ATTR_PER_FUNC_MASK 0x7
347 #define HINIC_AF1_MGMT_INIT_STATUS_MASK 0x1
348 #define HINIC_AF1_PF_INIT_STATUS_MASK 0x1
350 #define HINIC_AF1_GET(val, member) \
351 (((val) >> HINIC_AF1_##member##_SHIFT) & HINIC_AF1_##member##_MASK)
353 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_SHIFT 16
354 #define HINIC_AF2_GLOBAL_VF_ID_OF_PF_MASK 0x3FF
356 #define HINIC_AF2_GET(val, member) \
357 (((val) >> HINIC_AF2_##member##_SHIFT) & HINIC_AF2_##member##_MASK)
359 #define HINIC_AF4_OUTBOUND_CTRL_SHIFT 0
360 #define HINIC_AF4_DOORBELL_CTRL_SHIFT 1
361 #define HINIC_AF4_OUTBOUND_CTRL_MASK 0x1
362 #define HINIC_AF4_DOORBELL_CTRL_MASK 0x1
364 #define HINIC_AF4_GET(val, member) \
365 (((val) >> HINIC_AF4_##member##_SHIFT) & HINIC_AF4_##member##_MASK)
367 #define HINIC_AF4_SET(val, member) \
368 (((val) & HINIC_AF4_##member##_MASK) << HINIC_AF4_##member##_SHIFT)
370 #define HINIC_AF4_CLEAR(val, member) \
371 ((val) & (~(HINIC_AF4_##member##_MASK << \
372 HINIC_AF4_##member##_SHIFT)))
374 #define HINIC_AF5_PF_STATUS_SHIFT 0
375 #define HINIC_AF5_PF_STATUS_MASK 0xFFFF
377 #define HINIC_AF5_SET(val, member) \
378 (((val) & HINIC_AF5_##member##_MASK) << HINIC_AF5_##member##_SHIFT)
380 #define HINIC_AF5_GET(val, member) \
381 (((val) >> HINIC_AF5_##member##_SHIFT) & HINIC_AF5_##member##_MASK)
383 #define HINIC_AF5_CLEAR(val, member) \
384 ((val) & (~(HINIC_AF5_##member##_MASK << \
385 HINIC_AF5_##member##_SHIFT)))
387 #define HINIC_PPF_ELECTION_IDX_SHIFT 0
389 #define HINIC_PPF_ELECTION_IDX_MASK 0x1F
391 #define HINIC_PPF_ELECTION_SET(val, member) \
392 (((val) & HINIC_PPF_ELECTION_##member##_MASK) << \
393 HINIC_PPF_ELECTION_##member##_SHIFT)
395 #define HINIC_PPF_ELECTION_GET(val, member) \
396 (((val) >> HINIC_PPF_ELECTION_##member##_SHIFT) & \
397 HINIC_PPF_ELECTION_##member##_MASK)
399 #define HINIC_PPF_ELECTION_CLEAR(val, member) \
400 ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \
401 << HINIC_PPF_ELECTION_##member##_SHIFT)))
403 #define DB_IDX(db, db_base) \
404 ((u32)(((unsigned long)(db) - (unsigned long)(db_base)) / \
407 enum hinic_pcie_nosnoop
{
408 HINIC_PCIE_SNOOP
= 0,
409 HINIC_PCIE_NO_SNOOP
= 1,
412 enum hinic_pcie_tph
{
413 HINIC_PCIE_TPH_DISABLE
= 0,
414 HINIC_PCIE_TPH_ENABLE
= 1,
417 enum hinic_outbound_ctrl
{
418 ENABLE_OUTBOUND
= 0x0,
419 DISABLE_OUTBOUND
= 0x1,
422 enum hinic_doorbell_ctrl
{
423 ENABLE_DOORBELL
= 0x0,
424 DISABLE_DOORBELL
= 0x1,
427 enum hinic_pf_status
{
428 HINIC_PF_STATUS_INIT
= 0X0,
429 HINIC_PF_STATUS_ACTIVE_FLAG
= 0x11,
430 HINIC_PF_STATUS_FLR_START_FLAG
= 0x12,
431 HINIC_PF_STATUS_FLR_FINISH_FLAG
= 0x13,
434 /* total doorbell or direct wqe size is 512kB, db num: 128, dwqe: 128 */
435 #define HINIC_DB_DWQE_SIZE 0x00080000
437 /* db page size: 4K */
438 #define HINIC_DB_PAGE_SIZE 0x00001000ULL
440 #define HINIC_DB_MAX_AREAS (HINIC_DB_DWQE_SIZE / HINIC_DB_PAGE_SIZE)
442 #define HINIC_PCI_MSIX_ENTRY_SIZE 16
443 #define HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL 12
444 #define HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT 1
446 struct hinic_mgmt_msg_head
{
453 struct hinic_root_ctxt
{
454 struct hinic_mgmt_msg_head mgmt_msg_head
;
469 #endif /* _HINIC_PORT_CMD_H_ */