1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_string_fns.h>
16 #include <rte_ether.h>
17 #include <rte_ethdev_driver.h>
18 #include <rte_malloc.h>
19 #include <rte_memcpy.h>
21 #include "i40e_logs.h"
22 #include "base/i40e_prototype.h"
23 #include "base/i40e_adminq_cmd.h"
24 #include "base/i40e_type.h"
25 #include "i40e_ethdev.h"
26 #include "i40e_rxtx.h"
28 #include "rte_pmd_i40e.h"
30 #define I40E_CFG_CRCSTRIP_DEFAULT 1
33 i40e_pf_host_switch_queues(struct i40e_pf_vf
*vf
,
34 struct virtchnl_queue_select
*qsel
,
38 * Bind PF queues with VSI and VF.
41 i40e_pf_vf_queues_mapping(struct i40e_pf_vf
*vf
)
44 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
45 uint16_t vsi_id
= vf
->vsi
->vsi_id
;
46 uint16_t vf_id
= vf
->vf_idx
;
47 uint16_t nb_qps
= vf
->vsi
->nb_qps
;
48 uint16_t qbase
= vf
->vsi
->base_queue
;
53 * VF should use scatter range queues. So, it needn't
54 * to set QBASE in this register.
56 i40e_write_rx_ctl(hw
, I40E_VSILAN_QBASE(vsi_id
),
57 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK
);
59 /* Set to enable VFLAN_QTABLE[] registers valid */
60 I40E_WRITE_REG(hw
, I40E_VPLAN_MAPENA(vf_id
),
61 I40E_VPLAN_MAPENA_TXRX_ENA_MASK
);
63 /* map PF queues to VF */
64 for (i
= 0; i
< nb_qps
; i
++) {
65 val
= ((qbase
+ i
) & I40E_VPLAN_QTABLE_QINDEX_MASK
);
66 I40E_WRITE_REG(hw
, I40E_VPLAN_QTABLE(i
, vf_id
), val
);
69 /* map PF queues to VSI */
70 for (i
= 0; i
< I40E_MAX_QP_NUM_PER_VF
/ 2; i
++) {
71 if (2 * i
> nb_qps
- 1)
72 q1
= I40E_VSILAN_QTABLE_QINDEX_0_MASK
;
76 if (2 * i
+ 1 > nb_qps
- 1)
77 q2
= I40E_VSILAN_QTABLE_QINDEX_0_MASK
;
79 q2
= qbase
+ 2 * i
+ 1;
81 val
= (q2
<< I40E_VSILAN_QTABLE_QINDEX_1_SHIFT
) + q1
;
82 i40e_write_rx_ctl(hw
, I40E_VSILAN_QTABLE(i
, vsi_id
), val
);
91 * Proceed VF reset operation.
94 i40e_pf_host_vf_reset(struct i40e_pf_vf
*vf
, bool do_hw_reset
)
99 uint16_t vf_id
, abs_vf_id
, vf_msix_num
;
101 struct virtchnl_queue_select qsel
;
107 hw
= I40E_PF_TO_HW(vf
->pf
);
109 abs_vf_id
= vf_id
+ hw
->func_caps
.vf_base_id
;
111 /* Notify VF that we are in VFR progress */
112 I40E_WRITE_REG(hw
, I40E_VFGEN_RSTAT1(vf_id
), VIRTCHNL_VFR_INPROGRESS
);
115 * If require a SW VF reset, a VFLR interrupt will be generated,
116 * this function will be called again. To avoid it,
117 * disable interrupt first.
120 vf
->state
= I40E_VF_INRESET
;
121 val
= I40E_READ_REG(hw
, I40E_VPGEN_VFRTRIG(vf_id
));
122 val
|= I40E_VPGEN_VFRTRIG_VFSWR_MASK
;
123 I40E_WRITE_REG(hw
, I40E_VPGEN_VFRTRIG(vf_id
), val
);
124 I40E_WRITE_FLUSH(hw
);
127 #define VFRESET_MAX_WAIT_CNT 100
128 /* Wait until VF reset is done */
129 for (i
= 0; i
< VFRESET_MAX_WAIT_CNT
; i
++) {
131 val
= I40E_READ_REG(hw
, I40E_VPGEN_VFRSTAT(vf_id
));
132 if (val
& I40E_VPGEN_VFRSTAT_VFRD_MASK
)
136 if (i
>= VFRESET_MAX_WAIT_CNT
) {
137 PMD_DRV_LOG(ERR
, "VF reset timeout");
140 /* This is not first time to do reset, do cleanup job first */
143 memset(&qsel
, 0, sizeof(qsel
));
144 for (i
= 0; i
< vf
->vsi
->nb_qps
; i
++)
145 qsel
.rx_queues
|= 1 << i
;
146 qsel
.tx_queues
= qsel
.rx_queues
;
147 ret
= i40e_pf_host_switch_queues(vf
, &qsel
, false);
148 if (ret
!= I40E_SUCCESS
) {
149 PMD_DRV_LOG(ERR
, "Disable VF queues failed");
153 /* Disable VF interrupt setting */
154 vf_msix_num
= hw
->func_caps
.num_msix_vectors_vf
;
155 for (i
= 0; i
< vf_msix_num
; i
++) {
157 val
= I40E_VFINT_DYN_CTL0(vf_id
);
159 val
= I40E_VFINT_DYN_CTLN(((vf_msix_num
- 1) *
161 I40E_WRITE_REG(hw
, val
, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK
);
163 I40E_WRITE_FLUSH(hw
);
166 ret
= i40e_vsi_release(vf
->vsi
);
167 if (ret
!= I40E_SUCCESS
) {
168 PMD_DRV_LOG(ERR
, "Release VSI failed");
173 #define I40E_VF_PCI_ADDR 0xAA
174 #define I40E_VF_PEND_MASK 0x20
175 /* Check the pending transactions of this VF */
176 /* Use absolute VF id, refer to datasheet for details */
177 I40E_WRITE_REG(hw
, I40E_PF_PCI_CIAA
, I40E_VF_PCI_ADDR
|
178 (abs_vf_id
<< I40E_PF_PCI_CIAA_VF_NUM_SHIFT
));
179 for (i
= 0; i
< VFRESET_MAX_WAIT_CNT
; i
++) {
181 val
= I40E_READ_REG(hw
, I40E_PF_PCI_CIAD
);
182 if ((val
& I40E_VF_PEND_MASK
) == 0)
186 if (i
>= VFRESET_MAX_WAIT_CNT
) {
187 PMD_DRV_LOG(ERR
, "Wait VF PCI transaction end timeout");
191 /* Reset done, Set COMPLETE flag and clear reset bit */
192 I40E_WRITE_REG(hw
, I40E_VFGEN_RSTAT1(vf_id
), VIRTCHNL_VFR_COMPLETED
);
193 val
= I40E_READ_REG(hw
, I40E_VPGEN_VFRTRIG(vf_id
));
194 val
&= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK
;
195 I40E_WRITE_REG(hw
, I40E_VPGEN_VFRTRIG(vf_id
), val
);
197 I40E_WRITE_FLUSH(hw
);
199 /* Allocate resource again */
200 if (pf
->floating_veb
&& pf
->floating_veb_list
[vf_id
]) {
201 vf
->vsi
= i40e_vsi_setup(vf
->pf
, I40E_VSI_SRIOV
,
204 vf
->vsi
= i40e_vsi_setup(vf
->pf
, I40E_VSI_SRIOV
,
205 vf
->pf
->main_vsi
, vf
->vf_idx
);
208 if (vf
->vsi
== NULL
) {
209 PMD_DRV_LOG(ERR
, "Add vsi failed");
213 ret
= i40e_pf_vf_queues_mapping(vf
);
214 if (ret
!= I40E_SUCCESS
) {
215 PMD_DRV_LOG(ERR
, "queue mapping error");
216 i40e_vsi_release(vf
->vsi
);
220 I40E_WRITE_REG(hw
, I40E_VFGEN_RSTAT1(vf_id
), VIRTCHNL_VFR_VFACTIVE
);
226 i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf
*vf
,
232 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
233 uint16_t abs_vf_id
= hw
->func_caps
.vf_base_id
+ vf
->vf_idx
;
236 ret
= i40e_aq_send_msg_to_vf(hw
, abs_vf_id
, opcode
, retval
,
239 PMD_INIT_LOG(ERR
, "Fail to send message to VF, err %u",
240 hw
->aq
.asq_last_status
);
247 i40e_pf_host_process_cmd_version(struct i40e_pf_vf
*vf
, uint8_t *msg
,
250 struct virtchnl_version_info info
;
252 /* VF and PF drivers need to follow the Virtchnl definition, No matter
253 * it's DPDK or other kernel drivers.
254 * The original DPDK host specific feature
255 * like CFG_VLAN_PVID and CONFIG_VSI_QUEUES_EXT will not available.
258 info
.major
= VIRTCHNL_VERSION_MAJOR
;
259 vf
->version
= *(struct virtchnl_version_info
*)msg
;
260 if (VF_IS_V10(&vf
->version
))
261 info
.minor
= VIRTCHNL_VERSION_MINOR_NO_VF_CAPS
;
263 info
.minor
= VIRTCHNL_VERSION_MINOR
;
266 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_VERSION
,
271 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_VERSION
,
278 i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf
*vf
)
280 i40e_pf_host_vf_reset(vf
, 1);
282 /* No feedback will be sent to VF for VFLR */
287 i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf
*vf
, uint8_t *msg
,
290 struct virtchnl_vf_resource
*vf_res
= NULL
;
291 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
293 uint64_t default_hena
= I40E_RSS_HENA_ALL
;
294 int ret
= I40E_SUCCESS
;
297 i40e_pf_host_send_msg_to_vf(vf
,
298 VIRTCHNL_OP_GET_VF_RESOURCES
,
299 I40E_NOT_SUPPORTED
, NULL
, 0);
303 /* only have 1 VSI by default */
304 len
= sizeof(struct virtchnl_vf_resource
) +
305 I40E_DEFAULT_VF_VSI_NUM
*
306 sizeof(struct virtchnl_vsi_resource
);
308 vf_res
= rte_zmalloc("i40e_vf_res", len
, 0);
309 if (vf_res
== NULL
) {
310 PMD_DRV_LOG(ERR
, "failed to allocate mem");
311 ret
= I40E_ERR_NO_MEMORY
;
317 if (VF_IS_V10(&vf
->version
)) /* doesn't support offload negotiate */
318 vf
->request_caps
= VIRTCHNL_VF_OFFLOAD_L2
|
319 VIRTCHNL_VF_OFFLOAD_VLAN
;
321 vf
->request_caps
= *(uint32_t *)msg
;
323 /* enable all RSS by default,
324 * doesn't support hena setting by virtchnnl yet.
326 if (vf
->request_caps
& VIRTCHNL_VF_OFFLOAD_RSS_PF
) {
327 I40E_WRITE_REG(hw
, I40E_VFQF_HENA1(0, vf
->vf_idx
),
328 (uint32_t)default_hena
);
329 I40E_WRITE_REG(hw
, I40E_VFQF_HENA1(1, vf
->vf_idx
),
330 (uint32_t)(default_hena
>> 32));
331 I40E_WRITE_FLUSH(hw
);
334 vf_res
->vf_cap_flags
= vf
->request_caps
&
335 I40E_VIRTCHNL_OFFLOAD_CAPS
;
336 /* For X722, it supports write back on ITR
337 * without binding queue to interrupt vector.
339 if (hw
->mac
.type
== I40E_MAC_X722
)
340 vf_res
->vf_cap_flags
|= VIRTCHNL_VF_OFFLOAD_WB_ON_ITR
;
341 vf_res
->max_vectors
= hw
->func_caps
.num_msix_vectors_vf
;
342 vf_res
->num_queue_pairs
= vf
->vsi
->nb_qps
;
343 vf_res
->num_vsis
= I40E_DEFAULT_VF_VSI_NUM
;
344 vf_res
->rss_key_size
= (I40E_PFQF_HKEY_MAX_INDEX
+ 1) * 4;
345 vf_res
->rss_lut_size
= (I40E_VFQF_HLUT1_MAX_INDEX
+ 1) * 4;
347 /* Change below setting if PF host can support more VSIs for VF */
348 vf_res
->vsi_res
[0].vsi_type
= VIRTCHNL_VSI_SRIOV
;
349 vf_res
->vsi_res
[0].vsi_id
= vf
->vsi
->vsi_id
;
350 vf_res
->vsi_res
[0].num_queue_pairs
= vf
->vsi
->nb_qps
;
351 rte_ether_addr_copy(&vf
->mac_addr
,
352 (struct rte_ether_addr
*)vf_res
->vsi_res
[0].default_mac_addr
);
355 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_GET_VF_RESOURCES
,
356 ret
, (uint8_t *)vf_res
, len
);
363 i40e_pf_host_hmc_config_rxq(struct i40e_hw
*hw
,
364 struct i40e_pf_vf
*vf
,
365 struct virtchnl_rxq_info
*rxq
,
368 int err
= I40E_SUCCESS
;
369 struct i40e_hmc_obj_rxq rx_ctx
;
370 uint16_t abs_queue_id
= vf
->vsi
->base_queue
+ rxq
->queue_id
;
372 /* Clear the context structure first */
373 memset(&rx_ctx
, 0, sizeof(struct i40e_hmc_obj_rxq
));
374 rx_ctx
.dbuff
= rxq
->databuffer_size
>> I40E_RXQ_CTX_DBUFF_SHIFT
;
375 rx_ctx
.hbuff
= rxq
->hdr_size
>> I40E_RXQ_CTX_HBUFF_SHIFT
;
376 rx_ctx
.base
= rxq
->dma_ring_addr
/ I40E_QUEUE_BASE_ADDR_UNIT
;
377 rx_ctx
.qlen
= rxq
->ring_len
;
378 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
382 if (rxq
->splithdr_enabled
) {
383 rx_ctx
.hsplit_0
= I40E_HEADER_SPLIT_ALL
;
384 rx_ctx
.dtype
= i40e_header_split_enabled
;
386 rx_ctx
.hsplit_0
= I40E_HEADER_SPLIT_NONE
;
387 rx_ctx
.dtype
= i40e_header_split_none
;
389 rx_ctx
.rxmax
= rxq
->max_pkt_size
;
390 rx_ctx
.tphrdesc_ena
= 1;
391 rx_ctx
.tphwdesc_ena
= 1;
392 rx_ctx
.tphdata_ena
= 1;
393 rx_ctx
.tphhead_ena
= 1;
394 rx_ctx
.lrxqthresh
= 2;
395 rx_ctx
.crcstrip
= crcstrip
;
399 err
= i40e_clear_lan_rx_queue_context(hw
, abs_queue_id
);
400 if (err
!= I40E_SUCCESS
)
402 err
= i40e_set_lan_rx_queue_context(hw
, abs_queue_id
, &rx_ctx
);
407 static inline uint8_t
408 i40e_vsi_get_tc_of_queue(struct i40e_vsi
*vsi
,
411 struct i40e_aqc_vsi_properties_data
*info
= &vsi
->info
;
412 uint16_t bsf
, qp_idx
;
415 for (i
= 0; i
< I40E_MAX_TRAFFIC_CLASS
; i
++) {
416 if (vsi
->enabled_tc
& (1 << i
)) {
417 qp_idx
= rte_le_to_cpu_16((info
->tc_mapping
[i
] &
418 I40E_AQ_VSI_TC_QUE_OFFSET_MASK
) >>
419 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT
);
420 bsf
= rte_le_to_cpu_16((info
->tc_mapping
[i
] &
421 I40E_AQ_VSI_TC_QUE_NUMBER_MASK
) >>
422 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT
);
423 if (queue_id
>= qp_idx
&& queue_id
< qp_idx
+ (1 << bsf
))
431 i40e_pf_host_hmc_config_txq(struct i40e_hw
*hw
,
432 struct i40e_pf_vf
*vf
,
433 struct virtchnl_txq_info
*txq
)
435 int err
= I40E_SUCCESS
;
436 struct i40e_hmc_obj_txq tx_ctx
;
437 struct i40e_vsi
*vsi
= vf
->vsi
;
439 uint16_t abs_queue_id
= vsi
->base_queue
+ txq
->queue_id
;
442 /* clear the context structure first */
443 memset(&tx_ctx
, 0, sizeof(tx_ctx
));
444 tx_ctx
.base
= txq
->dma_ring_addr
/ I40E_QUEUE_BASE_ADDR_UNIT
;
445 tx_ctx
.qlen
= txq
->ring_len
;
446 dcb_tc
= i40e_vsi_get_tc_of_queue(vsi
, txq
->queue_id
);
447 tx_ctx
.rdylist
= rte_le_to_cpu_16(vsi
->info
.qs_handle
[dcb_tc
]);
448 tx_ctx
.head_wb_ena
= txq
->headwb_enabled
;
449 tx_ctx
.head_wb_addr
= txq
->dma_headwb_addr
;
451 err
= i40e_clear_lan_tx_queue_context(hw
, abs_queue_id
);
452 if (err
!= I40E_SUCCESS
)
455 err
= i40e_set_lan_tx_queue_context(hw
, abs_queue_id
, &tx_ctx
);
456 if (err
!= I40E_SUCCESS
)
459 /* bind queue with VF function, since TX/QX will appear in pair,
460 * so only has QTX_CTL to set.
462 qtx_ctl
= (I40E_QTX_CTL_VF_QUEUE
<< I40E_QTX_CTL_PFVF_Q_SHIFT
) |
463 ((hw
->pf_id
<< I40E_QTX_CTL_PF_INDX_SHIFT
) &
464 I40E_QTX_CTL_PF_INDX_MASK
) |
465 (((vf
->vf_idx
+ hw
->func_caps
.vf_base_id
) <<
466 I40E_QTX_CTL_VFVM_INDX_SHIFT
) &
467 I40E_QTX_CTL_VFVM_INDX_MASK
);
468 I40E_WRITE_REG(hw
, I40E_QTX_CTL(abs_queue_id
), qtx_ctl
);
469 I40E_WRITE_FLUSH(hw
);
475 i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf
*vf
,
480 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
481 struct i40e_vsi
*vsi
= vf
->vsi
;
482 struct virtchnl_vsi_queue_config_info
*vc_vqci
=
483 (struct virtchnl_vsi_queue_config_info
*)msg
;
484 struct virtchnl_queue_pair_info
*vc_qpi
;
485 int i
, ret
= I40E_SUCCESS
;
488 i40e_pf_host_send_msg_to_vf(vf
,
489 VIRTCHNL_OP_CONFIG_VSI_QUEUES
,
490 I40E_NOT_SUPPORTED
, NULL
, 0);
494 if (!msg
|| vc_vqci
->num_queue_pairs
> vsi
->nb_qps
||
495 vc_vqci
->num_queue_pairs
> I40E_MAX_VSI_QP
||
496 msglen
< I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci
,
497 vc_vqci
->num_queue_pairs
)) {
498 PMD_DRV_LOG(ERR
, "vsi_queue_config_info argument wrong");
499 ret
= I40E_ERR_PARAM
;
503 vc_qpi
= vc_vqci
->qpair
;
504 for (i
= 0; i
< vc_vqci
->num_queue_pairs
; i
++) {
505 if (vc_qpi
[i
].rxq
.queue_id
> vsi
->nb_qps
- 1 ||
506 vc_qpi
[i
].txq
.queue_id
> vsi
->nb_qps
- 1) {
507 ret
= I40E_ERR_PARAM
;
512 * Apply VF RX queue setting to HMC.
513 * If the opcode is VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
514 * then the extra information of
515 * 'struct virtchnl_queue_pair_extra_info' is needed,
516 * otherwise set the last parameter to NULL.
518 if (i40e_pf_host_hmc_config_rxq(hw
, vf
, &vc_qpi
[i
].rxq
,
519 I40E_CFG_CRCSTRIP_DEFAULT
) != I40E_SUCCESS
) {
520 PMD_DRV_LOG(ERR
, "Configure RX queue HMC failed");
521 ret
= I40E_ERR_PARAM
;
525 /* Apply VF TX queue setting to HMC */
526 if (i40e_pf_host_hmc_config_txq(hw
, vf
,
527 &vc_qpi
[i
].txq
) != I40E_SUCCESS
) {
528 PMD_DRV_LOG(ERR
, "Configure TX queue HMC failed");
529 ret
= I40E_ERR_PARAM
;
535 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_CONFIG_VSI_QUEUES
,
542 i40e_pf_config_irq_link_list(struct i40e_pf_vf
*vf
,
543 struct virtchnl_vector_map
*vvm
)
545 #define BITS_PER_CHAR 8
546 uint64_t linklistmap
= 0, tempmap
;
547 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
549 bool b_first_q
= true;
550 enum i40e_queue_type qtype
;
552 uint32_t reg
, reg_idx
;
553 uint16_t itr_idx
= 0, i
;
555 vector_id
= vvm
->vector_id
;
558 reg_idx
= I40E_VPINT_LNKLST0(vf
->vf_idx
);
560 reg_idx
= I40E_VPINT_LNKLSTN(
561 ((hw
->func_caps
.num_msix_vectors_vf
- 1) * vf
->vf_idx
)
564 if (vvm
->rxq_map
== 0 && vvm
->txq_map
== 0) {
565 I40E_WRITE_REG(hw
, reg_idx
,
566 I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK
);
570 /* sort all rx and tx queues */
571 tempmap
= vvm
->rxq_map
;
572 for (i
= 0; i
< sizeof(vvm
->rxq_map
) * BITS_PER_CHAR
; i
++) {
574 linklistmap
|= (1 << (2 * i
));
578 tempmap
= vvm
->txq_map
;
579 for (i
= 0; i
< sizeof(vvm
->txq_map
) * BITS_PER_CHAR
; i
++) {
581 linklistmap
|= (1 << (2 * i
+ 1));
585 /* Link all rx and tx queues into a chained list */
586 tempmap
= linklistmap
;
591 qtype
= (enum i40e_queue_type
)(i
% 2);
592 qid
= vf
->vsi
->base_queue
+ i
/ 2;
597 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT
)
600 /* element in the link list */
602 (qtype
<< I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT
) |
603 (qid
<< I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT
) |
604 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT
) |
605 (itr_idx
<< I40E_QINT_RQCTL_ITR_INDX_SHIFT
);
607 I40E_WRITE_REG(hw
, reg_idx
, reg
);
608 /* find next register to program */
610 case I40E_QUEUE_TYPE_RX
:
611 reg_idx
= I40E_QINT_RQCTL(qid
);
612 itr_idx
= vvm
->rxitr_idx
;
614 case I40E_QUEUE_TYPE_TX
:
615 reg_idx
= I40E_QINT_TQCTL(qid
);
616 itr_idx
= vvm
->txitr_idx
;
626 /* Terminate the link list */
628 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT
) |
629 (0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT
) |
630 BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT
) |
631 (itr_idx
<< I40E_QINT_RQCTL_ITR_INDX_SHIFT
);
632 I40E_WRITE_REG(hw
, reg_idx
, reg
);
635 I40E_WRITE_FLUSH(hw
);
639 i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf
*vf
,
640 uint8_t *msg
, uint16_t msglen
,
643 int ret
= I40E_SUCCESS
;
644 struct i40e_pf
*pf
= vf
->pf
;
645 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
646 struct virtchnl_irq_map_info
*irqmap
=
647 (struct virtchnl_irq_map_info
*)msg
;
648 struct virtchnl_vector_map
*map
;
650 uint16_t vector_id
, itr_idx
;
651 unsigned long qbit_max
;
654 i40e_pf_host_send_msg_to_vf(
656 VIRTCHNL_OP_CONFIG_IRQ_MAP
,
657 I40E_NOT_SUPPORTED
, NULL
, 0);
661 if (msg
== NULL
|| msglen
< sizeof(struct virtchnl_irq_map_info
)) {
662 PMD_DRV_LOG(ERR
, "buffer too short");
663 ret
= I40E_ERR_PARAM
;
667 /* PF host will support both DPDK VF or Linux VF driver, identify by
668 * number of vectors requested.
671 /* DPDK VF only requires single vector */
672 if (irqmap
->num_vectors
== 1) {
673 /* This MSIX intr store the intr in VF range */
674 vf
->vsi
->msix_intr
= irqmap
->vecmap
[0].vector_id
;
675 vf
->vsi
->nb_msix
= irqmap
->num_vectors
;
676 vf
->vsi
->nb_used_qps
= vf
->vsi
->nb_qps
;
677 itr_idx
= irqmap
->vecmap
[0].rxitr_idx
;
679 /* Don't care how the TX/RX queue mapping with this vector.
680 * Link all VF RX queues together. Only did mapping work.
681 * VF can disable/enable the intr by itself.
683 i40e_vsi_queues_bind_intr(vf
->vsi
, itr_idx
);
687 /* Then, it's Linux VF driver */
688 qbit_max
= 1 << pf
->vf_nb_qp_max
;
689 for (i
= 0; i
< irqmap
->num_vectors
; i
++) {
690 map
= &irqmap
->vecmap
[i
];
692 vector_id
= map
->vector_id
;
693 /* validate msg params */
694 if (vector_id
>= hw
->func_caps
.num_msix_vectors_vf
) {
695 ret
= I40E_ERR_PARAM
;
699 if ((map
->rxq_map
< qbit_max
) && (map
->txq_map
< qbit_max
)) {
700 i40e_pf_config_irq_link_list(vf
, map
);
702 /* configured queue size excceed limit */
703 ret
= I40E_ERR_PARAM
;
709 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_CONFIG_IRQ_MAP
,
716 i40e_pf_host_switch_queues(struct i40e_pf_vf
*vf
,
717 struct virtchnl_queue_select
*qsel
,
720 int ret
= I40E_SUCCESS
;
722 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
723 uint16_t baseq
= vf
->vsi
->base_queue
;
725 if (qsel
->rx_queues
+ qsel
->tx_queues
== 0)
726 return I40E_ERR_PARAM
;
728 /* always enable RX first and disable last */
729 /* Enable RX if it's enable */
731 for (i
= 0; i
< I40E_MAX_QP_NUM_PER_VF
; i
++)
732 if (qsel
->rx_queues
& (1 << i
)) {
733 ret
= i40e_switch_rx_queue(hw
, baseq
+ i
, on
);
734 if (ret
!= I40E_SUCCESS
)
739 /* Enable/Disable TX */
740 for (i
= 0; i
< I40E_MAX_QP_NUM_PER_VF
; i
++)
741 if (qsel
->tx_queues
& (1 << i
)) {
742 ret
= i40e_switch_tx_queue(hw
, baseq
+ i
, on
);
743 if (ret
!= I40E_SUCCESS
)
747 /* disable RX last if it's disable */
750 for (i
= 0; i
< I40E_MAX_QP_NUM_PER_VF
; i
++)
751 if (qsel
->rx_queues
& (1 << i
)) {
752 ret
= i40e_switch_rx_queue(hw
, baseq
+ i
, on
);
753 if (ret
!= I40E_SUCCESS
)
762 i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf
*vf
,
766 int ret
= I40E_SUCCESS
;
767 struct virtchnl_queue_select
*q_sel
=
768 (struct virtchnl_queue_select
*)msg
;
770 if (msg
== NULL
|| msglen
!= sizeof(*q_sel
)) {
771 ret
= I40E_ERR_PARAM
;
774 ret
= i40e_pf_host_switch_queues(vf
, q_sel
, true);
777 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_ENABLE_QUEUES
,
784 i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf
*vf
,
789 int ret
= I40E_SUCCESS
;
790 struct virtchnl_queue_select
*q_sel
=
791 (struct virtchnl_queue_select
*)msg
;
794 i40e_pf_host_send_msg_to_vf(
796 VIRTCHNL_OP_DISABLE_QUEUES
,
797 I40E_NOT_SUPPORTED
, NULL
, 0);
801 if (msg
== NULL
|| msglen
!= sizeof(*q_sel
)) {
802 ret
= I40E_ERR_PARAM
;
805 ret
= i40e_pf_host_switch_queues(vf
, q_sel
, false);
808 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_DISABLE_QUEUES
,
816 i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf
*vf
,
821 int ret
= I40E_SUCCESS
;
822 struct virtchnl_ether_addr_list
*addr_list
=
823 (struct virtchnl_ether_addr_list
*)msg
;
824 struct i40e_mac_filter_info filter
;
826 struct rte_ether_addr
*mac
;
829 i40e_pf_host_send_msg_to_vf(
831 VIRTCHNL_OP_ADD_ETH_ADDR
,
832 I40E_NOT_SUPPORTED
, NULL
, 0);
836 memset(&filter
, 0 , sizeof(struct i40e_mac_filter_info
));
838 if (msg
== NULL
|| msglen
<= sizeof(*addr_list
)) {
839 PMD_DRV_LOG(ERR
, "add_ether_address argument too short");
840 ret
= I40E_ERR_PARAM
;
844 for (i
= 0; i
< addr_list
->num_elements
; i
++) {
845 mac
= (struct rte_ether_addr
*)(addr_list
->list
[i
].addr
);
846 rte_memcpy(&filter
.mac_addr
, mac
, RTE_ETHER_ADDR_LEN
);
847 filter
.filter_type
= RTE_MACVLAN_PERFECT_MATCH
;
848 if (rte_is_zero_ether_addr(mac
) ||
849 i40e_vsi_add_mac(vf
->vsi
, &filter
)) {
850 ret
= I40E_ERR_INVALID_MAC_ADDR
;
856 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_ADD_ETH_ADDR
,
863 i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf
*vf
,
868 int ret
= I40E_SUCCESS
;
869 struct virtchnl_ether_addr_list
*addr_list
=
870 (struct virtchnl_ether_addr_list
*)msg
;
872 struct rte_ether_addr
*mac
;
875 i40e_pf_host_send_msg_to_vf(
877 VIRTCHNL_OP_DEL_ETH_ADDR
,
878 I40E_NOT_SUPPORTED
, NULL
, 0);
882 if (msg
== NULL
|| msglen
<= sizeof(*addr_list
)) {
883 PMD_DRV_LOG(ERR
, "delete_ether_address argument too short");
884 ret
= I40E_ERR_PARAM
;
888 for (i
= 0; i
< addr_list
->num_elements
; i
++) {
889 mac
= (struct rte_ether_addr
*)(addr_list
->list
[i
].addr
);
890 if (rte_is_zero_ether_addr(mac
) ||
891 i40e_vsi_delete_mac(vf
->vsi
, mac
)) {
892 ret
= I40E_ERR_INVALID_MAC_ADDR
;
898 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_DEL_ETH_ADDR
,
905 i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf
*vf
,
906 uint8_t *msg
, uint16_t msglen
,
909 int ret
= I40E_SUCCESS
;
910 struct virtchnl_vlan_filter_list
*vlan_filter_list
=
911 (struct virtchnl_vlan_filter_list
*)msg
;
916 i40e_pf_host_send_msg_to_vf(
918 VIRTCHNL_OP_ADD_VLAN
,
919 I40E_NOT_SUPPORTED
, NULL
, 0);
923 if (msg
== NULL
|| msglen
<= sizeof(*vlan_filter_list
)) {
924 PMD_DRV_LOG(ERR
, "add_vlan argument too short");
925 ret
= I40E_ERR_PARAM
;
929 vid
= vlan_filter_list
->vlan_id
;
931 for (i
= 0; i
< vlan_filter_list
->num_elements
; i
++) {
932 ret
= i40e_vsi_add_vlan(vf
->vsi
, vid
[i
]);
933 if(ret
!= I40E_SUCCESS
)
938 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_ADD_VLAN
,
945 i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf
*vf
,
950 int ret
= I40E_SUCCESS
;
951 struct virtchnl_vlan_filter_list
*vlan_filter_list
=
952 (struct virtchnl_vlan_filter_list
*)msg
;
957 i40e_pf_host_send_msg_to_vf(
959 VIRTCHNL_OP_DEL_VLAN
,
960 I40E_NOT_SUPPORTED
, NULL
, 0);
964 if (msg
== NULL
|| msglen
<= sizeof(*vlan_filter_list
)) {
965 PMD_DRV_LOG(ERR
, "delete_vlan argument too short");
966 ret
= I40E_ERR_PARAM
;
970 vid
= vlan_filter_list
->vlan_id
;
971 for (i
= 0; i
< vlan_filter_list
->num_elements
; i
++) {
972 ret
= i40e_vsi_delete_vlan(vf
->vsi
, vid
[i
]);
973 if(ret
!= I40E_SUCCESS
)
978 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_DEL_VLAN
,
985 i40e_pf_host_process_cmd_config_promisc_mode(
986 struct i40e_pf_vf
*vf
,
991 int ret
= I40E_SUCCESS
;
992 struct virtchnl_promisc_info
*promisc
=
993 (struct virtchnl_promisc_info
*)msg
;
994 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
995 bool unicast
= FALSE
, multicast
= FALSE
;
998 i40e_pf_host_send_msg_to_vf(
1000 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE
,
1001 I40E_NOT_SUPPORTED
, NULL
, 0);
1005 if (msg
== NULL
|| msglen
!= sizeof(*promisc
)) {
1006 ret
= I40E_ERR_PARAM
;
1010 if (promisc
->flags
& FLAG_VF_UNICAST_PROMISC
)
1012 ret
= i40e_aq_set_vsi_unicast_promiscuous(hw
,
1013 vf
->vsi
->seid
, unicast
, NULL
, true);
1014 if (ret
!= I40E_SUCCESS
)
1017 if (promisc
->flags
& FLAG_VF_MULTICAST_PROMISC
)
1019 ret
= i40e_aq_set_vsi_multicast_promiscuous(hw
, vf
->vsi
->seid
,
1023 i40e_pf_host_send_msg_to_vf(vf
,
1024 VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE
, ret
, NULL
, 0);
1030 i40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf
*vf
, bool b_op
)
1032 i40e_update_vsi_stats(vf
->vsi
);
1035 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_GET_STATS
,
1037 (uint8_t *)&vf
->vsi
->eth_stats
,
1038 sizeof(vf
->vsi
->eth_stats
));
1040 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_GET_STATS
,
1042 (uint8_t *)&vf
->vsi
->eth_stats
,
1043 sizeof(vf
->vsi
->eth_stats
));
1045 return I40E_SUCCESS
;
1049 i40e_pf_host_process_cmd_enable_vlan_strip(struct i40e_pf_vf
*vf
, bool b_op
)
1051 int ret
= I40E_SUCCESS
;
1054 i40e_pf_host_send_msg_to_vf(
1056 VIRTCHNL_OP_ENABLE_VLAN_STRIPPING
,
1057 I40E_NOT_SUPPORTED
, NULL
, 0);
1061 ret
= i40e_vsi_config_vlan_stripping(vf
->vsi
, TRUE
);
1063 PMD_DRV_LOG(ERR
, "Failed to enable vlan stripping");
1065 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_ENABLE_VLAN_STRIPPING
,
1072 i40e_pf_host_process_cmd_disable_vlan_strip(struct i40e_pf_vf
*vf
, bool b_op
)
1074 int ret
= I40E_SUCCESS
;
1077 i40e_pf_host_send_msg_to_vf(
1079 VIRTCHNL_OP_DISABLE_VLAN_STRIPPING
,
1080 I40E_NOT_SUPPORTED
, NULL
, 0);
1084 ret
= i40e_vsi_config_vlan_stripping(vf
->vsi
, FALSE
);
1086 PMD_DRV_LOG(ERR
, "Failed to disable vlan stripping");
1088 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_DISABLE_VLAN_STRIPPING
,
1095 i40e_pf_host_process_cmd_set_rss_lut(struct i40e_pf_vf
*vf
,
1100 struct virtchnl_rss_lut
*rss_lut
= (struct virtchnl_rss_lut
*)msg
;
1102 int ret
= I40E_SUCCESS
;
1105 i40e_pf_host_send_msg_to_vf(
1107 VIRTCHNL_OP_CONFIG_RSS_LUT
,
1108 I40E_NOT_SUPPORTED
, NULL
, 0);
1112 if (!msg
|| msglen
<= sizeof(struct virtchnl_rss_lut
)) {
1113 PMD_DRV_LOG(ERR
, "set_rss_lut argument too short");
1114 ret
= I40E_ERR_PARAM
;
1117 valid_len
= sizeof(struct virtchnl_rss_lut
) + rss_lut
->lut_entries
- 1;
1118 if (msglen
< valid_len
) {
1119 PMD_DRV_LOG(ERR
, "set_rss_lut length mismatch");
1120 ret
= I40E_ERR_PARAM
;
1124 ret
= i40e_set_rss_lut(vf
->vsi
, rss_lut
->lut
, rss_lut
->lut_entries
);
1127 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_CONFIG_RSS_LUT
,
1134 i40e_pf_host_process_cmd_set_rss_key(struct i40e_pf_vf
*vf
,
1139 struct virtchnl_rss_key
*rss_key
= (struct virtchnl_rss_key
*)msg
;
1141 int ret
= I40E_SUCCESS
;
1144 i40e_pf_host_send_msg_to_vf(
1146 VIRTCHNL_OP_DEL_VLAN
,
1147 VIRTCHNL_OP_CONFIG_RSS_KEY
, NULL
, 0);
1151 if (!msg
|| msglen
<= sizeof(struct virtchnl_rss_key
)) {
1152 PMD_DRV_LOG(ERR
, "set_rss_key argument too short");
1153 ret
= I40E_ERR_PARAM
;
1156 valid_len
= sizeof(struct virtchnl_rss_key
) + rss_key
->key_len
- 1;
1157 if (msglen
< valid_len
) {
1158 PMD_DRV_LOG(ERR
, "set_rss_key length mismatch");
1159 ret
= I40E_ERR_PARAM
;
1163 ret
= i40e_set_rss_key(vf
->vsi
, rss_key
->key
, rss_key
->key_len
);
1166 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_CONFIG_RSS_KEY
,
1173 i40e_notify_vf_link_status(struct rte_eth_dev
*dev
, struct i40e_pf_vf
*vf
)
1175 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
1176 struct virtchnl_pf_event event
;
1177 uint16_t vf_id
= vf
->vf_idx
;
1178 uint32_t tval
, rval
;
1180 event
.event
= VIRTCHNL_EVENT_LINK_CHANGE
;
1181 event
.event_data
.link_event
.link_status
=
1182 dev
->data
->dev_link
.link_status
;
1184 /* need to convert the ETH_SPEED_xxx into VIRTCHNL_LINK_SPEED_xxx */
1185 switch (dev
->data
->dev_link
.link_speed
) {
1186 case ETH_SPEED_NUM_100M
:
1187 event
.event_data
.link_event
.link_speed
= VIRTCHNL_LINK_SPEED_100MB
;
1189 case ETH_SPEED_NUM_1G
:
1190 event
.event_data
.link_event
.link_speed
= VIRTCHNL_LINK_SPEED_1GB
;
1192 case ETH_SPEED_NUM_10G
:
1193 event
.event_data
.link_event
.link_speed
= VIRTCHNL_LINK_SPEED_10GB
;
1195 case ETH_SPEED_NUM_20G
:
1196 event
.event_data
.link_event
.link_speed
= VIRTCHNL_LINK_SPEED_20GB
;
1198 case ETH_SPEED_NUM_25G
:
1199 event
.event_data
.link_event
.link_speed
= VIRTCHNL_LINK_SPEED_25GB
;
1201 case ETH_SPEED_NUM_40G
:
1202 event
.event_data
.link_event
.link_speed
= VIRTCHNL_LINK_SPEED_40GB
;
1205 event
.event_data
.link_event
.link_speed
=
1206 VIRTCHNL_LINK_SPEED_UNKNOWN
;
1210 tval
= I40E_READ_REG(hw
, I40E_VF_ATQLEN(vf_id
));
1211 rval
= I40E_READ_REG(hw
, I40E_VF_ARQLEN(vf_id
));
1213 if (tval
& I40E_VF_ATQLEN_ATQLEN_MASK
||
1214 tval
& I40E_VF_ATQLEN_ATQENABLE_MASK
||
1215 rval
& I40E_VF_ARQLEN_ARQLEN_MASK
||
1216 rval
& I40E_VF_ARQLEN_ARQENABLE_MASK
)
1217 i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_EVENT
,
1218 I40E_SUCCESS
, (uint8_t *)&event
, sizeof(event
));
1222 * i40e_vc_notify_vf_reset
1223 * @vf: pointer to the VF structure
1225 * indicate a pending reset to the given VF
1228 i40e_vc_notify_vf_reset(struct i40e_pf_vf
*vf
)
1230 struct i40e_hw
*hw
= I40E_PF_TO_HW(vf
->pf
);
1231 struct virtchnl_pf_event pfe
;
1233 uint16_t vf_id
= vf
->vf_idx
;
1235 abs_vf_id
= vf_id
+ hw
->func_caps
.vf_base_id
;
1236 pfe
.event
= VIRTCHNL_EVENT_RESET_IMPENDING
;
1237 pfe
.severity
= PF_EVENT_SEVERITY_CERTAIN_DOOM
;
1238 i40e_aq_send_msg_to_vf(hw
, abs_vf_id
, VIRTCHNL_OP_EVENT
, 0, (u8
*)&pfe
,
1239 sizeof(struct virtchnl_pf_event
), NULL
);
1243 i40e_pf_host_process_cmd_request_queues(struct i40e_pf_vf
*vf
, uint8_t *msg
)
1245 struct virtchnl_vf_res_request
*vfres
=
1246 (struct virtchnl_vf_res_request
*)msg
;
1248 uint32_t req_pairs
= vfres
->num_queue_pairs
;
1249 uint32_t cur_pairs
= vf
->vsi
->nb_used_qps
;
1253 if (!rte_is_power_of_2(req_pairs
))
1254 req_pairs
= i40e_align_floor(req_pairs
) << 1;
1256 if (req_pairs
== 0) {
1257 PMD_DRV_LOG(ERR
, "VF %d tried to request 0 queues. Ignoring.\n",
1259 } else if (req_pairs
> I40E_MAX_QP_NUM_PER_VF
) {
1261 "VF %d tried to request more than %d queues.\n",
1263 I40E_MAX_QP_NUM_PER_VF
);
1264 vfres
->num_queue_pairs
= I40E_MAX_QP_NUM_PER_VF
;
1265 } else if (req_pairs
> cur_pairs
+ pf
->qp_pool
.num_free
) {
1266 PMD_DRV_LOG(ERR
, "VF %d requested %d queues (rounded to %d) "
1267 "but only %d available\n",
1269 vfres
->num_queue_pairs
,
1271 cur_pairs
+ pf
->qp_pool
.num_free
);
1272 vfres
->num_queue_pairs
= i40e_align_floor(pf
->qp_pool
.num_free
+
1275 i40e_vc_notify_vf_reset(vf
);
1276 vf
->vsi
->nb_qps
= req_pairs
;
1277 pf
->vf_nb_qps
= req_pairs
;
1278 i40e_pf_host_process_cmd_reset_vf(vf
);
1283 return i40e_pf_host_send_msg_to_vf(vf
, VIRTCHNL_OP_REQUEST_QUEUES
, 0,
1284 (u8
*)vfres
, sizeof(*vfres
));
1288 i40e_pf_host_handle_vf_msg(struct rte_eth_dev
*dev
,
1289 uint16_t abs_vf_id
, uint32_t opcode
,
1290 __rte_unused
uint32_t retval
,
1294 struct i40e_pf
*pf
= I40E_DEV_PRIVATE_TO_PF(dev
->data
->dev_private
);
1295 struct i40e_hw
*hw
= I40E_DEV_PRIVATE_TO_HW(dev
->data
->dev_private
);
1296 struct i40e_pf_vf
*vf
;
1297 /* AdminQ will pass absolute VF id, transfer to internal vf id */
1298 uint16_t vf_id
= abs_vf_id
- hw
->func_caps
.vf_base_id
;
1299 struct rte_pmd_i40e_mb_event_param ret_param
;
1300 uint64_t first_cycle
, cur_cycle
;
1304 if (vf_id
> pf
->vf_num
- 1 || !pf
->vfs
) {
1305 PMD_DRV_LOG(ERR
, "invalid argument");
1309 vf
= &pf
->vfs
[vf_id
];
1311 cur_cycle
= rte_get_timer_cycles();
1313 /* if the VF being blocked, ignore the message and return */
1314 if (cur_cycle
< vf
->ignore_end_cycle
)
1318 PMD_DRV_LOG(ERR
, "NO VSI associated with VF found");
1319 i40e_pf_host_send_msg_to_vf(vf
, opcode
,
1320 I40E_ERR_NO_AVAILABLE_VSI
, NULL
, 0);
1324 /* perform basic checks on the msg */
1325 ret
= virtchnl_vc_validate_vf_msg(&vf
->version
, opcode
, msg
, msglen
);
1327 /* perform additional checks specific to this driver */
1328 if (opcode
== VIRTCHNL_OP_CONFIG_RSS_KEY
) {
1329 struct virtchnl_rss_key
*vrk
= (struct virtchnl_rss_key
*)msg
;
1331 if (vrk
->key_len
!= ((I40E_PFQF_HKEY_MAX_INDEX
+ 1) * 4))
1332 ret
= VIRTCHNL_ERR_PARAM
;
1333 } else if (opcode
== VIRTCHNL_OP_CONFIG_RSS_LUT
) {
1334 struct virtchnl_rss_lut
*vrl
= (struct virtchnl_rss_lut
*)msg
;
1336 if (vrl
->lut_entries
!= ((I40E_VFQF_HLUT1_MAX_INDEX
+ 1) * 4))
1337 ret
= VIRTCHNL_ERR_PARAM
;
1341 PMD_DRV_LOG(ERR
, "Invalid message from VF %u, opcode %u, len %u",
1342 vf_id
, opcode
, msglen
);
1343 i40e_pf_host_send_msg_to_vf(vf
, opcode
,
1344 I40E_ERR_PARAM
, NULL
, 0);
1349 * initialise structure to send to user application
1350 * will return response from user in retval field
1352 ret_param
.retval
= RTE_PMD_I40E_MB_EVENT_PROCEED
;
1353 ret_param
.vfid
= vf_id
;
1354 ret_param
.msg_type
= opcode
;
1355 ret_param
.msg
= (void *)msg
;
1356 ret_param
.msglen
= msglen
;
1359 * Ask user application if we're allowed to perform those functions.
1360 * If we get ret_param.retval == RTE_PMD_I40E_MB_EVENT_PROCEED,
1361 * then business as usual.
1362 * If RTE_PMD_I40E_MB_EVENT_NOOP_ACK or RTE_PMD_I40E_MB_EVENT_NOOP_NACK,
1363 * do nothing and send not_supported to VF. As PF must send a response
1364 * to VF and ACK/NACK is not defined.
1366 _rte_eth_dev_callback_process(dev
, RTE_ETH_EVENT_VF_MBOX
, &ret_param
);
1367 if (ret_param
.retval
!= RTE_PMD_I40E_MB_EVENT_PROCEED
) {
1368 PMD_DRV_LOG(WARNING
, "VF to PF message(%d) is not permitted!",
1374 case VIRTCHNL_OP_VERSION
:
1375 PMD_DRV_LOG(INFO
, "OP_VERSION received");
1376 i40e_pf_host_process_cmd_version(vf
, msg
, b_op
);
1378 case VIRTCHNL_OP_RESET_VF
:
1379 PMD_DRV_LOG(INFO
, "OP_RESET_VF received");
1380 i40e_pf_host_process_cmd_reset_vf(vf
);
1382 case VIRTCHNL_OP_GET_VF_RESOURCES
:
1383 PMD_DRV_LOG(INFO
, "OP_GET_VF_RESOURCES received");
1384 i40e_pf_host_process_cmd_get_vf_resource(vf
, msg
, b_op
);
1386 case VIRTCHNL_OP_CONFIG_VSI_QUEUES
:
1387 PMD_DRV_LOG(INFO
, "OP_CONFIG_VSI_QUEUES received");
1388 i40e_pf_host_process_cmd_config_vsi_queues(vf
, msg
,
1391 case VIRTCHNL_OP_CONFIG_IRQ_MAP
:
1392 PMD_DRV_LOG(INFO
, "OP_CONFIG_IRQ_MAP received");
1393 i40e_pf_host_process_cmd_config_irq_map(vf
, msg
, msglen
, b_op
);
1395 case VIRTCHNL_OP_ENABLE_QUEUES
:
1396 PMD_DRV_LOG(INFO
, "OP_ENABLE_QUEUES received");
1398 i40e_pf_host_process_cmd_enable_queues(vf
, msg
, msglen
);
1399 i40e_notify_vf_link_status(dev
, vf
);
1401 i40e_pf_host_send_msg_to_vf(
1402 vf
, VIRTCHNL_OP_ENABLE_QUEUES
,
1403 I40E_NOT_SUPPORTED
, NULL
, 0);
1406 case VIRTCHNL_OP_DISABLE_QUEUES
:
1407 PMD_DRV_LOG(INFO
, "OP_DISABLE_QUEUE received");
1408 i40e_pf_host_process_cmd_disable_queues(vf
, msg
, msglen
, b_op
);
1410 case VIRTCHNL_OP_ADD_ETH_ADDR
:
1411 PMD_DRV_LOG(INFO
, "OP_ADD_ETHER_ADDRESS received");
1412 i40e_pf_host_process_cmd_add_ether_address(vf
, msg
,
1415 case VIRTCHNL_OP_DEL_ETH_ADDR
:
1416 PMD_DRV_LOG(INFO
, "OP_DEL_ETHER_ADDRESS received");
1417 i40e_pf_host_process_cmd_del_ether_address(vf
, msg
,
1420 case VIRTCHNL_OP_ADD_VLAN
:
1421 PMD_DRV_LOG(INFO
, "OP_ADD_VLAN received");
1422 i40e_pf_host_process_cmd_add_vlan(vf
, msg
, msglen
, b_op
);
1424 case VIRTCHNL_OP_DEL_VLAN
:
1425 PMD_DRV_LOG(INFO
, "OP_DEL_VLAN received");
1426 i40e_pf_host_process_cmd_del_vlan(vf
, msg
, msglen
, b_op
);
1428 case VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE
:
1429 PMD_DRV_LOG(INFO
, "OP_CONFIG_PROMISCUOUS_MODE received");
1430 i40e_pf_host_process_cmd_config_promisc_mode(vf
, msg
,
1433 case VIRTCHNL_OP_GET_STATS
:
1434 PMD_DRV_LOG(INFO
, "OP_GET_STATS received");
1435 i40e_pf_host_process_cmd_get_stats(vf
, b_op
);
1437 case VIRTCHNL_OP_ENABLE_VLAN_STRIPPING
:
1438 PMD_DRV_LOG(INFO
, "OP_ENABLE_VLAN_STRIPPING received");
1439 i40e_pf_host_process_cmd_enable_vlan_strip(vf
, b_op
);
1441 case VIRTCHNL_OP_DISABLE_VLAN_STRIPPING
:
1442 PMD_DRV_LOG(INFO
, "OP_DISABLE_VLAN_STRIPPING received");
1443 i40e_pf_host_process_cmd_disable_vlan_strip(vf
, b_op
);
1445 case VIRTCHNL_OP_CONFIG_RSS_LUT
:
1446 PMD_DRV_LOG(INFO
, "OP_CONFIG_RSS_LUT received");
1447 i40e_pf_host_process_cmd_set_rss_lut(vf
, msg
, msglen
, b_op
);
1449 case VIRTCHNL_OP_CONFIG_RSS_KEY
:
1450 PMD_DRV_LOG(INFO
, "OP_CONFIG_RSS_KEY received");
1451 i40e_pf_host_process_cmd_set_rss_key(vf
, msg
, msglen
, b_op
);
1453 case VIRTCHNL_OP_REQUEST_QUEUES
:
1454 PMD_DRV_LOG(INFO
, "OP_REQUEST_QUEUES received");
1455 i40e_pf_host_process_cmd_request_queues(vf
, msg
);
1458 /* Don't add command supported below, which will
1459 * return an error code.
1462 PMD_DRV_LOG(ERR
, "%u received, not supported", opcode
);
1463 i40e_pf_host_send_msg_to_vf(vf
, opcode
, I40E_ERR_PARAM
,
1469 /* if message validation not enabled */
1470 if (!pf
->vf_msg_cfg
.max_msg
)
1473 /* store current cycle */
1474 vf
->msg_timestamps
[vf
->msg_index
++] = cur_cycle
;
1475 vf
->msg_index
%= pf
->vf_msg_cfg
.max_msg
;
1477 /* read the timestamp of earliest message */
1478 first_cycle
= vf
->msg_timestamps
[vf
->msg_index
];
1481 * If the time span from the arrival time of first message to
1482 * the arrival time of current message smaller than `period`,
1483 * that mean too much message in this statistic period.
1485 if (first_cycle
&& cur_cycle
< first_cycle
+
1486 (uint64_t)pf
->vf_msg_cfg
.period
* rte_get_timer_hz()) {
1487 PMD_DRV_LOG(WARNING
, "VF %u too much messages(%u in %u"
1488 " seconds),\n\tany new message from which"
1489 " will be ignored during next %u seconds!",
1490 vf_id
, pf
->vf_msg_cfg
.max_msg
,
1491 (uint32_t)((cur_cycle
- first_cycle
+
1492 rte_get_timer_hz() - 1) / rte_get_timer_hz()),
1493 pf
->vf_msg_cfg
.ignore_second
);
1494 vf
->ignore_end_cycle
= rte_get_timer_cycles() +
1495 pf
->vf_msg_cfg
.ignore_second
*
1501 i40e_pf_host_init(struct rte_eth_dev
*dev
)
1503 struct i40e_pf
*pf
= I40E_DEV_PRIVATE_TO_PF(dev
->data
->dev_private
);
1504 struct i40e_hw
*hw
= I40E_PF_TO_HW(pf
);
1509 PMD_INIT_FUNC_TRACE();
1512 * return if SRIOV not enabled, VF number not configured or
1513 * no queue assigned.
1515 if(!hw
->func_caps
.sr_iov_1_1
|| pf
->vf_num
== 0 || pf
->vf_nb_qps
== 0)
1516 return I40E_SUCCESS
;
1518 /* Allocate memory to store VF structure */
1519 pf
->vfs
= rte_zmalloc("i40e_pf_vf",sizeof(*pf
->vfs
) * pf
->vf_num
, 0);
1523 /* Disable irq0 for VFR event */
1524 i40e_pf_disable_irq0(hw
);
1526 /* Disable VF link status interrupt */
1527 val
= I40E_READ_REG(hw
, I40E_PFGEN_PORTMDIO_NUM
);
1528 val
&= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK
;
1529 I40E_WRITE_REG(hw
, I40E_PFGEN_PORTMDIO_NUM
, val
);
1530 I40E_WRITE_FLUSH(hw
);
1532 /* calculate the memory size for storing timestamp of messages */
1533 size
= pf
->vf_msg_cfg
.max_msg
* sizeof(uint64_t);
1535 for (i
= 0; i
< pf
->vf_num
; i
++) {
1537 pf
->vfs
[i
].state
= I40E_VF_INACTIVE
;
1538 pf
->vfs
[i
].vf_idx
= i
;
1541 /* allocate memory for store timestamp of messages */
1542 pf
->vfs
[i
].msg_timestamps
=
1543 rte_zmalloc("i40e_pf_vf", size
, 0);
1544 if (pf
->vfs
[i
].msg_timestamps
== NULL
) {
1550 ret
= i40e_pf_host_vf_reset(&pf
->vfs
[i
], 0);
1551 if (ret
!= I40E_SUCCESS
)
1555 RTE_ETH_DEV_SRIOV(dev
).active
= pf
->vf_num
;
1557 i40e_pf_enable_irq0(hw
);
1559 return I40E_SUCCESS
;
1563 rte_free(pf
->vfs
[i
].msg_timestamps
);
1565 i40e_pf_enable_irq0(hw
);
1571 i40e_pf_host_uninit(struct rte_eth_dev
*dev
)
1573 struct i40e_pf
*pf
= I40E_DEV_PRIVATE_TO_PF(dev
->data
->dev_private
);
1574 struct i40e_hw
*hw
= I40E_PF_TO_HW(pf
);
1578 PMD_INIT_FUNC_TRACE();
1581 * return if SRIOV not enabled, VF number not configured or
1582 * no queue assigned.
1584 if ((!hw
->func_caps
.sr_iov_1_1
) ||
1585 (pf
->vf_num
== 0) ||
1586 (pf
->vf_nb_qps
== 0))
1587 return I40E_SUCCESS
;
1589 /* free memory for store timestamp of messages */
1590 for (i
= 0; i
< pf
->vf_num
; i
++)
1591 rte_free(pf
->vfs
[i
].msg_timestamps
);
1593 /* free memory to store VF structure */
1597 /* Disable irq0 for VFR event */
1598 i40e_pf_disable_irq0(hw
);
1600 /* Disable VF link status interrupt */
1601 val
= I40E_READ_REG(hw
, I40E_PFGEN_PORTMDIO_NUM
);
1602 val
&= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK
;
1603 I40E_WRITE_REG(hw
, I40E_PFGEN_PORTMDIO_NUM
, val
);
1604 I40E_WRITE_FLUSH(hw
);
1606 return I40E_SUCCESS
;