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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / i40e / i40e_rxtx.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2016 Intel Corporation
3 */
4
5 #include <stdio.h>
6 #include <stdlib.h>
7 #include <string.h>
8 #include <errno.h>
9 #include <stdint.h>
10 #include <stdarg.h>
11 #include <unistd.h>
12 #include <inttypes.h>
13 #include <sys/queue.h>
14
15 #include <rte_string_fns.h>
16 #include <rte_memzone.h>
17 #include <rte_mbuf.h>
18 #include <rte_malloc.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_tcp.h>
22 #include <rte_sctp.h>
23 #include <rte_udp.h>
24 #include <rte_ip.h>
25 #include <rte_net.h>
26
27 #include "i40e_logs.h"
28 #include "base/i40e_prototype.h"
29 #include "base/i40e_type.h"
30 #include "i40e_ethdev.h"
31 #include "i40e_rxtx.h"
32
33 #define DEFAULT_TX_RS_THRESH 32
34 #define DEFAULT_TX_FREE_THRESH 32
35
36 #define I40E_TX_MAX_BURST 32
37
38 #define I40E_DMA_MEM_ALIGN 4096
39
40 /* Base address of the HW descriptor ring should be 128B aligned. */
41 #define I40E_RING_BASE_ALIGN 128
42
43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45 #ifdef RTE_LIBRTE_IEEE1588
46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
47 #else
48 #define I40E_TX_IEEE1588_TMST 0
49 #endif
50
51 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
52 PKT_TX_IP_CKSUM | \
53 PKT_TX_L4_MASK | \
54 PKT_TX_TCP_SEG | \
55 PKT_TX_OUTER_IP_CKSUM)
56
57 #define I40E_TX_OFFLOAD_MASK ( \
58 PKT_TX_IP_CKSUM | \
59 PKT_TX_L4_MASK | \
60 PKT_TX_OUTER_IP_CKSUM | \
61 PKT_TX_TCP_SEG | \
62 PKT_TX_QINQ_PKT | \
63 PKT_TX_VLAN_PKT | \
64 PKT_TX_TUNNEL_MASK | \
65 I40E_TX_IEEE1588_TMST)
66
67 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
68 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
69
70 static inline void
71 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
72 {
73 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
74 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
75 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
76 mb->vlan_tci =
77 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
78 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
79 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
80 } else {
81 mb->vlan_tci = 0;
82 }
83 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
84 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
85 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
86 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
87 mb->vlan_tci_outer = mb->vlan_tci;
88 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
89 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
90 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
91 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
92 } else {
93 mb->vlan_tci_outer = 0;
94 }
95 #endif
96 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
97 mb->vlan_tci, mb->vlan_tci_outer);
98 }
99
100 /* Translate the rx descriptor status to pkt flags */
101 static inline uint64_t
102 i40e_rxd_status_to_pkt_flags(uint64_t qword)
103 {
104 uint64_t flags;
105
106 /* Check if RSS_HASH */
107 flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
108 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
109 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
110
111 /* Check if FDIR Match */
112 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
113 PKT_RX_FDIR : 0);
114
115 return flags;
116 }
117
118 static inline uint64_t
119 i40e_rxd_error_to_pkt_flags(uint64_t qword)
120 {
121 uint64_t flags = 0;
122 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
123
124 #define I40E_RX_ERR_BITS 0x3f
125 if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
126 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
127 return flags;
128 }
129
130 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
131 flags |= PKT_RX_IP_CKSUM_BAD;
132 else
133 flags |= PKT_RX_IP_CKSUM_GOOD;
134
135 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
136 flags |= PKT_RX_L4_CKSUM_BAD;
137 else
138 flags |= PKT_RX_L4_CKSUM_GOOD;
139
140 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
141 flags |= PKT_RX_EIP_CKSUM_BAD;
142
143 return flags;
144 }
145
146 /* Function to check and set the ieee1588 timesync index and get the
147 * appropriate flags.
148 */
149 #ifdef RTE_LIBRTE_IEEE1588
150 static inline uint64_t
151 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
152 {
153 uint64_t pkt_flags = 0;
154 uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
155 | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
156 >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
157
158 if ((mb->packet_type & RTE_PTYPE_L2_MASK)
159 == RTE_PTYPE_L2_ETHER_TIMESYNC)
160 pkt_flags = PKT_RX_IEEE1588_PTP;
161 if (tsyn & 0x04) {
162 pkt_flags |= PKT_RX_IEEE1588_TMST;
163 mb->timesync = tsyn & 0x03;
164 }
165
166 return pkt_flags;
167 }
168 #endif
169
170 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
171 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
172 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
173 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
174 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
175
176 static inline uint64_t
177 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
178 {
179 uint64_t flags = 0;
180 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
181 uint16_t flexbh, flexbl;
182
183 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
184 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
185 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
186 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
187 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
188 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
189
190
191 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
192 mb->hash.fdir.hi =
193 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
194 flags |= PKT_RX_FDIR_ID;
195 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
196 mb->hash.fdir.hi =
197 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
198 flags |= PKT_RX_FDIR_FLX;
199 }
200 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
201 mb->hash.fdir.lo =
202 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
203 flags |= PKT_RX_FDIR_FLX;
204 }
205 #else
206 mb->hash.fdir.hi =
207 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
208 flags |= PKT_RX_FDIR_ID;
209 #endif
210 return flags;
211 }
212
213 static inline void
214 i40e_parse_tunneling_params(uint64_t ol_flags,
215 union i40e_tx_offload tx_offload,
216 uint32_t *cd_tunneling)
217 {
218 /* EIPT: External (outer) IP header type */
219 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
220 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
221 else if (ol_flags & PKT_TX_OUTER_IPV4)
222 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
223 else if (ol_flags & PKT_TX_OUTER_IPV6)
224 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
225
226 /* EIPLEN: External (outer) IP header length, in DWords */
227 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
228 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
229
230 /* L4TUNT: L4 Tunneling Type */
231 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
232 case PKT_TX_TUNNEL_IPIP:
233 /* for non UDP / GRE tunneling, set to 00b */
234 break;
235 case PKT_TX_TUNNEL_VXLAN:
236 case PKT_TX_TUNNEL_GENEVE:
237 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
238 break;
239 case PKT_TX_TUNNEL_GRE:
240 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
241 break;
242 default:
243 PMD_TX_LOG(ERR, "Tunnel type not supported");
244 return;
245 }
246
247 /* L4TUNLEN: L4 Tunneling Length, in Words
248 *
249 * We depend on app to set rte_mbuf.l2_len correctly.
250 * For IP in GRE it should be set to the length of the GRE
251 * header;
252 * for MAC in GRE or MAC in UDP it should be set to the length
253 * of the GRE or UDP headers plus the inner MAC up to including
254 * its last Ethertype.
255 */
256 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
257 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
258 }
259
260 static inline void
261 i40e_txd_enable_checksum(uint64_t ol_flags,
262 uint32_t *td_cmd,
263 uint32_t *td_offset,
264 union i40e_tx_offload tx_offload)
265 {
266 /* Set MACLEN */
267 if (ol_flags & PKT_TX_TUNNEL_MASK)
268 *td_offset |= (tx_offload.outer_l2_len >> 1)
269 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
270 else
271 *td_offset |= (tx_offload.l2_len >> 1)
272 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
273
274 /* Enable L3 checksum offloads */
275 if (ol_flags & PKT_TX_IP_CKSUM) {
276 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
277 *td_offset |= (tx_offload.l3_len >> 2)
278 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
279 } else if (ol_flags & PKT_TX_IPV4) {
280 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
281 *td_offset |= (tx_offload.l3_len >> 2)
282 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
283 } else if (ol_flags & PKT_TX_IPV6) {
284 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
285 *td_offset |= (tx_offload.l3_len >> 2)
286 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
287 }
288
289 if (ol_flags & PKT_TX_TCP_SEG) {
290 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
291 *td_offset |= (tx_offload.l4_len >> 2)
292 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
293 return;
294 }
295
296 /* Enable L4 checksum offloads */
297 switch (ol_flags & PKT_TX_L4_MASK) {
298 case PKT_TX_TCP_CKSUM:
299 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
300 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
301 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
302 break;
303 case PKT_TX_SCTP_CKSUM:
304 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
305 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
306 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
307 break;
308 case PKT_TX_UDP_CKSUM:
309 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
310 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
311 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
312 break;
313 default:
314 break;
315 }
316 }
317
318 /* Construct the tx flags */
319 static inline uint64_t
320 i40e_build_ctob(uint32_t td_cmd,
321 uint32_t td_offset,
322 unsigned int size,
323 uint32_t td_tag)
324 {
325 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
326 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
327 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
328 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
329 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
330 }
331
332 static inline int
333 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
334 {
335 struct i40e_tx_entry *sw_ring = txq->sw_ring;
336 volatile struct i40e_tx_desc *txd = txq->tx_ring;
337 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
338 uint16_t nb_tx_desc = txq->nb_tx_desc;
339 uint16_t desc_to_clean_to;
340 uint16_t nb_tx_to_clean;
341
342 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
343 if (desc_to_clean_to >= nb_tx_desc)
344 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
345
346 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
347 if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
348 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
349 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
350 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
351 "(port=%d queue=%d)", desc_to_clean_to,
352 txq->port_id, txq->queue_id);
353 return -1;
354 }
355
356 if (last_desc_cleaned > desc_to_clean_to)
357 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
358 desc_to_clean_to);
359 else
360 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
361 last_desc_cleaned);
362
363 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
364
365 txq->last_desc_cleaned = desc_to_clean_to;
366 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
367
368 return 0;
369 }
370
371 static inline int
372 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
373 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
374 #else
375 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
376 #endif
377 {
378 int ret = 0;
379
380 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
381 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
382 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
383 "rxq->rx_free_thresh=%d, "
384 "RTE_PMD_I40E_RX_MAX_BURST=%d",
385 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
386 ret = -EINVAL;
387 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
388 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
389 "rxq->rx_free_thresh=%d, "
390 "rxq->nb_rx_desc=%d",
391 rxq->rx_free_thresh, rxq->nb_rx_desc);
392 ret = -EINVAL;
393 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
394 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
395 "rxq->nb_rx_desc=%d, "
396 "rxq->rx_free_thresh=%d",
397 rxq->nb_rx_desc, rxq->rx_free_thresh);
398 ret = -EINVAL;
399 }
400 #else
401 ret = -EINVAL;
402 #endif
403
404 return ret;
405 }
406
407 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
408 #define I40E_LOOK_AHEAD 8
409 #if (I40E_LOOK_AHEAD != 8)
410 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
411 #endif
412 static inline int
413 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
414 {
415 volatile union i40e_rx_desc *rxdp;
416 struct i40e_rx_entry *rxep;
417 struct rte_mbuf *mb;
418 uint16_t pkt_len;
419 uint64_t qword1;
420 uint32_t rx_status;
421 int32_t s[I40E_LOOK_AHEAD], nb_dd;
422 int32_t i, j, nb_rx = 0;
423 uint64_t pkt_flags;
424 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
425
426 rxdp = &rxq->rx_ring[rxq->rx_tail];
427 rxep = &rxq->sw_ring[rxq->rx_tail];
428
429 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
430 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
431 I40E_RXD_QW1_STATUS_SHIFT;
432
433 /* Make sure there is at least 1 packet to receive */
434 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
435 return 0;
436
437 /**
438 * Scan LOOK_AHEAD descriptors at a time to determine which
439 * descriptors reference packets that are ready to be received.
440 */
441 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
442 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
443 /* Read desc statuses backwards to avoid race condition */
444 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
445 qword1 = rte_le_to_cpu_64(\
446 rxdp[j].wb.qword1.status_error_len);
447 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
448 I40E_RXD_QW1_STATUS_SHIFT;
449 }
450
451 rte_smp_rmb();
452
453 /* Compute how many status bits were set */
454 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
455 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
456
457 nb_rx += nb_dd;
458
459 /* Translate descriptor info to mbuf parameters */
460 for (j = 0; j < nb_dd; j++) {
461 mb = rxep[j].mbuf;
462 qword1 = rte_le_to_cpu_64(\
463 rxdp[j].wb.qword1.status_error_len);
464 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
465 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
466 mb->data_len = pkt_len;
467 mb->pkt_len = pkt_len;
468 mb->ol_flags = 0;
469 i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
470 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
471 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
472 mb->packet_type =
473 ptype_tbl[(uint8_t)((qword1 &
474 I40E_RXD_QW1_PTYPE_MASK) >>
475 I40E_RXD_QW1_PTYPE_SHIFT)];
476 if (pkt_flags & PKT_RX_RSS_HASH)
477 mb->hash.rss = rte_le_to_cpu_32(\
478 rxdp[j].wb.qword0.hi_dword.rss);
479 if (pkt_flags & PKT_RX_FDIR)
480 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
481
482 #ifdef RTE_LIBRTE_IEEE1588
483 pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
484 #endif
485 mb->ol_flags |= pkt_flags;
486
487 }
488
489 for (j = 0; j < I40E_LOOK_AHEAD; j++)
490 rxq->rx_stage[i + j] = rxep[j].mbuf;
491
492 if (nb_dd != I40E_LOOK_AHEAD)
493 break;
494 }
495
496 /* Clear software ring entries */
497 for (i = 0; i < nb_rx; i++)
498 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
499
500 return nb_rx;
501 }
502
503 static inline uint16_t
504 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
505 struct rte_mbuf **rx_pkts,
506 uint16_t nb_pkts)
507 {
508 uint16_t i;
509 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
510
511 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
512
513 for (i = 0; i < nb_pkts; i++)
514 rx_pkts[i] = stage[i];
515
516 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
517 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
518
519 return nb_pkts;
520 }
521
522 static inline int
523 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
524 {
525 volatile union i40e_rx_desc *rxdp;
526 struct i40e_rx_entry *rxep;
527 struct rte_mbuf *mb;
528 uint16_t alloc_idx, i;
529 uint64_t dma_addr;
530 int diag;
531
532 /* Allocate buffers in bulk */
533 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
534 (rxq->rx_free_thresh - 1));
535 rxep = &(rxq->sw_ring[alloc_idx]);
536 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
537 rxq->rx_free_thresh);
538 if (unlikely(diag != 0)) {
539 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
540 return -ENOMEM;
541 }
542
543 rxdp = &rxq->rx_ring[alloc_idx];
544 for (i = 0; i < rxq->rx_free_thresh; i++) {
545 if (likely(i < (rxq->rx_free_thresh - 1)))
546 /* Prefetch next mbuf */
547 rte_prefetch0(rxep[i + 1].mbuf);
548
549 mb = rxep[i].mbuf;
550 rte_mbuf_refcnt_set(mb, 1);
551 mb->next = NULL;
552 mb->data_off = RTE_PKTMBUF_HEADROOM;
553 mb->nb_segs = 1;
554 mb->port = rxq->port_id;
555 dma_addr = rte_cpu_to_le_64(\
556 rte_mbuf_data_iova_default(mb));
557 rxdp[i].read.hdr_addr = 0;
558 rxdp[i].read.pkt_addr = dma_addr;
559 }
560
561 /* Update rx tail regsiter */
562 rte_wmb();
563 I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
564
565 rxq->rx_free_trigger =
566 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
567 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
568 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
569
570 return 0;
571 }
572
573 static inline uint16_t
574 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
575 {
576 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
577 struct rte_eth_dev *dev;
578 uint16_t nb_rx = 0;
579
580 if (!nb_pkts)
581 return 0;
582
583 if (rxq->rx_nb_avail)
584 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
585
586 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
587 rxq->rx_next_avail = 0;
588 rxq->rx_nb_avail = nb_rx;
589 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
590
591 if (rxq->rx_tail > rxq->rx_free_trigger) {
592 if (i40e_rx_alloc_bufs(rxq) != 0) {
593 uint16_t i, j;
594
595 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
596 dev->data->rx_mbuf_alloc_failed +=
597 rxq->rx_free_thresh;
598
599 rxq->rx_nb_avail = 0;
600 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
601 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
602 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
603
604 return 0;
605 }
606 }
607
608 if (rxq->rx_tail >= rxq->nb_rx_desc)
609 rxq->rx_tail = 0;
610
611 if (rxq->rx_nb_avail)
612 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
613
614 return 0;
615 }
616
617 static uint16_t
618 i40e_recv_pkts_bulk_alloc(void *rx_queue,
619 struct rte_mbuf **rx_pkts,
620 uint16_t nb_pkts)
621 {
622 uint16_t nb_rx = 0, n, count;
623
624 if (unlikely(nb_pkts == 0))
625 return 0;
626
627 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
628 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
629
630 while (nb_pkts) {
631 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
632 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
633 nb_rx = (uint16_t)(nb_rx + count);
634 nb_pkts = (uint16_t)(nb_pkts - count);
635 if (count < n)
636 break;
637 }
638
639 return nb_rx;
640 }
641 #else
642 static uint16_t
643 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
644 struct rte_mbuf __rte_unused **rx_pkts,
645 uint16_t __rte_unused nb_pkts)
646 {
647 return 0;
648 }
649 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
650
651 uint16_t
652 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
653 {
654 struct i40e_rx_queue *rxq;
655 volatile union i40e_rx_desc *rx_ring;
656 volatile union i40e_rx_desc *rxdp;
657 union i40e_rx_desc rxd;
658 struct i40e_rx_entry *sw_ring;
659 struct i40e_rx_entry *rxe;
660 struct rte_eth_dev *dev;
661 struct rte_mbuf *rxm;
662 struct rte_mbuf *nmb;
663 uint16_t nb_rx;
664 uint32_t rx_status;
665 uint64_t qword1;
666 uint16_t rx_packet_len;
667 uint16_t rx_id, nb_hold;
668 uint64_t dma_addr;
669 uint64_t pkt_flags;
670 uint32_t *ptype_tbl;
671
672 nb_rx = 0;
673 nb_hold = 0;
674 rxq = rx_queue;
675 rx_id = rxq->rx_tail;
676 rx_ring = rxq->rx_ring;
677 sw_ring = rxq->sw_ring;
678 ptype_tbl = rxq->vsi->adapter->ptype_tbl;
679
680 while (nb_rx < nb_pkts) {
681 rxdp = &rx_ring[rx_id];
682 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
683 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
684 >> I40E_RXD_QW1_STATUS_SHIFT;
685
686 /* Check the DD bit first */
687 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
688 break;
689
690 nmb = rte_mbuf_raw_alloc(rxq->mp);
691 if (unlikely(!nmb)) {
692 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
693 dev->data->rx_mbuf_alloc_failed++;
694 break;
695 }
696
697 rxd = *rxdp;
698 nb_hold++;
699 rxe = &sw_ring[rx_id];
700 rx_id++;
701 if (unlikely(rx_id == rxq->nb_rx_desc))
702 rx_id = 0;
703
704 /* Prefetch next mbuf */
705 rte_prefetch0(sw_ring[rx_id].mbuf);
706
707 /**
708 * When next RX descriptor is on a cache line boundary,
709 * prefetch the next 4 RX descriptors and next 8 pointers
710 * to mbufs.
711 */
712 if ((rx_id & 0x3) == 0) {
713 rte_prefetch0(&rx_ring[rx_id]);
714 rte_prefetch0(&sw_ring[rx_id]);
715 }
716 rxm = rxe->mbuf;
717 rxe->mbuf = nmb;
718 dma_addr =
719 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
720 rxdp->read.hdr_addr = 0;
721 rxdp->read.pkt_addr = dma_addr;
722
723 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
724 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
725
726 rxm->data_off = RTE_PKTMBUF_HEADROOM;
727 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
728 rxm->nb_segs = 1;
729 rxm->next = NULL;
730 rxm->pkt_len = rx_packet_len;
731 rxm->data_len = rx_packet_len;
732 rxm->port = rxq->port_id;
733 rxm->ol_flags = 0;
734 i40e_rxd_to_vlan_tci(rxm, &rxd);
735 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
736 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
737 rxm->packet_type =
738 ptype_tbl[(uint8_t)((qword1 &
739 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
740 if (pkt_flags & PKT_RX_RSS_HASH)
741 rxm->hash.rss =
742 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
743 if (pkt_flags & PKT_RX_FDIR)
744 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
745
746 #ifdef RTE_LIBRTE_IEEE1588
747 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
748 #endif
749 rxm->ol_flags |= pkt_flags;
750
751 rx_pkts[nb_rx++] = rxm;
752 }
753 rxq->rx_tail = rx_id;
754
755 /**
756 * If the number of free RX descriptors is greater than the RX free
757 * threshold of the queue, advance the receive tail register of queue.
758 * Update that register with the value of the last processed RX
759 * descriptor minus 1.
760 */
761 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
762 if (nb_hold > rxq->rx_free_thresh) {
763 rx_id = (uint16_t) ((rx_id == 0) ?
764 (rxq->nb_rx_desc - 1) : (rx_id - 1));
765 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
766 nb_hold = 0;
767 }
768 rxq->nb_rx_hold = nb_hold;
769
770 return nb_rx;
771 }
772
773 uint16_t
774 i40e_recv_scattered_pkts(void *rx_queue,
775 struct rte_mbuf **rx_pkts,
776 uint16_t nb_pkts)
777 {
778 struct i40e_rx_queue *rxq = rx_queue;
779 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
780 volatile union i40e_rx_desc *rxdp;
781 union i40e_rx_desc rxd;
782 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
783 struct i40e_rx_entry *rxe;
784 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
785 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
786 struct rte_mbuf *nmb, *rxm;
787 uint16_t rx_id = rxq->rx_tail;
788 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
789 struct rte_eth_dev *dev;
790 uint32_t rx_status;
791 uint64_t qword1;
792 uint64_t dma_addr;
793 uint64_t pkt_flags;
794 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
795
796 while (nb_rx < nb_pkts) {
797 rxdp = &rx_ring[rx_id];
798 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
799 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
800 I40E_RXD_QW1_STATUS_SHIFT;
801
802 /* Check the DD bit */
803 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
804 break;
805
806 nmb = rte_mbuf_raw_alloc(rxq->mp);
807 if (unlikely(!nmb)) {
808 dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
809 dev->data->rx_mbuf_alloc_failed++;
810 break;
811 }
812
813 rxd = *rxdp;
814 nb_hold++;
815 rxe = &sw_ring[rx_id];
816 rx_id++;
817 if (rx_id == rxq->nb_rx_desc)
818 rx_id = 0;
819
820 /* Prefetch next mbuf */
821 rte_prefetch0(sw_ring[rx_id].mbuf);
822
823 /**
824 * When next RX descriptor is on a cache line boundary,
825 * prefetch the next 4 RX descriptors and next 8 pointers
826 * to mbufs.
827 */
828 if ((rx_id & 0x3) == 0) {
829 rte_prefetch0(&rx_ring[rx_id]);
830 rte_prefetch0(&sw_ring[rx_id]);
831 }
832
833 rxm = rxe->mbuf;
834 rxe->mbuf = nmb;
835 dma_addr =
836 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
837
838 /* Set data buffer address and data length of the mbuf */
839 rxdp->read.hdr_addr = 0;
840 rxdp->read.pkt_addr = dma_addr;
841 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
842 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
843 rxm->data_len = rx_packet_len;
844 rxm->data_off = RTE_PKTMBUF_HEADROOM;
845
846 /**
847 * If this is the first buffer of the received packet, set the
848 * pointer to the first mbuf of the packet and initialize its
849 * context. Otherwise, update the total length and the number
850 * of segments of the current scattered packet, and update the
851 * pointer to the last mbuf of the current packet.
852 */
853 if (!first_seg) {
854 first_seg = rxm;
855 first_seg->nb_segs = 1;
856 first_seg->pkt_len = rx_packet_len;
857 } else {
858 first_seg->pkt_len =
859 (uint16_t)(first_seg->pkt_len +
860 rx_packet_len);
861 first_seg->nb_segs++;
862 last_seg->next = rxm;
863 }
864
865 /**
866 * If this is not the last buffer of the received packet,
867 * update the pointer to the last mbuf of the current scattered
868 * packet and continue to parse the RX ring.
869 */
870 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
871 last_seg = rxm;
872 continue;
873 }
874
875 /**
876 * This is the last buffer of the received packet. If the CRC
877 * is not stripped by the hardware:
878 * - Subtract the CRC length from the total packet length.
879 * - If the last buffer only contains the whole CRC or a part
880 * of it, free the mbuf associated to the last buffer. If part
881 * of the CRC is also contained in the previous mbuf, subtract
882 * the length of that CRC part from the data length of the
883 * previous mbuf.
884 */
885 rxm->next = NULL;
886 if (unlikely(rxq->crc_len > 0)) {
887 first_seg->pkt_len -= ETHER_CRC_LEN;
888 if (rx_packet_len <= ETHER_CRC_LEN) {
889 rte_pktmbuf_free_seg(rxm);
890 first_seg->nb_segs--;
891 last_seg->data_len =
892 (uint16_t)(last_seg->data_len -
893 (ETHER_CRC_LEN - rx_packet_len));
894 last_seg->next = NULL;
895 } else
896 rxm->data_len = (uint16_t)(rx_packet_len -
897 ETHER_CRC_LEN);
898 }
899
900 first_seg->port = rxq->port_id;
901 first_seg->ol_flags = 0;
902 i40e_rxd_to_vlan_tci(first_seg, &rxd);
903 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
904 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
905 first_seg->packet_type =
906 ptype_tbl[(uint8_t)((qword1 &
907 I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
908 if (pkt_flags & PKT_RX_RSS_HASH)
909 first_seg->hash.rss =
910 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
911 if (pkt_flags & PKT_RX_FDIR)
912 pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
913
914 #ifdef RTE_LIBRTE_IEEE1588
915 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
916 #endif
917 first_seg->ol_flags |= pkt_flags;
918
919 /* Prefetch data of first segment, if configured to do so. */
920 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
921 first_seg->data_off));
922 rx_pkts[nb_rx++] = first_seg;
923 first_seg = NULL;
924 }
925
926 /* Record index of the next RX descriptor to probe. */
927 rxq->rx_tail = rx_id;
928 rxq->pkt_first_seg = first_seg;
929 rxq->pkt_last_seg = last_seg;
930
931 /**
932 * If the number of free RX descriptors is greater than the RX free
933 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
934 * register. Update the RDT with the value of the last processed RX
935 * descriptor minus 1, to guarantee that the RDT register is never
936 * equal to the RDH register, which creates a "full" ring situtation
937 * from the hardware point of view.
938 */
939 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
940 if (nb_hold > rxq->rx_free_thresh) {
941 rx_id = (uint16_t)(rx_id == 0 ?
942 (rxq->nb_rx_desc - 1) : (rx_id - 1));
943 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
944 nb_hold = 0;
945 }
946 rxq->nb_rx_hold = nb_hold;
947
948 return nb_rx;
949 }
950
951 /* Check if the context descriptor is needed for TX offloading */
952 static inline uint16_t
953 i40e_calc_context_desc(uint64_t flags)
954 {
955 static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
956 PKT_TX_TCP_SEG |
957 PKT_TX_QINQ_PKT |
958 PKT_TX_TUNNEL_MASK;
959
960 #ifdef RTE_LIBRTE_IEEE1588
961 mask |= PKT_TX_IEEE1588_TMST;
962 #endif
963
964 return (flags & mask) ? 1 : 0;
965 }
966
967 /* set i40e TSO context descriptor */
968 static inline uint64_t
969 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
970 {
971 uint64_t ctx_desc = 0;
972 uint32_t cd_cmd, hdr_len, cd_tso_len;
973
974 if (!tx_offload.l4_len) {
975 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
976 return ctx_desc;
977 }
978
979 /**
980 * in case of non tunneling packet, the outer_l2_len and
981 * outer_l3_len must be 0.
982 */
983 hdr_len = tx_offload.outer_l2_len +
984 tx_offload.outer_l3_len +
985 tx_offload.l2_len +
986 tx_offload.l3_len +
987 tx_offload.l4_len;
988
989 cd_cmd = I40E_TX_CTX_DESC_TSO;
990 cd_tso_len = mbuf->pkt_len - hdr_len;
991 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
992 ((uint64_t)cd_tso_len <<
993 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
994 ((uint64_t)mbuf->tso_segsz <<
995 I40E_TXD_CTX_QW1_MSS_SHIFT);
996
997 return ctx_desc;
998 }
999
1000 uint16_t
1001 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1002 {
1003 struct i40e_tx_queue *txq;
1004 struct i40e_tx_entry *sw_ring;
1005 struct i40e_tx_entry *txe, *txn;
1006 volatile struct i40e_tx_desc *txd;
1007 volatile struct i40e_tx_desc *txr;
1008 struct rte_mbuf *tx_pkt;
1009 struct rte_mbuf *m_seg;
1010 uint32_t cd_tunneling_params;
1011 uint16_t tx_id;
1012 uint16_t nb_tx;
1013 uint32_t td_cmd;
1014 uint32_t td_offset;
1015 uint32_t td_tag;
1016 uint64_t ol_flags;
1017 uint16_t nb_used;
1018 uint16_t nb_ctx;
1019 uint16_t tx_last;
1020 uint16_t slen;
1021 uint64_t buf_dma_addr;
1022 union i40e_tx_offload tx_offload = {0};
1023
1024 txq = tx_queue;
1025 sw_ring = txq->sw_ring;
1026 txr = txq->tx_ring;
1027 tx_id = txq->tx_tail;
1028 txe = &sw_ring[tx_id];
1029
1030 /* Check if the descriptor ring needs to be cleaned. */
1031 if (txq->nb_tx_free < txq->tx_free_thresh)
1032 i40e_xmit_cleanup(txq);
1033
1034 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1035 td_cmd = 0;
1036 td_tag = 0;
1037 td_offset = 0;
1038
1039 tx_pkt = *tx_pkts++;
1040 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1041
1042 ol_flags = tx_pkt->ol_flags;
1043 tx_offload.l2_len = tx_pkt->l2_len;
1044 tx_offload.l3_len = tx_pkt->l3_len;
1045 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1046 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1047 tx_offload.l4_len = tx_pkt->l4_len;
1048 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1049
1050 /* Calculate the number of context descriptors needed. */
1051 nb_ctx = i40e_calc_context_desc(ol_flags);
1052
1053 /**
1054 * The number of descriptors that must be allocated for
1055 * a packet equals to the number of the segments of that
1056 * packet plus 1 context descriptor if needed.
1057 */
1058 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1059 tx_last = (uint16_t)(tx_id + nb_used - 1);
1060
1061 /* Circular ring */
1062 if (tx_last >= txq->nb_tx_desc)
1063 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1064
1065 if (nb_used > txq->nb_tx_free) {
1066 if (i40e_xmit_cleanup(txq) != 0) {
1067 if (nb_tx == 0)
1068 return 0;
1069 goto end_of_tx;
1070 }
1071 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1072 while (nb_used > txq->nb_tx_free) {
1073 if (i40e_xmit_cleanup(txq) != 0) {
1074 if (nb_tx == 0)
1075 return 0;
1076 goto end_of_tx;
1077 }
1078 }
1079 }
1080 }
1081
1082 /* Descriptor based VLAN insertion */
1083 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1084 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1085 td_tag = tx_pkt->vlan_tci;
1086 }
1087
1088 /* Always enable CRC offload insertion */
1089 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1090
1091 /* Fill in tunneling parameters if necessary */
1092 cd_tunneling_params = 0;
1093 if (ol_flags & PKT_TX_TUNNEL_MASK)
1094 i40e_parse_tunneling_params(ol_flags, tx_offload,
1095 &cd_tunneling_params);
1096 /* Enable checksum offloading */
1097 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1098 i40e_txd_enable_checksum(ol_flags, &td_cmd,
1099 &td_offset, tx_offload);
1100
1101 if (nb_ctx) {
1102 /* Setup TX context descriptor if required */
1103 volatile struct i40e_tx_context_desc *ctx_txd =
1104 (volatile struct i40e_tx_context_desc *)\
1105 &txr[tx_id];
1106 uint16_t cd_l2tag2 = 0;
1107 uint64_t cd_type_cmd_tso_mss =
1108 I40E_TX_DESC_DTYPE_CONTEXT;
1109
1110 txn = &sw_ring[txe->next_id];
1111 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1112 if (txe->mbuf != NULL) {
1113 rte_pktmbuf_free_seg(txe->mbuf);
1114 txe->mbuf = NULL;
1115 }
1116
1117 /* TSO enabled means no timestamp */
1118 if (ol_flags & PKT_TX_TCP_SEG)
1119 cd_type_cmd_tso_mss |=
1120 i40e_set_tso_ctx(tx_pkt, tx_offload);
1121 else {
1122 #ifdef RTE_LIBRTE_IEEE1588
1123 if (ol_flags & PKT_TX_IEEE1588_TMST)
1124 cd_type_cmd_tso_mss |=
1125 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1126 I40E_TXD_CTX_QW1_CMD_SHIFT);
1127 #endif
1128 }
1129
1130 ctx_txd->tunneling_params =
1131 rte_cpu_to_le_32(cd_tunneling_params);
1132 if (ol_flags & PKT_TX_QINQ_PKT) {
1133 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1134 cd_type_cmd_tso_mss |=
1135 ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1136 I40E_TXD_CTX_QW1_CMD_SHIFT);
1137 }
1138 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1139 ctx_txd->type_cmd_tso_mss =
1140 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1141
1142 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1143 "tunneling_params: %#x;\n"
1144 "l2tag2: %#hx;\n"
1145 "rsvd: %#hx;\n"
1146 "type_cmd_tso_mss: %#"PRIx64";\n",
1147 tx_pkt, tx_id,
1148 ctx_txd->tunneling_params,
1149 ctx_txd->l2tag2,
1150 ctx_txd->rsvd,
1151 ctx_txd->type_cmd_tso_mss);
1152
1153 txe->last_id = tx_last;
1154 tx_id = txe->next_id;
1155 txe = txn;
1156 }
1157
1158 m_seg = tx_pkt;
1159 do {
1160 txd = &txr[tx_id];
1161 txn = &sw_ring[txe->next_id];
1162
1163 if (txe->mbuf)
1164 rte_pktmbuf_free_seg(txe->mbuf);
1165 txe->mbuf = m_seg;
1166
1167 /* Setup TX Descriptor */
1168 slen = m_seg->data_len;
1169 buf_dma_addr = rte_mbuf_data_iova(m_seg);
1170
1171 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1172 "buf_dma_addr: %#"PRIx64";\n"
1173 "td_cmd: %#x;\n"
1174 "td_offset: %#x;\n"
1175 "td_len: %u;\n"
1176 "td_tag: %#x;\n",
1177 tx_pkt, tx_id, buf_dma_addr,
1178 td_cmd, td_offset, slen, td_tag);
1179
1180 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1181 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1182 td_offset, slen, td_tag);
1183 txe->last_id = tx_last;
1184 tx_id = txe->next_id;
1185 txe = txn;
1186 m_seg = m_seg->next;
1187 } while (m_seg != NULL);
1188
1189 /* The last packet data descriptor needs End Of Packet (EOP) */
1190 td_cmd |= I40E_TX_DESC_CMD_EOP;
1191 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1192 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1193
1194 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1195 PMD_TX_FREE_LOG(DEBUG,
1196 "Setting RS bit on TXD id="
1197 "%4u (port=%d queue=%d)",
1198 tx_last, txq->port_id, txq->queue_id);
1199
1200 td_cmd |= I40E_TX_DESC_CMD_RS;
1201
1202 /* Update txq RS bit counters */
1203 txq->nb_tx_used = 0;
1204 }
1205
1206 txd->cmd_type_offset_bsz |=
1207 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1208 I40E_TXD_QW1_CMD_SHIFT);
1209 }
1210
1211 end_of_tx:
1212 rte_wmb();
1213
1214 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1215 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1216 (unsigned) tx_id, (unsigned) nb_tx);
1217
1218 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1219 txq->tx_tail = tx_id;
1220
1221 return nb_tx;
1222 }
1223
1224 static __rte_always_inline int
1225 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1226 {
1227 struct i40e_tx_entry *txep;
1228 uint16_t i;
1229
1230 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1231 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1232 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1233 return 0;
1234
1235 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1236
1237 for (i = 0; i < txq->tx_rs_thresh; i++)
1238 rte_prefetch0((txep + i)->mbuf);
1239
1240 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1241 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1242 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1243 txep->mbuf = NULL;
1244 }
1245 } else {
1246 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1247 rte_pktmbuf_free_seg(txep->mbuf);
1248 txep->mbuf = NULL;
1249 }
1250 }
1251
1252 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1253 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1254 if (txq->tx_next_dd >= txq->nb_tx_desc)
1255 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1256
1257 return txq->tx_rs_thresh;
1258 }
1259
1260 /* Populate 4 descriptors with data from 4 mbufs */
1261 static inline void
1262 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1263 {
1264 uint64_t dma_addr;
1265 uint32_t i;
1266
1267 for (i = 0; i < 4; i++, txdp++, pkts++) {
1268 dma_addr = rte_mbuf_data_iova(*pkts);
1269 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1270 txdp->cmd_type_offset_bsz =
1271 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1272 (*pkts)->data_len, 0);
1273 }
1274 }
1275
1276 /* Populate 1 descriptor with data from 1 mbuf */
1277 static inline void
1278 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1279 {
1280 uint64_t dma_addr;
1281
1282 dma_addr = rte_mbuf_data_iova(*pkts);
1283 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1284 txdp->cmd_type_offset_bsz =
1285 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1286 (*pkts)->data_len, 0);
1287 }
1288
1289 /* Fill hardware descriptor ring with mbuf data */
1290 static inline void
1291 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1292 struct rte_mbuf **pkts,
1293 uint16_t nb_pkts)
1294 {
1295 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1296 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1297 const int N_PER_LOOP = 4;
1298 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1299 int mainpart, leftover;
1300 int i, j;
1301
1302 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1303 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1304 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1305 for (j = 0; j < N_PER_LOOP; ++j) {
1306 (txep + i + j)->mbuf = *(pkts + i + j);
1307 }
1308 tx4(txdp + i, pkts + i);
1309 }
1310 if (unlikely(leftover > 0)) {
1311 for (i = 0; i < leftover; ++i) {
1312 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1313 tx1(txdp + mainpart + i, pkts + mainpart + i);
1314 }
1315 }
1316 }
1317
1318 static inline uint16_t
1319 tx_xmit_pkts(struct i40e_tx_queue *txq,
1320 struct rte_mbuf **tx_pkts,
1321 uint16_t nb_pkts)
1322 {
1323 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1324 uint16_t n = 0;
1325
1326 /**
1327 * Begin scanning the H/W ring for done descriptors when the number
1328 * of available descriptors drops below tx_free_thresh. For each done
1329 * descriptor, free the associated buffer.
1330 */
1331 if (txq->nb_tx_free < txq->tx_free_thresh)
1332 i40e_tx_free_bufs(txq);
1333
1334 /* Use available descriptor only */
1335 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1336 if (unlikely(!nb_pkts))
1337 return 0;
1338
1339 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1340 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1341 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1342 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1343 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1344 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1345 I40E_TXD_QW1_CMD_SHIFT);
1346 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1347 txq->tx_tail = 0;
1348 }
1349
1350 /* Fill hardware descriptor ring with mbuf data */
1351 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1352 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1353
1354 /* Determin if RS bit needs to be set */
1355 if (txq->tx_tail > txq->tx_next_rs) {
1356 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1357 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1358 I40E_TXD_QW1_CMD_SHIFT);
1359 txq->tx_next_rs =
1360 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1361 if (txq->tx_next_rs >= txq->nb_tx_desc)
1362 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1363 }
1364
1365 if (txq->tx_tail >= txq->nb_tx_desc)
1366 txq->tx_tail = 0;
1367
1368 /* Update the tx tail register */
1369 rte_wmb();
1370 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1371
1372 return nb_pkts;
1373 }
1374
1375 static uint16_t
1376 i40e_xmit_pkts_simple(void *tx_queue,
1377 struct rte_mbuf **tx_pkts,
1378 uint16_t nb_pkts)
1379 {
1380 uint16_t nb_tx = 0;
1381
1382 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1383 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1384 tx_pkts, nb_pkts);
1385
1386 while (nb_pkts) {
1387 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1388 I40E_TX_MAX_BURST);
1389
1390 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1391 &tx_pkts[nb_tx], num);
1392 nb_tx = (uint16_t)(nb_tx + ret);
1393 nb_pkts = (uint16_t)(nb_pkts - ret);
1394 if (ret < num)
1395 break;
1396 }
1397
1398 return nb_tx;
1399 }
1400
1401 static uint16_t
1402 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1403 uint16_t nb_pkts)
1404 {
1405 uint16_t nb_tx = 0;
1406 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1407
1408 while (nb_pkts) {
1409 uint16_t ret, num;
1410
1411 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1412 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1413 num);
1414 nb_tx += ret;
1415 nb_pkts -= ret;
1416 if (ret < num)
1417 break;
1418 }
1419
1420 return nb_tx;
1421 }
1422
1423 /*********************************************************************
1424 *
1425 * TX prep functions
1426 *
1427 **********************************************************************/
1428 uint16_t
1429 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1430 uint16_t nb_pkts)
1431 {
1432 int i, ret;
1433 uint64_t ol_flags;
1434 struct rte_mbuf *m;
1435
1436 for (i = 0; i < nb_pkts; i++) {
1437 m = tx_pkts[i];
1438 ol_flags = m->ol_flags;
1439
1440 /* Check for m->nb_segs to not exceed the limits. */
1441 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1442 if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1443 m->pkt_len > I40E_FRAME_SIZE_MAX) {
1444 rte_errno = -EINVAL;
1445 return i;
1446 }
1447 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1448 m->tso_segsz < I40E_MIN_TSO_MSS ||
1449 m->tso_segsz > I40E_MAX_TSO_MSS ||
1450 m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1451 /* MSS outside the range (256B - 9674B) are considered
1452 * malicious
1453 */
1454 rte_errno = -EINVAL;
1455 return i;
1456 }
1457
1458 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1459 rte_errno = -ENOTSUP;
1460 return i;
1461 }
1462
1463 /* check the size of packet */
1464 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1465 rte_errno = -EINVAL;
1466 return i;
1467 }
1468
1469 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1470 ret = rte_validate_tx_offload(m);
1471 if (ret != 0) {
1472 rte_errno = ret;
1473 return i;
1474 }
1475 #endif
1476 ret = rte_net_intel_cksum_prepare(m);
1477 if (ret != 0) {
1478 rte_errno = ret;
1479 return i;
1480 }
1481 }
1482 return i;
1483 }
1484
1485 /*
1486 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1487 * application used, which assume having sequential ones. But from driver's
1488 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1489 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1490 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1491 * use queue_idx from 0 to 95 to access queues, while real queue would be
1492 * different. This function will do a queue mapping to find VSI the queue
1493 * belongs to.
1494 */
1495 static struct i40e_vsi*
1496 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1497 {
1498 /* the queue in MAIN VSI range */
1499 if (queue_idx < pf->main_vsi->nb_qps)
1500 return pf->main_vsi;
1501
1502 queue_idx -= pf->main_vsi->nb_qps;
1503
1504 /* queue_idx is greater than VMDQ VSIs range */
1505 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1506 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1507 return NULL;
1508 }
1509
1510 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1511 }
1512
1513 static uint16_t
1514 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1515 {
1516 /* the queue in MAIN VSI range */
1517 if (queue_idx < pf->main_vsi->nb_qps)
1518 return queue_idx;
1519
1520 /* It's VMDQ queues */
1521 queue_idx -= pf->main_vsi->nb_qps;
1522
1523 if (pf->nb_cfg_vmdq_vsi)
1524 return queue_idx % pf->vmdq_nb_qps;
1525 else {
1526 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1527 return (uint16_t)(-1);
1528 }
1529 }
1530
1531 int
1532 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1533 {
1534 struct i40e_rx_queue *rxq;
1535 int err;
1536 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537
1538 PMD_INIT_FUNC_TRACE();
1539
1540 rxq = dev->data->rx_queues[rx_queue_id];
1541
1542 err = i40e_alloc_rx_queue_mbufs(rxq);
1543 if (err) {
1544 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1545 return err;
1546 }
1547
1548 rte_wmb();
1549
1550 /* Init the RX tail regieter. */
1551 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1552
1553 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1554 if (err) {
1555 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1556 rx_queue_id);
1557
1558 i40e_rx_queue_release_mbufs(rxq);
1559 i40e_reset_rx_queue(rxq);
1560 return err;
1561 }
1562 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1563
1564 return 0;
1565 }
1566
1567 int
1568 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1569 {
1570 struct i40e_rx_queue *rxq;
1571 int err;
1572 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1573
1574 rxq = dev->data->rx_queues[rx_queue_id];
1575
1576 /*
1577 * rx_queue_id is queue id application refers to, while
1578 * rxq->reg_idx is the real queue index.
1579 */
1580 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1581 if (err) {
1582 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1583 rx_queue_id);
1584 return err;
1585 }
1586 i40e_rx_queue_release_mbufs(rxq);
1587 i40e_reset_rx_queue(rxq);
1588 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1589
1590 return 0;
1591 }
1592
1593 int
1594 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1595 {
1596 int err;
1597 struct i40e_tx_queue *txq;
1598 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599
1600 PMD_INIT_FUNC_TRACE();
1601
1602 txq = dev->data->tx_queues[tx_queue_id];
1603
1604 /*
1605 * tx_queue_id is queue id application refers to, while
1606 * rxq->reg_idx is the real queue index.
1607 */
1608 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1609 if (err) {
1610 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1611 tx_queue_id);
1612 return err;
1613 }
1614 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1615
1616 return 0;
1617 }
1618
1619 int
1620 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1621 {
1622 struct i40e_tx_queue *txq;
1623 int err;
1624 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1625
1626 txq = dev->data->tx_queues[tx_queue_id];
1627
1628 /*
1629 * tx_queue_id is queue id application refers to, while
1630 * txq->reg_idx is the real queue index.
1631 */
1632 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1633 if (err) {
1634 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1635 tx_queue_id);
1636 return err;
1637 }
1638
1639 i40e_tx_queue_release_mbufs(txq);
1640 i40e_reset_tx_queue(txq);
1641 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1642
1643 return 0;
1644 }
1645
1646 const uint32_t *
1647 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1648 {
1649 static const uint32_t ptypes[] = {
1650 /* refers to i40e_rxd_pkt_type_mapping() */
1651 RTE_PTYPE_L2_ETHER,
1652 RTE_PTYPE_L2_ETHER_TIMESYNC,
1653 RTE_PTYPE_L2_ETHER_LLDP,
1654 RTE_PTYPE_L2_ETHER_ARP,
1655 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1656 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1657 RTE_PTYPE_L4_FRAG,
1658 RTE_PTYPE_L4_ICMP,
1659 RTE_PTYPE_L4_NONFRAG,
1660 RTE_PTYPE_L4_SCTP,
1661 RTE_PTYPE_L4_TCP,
1662 RTE_PTYPE_L4_UDP,
1663 RTE_PTYPE_TUNNEL_GRENAT,
1664 RTE_PTYPE_TUNNEL_IP,
1665 RTE_PTYPE_INNER_L2_ETHER,
1666 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1667 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1668 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1669 RTE_PTYPE_INNER_L4_FRAG,
1670 RTE_PTYPE_INNER_L4_ICMP,
1671 RTE_PTYPE_INNER_L4_NONFRAG,
1672 RTE_PTYPE_INNER_L4_SCTP,
1673 RTE_PTYPE_INNER_L4_TCP,
1674 RTE_PTYPE_INNER_L4_UDP,
1675 RTE_PTYPE_UNKNOWN
1676 };
1677
1678 if (dev->rx_pkt_burst == i40e_recv_pkts ||
1679 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1680 dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1681 #endif
1682 dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1683 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1684 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1685 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1686 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1687 return ptypes;
1688 return NULL;
1689 }
1690
1691 static int
1692 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1693 {
1694 uint16_t i;
1695
1696 for (i = 0; i < num; i++) {
1697 if (i != idx && queues[i])
1698 return 0;
1699 }
1700
1701 return 1;
1702 }
1703
1704 static int
1705 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1706 struct i40e_rx_queue *rxq)
1707 {
1708 struct i40e_adapter *ad =
1709 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1710 int use_def_burst_func =
1711 check_rx_burst_bulk_alloc_preconditions(rxq);
1712 uint16_t buf_size =
1713 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1714 RTE_PKTMBUF_HEADROOM);
1715 int use_scattered_rx =
1716 ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size);
1717
1718 if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1719 PMD_DRV_LOG(ERR,
1720 "Failed to do RX queue initialization");
1721 return -EINVAL;
1722 }
1723
1724 if (i40e_dev_first_queue(rxq->queue_id,
1725 dev->data->rx_queues,
1726 dev->data->nb_rx_queues)) {
1727 /**
1728 * If it is the first queue to setup,
1729 * set all flags to default and call
1730 * i40e_set_rx_function.
1731 */
1732 ad->rx_bulk_alloc_allowed = true;
1733 ad->rx_vec_allowed = true;
1734 dev->data->scattered_rx = use_scattered_rx;
1735 if (use_def_burst_func)
1736 ad->rx_bulk_alloc_allowed = false;
1737 i40e_set_rx_function(dev);
1738 return 0;
1739 }
1740
1741 /* check bulk alloc conflict */
1742 if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1743 PMD_DRV_LOG(ERR, "Can't use default burst.");
1744 return -EINVAL;
1745 }
1746 /* check scatterred conflict */
1747 if (!dev->data->scattered_rx && use_scattered_rx) {
1748 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1749 return -EINVAL;
1750 }
1751 /* check vector conflict */
1752 if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1753 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1754 return -EINVAL;
1755 }
1756
1757 return 0;
1758 }
1759
1760 int
1761 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1762 uint16_t queue_idx,
1763 uint16_t nb_desc,
1764 unsigned int socket_id,
1765 const struct rte_eth_rxconf *rx_conf,
1766 struct rte_mempool *mp)
1767 {
1768 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1769 struct i40e_adapter *ad =
1770 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1771 struct i40e_vsi *vsi;
1772 struct i40e_pf *pf = NULL;
1773 struct i40e_vf *vf = NULL;
1774 struct i40e_rx_queue *rxq;
1775 const struct rte_memzone *rz;
1776 uint32_t ring_size;
1777 uint16_t len, i;
1778 uint16_t reg_idx, base, bsf, tc_mapping;
1779 int q_offset, use_def_burst_func = 1;
1780 uint64_t offloads;
1781
1782 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1783
1784 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1785 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1786 vsi = &vf->vsi;
1787 if (!vsi)
1788 return -EINVAL;
1789 reg_idx = queue_idx;
1790 } else {
1791 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1792 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1793 if (!vsi)
1794 return -EINVAL;
1795 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1796 if (q_offset < 0)
1797 return -EINVAL;
1798 reg_idx = vsi->base_queue + q_offset;
1799 }
1800
1801 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1802 (nb_desc > I40E_MAX_RING_DESC) ||
1803 (nb_desc < I40E_MIN_RING_DESC)) {
1804 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1805 "invalid", nb_desc);
1806 return -EINVAL;
1807 }
1808
1809 /* Free memory if needed */
1810 if (dev->data->rx_queues[queue_idx]) {
1811 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1812 dev->data->rx_queues[queue_idx] = NULL;
1813 }
1814
1815 /* Allocate the rx queue data structure */
1816 rxq = rte_zmalloc_socket("i40e rx queue",
1817 sizeof(struct i40e_rx_queue),
1818 RTE_CACHE_LINE_SIZE,
1819 socket_id);
1820 if (!rxq) {
1821 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1822 "rx queue data structure");
1823 return -ENOMEM;
1824 }
1825 rxq->mp = mp;
1826 rxq->nb_rx_desc = nb_desc;
1827 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1828 rxq->queue_id = queue_idx;
1829 rxq->reg_idx = reg_idx;
1830 rxq->port_id = dev->data->port_id;
1831 if (rte_eth_dev_must_keep_crc(dev->data->dev_conf.rxmode.offloads))
1832 rxq->crc_len = ETHER_CRC_LEN;
1833 else
1834 rxq->crc_len = 0;
1835 rxq->drop_en = rx_conf->rx_drop_en;
1836 rxq->vsi = vsi;
1837 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1838 rxq->offloads = offloads;
1839
1840 /* Allocate the maximun number of RX ring hardware descriptor. */
1841 len = I40E_MAX_RING_DESC;
1842
1843 /**
1844 * Allocating a little more memory because vectorized/bulk_alloc Rx
1845 * functions doesn't check boundaries each time.
1846 */
1847 len += RTE_PMD_I40E_RX_MAX_BURST;
1848
1849 ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1850 I40E_DMA_MEM_ALIGN);
1851
1852 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1853 ring_size, I40E_RING_BASE_ALIGN, socket_id);
1854 if (!rz) {
1855 i40e_dev_rx_queue_release(rxq);
1856 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1857 return -ENOMEM;
1858 }
1859
1860 /* Zero all the descriptors in the ring. */
1861 memset(rz->addr, 0, ring_size);
1862
1863 rxq->rx_ring_phys_addr = rz->iova;
1864 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1865
1866 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1867
1868 /* Allocate the software ring. */
1869 rxq->sw_ring =
1870 rte_zmalloc_socket("i40e rx sw ring",
1871 sizeof(struct i40e_rx_entry) * len,
1872 RTE_CACHE_LINE_SIZE,
1873 socket_id);
1874 if (!rxq->sw_ring) {
1875 i40e_dev_rx_queue_release(rxq);
1876 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1877 return -ENOMEM;
1878 }
1879
1880 i40e_reset_rx_queue(rxq);
1881 rxq->q_set = TRUE;
1882
1883 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1884 if (!(vsi->enabled_tc & (1 << i)))
1885 continue;
1886 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1887 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1888 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1889 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1890 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1891
1892 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1893 rxq->dcb_tc = i;
1894 }
1895
1896 if (dev->data->dev_started) {
1897 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1898 i40e_dev_rx_queue_release(rxq);
1899 return -EINVAL;
1900 }
1901 } else {
1902 use_def_burst_func =
1903 check_rx_burst_bulk_alloc_preconditions(rxq);
1904 if (!use_def_burst_func) {
1905 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1906 PMD_INIT_LOG(DEBUG,
1907 "Rx Burst Bulk Alloc Preconditions are "
1908 "satisfied. Rx Burst Bulk Alloc function will be "
1909 "used on port=%d, queue=%d.",
1910 rxq->port_id, rxq->queue_id);
1911 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1912 } else {
1913 PMD_INIT_LOG(DEBUG,
1914 "Rx Burst Bulk Alloc Preconditions are "
1915 "not satisfied, Scattered Rx is requested, "
1916 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1917 "not enabled on port=%d, queue=%d.",
1918 rxq->port_id, rxq->queue_id);
1919 ad->rx_bulk_alloc_allowed = false;
1920 }
1921 }
1922
1923 dev->data->rx_queues[queue_idx] = rxq;
1924 return 0;
1925 }
1926
1927 void
1928 i40e_dev_rx_queue_release(void *rxq)
1929 {
1930 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1931
1932 if (!q) {
1933 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1934 return;
1935 }
1936
1937 i40e_rx_queue_release_mbufs(q);
1938 rte_free(q->sw_ring);
1939 rte_free(q);
1940 }
1941
1942 uint32_t
1943 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1944 {
1945 #define I40E_RXQ_SCAN_INTERVAL 4
1946 volatile union i40e_rx_desc *rxdp;
1947 struct i40e_rx_queue *rxq;
1948 uint16_t desc = 0;
1949
1950 rxq = dev->data->rx_queues[rx_queue_id];
1951 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1952 while ((desc < rxq->nb_rx_desc) &&
1953 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1954 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1955 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1956 /**
1957 * Check the DD bit of a rx descriptor of each 4 in a group,
1958 * to avoid checking too frequently and downgrading performance
1959 * too much.
1960 */
1961 desc += I40E_RXQ_SCAN_INTERVAL;
1962 rxdp += I40E_RXQ_SCAN_INTERVAL;
1963 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1964 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1965 desc - rxq->nb_rx_desc]);
1966 }
1967
1968 return desc;
1969 }
1970
1971 int
1972 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1973 {
1974 volatile union i40e_rx_desc *rxdp;
1975 struct i40e_rx_queue *rxq = rx_queue;
1976 uint16_t desc;
1977 int ret;
1978
1979 if (unlikely(offset >= rxq->nb_rx_desc)) {
1980 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1981 return 0;
1982 }
1983
1984 desc = rxq->rx_tail + offset;
1985 if (desc >= rxq->nb_rx_desc)
1986 desc -= rxq->nb_rx_desc;
1987
1988 rxdp = &(rxq->rx_ring[desc]);
1989
1990 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1991 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1992 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1993
1994 return ret;
1995 }
1996
1997 int
1998 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1999 {
2000 struct i40e_rx_queue *rxq = rx_queue;
2001 volatile uint64_t *status;
2002 uint64_t mask;
2003 uint32_t desc;
2004
2005 if (unlikely(offset >= rxq->nb_rx_desc))
2006 return -EINVAL;
2007
2008 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2009 return RTE_ETH_RX_DESC_UNAVAIL;
2010
2011 desc = rxq->rx_tail + offset;
2012 if (desc >= rxq->nb_rx_desc)
2013 desc -= rxq->nb_rx_desc;
2014
2015 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2016 mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2017 << I40E_RXD_QW1_STATUS_SHIFT);
2018 if (*status & mask)
2019 return RTE_ETH_RX_DESC_DONE;
2020
2021 return RTE_ETH_RX_DESC_AVAIL;
2022 }
2023
2024 int
2025 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2026 {
2027 struct i40e_tx_queue *txq = tx_queue;
2028 volatile uint64_t *status;
2029 uint64_t mask, expect;
2030 uint32_t desc;
2031
2032 if (unlikely(offset >= txq->nb_tx_desc))
2033 return -EINVAL;
2034
2035 desc = txq->tx_tail + offset;
2036 /* go to next desc that has the RS bit */
2037 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2038 txq->tx_rs_thresh;
2039 if (desc >= txq->nb_tx_desc) {
2040 desc -= txq->nb_tx_desc;
2041 if (desc >= txq->nb_tx_desc)
2042 desc -= txq->nb_tx_desc;
2043 }
2044
2045 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2046 mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2047 expect = rte_cpu_to_le_64(
2048 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2049 if ((*status & mask) == expect)
2050 return RTE_ETH_TX_DESC_DONE;
2051
2052 return RTE_ETH_TX_DESC_FULL;
2053 }
2054
2055 static int
2056 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2057 struct i40e_tx_queue *txq)
2058 {
2059 struct i40e_adapter *ad =
2060 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2061
2062 if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2063 PMD_DRV_LOG(ERR,
2064 "Failed to do TX queue initialization");
2065 return -EINVAL;
2066 }
2067
2068 if (i40e_dev_first_queue(txq->queue_id,
2069 dev->data->tx_queues,
2070 dev->data->nb_tx_queues)) {
2071 /**
2072 * If it is the first queue to setup,
2073 * set all flags and call
2074 * i40e_set_tx_function.
2075 */
2076 i40e_set_tx_function_flag(dev, txq);
2077 i40e_set_tx_function(dev);
2078 return 0;
2079 }
2080
2081 /* check vector conflict */
2082 if (ad->tx_vec_allowed) {
2083 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2084 i40e_txq_vec_setup(txq)) {
2085 PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2086 return -EINVAL;
2087 }
2088 }
2089 /* check simple tx conflict */
2090 if (ad->tx_simple_allowed) {
2091 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2092 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2093 PMD_DRV_LOG(ERR, "No-simple tx is required.");
2094 return -EINVAL;
2095 }
2096 }
2097
2098 return 0;
2099 }
2100
2101 int
2102 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2103 uint16_t queue_idx,
2104 uint16_t nb_desc,
2105 unsigned int socket_id,
2106 const struct rte_eth_txconf *tx_conf)
2107 {
2108 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2109 struct i40e_vsi *vsi;
2110 struct i40e_pf *pf = NULL;
2111 struct i40e_vf *vf = NULL;
2112 struct i40e_tx_queue *txq;
2113 const struct rte_memzone *tz;
2114 uint32_t ring_size;
2115 uint16_t tx_rs_thresh, tx_free_thresh;
2116 uint16_t reg_idx, i, base, bsf, tc_mapping;
2117 int q_offset;
2118 uint64_t offloads;
2119
2120 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2121
2122 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2123 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2124 vsi = &vf->vsi;
2125 if (!vsi)
2126 return -EINVAL;
2127 reg_idx = queue_idx;
2128 } else {
2129 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2130 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2131 if (!vsi)
2132 return -EINVAL;
2133 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2134 if (q_offset < 0)
2135 return -EINVAL;
2136 reg_idx = vsi->base_queue + q_offset;
2137 }
2138
2139 if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2140 (nb_desc > I40E_MAX_RING_DESC) ||
2141 (nb_desc < I40E_MIN_RING_DESC)) {
2142 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2143 "invalid", nb_desc);
2144 return -EINVAL;
2145 }
2146
2147 /**
2148 * The following two parameters control the setting of the RS bit on
2149 * transmit descriptors. TX descriptors will have their RS bit set
2150 * after txq->tx_rs_thresh descriptors have been used. The TX
2151 * descriptor ring will be cleaned after txq->tx_free_thresh
2152 * descriptors are used or if the number of descriptors required to
2153 * transmit a packet is greater than the number of free TX descriptors.
2154 *
2155 * The following constraints must be satisfied:
2156 * - tx_rs_thresh must be greater than 0.
2157 * - tx_rs_thresh must be less than the size of the ring minus 2.
2158 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2159 * - tx_rs_thresh must be a divisor of the ring size.
2160 * - tx_free_thresh must be greater than 0.
2161 * - tx_free_thresh must be less than the size of the ring minus 3.
2162 *
2163 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2164 * race condition, hence the maximum threshold constraints. When set
2165 * to zero use default values.
2166 */
2167 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2168 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2169 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2170 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2171 if (tx_rs_thresh >= (nb_desc - 2)) {
2172 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2173 "number of TX descriptors minus 2. "
2174 "(tx_rs_thresh=%u port=%d queue=%d)",
2175 (unsigned int)tx_rs_thresh,
2176 (int)dev->data->port_id,
2177 (int)queue_idx);
2178 return I40E_ERR_PARAM;
2179 }
2180 if (tx_free_thresh >= (nb_desc - 3)) {
2181 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2182 "number of TX descriptors minus 3. "
2183 "(tx_free_thresh=%u port=%d queue=%d)",
2184 (unsigned int)tx_free_thresh,
2185 (int)dev->data->port_id,
2186 (int)queue_idx);
2187 return I40E_ERR_PARAM;
2188 }
2189 if (tx_rs_thresh > tx_free_thresh) {
2190 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2191 "equal to tx_free_thresh. (tx_free_thresh=%u"
2192 " tx_rs_thresh=%u port=%d queue=%d)",
2193 (unsigned int)tx_free_thresh,
2194 (unsigned int)tx_rs_thresh,
2195 (int)dev->data->port_id,
2196 (int)queue_idx);
2197 return I40E_ERR_PARAM;
2198 }
2199 if ((nb_desc % tx_rs_thresh) != 0) {
2200 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2201 "number of TX descriptors. (tx_rs_thresh=%u"
2202 " port=%d queue=%d)",
2203 (unsigned int)tx_rs_thresh,
2204 (int)dev->data->port_id,
2205 (int)queue_idx);
2206 return I40E_ERR_PARAM;
2207 }
2208 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2209 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2210 "tx_rs_thresh is greater than 1. "
2211 "(tx_rs_thresh=%u port=%d queue=%d)",
2212 (unsigned int)tx_rs_thresh,
2213 (int)dev->data->port_id,
2214 (int)queue_idx);
2215 return I40E_ERR_PARAM;
2216 }
2217
2218 /* Free memory if needed. */
2219 if (dev->data->tx_queues[queue_idx]) {
2220 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2221 dev->data->tx_queues[queue_idx] = NULL;
2222 }
2223
2224 /* Allocate the TX queue data structure. */
2225 txq = rte_zmalloc_socket("i40e tx queue",
2226 sizeof(struct i40e_tx_queue),
2227 RTE_CACHE_LINE_SIZE,
2228 socket_id);
2229 if (!txq) {
2230 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2231 "tx queue structure");
2232 return -ENOMEM;
2233 }
2234
2235 /* Allocate TX hardware ring descriptors. */
2236 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2237 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2238 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2239 ring_size, I40E_RING_BASE_ALIGN, socket_id);
2240 if (!tz) {
2241 i40e_dev_tx_queue_release(txq);
2242 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2243 return -ENOMEM;
2244 }
2245
2246 txq->nb_tx_desc = nb_desc;
2247 txq->tx_rs_thresh = tx_rs_thresh;
2248 txq->tx_free_thresh = tx_free_thresh;
2249 txq->pthresh = tx_conf->tx_thresh.pthresh;
2250 txq->hthresh = tx_conf->tx_thresh.hthresh;
2251 txq->wthresh = tx_conf->tx_thresh.wthresh;
2252 txq->queue_id = queue_idx;
2253 txq->reg_idx = reg_idx;
2254 txq->port_id = dev->data->port_id;
2255 txq->offloads = offloads;
2256 txq->vsi = vsi;
2257 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2258
2259 txq->tx_ring_phys_addr = tz->iova;
2260 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2261
2262 /* Allocate software ring */
2263 txq->sw_ring =
2264 rte_zmalloc_socket("i40e tx sw ring",
2265 sizeof(struct i40e_tx_entry) * nb_desc,
2266 RTE_CACHE_LINE_SIZE,
2267 socket_id);
2268 if (!txq->sw_ring) {
2269 i40e_dev_tx_queue_release(txq);
2270 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2271 return -ENOMEM;
2272 }
2273
2274 i40e_reset_tx_queue(txq);
2275 txq->q_set = TRUE;
2276
2277 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2278 if (!(vsi->enabled_tc & (1 << i)))
2279 continue;
2280 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2281 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2282 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2283 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2284 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2285
2286 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2287 txq->dcb_tc = i;
2288 }
2289
2290 if (dev->data->dev_started) {
2291 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2292 i40e_dev_tx_queue_release(txq);
2293 return -EINVAL;
2294 }
2295 } else {
2296 /**
2297 * Use a simple TX queue without offloads or
2298 * multi segs if possible
2299 */
2300 i40e_set_tx_function_flag(dev, txq);
2301 }
2302 dev->data->tx_queues[queue_idx] = txq;
2303
2304 return 0;
2305 }
2306
2307 void
2308 i40e_dev_tx_queue_release(void *txq)
2309 {
2310 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2311
2312 if (!q) {
2313 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2314 return;
2315 }
2316
2317 i40e_tx_queue_release_mbufs(q);
2318 rte_free(q->sw_ring);
2319 rte_free(q);
2320 }
2321
2322 const struct rte_memzone *
2323 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2324 {
2325 const struct rte_memzone *mz;
2326
2327 mz = rte_memzone_lookup(name);
2328 if (mz)
2329 return mz;
2330
2331 mz = rte_memzone_reserve_aligned(name, len, socket_id,
2332 RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2333 return mz;
2334 }
2335
2336 void
2337 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2338 {
2339 uint16_t i;
2340
2341 /* SSE Vector driver has a different way of releasing mbufs. */
2342 if (rxq->rx_using_sse) {
2343 i40e_rx_queue_release_mbufs_vec(rxq);
2344 return;
2345 }
2346
2347 if (!rxq->sw_ring) {
2348 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2349 return;
2350 }
2351
2352 for (i = 0; i < rxq->nb_rx_desc; i++) {
2353 if (rxq->sw_ring[i].mbuf) {
2354 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2355 rxq->sw_ring[i].mbuf = NULL;
2356 }
2357 }
2358 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2359 if (rxq->rx_nb_avail == 0)
2360 return;
2361 for (i = 0; i < rxq->rx_nb_avail; i++) {
2362 struct rte_mbuf *mbuf;
2363
2364 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2365 rte_pktmbuf_free_seg(mbuf);
2366 }
2367 rxq->rx_nb_avail = 0;
2368 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2369 }
2370
2371 void
2372 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2373 {
2374 unsigned i;
2375 uint16_t len;
2376
2377 if (!rxq) {
2378 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2379 return;
2380 }
2381
2382 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2383 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2384 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2385 else
2386 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2387 len = rxq->nb_rx_desc;
2388
2389 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2390 ((volatile char *)rxq->rx_ring)[i] = 0;
2391
2392 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2393 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2394 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2395
2396 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2397 rxq->rx_nb_avail = 0;
2398 rxq->rx_next_avail = 0;
2399 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2400 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2401 rxq->rx_tail = 0;
2402 rxq->nb_rx_hold = 0;
2403 rxq->pkt_first_seg = NULL;
2404 rxq->pkt_last_seg = NULL;
2405
2406 rxq->rxrearm_start = 0;
2407 rxq->rxrearm_nb = 0;
2408 }
2409
2410 void
2411 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2412 {
2413 struct rte_eth_dev *dev;
2414 uint16_t i;
2415
2416 dev = &rte_eth_devices[txq->port_id];
2417
2418 if (!txq || !txq->sw_ring) {
2419 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2420 return;
2421 }
2422
2423 /**
2424 * vPMD tx will not set sw_ring's mbuf to NULL after free,
2425 * so need to free remains more carefully.
2426 */
2427 if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2428 dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2429 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2430 if (txq->tx_tail < i) {
2431 for (; i < txq->nb_tx_desc; i++) {
2432 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2433 txq->sw_ring[i].mbuf = NULL;
2434 }
2435 i = 0;
2436 }
2437 for (; i < txq->tx_tail; i++) {
2438 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2439 txq->sw_ring[i].mbuf = NULL;
2440 }
2441 } else {
2442 for (i = 0; i < txq->nb_tx_desc; i++) {
2443 if (txq->sw_ring[i].mbuf) {
2444 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2445 txq->sw_ring[i].mbuf = NULL;
2446 }
2447 }
2448 }
2449 }
2450
2451 void
2452 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2453 {
2454 struct i40e_tx_entry *txe;
2455 uint16_t i, prev, size;
2456
2457 if (!txq) {
2458 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2459 return;
2460 }
2461
2462 txe = txq->sw_ring;
2463 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2464 for (i = 0; i < size; i++)
2465 ((volatile char *)txq->tx_ring)[i] = 0;
2466
2467 prev = (uint16_t)(txq->nb_tx_desc - 1);
2468 for (i = 0; i < txq->nb_tx_desc; i++) {
2469 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2470
2471 txd->cmd_type_offset_bsz =
2472 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2473 txe[i].mbuf = NULL;
2474 txe[i].last_id = i;
2475 txe[prev].next_id = i;
2476 prev = i;
2477 }
2478
2479 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2480 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2481
2482 txq->tx_tail = 0;
2483 txq->nb_tx_used = 0;
2484
2485 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2486 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2487 }
2488
2489 /* Init the TX queue in hardware */
2490 int
2491 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2492 {
2493 enum i40e_status_code err = I40E_SUCCESS;
2494 struct i40e_vsi *vsi = txq->vsi;
2495 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2496 uint16_t pf_q = txq->reg_idx;
2497 struct i40e_hmc_obj_txq tx_ctx;
2498 uint32_t qtx_ctl;
2499
2500 /* clear the context structure first */
2501 memset(&tx_ctx, 0, sizeof(tx_ctx));
2502 tx_ctx.new_context = 1;
2503 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2504 tx_ctx.qlen = txq->nb_tx_desc;
2505
2506 #ifdef RTE_LIBRTE_IEEE1588
2507 tx_ctx.timesync_ena = 1;
2508 #endif
2509 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2510 if (vsi->type == I40E_VSI_FDIR)
2511 tx_ctx.fd_ena = TRUE;
2512
2513 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2514 if (err != I40E_SUCCESS) {
2515 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2516 return err;
2517 }
2518
2519 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2520 if (err != I40E_SUCCESS) {
2521 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2522 return err;
2523 }
2524
2525 /* Now associate this queue with this PCI function */
2526 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2527 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2528 I40E_QTX_CTL_PF_INDX_MASK);
2529 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2530 I40E_WRITE_FLUSH(hw);
2531
2532 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2533
2534 return err;
2535 }
2536
2537 int
2538 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2539 {
2540 struct i40e_rx_entry *rxe = rxq->sw_ring;
2541 uint64_t dma_addr;
2542 uint16_t i;
2543
2544 for (i = 0; i < rxq->nb_rx_desc; i++) {
2545 volatile union i40e_rx_desc *rxd;
2546 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2547
2548 if (unlikely(!mbuf)) {
2549 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2550 return -ENOMEM;
2551 }
2552
2553 rte_mbuf_refcnt_set(mbuf, 1);
2554 mbuf->next = NULL;
2555 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2556 mbuf->nb_segs = 1;
2557 mbuf->port = rxq->port_id;
2558
2559 dma_addr =
2560 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2561
2562 rxd = &rxq->rx_ring[i];
2563 rxd->read.pkt_addr = dma_addr;
2564 rxd->read.hdr_addr = 0;
2565 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2566 rxd->read.rsvd1 = 0;
2567 rxd->read.rsvd2 = 0;
2568 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2569
2570 rxe[i].mbuf = mbuf;
2571 }
2572
2573 return 0;
2574 }
2575
2576 /*
2577 * Calculate the buffer length, and check the jumbo frame
2578 * and maximum packet length.
2579 */
2580 static int
2581 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2582 {
2583 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2584 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2585 struct rte_eth_dev_data *data = pf->dev_data;
2586 uint16_t buf_size, len;
2587
2588 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2589 RTE_PKTMBUF_HEADROOM);
2590
2591 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2592 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2593 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2594 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2595 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2596 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2597 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2598 rxq->hs_mode = i40e_header_split_enabled;
2599 break;
2600 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2601 default:
2602 rxq->rx_hdr_len = 0;
2603 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2604 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2605 rxq->hs_mode = i40e_header_split_none;
2606 break;
2607 }
2608
2609 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2610 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2611 if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2612 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2613 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2614 PMD_DRV_LOG(ERR, "maximum packet length must "
2615 "be larger than %u and smaller than %u,"
2616 "as jumbo frame is enabled",
2617 (uint32_t)ETHER_MAX_LEN,
2618 (uint32_t)I40E_FRAME_SIZE_MAX);
2619 return I40E_ERR_CONFIG;
2620 }
2621 } else {
2622 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2623 rxq->max_pkt_len > ETHER_MAX_LEN) {
2624 PMD_DRV_LOG(ERR, "maximum packet length must be "
2625 "larger than %u and smaller than %u, "
2626 "as jumbo frame is disabled",
2627 (uint32_t)ETHER_MIN_LEN,
2628 (uint32_t)ETHER_MAX_LEN);
2629 return I40E_ERR_CONFIG;
2630 }
2631 }
2632
2633 return 0;
2634 }
2635
2636 /* Init the RX queue in hardware */
2637 int
2638 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2639 {
2640 int err = I40E_SUCCESS;
2641 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2642 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2643 uint16_t pf_q = rxq->reg_idx;
2644 uint16_t buf_size;
2645 struct i40e_hmc_obj_rxq rx_ctx;
2646
2647 err = i40e_rx_queue_config(rxq);
2648 if (err < 0) {
2649 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2650 return err;
2651 }
2652
2653 /* Clear the context structure first */
2654 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2655 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2656 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2657
2658 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2659 rx_ctx.qlen = rxq->nb_rx_desc;
2660 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2661 rx_ctx.dsize = 1;
2662 #endif
2663 rx_ctx.dtype = rxq->hs_mode;
2664 if (rxq->hs_mode)
2665 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2666 else
2667 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2668 rx_ctx.rxmax = rxq->max_pkt_len;
2669 rx_ctx.tphrdesc_ena = 1;
2670 rx_ctx.tphwdesc_ena = 1;
2671 rx_ctx.tphdata_ena = 1;
2672 rx_ctx.tphhead_ena = 1;
2673 rx_ctx.lrxqthresh = 2;
2674 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2675 rx_ctx.l2tsel = 1;
2676 /* showiv indicates if inner VLAN is stripped inside of tunnel
2677 * packet. When set it to 1, vlan information is stripped from
2678 * the inner header, but the hardware does not put it in the
2679 * descriptor. So set it zero by default.
2680 */
2681 rx_ctx.showiv = 0;
2682 rx_ctx.prefena = 1;
2683
2684 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2685 if (err != I40E_SUCCESS) {
2686 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2687 return err;
2688 }
2689 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2690 if (err != I40E_SUCCESS) {
2691 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2692 return err;
2693 }
2694
2695 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2696
2697 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2698 RTE_PKTMBUF_HEADROOM);
2699
2700 /* Check if scattered RX needs to be used. */
2701 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2702 dev_data->scattered_rx = 1;
2703 }
2704
2705 /* Init the RX tail regieter. */
2706 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2707
2708 return 0;
2709 }
2710
2711 void
2712 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2713 {
2714 uint16_t i;
2715
2716 PMD_INIT_FUNC_TRACE();
2717
2718 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2719 if (!dev->data->tx_queues[i])
2720 continue;
2721 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2722 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2723 }
2724
2725 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2726 if (!dev->data->rx_queues[i])
2727 continue;
2728 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2729 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2730 }
2731 }
2732
2733 void
2734 i40e_dev_free_queues(struct rte_eth_dev *dev)
2735 {
2736 uint16_t i;
2737
2738 PMD_INIT_FUNC_TRACE();
2739
2740 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2741 if (!dev->data->rx_queues[i])
2742 continue;
2743 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2744 dev->data->rx_queues[i] = NULL;
2745 }
2746 dev->data->nb_rx_queues = 0;
2747
2748 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2749 if (!dev->data->tx_queues[i])
2750 continue;
2751 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2752 dev->data->tx_queues[i] = NULL;
2753 }
2754 dev->data->nb_tx_queues = 0;
2755 }
2756
2757 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2758 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2759
2760 enum i40e_status_code
2761 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2762 {
2763 struct i40e_tx_queue *txq;
2764 const struct rte_memzone *tz = NULL;
2765 uint32_t ring_size;
2766 struct rte_eth_dev *dev;
2767
2768 if (!pf) {
2769 PMD_DRV_LOG(ERR, "PF is not available");
2770 return I40E_ERR_BAD_PTR;
2771 }
2772
2773 dev = pf->adapter->eth_dev;
2774
2775 /* Allocate the TX queue data structure. */
2776 txq = rte_zmalloc_socket("i40e fdir tx queue",
2777 sizeof(struct i40e_tx_queue),
2778 RTE_CACHE_LINE_SIZE,
2779 SOCKET_ID_ANY);
2780 if (!txq) {
2781 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2782 "tx queue structure.");
2783 return I40E_ERR_NO_MEMORY;
2784 }
2785
2786 /* Allocate TX hardware ring descriptors. */
2787 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2788 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2789
2790 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2791 I40E_FDIR_QUEUE_ID, ring_size,
2792 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2793 if (!tz) {
2794 i40e_dev_tx_queue_release(txq);
2795 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2796 return I40E_ERR_NO_MEMORY;
2797 }
2798
2799 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2800 txq->queue_id = I40E_FDIR_QUEUE_ID;
2801 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2802 txq->vsi = pf->fdir.fdir_vsi;
2803
2804 txq->tx_ring_phys_addr = tz->iova;
2805 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2806 /*
2807 * don't need to allocate software ring and reset for the fdir
2808 * program queue just set the queue has been configured.
2809 */
2810 txq->q_set = TRUE;
2811 pf->fdir.txq = txq;
2812
2813 return I40E_SUCCESS;
2814 }
2815
2816 enum i40e_status_code
2817 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2818 {
2819 struct i40e_rx_queue *rxq;
2820 const struct rte_memzone *rz = NULL;
2821 uint32_t ring_size;
2822 struct rte_eth_dev *dev;
2823
2824 if (!pf) {
2825 PMD_DRV_LOG(ERR, "PF is not available");
2826 return I40E_ERR_BAD_PTR;
2827 }
2828
2829 dev = pf->adapter->eth_dev;
2830
2831 /* Allocate the RX queue data structure. */
2832 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2833 sizeof(struct i40e_rx_queue),
2834 RTE_CACHE_LINE_SIZE,
2835 SOCKET_ID_ANY);
2836 if (!rxq) {
2837 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2838 "rx queue structure.");
2839 return I40E_ERR_NO_MEMORY;
2840 }
2841
2842 /* Allocate RX hardware ring descriptors. */
2843 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2844 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2845
2846 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2847 I40E_FDIR_QUEUE_ID, ring_size,
2848 I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2849 if (!rz) {
2850 i40e_dev_rx_queue_release(rxq);
2851 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2852 return I40E_ERR_NO_MEMORY;
2853 }
2854
2855 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2856 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2857 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2858 rxq->vsi = pf->fdir.fdir_vsi;
2859
2860 rxq->rx_ring_phys_addr = rz->iova;
2861 memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2862 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2863
2864 /*
2865 * Don't need to allocate software ring and reset for the fdir
2866 * rx queue, just set the queue has been configured.
2867 */
2868 rxq->q_set = TRUE;
2869 pf->fdir.rxq = rxq;
2870
2871 return I40E_SUCCESS;
2872 }
2873
2874 void
2875 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2876 struct rte_eth_rxq_info *qinfo)
2877 {
2878 struct i40e_rx_queue *rxq;
2879
2880 rxq = dev->data->rx_queues[queue_id];
2881
2882 qinfo->mp = rxq->mp;
2883 qinfo->scattered_rx = dev->data->scattered_rx;
2884 qinfo->nb_desc = rxq->nb_rx_desc;
2885
2886 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2887 qinfo->conf.rx_drop_en = rxq->drop_en;
2888 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2889 qinfo->conf.offloads = rxq->offloads;
2890 }
2891
2892 void
2893 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2894 struct rte_eth_txq_info *qinfo)
2895 {
2896 struct i40e_tx_queue *txq;
2897
2898 txq = dev->data->tx_queues[queue_id];
2899
2900 qinfo->nb_desc = txq->nb_tx_desc;
2901
2902 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2903 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2904 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2905
2906 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2907 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2908 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2909 qinfo->conf.offloads = txq->offloads;
2910 }
2911
2912 void __attribute__((cold))
2913 i40e_set_rx_function(struct rte_eth_dev *dev)
2914 {
2915 struct i40e_adapter *ad =
2916 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2917 uint16_t rx_using_sse, i;
2918 /* In order to allow Vector Rx there are a few configuration
2919 * conditions to be met and Rx Bulk Allocation should be allowed.
2920 */
2921 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2922 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2923 !ad->rx_bulk_alloc_allowed) {
2924 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2925 " Vector Rx preconditions",
2926 dev->data->port_id);
2927
2928 ad->rx_vec_allowed = false;
2929 }
2930 if (ad->rx_vec_allowed) {
2931 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2932 struct i40e_rx_queue *rxq =
2933 dev->data->rx_queues[i];
2934
2935 if (rxq && i40e_rxq_vec_setup(rxq)) {
2936 ad->rx_vec_allowed = false;
2937 break;
2938 }
2939 }
2940 }
2941 }
2942
2943 if (dev->data->scattered_rx) {
2944 /* Set the non-LRO scattered callback: there are Vector and
2945 * single allocation versions.
2946 */
2947 if (ad->rx_vec_allowed) {
2948 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2949 "callback (port=%d).",
2950 dev->data->port_id);
2951
2952 dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2953 #ifdef RTE_ARCH_X86
2954 /*
2955 * since AVX frequency can be different to base
2956 * frequency, limit use of AVX2 version to later
2957 * plaforms, not all those that could theoretically
2958 * run it.
2959 */
2960 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2961 dev->rx_pkt_burst =
2962 i40e_recv_scattered_pkts_vec_avx2;
2963 #endif
2964 } else {
2965 PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2966 "allocation callback (port=%d).",
2967 dev->data->port_id);
2968 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2969 }
2970 /* If parameters allow we are going to choose between the following
2971 * callbacks:
2972 * - Vector
2973 * - Bulk Allocation
2974 * - Single buffer allocation (the simplest one)
2975 */
2976 } else if (ad->rx_vec_allowed) {
2977 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2978 "burst size no less than %d (port=%d).",
2979 RTE_I40E_DESCS_PER_LOOP,
2980 dev->data->port_id);
2981
2982 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2983 #ifdef RTE_ARCH_X86
2984 /*
2985 * since AVX frequency can be different to base
2986 * frequency, limit use of AVX2 version to later
2987 * plaforms, not all those that could theoretically
2988 * run it.
2989 */
2990 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2991 dev->rx_pkt_burst = i40e_recv_pkts_vec_avx2;
2992 #endif
2993 } else if (ad->rx_bulk_alloc_allowed) {
2994 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2995 "satisfied. Rx Burst Bulk Alloc function "
2996 "will be used on port=%d.",
2997 dev->data->port_id);
2998
2999 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3000 } else {
3001 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3002 "satisfied, or Scattered Rx is requested "
3003 "(port=%d).",
3004 dev->data->port_id);
3005
3006 dev->rx_pkt_burst = i40e_recv_pkts;
3007 }
3008
3009 /* Propagate information about RX function choice through all queues. */
3010 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3011 rx_using_sse =
3012 (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3013 dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3014 dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3015 dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3016
3017 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3018 struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3019
3020 if (rxq)
3021 rxq->rx_using_sse = rx_using_sse;
3022 }
3023 }
3024 }
3025
3026 void __attribute__((cold))
3027 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3028 {
3029 struct i40e_adapter *ad =
3030 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3031
3032 /* Use a simple Tx queue if possible (only fast free is allowed) */
3033 ad->tx_simple_allowed =
3034 (txq->offloads ==
3035 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3036 txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3037 ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3038 txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3039
3040 if (ad->tx_vec_allowed)
3041 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3042 txq->queue_id);
3043 else if (ad->tx_simple_allowed)
3044 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3045 txq->queue_id);
3046 else
3047 PMD_INIT_LOG(DEBUG,
3048 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3049 txq->queue_id);
3050 }
3051
3052 void __attribute__((cold))
3053 i40e_set_tx_function(struct rte_eth_dev *dev)
3054 {
3055 struct i40e_adapter *ad =
3056 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3057 int i;
3058
3059 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3060 if (ad->tx_vec_allowed) {
3061 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3062 struct i40e_tx_queue *txq =
3063 dev->data->tx_queues[i];
3064
3065 if (txq && i40e_txq_vec_setup(txq)) {
3066 ad->tx_vec_allowed = false;
3067 break;
3068 }
3069 }
3070 }
3071 }
3072
3073 if (ad->tx_simple_allowed) {
3074 if (ad->tx_vec_allowed) {
3075 PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3076 dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3077 #ifdef RTE_ARCH_X86
3078 /*
3079 * since AVX frequency can be different to base
3080 * frequency, limit use of AVX2 version to later
3081 * plaforms, not all those that could theoretically
3082 * run it.
3083 */
3084 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3085 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx2;
3086 #endif
3087 } else {
3088 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3089 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3090 }
3091 dev->tx_pkt_prepare = NULL;
3092 } else {
3093 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3094 dev->tx_pkt_burst = i40e_xmit_pkts;
3095 dev->tx_pkt_prepare = i40e_prep_pkts;
3096 }
3097 }
3098
3099 void __attribute__((cold))
3100 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3101 {
3102 struct i40e_adapter *ad =
3103 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3104 int i;
3105
3106 for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3107 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3108 }
3109
3110 void __attribute__((cold))
3111 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3112 {
3113 struct i40e_adapter *ad =
3114 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3115 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3116 int i;
3117
3118 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3119 ad->pctypes_tbl[i] = 0ULL;
3120 ad->flow_types_mask = 0ULL;
3121 ad->pctypes_mask = 0ULL;
3122
3123 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3124 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3125 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3126 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3127 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3128 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3129 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3130 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3131 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3132 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3133 ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3134 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3135 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3136 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3137 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3138 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3139 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3140 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3141 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3142 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3143 ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3144 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3145
3146 if (hw->mac.type == I40E_MAC_X722) {
3147 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3148 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3149 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3150 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3151 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3152 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3153 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3154 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3155 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3156 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3157 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3158 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3159 }
3160
3161 for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3162 if (ad->pctypes_tbl[i])
3163 ad->flow_types_mask |= (1ULL << i);
3164 ad->pctypes_mask |= ad->pctypes_tbl[i];
3165 }
3166 }
3167
3168 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3169 int __attribute__((weak))
3170 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3171 {
3172 return -1;
3173 }
3174
3175 uint16_t __attribute__((weak))
3176 i40e_recv_pkts_vec(
3177 void __rte_unused *rx_queue,
3178 struct rte_mbuf __rte_unused **rx_pkts,
3179 uint16_t __rte_unused nb_pkts)
3180 {
3181 return 0;
3182 }
3183
3184 uint16_t __attribute__((weak))
3185 i40e_recv_scattered_pkts_vec(
3186 void __rte_unused *rx_queue,
3187 struct rte_mbuf __rte_unused **rx_pkts,
3188 uint16_t __rte_unused nb_pkts)
3189 {
3190 return 0;
3191 }
3192
3193 uint16_t __attribute__((weak))
3194 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3195 struct rte_mbuf __rte_unused **rx_pkts,
3196 uint16_t __rte_unused nb_pkts)
3197 {
3198 return 0;
3199 }
3200
3201 uint16_t __attribute__((weak))
3202 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3203 struct rte_mbuf __rte_unused **rx_pkts,
3204 uint16_t __rte_unused nb_pkts)
3205 {
3206 return 0;
3207 }
3208
3209 int __attribute__((weak))
3210 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3211 {
3212 return -1;
3213 }
3214
3215 int __attribute__((weak))
3216 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3217 {
3218 return -1;
3219 }
3220
3221 void __attribute__((weak))
3222 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3223 {
3224 return;
3225 }
3226
3227 uint16_t __attribute__((weak))
3228 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3229 struct rte_mbuf __rte_unused **tx_pkts,
3230 uint16_t __rte_unused nb_pkts)
3231 {
3232 return 0;
3233 }
3234
3235 uint16_t __attribute__((weak))
3236 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3237 struct rte_mbuf __rte_unused **tx_pkts,
3238 uint16_t __rte_unused nb_pkts)
3239 {
3240 return 0;
3241 }
Ceph