ceph/src/spdk/dpdk/drivers/net/igc/base/igc_manage.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2020 Intel Corporation
   3  */
   4
   5 #ifndef _IGC_MANAGE_H_
   6 #define _IGC_MANAGE_H_
   7
   8 bool igc_check_mng_mode_generic(struct igc_hw *hw);
   9 bool igc_enable_tx_pkt_filtering_generic(struct igc_hw *hw);
  10 s32  igc_mng_enable_host_if_generic(struct igc_hw *hw);
  11 s32  igc_mng_host_if_write_generic(struct igc_hw *hw, u8 *buffer,
  12                                      u16 length, u16 offset, u8 *sum);
  13 s32  igc_mng_write_cmd_header_generic(struct igc_hw *hw,
  14                                      struct igc_host_mng_command_header *hdr);
  15 s32  igc_mng_write_dhcp_info_generic(struct igc_hw *hw,
  16                                        u8 *buffer, u16 length);
  17 bool igc_enable_mng_pass_thru(struct igc_hw *hw);
  18 u8 igc_calculate_checksum(u8 *buffer, u32 length);
  19 s32 igc_host_interface_command(struct igc_hw *hw, u8 *buffer, u32 length);
  20 s32 igc_load_firmware(struct igc_hw *hw, u8 *buffer, u32 length);
  21
  22 enum igc_mng_mode {
  23         igc_mng_mode_none = 0,
  24         igc_mng_mode_asf,
  25         igc_mng_mode_pt,
  26         igc_mng_mode_ipmi,
  27         igc_mng_mode_host_if_only
  28 };
  29
  30 #define IGC_FACTPS_MNGCG                        0x20000000
  31
  32 #define IGC_FWSM_MODE_MASK                      0xE
  33 #define IGC_FWSM_MODE_SHIFT                     1
  34 #define IGC_FWSM_FW_VALID                       0x00008000
  35 #define IGC_FWSM_HI_EN_ONLY_MODE                0x4
  36
  37 #define IGC_MNG_IAMT_MODE                       0x3
  38 #define IGC_MNG_DHCP_COOKIE_LENGTH              0x10
  39 #define IGC_MNG_DHCP_COOKIE_OFFSET              0x6F0
  40 #define IGC_MNG_DHCP_COMMAND_TIMEOUT            10
  41 #define IGC_MNG_DHCP_TX_PAYLOAD_CMD             64
  42 #define IGC_MNG_DHCP_COOKIE_STATUS_PARSING      0x1
  43 #define IGC_MNG_DHCP_COOKIE_STATUS_VLAN 0x2
  44
  45 #define IGC_VFTA_ENTRY_SHIFT                    5
  46 #define IGC_VFTA_ENTRY_MASK                     0x7F
  47 #define IGC_VFTA_ENTRY_BIT_SHIFT_MASK           0x1F
  48
  49 #define IGC_HI_MAX_BLOCK_BYTE_LENGTH            1792 /* Num of bytes in range */
  50 #define IGC_HI_MAX_BLOCK_DWORD_LENGTH           448 /* Num of dwords in range */
  51 #define IGC_HI_COMMAND_TIMEOUT          500 /* Process HI cmd limit */
  52 #define IGC_HI_FW_BASE_ADDRESS          0x10000
  53 #define IGC_HI_FW_MAX_LENGTH                    (64 * 1024) /* Num of bytes */
  54 #define IGC_HI_FW_BLOCK_DWORD_LENGTH            256 /* Num of DWORDs per page */
  55 #define IGC_HICR_MEMORY_BASE_EN         0x200 /* MB Enable bit - RO */
  56 #define IGC_HICR_EN                     0x01  /* Enable bit - RO */
  57 /* Driver sets this bit when done to put command in RAM */
  58 #define IGC_HICR_C                      0x02
  59 #define IGC_HICR_SV                     0x04  /* Status Validity */
  60 #define IGC_HICR_FW_RESET_ENABLE        0x40
  61 #define IGC_HICR_FW_RESET               0x80
  62
  63 /* Intel(R) Active Management Technology signature */
  64 #define IGC_IAMT_SIGNATURE              0x544D4149
  65 #endif