ceph/src/spdk/dpdk/drivers/net/igc/igc_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2020 Intel Corporation
   3  */
   4
   5 #ifndef _IGC_ETHDEV_H_
   6 #define _IGC_ETHDEV_H_
   7
   8 #include <rte_ethdev.h>
   9
  10 #include "base/igc_osdep.h"
  11 #include "base/igc_hw.h"
  12 #include "base/igc_i225.h"
  13 #include "base/igc_api.h"
  14
  15 #ifdef __cplusplus
  16 extern "C" {
  17 #endif
  18
  19 #define IGC_RSS_RDT_SIZD                128
  20
  21 /* VLAN filter table size */
  22 #define IGC_VFTA_SIZE                   128
  23
  24 #define IGC_QUEUE_PAIRS_NUM             4
  25
  26 #define IGC_HKEY_MAX_INDEX              10
  27 #define IGC_RSS_RDT_SIZD                128
  28
  29 #define IGC_DEFAULT_REG_SIZE            4
  30 #define IGC_DEFAULT_REG_SIZE_MASK       0xf
  31
  32 #define IGC_RSS_RDT_REG_SIZE            IGC_DEFAULT_REG_SIZE
  33 #define IGC_RSS_RDT_REG_SIZE_MASK       IGC_DEFAULT_REG_SIZE_MASK
  34 #define IGC_HKEY_REG_SIZE               IGC_DEFAULT_REG_SIZE
  35 #define IGC_HKEY_SIZE                   (IGC_HKEY_REG_SIZE * IGC_HKEY_MAX_INDEX)
  36
  37 /*
  38  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
  39  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
  40  * This will also optimize cache line size effect.
  41  * H/W supports up to cache line size 128.
  42  */
  43 #define IGC_ALIGN                       128
  44
  45 #define IGC_TX_DESCRIPTOR_MULTIPLE      8
  46 #define IGC_RX_DESCRIPTOR_MULTIPLE      8
  47
  48 #define IGC_RXD_ALIGN   ((uint16_t)(IGC_ALIGN / \
  49                 sizeof(union igc_adv_rx_desc)))
  50 #define IGC_TXD_ALIGN   ((uint16_t)(IGC_ALIGN / \
  51                 sizeof(union igc_adv_tx_desc)))
  52 #define IGC_MIN_TXD     IGC_TX_DESCRIPTOR_MULTIPLE
  53 #define IGC_MAX_TXD     ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc)))
  54 #define IGC_MIN_RXD     IGC_RX_DESCRIPTOR_MULTIPLE
  55 #define IGC_MAX_RXD     ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc)))
  56
  57 #define IGC_TX_MAX_SEG          UINT8_MAX
  58 #define IGC_TX_MAX_MTU_SEG      UINT8_MAX
  59
  60 #define IGC_RX_OFFLOAD_ALL      (    \
  61         DEV_RX_OFFLOAD_VLAN_STRIP  | \
  62         DEV_RX_OFFLOAD_VLAN_FILTER | \
  63         DEV_RX_OFFLOAD_VLAN_EXTEND | \
  64         DEV_RX_OFFLOAD_IPV4_CKSUM  | \
  65         DEV_RX_OFFLOAD_UDP_CKSUM   | \
  66         DEV_RX_OFFLOAD_TCP_CKSUM   | \
  67         DEV_RX_OFFLOAD_SCTP_CKSUM  | \
  68         DEV_RX_OFFLOAD_JUMBO_FRAME | \
  69         DEV_RX_OFFLOAD_KEEP_CRC    | \
  70         DEV_RX_OFFLOAD_SCATTER)
  71
  72 #define IGC_TX_OFFLOAD_ALL      (    \
  73         DEV_TX_OFFLOAD_VLAN_INSERT | \
  74         DEV_TX_OFFLOAD_IPV4_CKSUM  | \
  75         DEV_TX_OFFLOAD_UDP_CKSUM   | \
  76         DEV_TX_OFFLOAD_TCP_CKSUM   | \
  77         DEV_TX_OFFLOAD_SCTP_CKSUM  | \
  78         DEV_TX_OFFLOAD_TCP_TSO     | \
  79         DEV_TX_OFFLOAD_UDP_TSO     | \
  80         DEV_TX_OFFLOAD_MULTI_SEGS)
  81
  82 #define IGC_RSS_OFFLOAD_ALL     (    \
  83         ETH_RSS_IPV4               | \
  84         ETH_RSS_NONFRAG_IPV4_TCP   | \
  85         ETH_RSS_NONFRAG_IPV4_UDP   | \
  86         ETH_RSS_IPV6               | \
  87         ETH_RSS_NONFRAG_IPV6_TCP   | \
  88         ETH_RSS_NONFRAG_IPV6_UDP   | \
  89         ETH_RSS_IPV6_EX            | \
  90         ETH_RSS_IPV6_TCP_EX        | \
  91         ETH_RSS_IPV6_UDP_EX)
  92
  93 #define IGC_MAX_ETQF_FILTERS            3       /* etqf(3) is used for 1588 */
  94 #define IGC_ETQF_FILTER_1588            3
  95 #define IGC_ETQF_QUEUE_SHIFT            16
  96 #define IGC_ETQF_QUEUE_MASK             (7u << IGC_ETQF_QUEUE_SHIFT)
  97
  98 #define IGC_MAX_NTUPLE_FILTERS          8
  99 #define IGC_NTUPLE_MAX_PRI              7
 100
 101 #define IGC_SYN_FILTER_ENABLE           0x01    /* syn filter enable field */
 102 #define IGC_SYN_FILTER_QUEUE_SHIFT      1       /* syn filter queue field */
 103 #define IGC_SYN_FILTER_QUEUE    0x0000000E      /* syn filter queue field */
 104 #define IGC_RFCTL_SYNQFP        0x00080000      /* SYNQFP in RFCTL register */
 105
 106 /* structure for interrupt relative data */
 107 struct igc_interrupt {
 108         uint32_t flags;
 109         uint32_t mask;
 110 };
 111
 112 /* Union of RSS redirect table register */
 113 union igc_rss_reta_reg {
 114         uint32_t dword;
 115         uint8_t  bytes[4];
 116 };
 117
 118 /* Structure to per-queue statics */
 119 struct igc_hw_queue_stats {
 120         u64     pqgprc[IGC_QUEUE_PAIRS_NUM];
 121         /* per queue good packets received count */
 122         u64     pqgptc[IGC_QUEUE_PAIRS_NUM];
 123         /* per queue good packets transmitted count */
 124         u64     pqgorc[IGC_QUEUE_PAIRS_NUM];
 125         /* per queue good octets received count */
 126         u64     pqgotc[IGC_QUEUE_PAIRS_NUM];
 127         /* per queue good octets transmitted count */
 128         u64     pqmprc[IGC_QUEUE_PAIRS_NUM];
 129         /* per queue multicast packets received count */
 130         u64     rqdpc[IGC_QUEUE_PAIRS_NUM];
 131         /* per receive queue drop packet count */
 132         u64     tqdpc[IGC_QUEUE_PAIRS_NUM];
 133         /* per transmit queue drop packet count */
 134 };
 135
 136 /* local vfta copy */
 137 struct igc_vfta {
 138         uint32_t vfta[IGC_VFTA_SIZE];
 139 };
 140
 141 /* ethertype filter structure */
 142 struct igc_ethertype_filter {
 143         uint16_t ether_type;
 144         uint16_t queue;
 145 };
 146
 147 /* Structure of ntuple filter info. */
 148 struct igc_ntuple_info {
 149         uint16_t dst_port;
 150         uint8_t proto;          /* l4 protocol. */
 151
 152         /*
 153          * the packet matched above 2tuple and contain any set bit will hit
 154          * this filter.
 155          */
 156         uint8_t tcp_flags;
 157
 158         /*
 159          * seven levels (001b-111b), 111b is highest, used when more than one
 160          * filter matches.
 161          */
 162         uint8_t priority;
 163         uint8_t dst_port_mask:1, /* if mask is 1b, do compare dst port. */
 164                 proto_mask:1;    /* if mask is 1b, do compare protocol. */
 165 };
 166
 167 /* Structure of n-tuple filter */
 168 struct igc_ntuple_filter {
 169         RTE_STD_C11
 170         union {
 171                 uint64_t hash_val;
 172                 struct igc_ntuple_info tuple_info;
 173         };
 174
 175         uint8_t queue;
 176 };
 177
 178 /* Structure of TCP SYN filter */
 179 struct igc_syn_filter {
 180         uint8_t queue;
 181
 182         uint8_t hig_pri:1,      /* 1 - higher priority than other filters, */
 183                                 /* 0 - lower priority. */
 184                 enable:1;       /* 1-enable; 0-disable */
 185 };
 186
 187 /* Structure to store RTE flow RSS configure. */
 188 struct igc_rss_filter {
 189         struct rte_flow_action_rss conf; /* RSS parameters. */
 190         uint8_t key[IGC_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
 191         uint16_t queue[IGC_RSS_RDT_SIZD];/* Queues indices to use. */
 192         uint8_t enable; /* 1-enabled, 0-disabled */
 193 };
 194
 195 /* Feature filter types */
 196 enum igc_filter_type {
 197         IGC_FILTER_TYPE_ETHERTYPE,
 198         IGC_FILTER_TYPE_NTUPLE,
 199         IGC_FILTER_TYPE_SYN,
 200         IGC_FILTER_TYPE_HASH
 201 };
 202
 203 /* Structure to store flow */
 204 struct rte_flow {
 205         TAILQ_ENTRY(rte_flow) node;
 206         enum igc_filter_type filter_type;
 207         RTE_STD_C11
 208         char filter[0];         /* filter data */
 209 };
 210
 211 /* Flow list header */
 212 TAILQ_HEAD(igc_flow_list, rte_flow);
 213
 214 /*
 215  * Structure to store private data for each driver instance (for each port).
 216  */
 217 struct igc_adapter {
 218         struct igc_hw           hw;
 219         struct igc_hw_stats     stats;
 220         struct igc_hw_queue_stats queue_stats;
 221         int16_t txq_stats_map[IGC_QUEUE_PAIRS_NUM];
 222         int16_t rxq_stats_map[IGC_QUEUE_PAIRS_NUM];
 223
 224         struct igc_interrupt    intr;
 225         struct igc_vfta shadow_vfta;
 226         bool            stopped;
 227
 228         struct igc_ethertype_filter ethertype_filters[IGC_MAX_ETQF_FILTERS];
 229         struct igc_ntuple_filter ntuple_filters[IGC_MAX_NTUPLE_FILTERS];
 230         struct igc_syn_filter syn_filter;
 231         struct igc_rss_filter rss_filter;
 232         struct igc_flow_list flow_list;
 233 };
 234
 235 #define IGC_DEV_PRIVATE(_dev)   ((_dev)->data->dev_private)
 236
 237 #define IGC_DEV_PRIVATE_HW(_dev) \
 238         (&((struct igc_adapter *)(_dev)->data->dev_private)->hw)
 239
 240 #define IGC_DEV_PRIVATE_STATS(_dev) \
 241         (&((struct igc_adapter *)(_dev)->data->dev_private)->stats)
 242
 243 #define IGC_DEV_PRIVATE_QUEUE_STATS(_dev) \
 244         (&((struct igc_adapter *)(_dev)->data->dev_private)->queue_stats)
 245
 246 #define IGC_DEV_PRIVATE_INTR(_dev) \
 247         (&((struct igc_adapter *)(_dev)->data->dev_private)->intr)
 248
 249 #define IGC_DEV_PRIVATE_VFTA(_dev) \
 250         (&((struct igc_adapter *)(_dev)->data->dev_private)->shadow_vfta)
 251
 252 #define IGC_DEV_PRIVATE_RSS_FILTER(_dev) \
 253         (&((struct igc_adapter *)(_dev)->data->dev_private)->rss_filter)
 254
 255 #define IGC_DEV_PRIVATE_FLOW_LIST(_dev) \
 256         (&((struct igc_adapter *)(_dev)->data->dev_private)->flow_list)
 257
 258 static inline void
 259 igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
 260 {
 261         uint32_t reg_val = IGC_READ_REG(hw, reg);
 262
 263         bits |= reg_val;
 264         if (bits == reg_val)
 265                 return; /* no need to write back */
 266
 267         IGC_WRITE_REG(hw, reg, bits);
 268 }
 269
 270 static inline void
 271 igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
 272 {
 273         uint32_t reg_val = IGC_READ_REG(hw, reg);
 274
 275         bits = reg_val & ~bits;
 276         if (bits == reg_val)
 277                 return; /* no need to write back */
 278
 279         IGC_WRITE_REG(hw, reg, bits);
 280 }
 281
 282 #ifdef __cplusplus
 283 }
 284 #endif
 285
 286 #endif /* _IGC_ETHDEV_H_ */