ceph/src/spdk/dpdk/drivers/net/ionic/ionic_regs.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
   3  */
   4
   5 #ifndef _IONIC_REGS_H_
   6 #define _IONIC_REGS_H_
   7
   8 /** struct ionic_intr - interrupt control register set.
   9  * @coal_init:                  coalesce timer initial value.
  10  * @mask:                       interrupt mask value.
  11  * @credits:                    interrupt credit count and return.
  12  * @mask_assert:                interrupt mask value on assert.
  13  * @coal:                       coalesce timer time remaining.
  14  */
  15 struct ionic_intr {
  16         uint32_t coal_init;
  17         uint32_t mask;
  18         uint32_t credits;
  19         uint32_t mask_assert;
  20         uint32_t coal;
  21         uint32_t rsvd[3];
  22 };
  23
  24 #define IONIC_INTR_CTRL_REGS_MAX        2048
  25 #define IONIC_INTR_CTRL_COAL_MAX        0x3F
  26
  27 /** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
  28  * @IONIC_INTR_MASK_CLEAR:      unmask interrupt.
  29  * @IONIC_INTR_MASK_SET:        mask interrupt.
  30  */
  31 enum ionic_intr_mask_vals {
  32         IONIC_INTR_MASK_CLEAR           = 0,
  33         IONIC_INTR_MASK_SET             = 1,
  34 };
  35
  36 /** enum ionic_intr_credits_bits - bitwise composition of credits values.
  37  * @IONIC_INTR_CRED_COUNT:      bit mask of credit count, no shift needed.
  38  * @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit.
  39  * @IONIC_INTR_CRED_UNMASK:     unmask the interrupt.
  40  * @IONIC_INTR_CRED_RESET_COALESCE: reset the coalesce timer.
  41  * @IONIC_INTR_CRED_REARM:      unmask the and reset the timer.
  42  */
  43 enum ionic_intr_credits_bits {
  44         IONIC_INTR_CRED_COUNT           = 0x7fffu,
  45         IONIC_INTR_CRED_COUNT_SIGNED    = 0xffffu,
  46         IONIC_INTR_CRED_UNMASK          = 0x10000u,
  47         IONIC_INTR_CRED_RESET_COALESCE  = 0x20000u,
  48         IONIC_INTR_CRED_REARM           = (IONIC_INTR_CRED_UNMASK |
  49                                            IONIC_INTR_CRED_RESET_COALESCE),
  50 };
  51
  52 static inline void
  53 ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl,
  54                 int intr_idx, uint32_t coal)
  55 {
  56         iowrite32(coal, &intr_ctrl[intr_idx].coal_init);
  57 }
  58
  59 static inline void
  60 ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl,
  61                 int intr_idx, uint32_t mask)
  62 {
  63         iowrite32(mask, &intr_ctrl[intr_idx].mask);
  64 }
  65
  66 static inline void
  67 ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl,
  68                 int intr_idx, uint32_t cred, uint32_t flags)
  69 {
  70         if (cred > IONIC_INTR_CRED_COUNT) {
  71                 IONIC_WARN_ON(cred > IONIC_INTR_CRED_COUNT);
  72                 cred = ioread32(&intr_ctrl[intr_idx].credits);
  73                 cred &= IONIC_INTR_CRED_COUNT_SIGNED;
  74         }
  75
  76         iowrite32(cred | flags, &intr_ctrl[intr_idx].credits);
  77 }
  78
  79 static inline void
  80 ionic_intr_clean(struct ionic_intr __iomem *intr_ctrl,
  81                 int intr_idx)
  82 {
  83         uint32_t cred;
  84
  85         cred = ioread32(&intr_ctrl[intr_idx].credits);
  86         cred &= IONIC_INTR_CRED_COUNT_SIGNED;
  87         cred |= IONIC_INTR_CRED_RESET_COALESCE;
  88         iowrite32(cred, &intr_ctrl[intr_idx].credits);
  89 }
  90
  91 static inline void
  92 ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl,
  93                 int intr_idx, uint32_t mask)
  94 {
  95         iowrite32(mask, &intr_ctrl[intr_idx].mask_assert);
  96 }
  97
  98 /** enum ionic_dbell_bits - bitwise composition of dbell values.
  99  *
 100  * @IONIC_DBELL_QID_MASK:       unshifted mask of valid queue id bits.
 101  * @IONIC_DBELL_QID_SHIFT:      queue id shift amount in dbell value.
 102  * @IONIC_DBELL_QID:            macro to build QID component of dbell value.
 103  *
 104  * @IONIC_DBELL_RING_MASK:      unshifted mask of valid ring bits.
 105  * @IONIC_DBELL_RING_SHIFT:     ring shift amount in dbell value.
 106  * @IONIC_DBELL_RING:           macro to build ring component of dbell value.
 107  *
 108  * @IONIC_DBELL_RING_0:         ring zero dbell component value.
 109  * @IONIC_DBELL_RING_1:         ring one dbell component value.
 110  * @IONIC_DBELL_RING_2:         ring two dbell component value.
 111  * @IONIC_DBELL_RING_3:         ring three dbell component value.
 112  *
 113  * @IONIC_DBELL_INDEX_MASK:     bit mask of valid index bits, no shift needed.
 114  */
 115 enum ionic_dbell_bits {
 116         IONIC_DBELL_QID_MASK            = 0xffffff,
 117         IONIC_DBELL_QID_SHIFT           = 24,
 118
 119 #define IONIC_DBELL_QID(n) \
 120         (((u64)(n) & IONIC_DBELL_QID_MASK) << IONIC_DBELL_QID_SHIFT)
 121
 122         IONIC_DBELL_RING_MASK           = 0x7,
 123         IONIC_DBELL_RING_SHIFT          = 16,
 124
 125 #define IONIC_DBELL_RING(n) \
 126         (((u64)(n) & IONIC_DBELL_RING_MASK) << IONIC_DBELL_RING_SHIFT)
 127
 128         IONIC_DBELL_RING_0              = 0,
 129         IONIC_DBELL_RING_1              = IONIC_DBELL_RING(1),
 130         IONIC_DBELL_RING_2              = IONIC_DBELL_RING(2),
 131         IONIC_DBELL_RING_3              = IONIC_DBELL_RING(3),
 132
 133         IONIC_DBELL_INDEX_MASK          = 0xffff,
 134 };
 135
 136 static inline void
 137 ionic_dbell_ring(u64 __iomem *db_page, int qtype, u64 val)
 138 {
 139         writeq(val, &db_page[qtype]);
 140 }
 141
 142 #endif /* _IONIC_REGS_H_ */