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1 /*******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ***************************************************************************/
33
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36
37 #define IXGBE_EMPTY_PARAM
38
39 static const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = {
40 IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM)
41 };
42
43 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
44 IXGBE_MVALS_INIT(_X540)
45 };
46
47 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
48 IXGBE_MVALS_INIT(_X550)
49 };
50
51 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
52 IXGBE_MVALS_INIT(_X550EM_x)
53 };
54
55 static const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = {
56 IXGBE_MVALS_INIT(_X550EM_a)
57 };
58
59 /**
60 * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg
61 * @hw: pointer to hardware structure
62 * @map: pointer to u8 arr for returning map
63 *
64 * Read the rtrup2tc HW register and resolve its content into map
65 **/
66 void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)
67 {
68 if (hw->mac.ops.get_rtrup2tc)
69 hw->mac.ops.get_rtrup2tc(hw, map);
70 }
71
72 /**
73 * ixgbe_init_shared_code - Initialize the shared code
74 * @hw: pointer to hardware structure
75 *
76 * This will assign function pointers and assign the MAC type and PHY code.
77 * Does not touch the hardware. This function must be called prior to any
78 * other function in the shared code. The ixgbe_hw structure should be
79 * memset to 0 prior to calling this function. The following fields in
80 * hw structure should be filled in prior to calling this function:
81 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
82 * subsystem_vendor_id, and revision_id
83 **/
84 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
85 {
86 s32 status;
87
88 DEBUGFUNC("ixgbe_init_shared_code");
89
90 /*
91 * Set the mac type
92 */
93 ixgbe_set_mac_type(hw);
94
95 switch (hw->mac.type) {
96 case ixgbe_mac_82598EB:
97 status = ixgbe_init_ops_82598(hw);
98 break;
99 case ixgbe_mac_82599EB:
100 status = ixgbe_init_ops_82599(hw);
101 break;
102 case ixgbe_mac_X540:
103 status = ixgbe_init_ops_X540(hw);
104 break;
105 case ixgbe_mac_X550:
106 status = ixgbe_init_ops_X550(hw);
107 break;
108 case ixgbe_mac_X550EM_x:
109 status = ixgbe_init_ops_X550EM_x(hw);
110 break;
111 case ixgbe_mac_X550EM_a:
112 status = ixgbe_init_ops_X550EM_a(hw);
113 break;
114 case ixgbe_mac_82599_vf:
115 case ixgbe_mac_X540_vf:
116 case ixgbe_mac_X550_vf:
117 case ixgbe_mac_X550EM_x_vf:
118 case ixgbe_mac_X550EM_a_vf:
119 status = ixgbe_init_ops_vf(hw);
120 break;
121 default:
122 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
123 break;
124 }
125 hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;
126
127 return status;
128 }
129
130 /**
131 * ixgbe_set_mac_type - Sets MAC type
132 * @hw: pointer to the HW structure
133 *
134 * This function sets the mac type of the adapter based on the
135 * vendor ID and device ID stored in the hw structure.
136 **/
137 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
138 {
139 s32 ret_val = IXGBE_SUCCESS;
140
141 DEBUGFUNC("ixgbe_set_mac_type\n");
142
143 if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) {
144 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
145 "Unsupported vendor id: %x", hw->vendor_id);
146 return IXGBE_ERR_DEVICE_NOT_SUPPORTED;
147 }
148
149 hw->mvals = ixgbe_mvals_base;
150
151 switch (hw->device_id) {
152 case IXGBE_DEV_ID_82598:
153 case IXGBE_DEV_ID_82598_BX:
154 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
155 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
156 case IXGBE_DEV_ID_82598AT:
157 case IXGBE_DEV_ID_82598AT2:
158 case IXGBE_DEV_ID_82598EB_CX4:
159 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
160 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
161 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
162 case IXGBE_DEV_ID_82598EB_XF_LR:
163 case IXGBE_DEV_ID_82598EB_SFP_LOM:
164 hw->mac.type = ixgbe_mac_82598EB;
165 break;
166 case IXGBE_DEV_ID_82599_KX4:
167 case IXGBE_DEV_ID_82599_KX4_MEZZ:
168 case IXGBE_DEV_ID_82599_XAUI_LOM:
169 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
170 case IXGBE_DEV_ID_82599_KR:
171 case IXGBE_DEV_ID_82599_SFP:
172 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
173 case IXGBE_DEV_ID_82599_SFP_FCOE:
174 case IXGBE_DEV_ID_82599_SFP_EM:
175 case IXGBE_DEV_ID_82599_SFP_SF2:
176 case IXGBE_DEV_ID_82599_SFP_SF_QP:
177 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
178 case IXGBE_DEV_ID_82599EN_SFP:
179 case IXGBE_DEV_ID_82599_CX4:
180 case IXGBE_DEV_ID_82599_LS:
181 case IXGBE_DEV_ID_82599_BYPASS:
182 case IXGBE_DEV_ID_82599_T3_LOM:
183 hw->mac.type = ixgbe_mac_82599EB;
184 break;
185 case IXGBE_DEV_ID_82599_VF:
186 case IXGBE_DEV_ID_82599_VF_HV:
187 hw->mac.type = ixgbe_mac_82599_vf;
188 break;
189 case IXGBE_DEV_ID_X540_VF:
190 case IXGBE_DEV_ID_X540_VF_HV:
191 hw->mac.type = ixgbe_mac_X540_vf;
192 hw->mvals = ixgbe_mvals_X540;
193 break;
194 case IXGBE_DEV_ID_X540T:
195 case IXGBE_DEV_ID_X540T1:
196 case IXGBE_DEV_ID_X540_BYPASS:
197 hw->mac.type = ixgbe_mac_X540;
198 hw->mvals = ixgbe_mvals_X540;
199 break;
200 case IXGBE_DEV_ID_X550T:
201 case IXGBE_DEV_ID_X550T1:
202 hw->mac.type = ixgbe_mac_X550;
203 hw->mvals = ixgbe_mvals_X550;
204 break;
205 case IXGBE_DEV_ID_X550EM_X_KX4:
206 case IXGBE_DEV_ID_X550EM_X_KR:
207 case IXGBE_DEV_ID_X550EM_X_10G_T:
208 case IXGBE_DEV_ID_X550EM_X_1G_T:
209 case IXGBE_DEV_ID_X550EM_X_SFP:
210 case IXGBE_DEV_ID_X550EM_X_XFI:
211 hw->mac.type = ixgbe_mac_X550EM_x;
212 hw->mvals = ixgbe_mvals_X550EM_x;
213 break;
214 case IXGBE_DEV_ID_X550EM_A_KR:
215 case IXGBE_DEV_ID_X550EM_A_KR_L:
216 case IXGBE_DEV_ID_X550EM_A_SFP_N:
217 case IXGBE_DEV_ID_X550EM_A_SGMII:
218 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
219 case IXGBE_DEV_ID_X550EM_A_1G_T:
220 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
221 case IXGBE_DEV_ID_X550EM_A_10G_T:
222 case IXGBE_DEV_ID_X550EM_A_QSFP:
223 case IXGBE_DEV_ID_X550EM_A_QSFP_N:
224 case IXGBE_DEV_ID_X550EM_A_SFP:
225 hw->mac.type = ixgbe_mac_X550EM_a;
226 hw->mvals = ixgbe_mvals_X550EM_a;
227 break;
228 case IXGBE_DEV_ID_X550_VF:
229 case IXGBE_DEV_ID_X550_VF_HV:
230 hw->mac.type = ixgbe_mac_X550_vf;
231 hw->mvals = ixgbe_mvals_X550;
232 break;
233 case IXGBE_DEV_ID_X550EM_X_VF:
234 case IXGBE_DEV_ID_X550EM_X_VF_HV:
235 hw->mac.type = ixgbe_mac_X550EM_x_vf;
236 hw->mvals = ixgbe_mvals_X550EM_x;
237 break;
238 case IXGBE_DEV_ID_X550EM_A_VF:
239 case IXGBE_DEV_ID_X550EM_A_VF_HV:
240 hw->mac.type = ixgbe_mac_X550EM_a_vf;
241 hw->mvals = ixgbe_mvals_X550EM_a;
242 break;
243 default:
244 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
245 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
246 "Unsupported device id: %x",
247 hw->device_id);
248 break;
249 }
250
251 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
252 hw->mac.type, ret_val);
253 return ret_val;
254 }
255
256 /**
257 * ixgbe_init_hw - Initialize the hardware
258 * @hw: pointer to hardware structure
259 *
260 * Initialize the hardware by resetting and then starting the hardware
261 **/
262 s32 ixgbe_init_hw(struct ixgbe_hw *hw)
263 {
264 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
265 IXGBE_NOT_IMPLEMENTED);
266 }
267
268 /**
269 * ixgbe_reset_hw - Performs a hardware reset
270 * @hw: pointer to hardware structure
271 *
272 * Resets the hardware by resetting the transmit and receive units, masks and
273 * clears all interrupts, performs a PHY reset, and performs a MAC reset
274 **/
275 s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
276 {
277 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
278 IXGBE_NOT_IMPLEMENTED);
279 }
280
281 /**
282 * ixgbe_start_hw - Prepares hardware for Rx/Tx
283 * @hw: pointer to hardware structure
284 *
285 * Starts the hardware by filling the bus info structure and media type,
286 * clears all on chip counters, initializes receive address registers,
287 * multicast table, VLAN filter table, calls routine to setup link and
288 * flow control settings, and leaves transmit and receive units disabled
289 * and uninitialized.
290 **/
291 s32 ixgbe_start_hw(struct ixgbe_hw *hw)
292 {
293 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
294 IXGBE_NOT_IMPLEMENTED);
295 }
296
297 /**
298 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
299 * which is disabled by default in ixgbe_start_hw();
300 *
301 * @hw: pointer to hardware structure
302 *
303 * Enable relaxed ordering;
304 **/
305 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)
306 {
307 if (hw->mac.ops.enable_relaxed_ordering)
308 hw->mac.ops.enable_relaxed_ordering(hw);
309 }
310
311 /**
312 * ixgbe_clear_hw_cntrs - Clear hardware counters
313 * @hw: pointer to hardware structure
314 *
315 * Clears all hardware statistics counters by reading them from the hardware
316 * Statistics counters are clear on read.
317 **/
318 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
319 {
320 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
321 IXGBE_NOT_IMPLEMENTED);
322 }
323
324 /**
325 * ixgbe_get_media_type - Get media type
326 * @hw: pointer to hardware structure
327 *
328 * Returns the media type (fiber, copper, backplane)
329 **/
330 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
331 {
332 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
333 ixgbe_media_type_unknown);
334 }
335
336 /**
337 * ixgbe_get_mac_addr - Get MAC address
338 * @hw: pointer to hardware structure
339 * @mac_addr: Adapter MAC address
340 *
341 * Reads the adapter's MAC address from the first Receive Address Register
342 * (RAR0) A reset of the adapter must have been performed prior to calling
343 * this function in order for the MAC address to have been loaded from the
344 * EEPROM into RAR0
345 **/
346 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
347 {
348 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
349 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
350 }
351
352 /**
353 * ixgbe_get_san_mac_addr - Get SAN MAC address
354 * @hw: pointer to hardware structure
355 * @san_mac_addr: SAN MAC address
356 *
357 * Reads the SAN MAC address from the EEPROM, if it's available. This is
358 * per-port, so set_lan_id() must be called before reading the addresses.
359 **/
360 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
361 {
362 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
363 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
364 }
365
366 /**
367 * ixgbe_set_san_mac_addr - Write a SAN MAC address
368 * @hw: pointer to hardware structure
369 * @san_mac_addr: SAN MAC address
370 *
371 * Writes A SAN MAC address to the EEPROM.
372 **/
373 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
374 {
375 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
376 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
377 }
378
379 /**
380 * ixgbe_get_device_caps - Get additional device capabilities
381 * @hw: pointer to hardware structure
382 * @device_caps: the EEPROM word for device capabilities
383 *
384 * Reads the extra device capabilities from the EEPROM
385 **/
386 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
387 {
388 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
389 (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
390 }
391
392 /**
393 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
394 * @hw: pointer to hardware structure
395 * @wwnn_prefix: the alternative WWNN prefix
396 * @wwpn_prefix: the alternative WWPN prefix
397 *
398 * This function will read the EEPROM from the alternative SAN MAC address
399 * block to check the support for the alternative WWNN/WWPN prefix support.
400 **/
401 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
402 u16 *wwpn_prefix)
403 {
404 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
405 (hw, wwnn_prefix, wwpn_prefix),
406 IXGBE_NOT_IMPLEMENTED);
407 }
408
409 /**
410 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM
411 * @hw: pointer to hardware structure
412 * @bs: the fcoe boot status
413 *
414 * This function will read the FCOE boot status from the iSCSI FCOE block
415 **/
416 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
417 {
418 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
419 (hw, bs),
420 IXGBE_NOT_IMPLEMENTED);
421 }
422
423 /**
424 * ixgbe_get_bus_info - Set PCI bus info
425 * @hw: pointer to hardware structure
426 *
427 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
428 **/
429 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
430 {
431 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
432 IXGBE_NOT_IMPLEMENTED);
433 }
434
435 /**
436 * ixgbe_get_num_of_tx_queues - Get Tx queues
437 * @hw: pointer to hardware structure
438 *
439 * Returns the number of transmit queues for the given adapter.
440 **/
441 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
442 {
443 return hw->mac.max_tx_queues;
444 }
445
446 /**
447 * ixgbe_get_num_of_rx_queues - Get Rx queues
448 * @hw: pointer to hardware structure
449 *
450 * Returns the number of receive queues for the given adapter.
451 **/
452 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
453 {
454 return hw->mac.max_rx_queues;
455 }
456
457 /**
458 * ixgbe_stop_adapter - Disable Rx/Tx units
459 * @hw: pointer to hardware structure
460 *
461 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
462 * disables transmit and receive units. The adapter_stopped flag is used by
463 * the shared code and drivers to determine if the adapter is in a stopped
464 * state and should not touch the hardware.
465 **/
466 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
467 {
468 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
469 IXGBE_NOT_IMPLEMENTED);
470 }
471
472 /**
473 * ixgbe_read_pba_string - Reads part number string from EEPROM
474 * @hw: pointer to hardware structure
475 * @pba_num: stores the part number string from the EEPROM
476 * @pba_num_size: part number string buffer length
477 *
478 * Reads the part number string from the EEPROM.
479 **/
480 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
481 {
482 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
483 }
484
485 /**
486 * ixgbe_read_pba_num - Reads part number from EEPROM
487 * @hw: pointer to hardware structure
488 * @pba_num: stores the part number from the EEPROM
489 *
490 * Reads the part number from the EEPROM.
491 **/
492 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
493 {
494 return ixgbe_read_pba_num_generic(hw, pba_num);
495 }
496
497 /**
498 * ixgbe_identify_phy - Get PHY type
499 * @hw: pointer to hardware structure
500 *
501 * Determines the physical layer module found on the current adapter.
502 **/
503 s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
504 {
505 s32 status = IXGBE_SUCCESS;
506
507 if (hw->phy.type == ixgbe_phy_unknown) {
508 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
509 IXGBE_NOT_IMPLEMENTED);
510 }
511
512 return status;
513 }
514
515 /**
516 * ixgbe_reset_phy - Perform a PHY reset
517 * @hw: pointer to hardware structure
518 **/
519 s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
520 {
521 s32 status = IXGBE_SUCCESS;
522
523 if (hw->phy.type == ixgbe_phy_unknown) {
524 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)
525 status = IXGBE_ERR_PHY;
526 }
527
528 if (status == IXGBE_SUCCESS) {
529 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
530 IXGBE_NOT_IMPLEMENTED);
531 }
532 return status;
533 }
534
535 /**
536 * ixgbe_get_phy_firmware_version -
537 * @hw: pointer to hardware structure
538 * @firmware_version: pointer to firmware version
539 **/
540 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
541 {
542 s32 status = IXGBE_SUCCESS;
543
544 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
545 (hw, firmware_version),
546 IXGBE_NOT_IMPLEMENTED);
547 return status;
548 }
549
550 /**
551 * ixgbe_read_phy_reg - Read PHY register
552 * @hw: pointer to hardware structure
553 * @reg_addr: 32 bit address of PHY register to read
554 * @device_type: type of device you want to communicate with
555 * @phy_data: Pointer to read data from PHY register
556 *
557 * Reads a value from a specified PHY register
558 **/
559 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
560 u16 *phy_data)
561 {
562 if (hw->phy.id == 0)
563 ixgbe_identify_phy(hw);
564
565 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
566 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
567 }
568
569 /**
570 * ixgbe_write_phy_reg - Write PHY register
571 * @hw: pointer to hardware structure
572 * @reg_addr: 32 bit PHY register to write
573 * @device_type: type of device you want to communicate with
574 * @phy_data: Data to write to the PHY register
575 *
576 * Writes a value to specified PHY register
577 **/
578 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
579 u16 phy_data)
580 {
581 if (hw->phy.id == 0)
582 ixgbe_identify_phy(hw);
583
584 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
585 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
586 }
587
588 /**
589 * ixgbe_setup_phy_link - Restart PHY autoneg
590 * @hw: pointer to hardware structure
591 *
592 * Restart autonegotiation and PHY and waits for completion.
593 **/
594 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
595 {
596 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
597 IXGBE_NOT_IMPLEMENTED);
598 }
599
600 /**
601 * ixgbe_setup_internal_phy - Configure integrated PHY
602 * @hw: pointer to hardware structure
603 *
604 * Reconfigure the integrated PHY in order to enable talk to the external PHY.
605 * Returns success if not implemented, since nothing needs to be done in this
606 * case.
607 */
608 s32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw)
609 {
610 return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw),
611 IXGBE_SUCCESS);
612 }
613
614 /**
615 * ixgbe_check_phy_link - Determine link and speed status
616 * @hw: pointer to hardware structure
617 * @speed: link speed
618 * @link_up: true when link is up
619 *
620 * Reads a PHY register to determine if link is up and the current speed for
621 * the PHY.
622 **/
623 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
624 bool *link_up)
625 {
626 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
627 link_up), IXGBE_NOT_IMPLEMENTED);
628 }
629
630 /**
631 * ixgbe_setup_phy_link_speed - Set auto advertise
632 * @hw: pointer to hardware structure
633 * @speed: new link speed
634 * @autoneg_wait_to_complete: true when waiting for completion is needed
635 *
636 * Sets the auto advertised capabilities
637 **/
638 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
639 bool autoneg_wait_to_complete)
640 {
641 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
642 autoneg_wait_to_complete),
643 IXGBE_NOT_IMPLEMENTED);
644 }
645
646 /**
647 * ixgbe_set_phy_power - Control the phy power state
648 * @hw: pointer to hardware structure
649 * @on: true for on, false for off
650 */
651 s32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on)
652 {
653 return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on),
654 IXGBE_NOT_IMPLEMENTED);
655 }
656
657 /**
658 * ixgbe_check_link - Get link and speed status
659 * @hw: pointer to hardware structure
660 * @speed: pointer to link speed
661 * @link_up: true when link is up
662 * @link_up_wait_to_complete: bool used to wait for link up or not
663 *
664 * Reads the links register to determine if link is up and the current speed
665 **/
666 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
667 bool *link_up, bool link_up_wait_to_complete)
668 {
669 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
670 link_up, link_up_wait_to_complete),
671 IXGBE_NOT_IMPLEMENTED);
672 }
673
674 /**
675 * ixgbe_disable_tx_laser - Disable Tx laser
676 * @hw: pointer to hardware structure
677 *
678 * If the driver needs to disable the laser on SFI optics.
679 **/
680 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
681 {
682 if (hw->mac.ops.disable_tx_laser)
683 hw->mac.ops.disable_tx_laser(hw);
684 }
685
686 /**
687 * ixgbe_enable_tx_laser - Enable Tx laser
688 * @hw: pointer to hardware structure
689 *
690 * If the driver needs to enable the laser on SFI optics.
691 **/
692 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
693 {
694 if (hw->mac.ops.enable_tx_laser)
695 hw->mac.ops.enable_tx_laser(hw);
696 }
697
698 /**
699 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
700 * @hw: pointer to hardware structure
701 *
702 * When the driver changes the link speeds that it can support then
703 * flap the tx laser to alert the link partner to start autotry
704 * process on its end.
705 **/
706 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
707 {
708 if (hw->mac.ops.flap_tx_laser)
709 hw->mac.ops.flap_tx_laser(hw);
710 }
711
712 /**
713 * ixgbe_setup_link - Set link speed
714 * @hw: pointer to hardware structure
715 * @speed: new link speed
716 * @autoneg_wait_to_complete: true when waiting for completion is needed
717 *
718 * Configures link settings. Restarts the link.
719 * Performs autonegotiation if needed.
720 **/
721 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
722 bool autoneg_wait_to_complete)
723 {
724 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
725 autoneg_wait_to_complete),
726 IXGBE_NOT_IMPLEMENTED);
727 }
728
729 /**
730 * ixgbe_setup_mac_link - Set link speed
731 * @hw: pointer to hardware structure
732 * @speed: new link speed
733 * @autoneg_wait_to_complete: true when waiting for completion is needed
734 *
735 * Configures link settings. Restarts the link.
736 * Performs autonegotiation if needed.
737 **/
738 s32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
739 bool autoneg_wait_to_complete)
740 {
741 return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed,
742 autoneg_wait_to_complete),
743 IXGBE_NOT_IMPLEMENTED);
744 }
745
746 /**
747 * ixgbe_get_link_capabilities - Returns link capabilities
748 * @hw: pointer to hardware structure
749 * @speed: link speed capabilities
750 * @autoneg: true when autoneg or autotry is enabled
751 *
752 * Determines the link capabilities of the current configuration.
753 **/
754 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
755 bool *autoneg)
756 {
757 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
758 speed, autoneg), IXGBE_NOT_IMPLEMENTED);
759 }
760
761 /**
762 * ixgbe_led_on - Turn on LEDs
763 * @hw: pointer to hardware structure
764 * @index: led number to turn on
765 *
766 * Turns on the software controllable LEDs.
767 **/
768 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
769 {
770 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
771 IXGBE_NOT_IMPLEMENTED);
772 }
773
774 /**
775 * ixgbe_led_off - Turn off LEDs
776 * @hw: pointer to hardware structure
777 * @index: led number to turn off
778 *
779 * Turns off the software controllable LEDs.
780 **/
781 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
782 {
783 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
784 IXGBE_NOT_IMPLEMENTED);
785 }
786
787 /**
788 * ixgbe_blink_led_start - Blink LEDs
789 * @hw: pointer to hardware structure
790 * @index: led number to blink
791 *
792 * Blink LED based on index.
793 **/
794 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
795 {
796 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
797 IXGBE_NOT_IMPLEMENTED);
798 }
799
800 /**
801 * ixgbe_blink_led_stop - Stop blinking LEDs
802 * @hw: pointer to hardware structure
803 * @index: led number to stop
804 *
805 * Stop blinking LED based on index.
806 **/
807 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
808 {
809 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
810 IXGBE_NOT_IMPLEMENTED);
811 }
812
813 /**
814 * ixgbe_init_eeprom_params - Initialize EEPROM parameters
815 * @hw: pointer to hardware structure
816 *
817 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
818 * ixgbe_hw struct in order to set up EEPROM access.
819 **/
820 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
821 {
822 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
823 IXGBE_NOT_IMPLEMENTED);
824 }
825
826
827 /**
828 * ixgbe_write_eeprom - Write word to EEPROM
829 * @hw: pointer to hardware structure
830 * @offset: offset within the EEPROM to be written to
831 * @data: 16 bit word to be written to the EEPROM
832 *
833 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
834 * called after this function, the EEPROM will most likely contain an
835 * invalid checksum.
836 **/
837 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
838 {
839 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
840 IXGBE_NOT_IMPLEMENTED);
841 }
842
843 /**
844 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
845 * @hw: pointer to hardware structure
846 * @offset: offset within the EEPROM to be written to
847 * @data: 16 bit word(s) to be written to the EEPROM
848 * @words: number of words
849 *
850 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
851 * called after this function, the EEPROM will most likely contain an
852 * invalid checksum.
853 **/
854 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
855 u16 *data)
856 {
857 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
858 (hw, offset, words, data),
859 IXGBE_NOT_IMPLEMENTED);
860 }
861
862 /**
863 * ixgbe_read_eeprom - Read word from EEPROM
864 * @hw: pointer to hardware structure
865 * @offset: offset within the EEPROM to be read
866 * @data: read 16 bit value from EEPROM
867 *
868 * Reads 16 bit value from EEPROM
869 **/
870 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
871 {
872 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
873 IXGBE_NOT_IMPLEMENTED);
874 }
875
876 /**
877 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
878 * @hw: pointer to hardware structure
879 * @offset: offset within the EEPROM to be read
880 * @data: read 16 bit word(s) from EEPROM
881 * @words: number of words
882 *
883 * Reads 16 bit word(s) from EEPROM
884 **/
885 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
886 u16 words, u16 *data)
887 {
888 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
889 (hw, offset, words, data),
890 IXGBE_NOT_IMPLEMENTED);
891 }
892
893 /**
894 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
895 * @hw: pointer to hardware structure
896 * @checksum_val: calculated checksum
897 *
898 * Performs checksum calculation and validates the EEPROM checksum
899 **/
900 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
901 {
902 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
903 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
904 }
905
906 /**
907 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
908 * @hw: pointer to hardware structure
909 **/
910 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
911 {
912 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
913 IXGBE_NOT_IMPLEMENTED);
914 }
915
916 /**
917 * ixgbe_insert_mac_addr - Find a RAR for this mac address
918 * @hw: pointer to hardware structure
919 * @addr: Address to put into receive address register
920 * @vmdq: VMDq pool to assign
921 *
922 * Puts an ethernet address into a receive address register, or
923 * finds the rar that it is aleady in; adds to the pool list
924 **/
925 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
926 {
927 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
928 (hw, addr, vmdq),
929 IXGBE_NOT_IMPLEMENTED);
930 }
931
932 /**
933 * ixgbe_set_rar - Set Rx address register
934 * @hw: pointer to hardware structure
935 * @index: Receive address register to write
936 * @addr: Address to put into receive address register
937 * @vmdq: VMDq "set"
938 * @enable_addr: set flag that address is active
939 *
940 * Puts an ethernet address into a receive address register.
941 **/
942 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
943 u32 enable_addr)
944 {
945 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
946 enable_addr), IXGBE_NOT_IMPLEMENTED);
947 }
948
949 /**
950 * ixgbe_clear_rar - Clear Rx address register
951 * @hw: pointer to hardware structure
952 * @index: Receive address register to write
953 *
954 * Puts an ethernet address into a receive address register.
955 **/
956 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
957 {
958 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
959 IXGBE_NOT_IMPLEMENTED);
960 }
961
962 /**
963 * ixgbe_set_vmdq - Associate a VMDq index with a receive address
964 * @hw: pointer to hardware structure
965 * @rar: receive address register index to associate with VMDq index
966 * @vmdq: VMDq set or pool index
967 **/
968 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
969 {
970 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
971 IXGBE_NOT_IMPLEMENTED);
972
973 }
974
975 /**
976 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
977 * @hw: pointer to hardware structure
978 * @vmdq: VMDq default pool index
979 **/
980 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
981 {
982 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
983 (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
984 }
985
986 /**
987 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
988 * @hw: pointer to hardware structure
989 * @rar: receive address register index to disassociate with VMDq index
990 * @vmdq: VMDq set or pool index
991 **/
992 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
993 {
994 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
995 IXGBE_NOT_IMPLEMENTED);
996 }
997
998 /**
999 * ixgbe_init_rx_addrs - Initializes receive address filters.
1000 * @hw: pointer to hardware structure
1001 *
1002 * Places the MAC address in receive address register 0 and clears the rest
1003 * of the receive address registers. Clears the multicast table. Assumes
1004 * the receiver is in reset when the routine is called.
1005 **/
1006 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
1007 {
1008 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
1009 IXGBE_NOT_IMPLEMENTED);
1010 }
1011
1012 /**
1013 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
1014 * @hw: pointer to hardware structure
1015 **/
1016 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
1017 {
1018 return hw->mac.num_rar_entries;
1019 }
1020
1021 /**
1022 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
1023 * @hw: pointer to hardware structure
1024 * @addr_list: the list of new multicast addresses
1025 * @addr_count: number of addresses
1026 * @func: iterator function to walk the multicast address list
1027 *
1028 * The given list replaces any existing list. Clears the secondary addrs from
1029 * receive address registers. Uses unused receive address registers for the
1030 * first secondary addresses, and falls back to promiscuous mode as needed.
1031 **/
1032 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
1033 u32 addr_count, ixgbe_mc_addr_itr func)
1034 {
1035 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
1036 addr_list, addr_count, func),
1037 IXGBE_NOT_IMPLEMENTED);
1038 }
1039
1040 /**
1041 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
1042 * @hw: pointer to hardware structure
1043 * @mc_addr_list: the list of new multicast addresses
1044 * @mc_addr_count: number of addresses
1045 * @func: iterator function to walk the multicast address list
1046 * @clear: flag, when set clears the table beforehand
1047 *
1048 * The given list replaces any existing list. Clears the MC addrs from receive
1049 * address registers and the multicast table. Uses unused receive address
1050 * registers for the first multicast addresses, and hashes the rest into the
1051 * multicast table.
1052 **/
1053 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
1054 u32 mc_addr_count, ixgbe_mc_addr_itr func,
1055 bool clear)
1056 {
1057 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
1058 mc_addr_list, mc_addr_count, func, clear),
1059 IXGBE_NOT_IMPLEMENTED);
1060 }
1061
1062 /**
1063 * ixgbe_enable_mc - Enable multicast address in RAR
1064 * @hw: pointer to hardware structure
1065 *
1066 * Enables multicast address in RAR and the use of the multicast hash table.
1067 **/
1068 s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
1069 {
1070 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
1071 IXGBE_NOT_IMPLEMENTED);
1072 }
1073
1074 /**
1075 * ixgbe_disable_mc - Disable multicast address in RAR
1076 * @hw: pointer to hardware structure
1077 *
1078 * Disables multicast address in RAR and the use of the multicast hash table.
1079 **/
1080 s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
1081 {
1082 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
1083 IXGBE_NOT_IMPLEMENTED);
1084 }
1085
1086 /**
1087 * ixgbe_clear_vfta - Clear VLAN filter table
1088 * @hw: pointer to hardware structure
1089 *
1090 * Clears the VLAN filer table, and the VMDq index associated with the filter
1091 **/
1092 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
1093 {
1094 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
1095 IXGBE_NOT_IMPLEMENTED);
1096 }
1097
1098 /**
1099 * ixgbe_set_vfta - Set VLAN filter table
1100 * @hw: pointer to hardware structure
1101 * @vlan: VLAN id to write to VLAN filter
1102 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1103 * @vlan_on: boolean flag to turn on/off VLAN
1104 * @vlvf_bypass: boolean flag indicating updating the default pool is okay
1105 *
1106 * Turn on/off specified VLAN in the VLAN filter table.
1107 **/
1108 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
1109 bool vlvf_bypass)
1110 {
1111 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
1112 vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED);
1113 }
1114
1115 /**
1116 * ixgbe_set_vlvf - Set VLAN Pool Filter
1117 * @hw: pointer to hardware structure
1118 * @vlan: VLAN id to write to VLAN filter
1119 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1120 * @vlan_on: boolean flag to turn on/off VLAN in VLVF
1121 * @vfta_delta: pointer to the difference between the current value of VFTA
1122 * and the desired value
1123 * @vfta: the desired value of the VFTA
1124 * @vlvf_bypass: boolean flag indicating updating the default pool is okay
1125 *
1126 * Turn on/off specified bit in VLVF table.
1127 **/
1128 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
1129 u32 *vfta_delta, u32 vfta, bool vlvf_bypass)
1130 {
1131 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
1132 vlan_on, vfta_delta, vfta, vlvf_bypass),
1133 IXGBE_NOT_IMPLEMENTED);
1134 }
1135
1136 /**
1137 * ixgbe_fc_enable - Enable flow control
1138 * @hw: pointer to hardware structure
1139 *
1140 * Configures the flow control settings based on SW configuration.
1141 **/
1142 s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
1143 {
1144 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
1145 IXGBE_NOT_IMPLEMENTED);
1146 }
1147
1148 /**
1149 * ixgbe_setup_fc - Set up flow control
1150 * @hw: pointer to hardware structure
1151 *
1152 * Called at init time to set up flow control.
1153 **/
1154 s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
1155 {
1156 return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw),
1157 IXGBE_NOT_IMPLEMENTED);
1158 }
1159
1160 /**
1161 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
1162 * @hw: pointer to hardware structure
1163 * @maj: driver major number to be sent to firmware
1164 * @min: driver minor number to be sent to firmware
1165 * @build: driver build number to be sent to firmware
1166 * @ver: driver version number to be sent to firmware
1167 * @len: length of driver_ver string
1168 * @driver_ver: driver string
1169 **/
1170 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
1171 u8 ver, u16 len, char *driver_ver)
1172 {
1173 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1174 build, ver, len, driver_ver),
1175 IXGBE_NOT_IMPLEMENTED);
1176 }
1177
1178
1179 /**
1180 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
1181 * @hw: pointer to hardware structure
1182 *
1183 * Updates the temperatures in mac.thermal_sensor_data
1184 **/
1185 s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw)
1186 {
1187 return ixgbe_call_func(hw, hw->mac.ops.get_thermal_sensor_data, (hw),
1188 IXGBE_NOT_IMPLEMENTED);
1189 }
1190
1191 /**
1192 * ixgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1193 * @hw: pointer to hardware structure
1194 *
1195 * Inits the thermal sensor thresholds according to the NVM map
1196 **/
1197 s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw)
1198 {
1199 return ixgbe_call_func(hw, hw->mac.ops.init_thermal_sensor_thresh, (hw),
1200 IXGBE_NOT_IMPLEMENTED);
1201 }
1202
1203 /**
1204 * ixgbe_dmac_config - Configure DMA Coalescing registers.
1205 * @hw: pointer to hardware structure
1206 *
1207 * Configure DMA coalescing. If enabling dmac, dmac is activated.
1208 * When disabling dmac, dmac enable dmac bit is cleared.
1209 **/
1210 s32 ixgbe_dmac_config(struct ixgbe_hw *hw)
1211 {
1212 return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw),
1213 IXGBE_NOT_IMPLEMENTED);
1214 }
1215
1216 /**
1217 * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers.
1218 * @hw: pointer to hardware structure
1219 *
1220 * Disables dmac, updates per TC settings, and then enable dmac.
1221 **/
1222 s32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw)
1223 {
1224 return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw),
1225 IXGBE_NOT_IMPLEMENTED);
1226 }
1227
1228 /**
1229 * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers.
1230 * @hw: pointer to hardware structure
1231 *
1232 * Configure DMA coalescing threshold per TC and set high priority bit for
1233 * FCOE TC. The dmac enable bit must be cleared before configuring.
1234 **/
1235 s32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw)
1236 {
1237 return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw),
1238 IXGBE_NOT_IMPLEMENTED);
1239 }
1240
1241 /**
1242 * ixgbe_setup_eee - Enable/disable EEE support
1243 * @hw: pointer to the HW structure
1244 * @enable_eee: boolean flag to enable EEE
1245 *
1246 * Enable/disable EEE based on enable_ee flag.
1247 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C
1248 * are modified.
1249 *
1250 **/
1251 s32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee)
1252 {
1253 return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee),
1254 IXGBE_NOT_IMPLEMENTED);
1255 }
1256
1257 /**
1258 * ixgbe_set_source_address_pruning - Enable/Disable source address pruning
1259 * @hw: pointer to hardware structure
1260 * @enable: enable or disable source address pruning
1261 * @pool: Rx pool - Rx pool to toggle source address pruning
1262 **/
1263 void ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable,
1264 unsigned int pool)
1265 {
1266 if (hw->mac.ops.set_source_address_pruning)
1267 hw->mac.ops.set_source_address_pruning(hw, enable, pool);
1268 }
1269
1270 /**
1271 * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing
1272 * @hw: pointer to hardware structure
1273 * @enable: enable or disable switch for Ethertype anti-spoofing
1274 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1275 *
1276 **/
1277 void ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
1278 {
1279 if (hw->mac.ops.set_ethertype_anti_spoofing)
1280 hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf);
1281 }
1282
1283 /**
1284 * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register
1285 * @hw: pointer to hardware structure
1286 * @reg_addr: 32 bit address of PHY register to read
1287 * @device_type: type of device you want to communicate with
1288 * @phy_data: Pointer to read data from PHY register
1289 *
1290 * Reads a value from a specified PHY register
1291 **/
1292 s32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
1293 u32 device_type, u32 *phy_data)
1294 {
1295 return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr,
1296 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
1297 }
1298
1299 /**
1300 * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband
1301 * @hw: pointer to hardware structure
1302 * @reg_addr: 32 bit PHY register to write
1303 * @device_type: type of device you want to communicate with
1304 * @phy_data: Data to write to the PHY register
1305 *
1306 * Writes a value to specified PHY register
1307 **/
1308 s32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr,
1309 u32 device_type, u32 phy_data)
1310 {
1311 return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr,
1312 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
1313 }
1314
1315 /**
1316 * ixgbe_disable_mdd - Disable malicious driver detection
1317 * @hw: pointer to hardware structure
1318 *
1319 **/
1320 void ixgbe_disable_mdd(struct ixgbe_hw *hw)
1321 {
1322 if (hw->mac.ops.disable_mdd)
1323 hw->mac.ops.disable_mdd(hw);
1324 }
1325
1326 /**
1327 * ixgbe_enable_mdd - Enable malicious driver detection
1328 * @hw: pointer to hardware structure
1329 *
1330 **/
1331 void ixgbe_enable_mdd(struct ixgbe_hw *hw)
1332 {
1333 if (hw->mac.ops.enable_mdd)
1334 hw->mac.ops.enable_mdd(hw);
1335 }
1336
1337 /**
1338 * ixgbe_mdd_event - Handle malicious driver detection event
1339 * @hw: pointer to hardware structure
1340 * @vf_bitmap: vf bitmap of malicious vfs
1341 *
1342 **/
1343 void ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap)
1344 {
1345 if (hw->mac.ops.mdd_event)
1346 hw->mac.ops.mdd_event(hw, vf_bitmap);
1347 }
1348
1349 /**
1350 * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver
1351 * detection event
1352 * @hw: pointer to hardware structure
1353 * @vf: vf index
1354 *
1355 **/
1356 void ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf)
1357 {
1358 if (hw->mac.ops.restore_mdd_vf)
1359 hw->mac.ops.restore_mdd_vf(hw, vf);
1360 }
1361
1362 /**
1363 * ixgbe_enter_lplu - Transition to low power states
1364 * @hw: pointer to hardware structure
1365 *
1366 * Configures Low Power Link Up on transition to low power states
1367 * (from D0 to non-D0).
1368 **/
1369 s32 ixgbe_enter_lplu(struct ixgbe_hw *hw)
1370 {
1371 return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw),
1372 IXGBE_NOT_IMPLEMENTED);
1373 }
1374
1375 /**
1376 * ixgbe_handle_lasi - Handle external Base T PHY interrupt
1377 * @hw: pointer to hardware structure
1378 *
1379 * Handle external Base T PHY interrupt. If high temperature
1380 * failure alarm then return error, else if link status change
1381 * then setup internal/external PHY link
1382 *
1383 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1384 * failure alarm, else return PHY access status.
1385 */
1386 s32 ixgbe_handle_lasi(struct ixgbe_hw *hw)
1387 {
1388 return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw),
1389 IXGBE_NOT_IMPLEMENTED);
1390 }
1391
1392 /**
1393 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
1394 * @hw: pointer to hardware structure
1395 * @reg: analog register to read
1396 * @val: read value
1397 *
1398 * Performs write operation to analog register specified.
1399 **/
1400 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1401 {
1402 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
1403 val), IXGBE_NOT_IMPLEMENTED);
1404 }
1405
1406 /**
1407 * ixgbe_write_analog_reg8 - Writes 8 bit analog register
1408 * @hw: pointer to hardware structure
1409 * @reg: analog register to write
1410 * @val: value to write
1411 *
1412 * Performs write operation to Atlas analog register specified.
1413 **/
1414 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
1415 {
1416 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
1417 val), IXGBE_NOT_IMPLEMENTED);
1418 }
1419
1420 /**
1421 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
1422 * @hw: pointer to hardware structure
1423 *
1424 * Initializes the Unicast Table Arrays to zero on device load. This
1425 * is part of the Rx init addr execution path.
1426 **/
1427 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
1428 {
1429 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
1430 IXGBE_NOT_IMPLEMENTED);
1431 }
1432
1433 /**
1434 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
1435 * @hw: pointer to hardware structure
1436 * @byte_offset: byte offset to read
1437 * @dev_addr: I2C bus address to read from
1438 * @data: value read
1439 *
1440 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1441 **/
1442 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1443 u8 *data)
1444 {
1445 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
1446 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1447 }
1448
1449 /**
1450 * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address
1451 * @hw: pointer to hardware structure
1452 * @byte_offset: byte offset to read
1453 * @dev_addr: I2C bus address to read from
1454 * @data: value read
1455 *
1456 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1457 **/
1458 s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1459 u8 dev_addr, u8 *data)
1460 {
1461 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked,
1462 (hw, byte_offset, dev_addr, data),
1463 IXGBE_NOT_IMPLEMENTED);
1464 }
1465
1466 /**
1467 * ixgbe_read_link - Perform read operation on link device
1468 * @hw: pointer to the hardware structure
1469 * @addr: bus address to read from
1470 * @reg: device register to read from
1471 * @val: pointer to location to receive read value
1472 *
1473 * Returns an error code on error.
1474 */
1475 s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
1476 {
1477 return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr,
1478 reg, val), IXGBE_NOT_IMPLEMENTED);
1479 }
1480
1481 /**
1482 * ixgbe_read_link_unlocked - Perform read operation on link device
1483 * @hw: pointer to the hardware structure
1484 * @addr: bus address to read from
1485 * @reg: device register to read from
1486 * @val: pointer to location to receive read value
1487 *
1488 * Returns an error code on error.
1489 **/
1490 s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)
1491 {
1492 return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked,
1493 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1494 }
1495
1496 /**
1497 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1498 * @hw: pointer to hardware structure
1499 * @byte_offset: byte offset to write
1500 * @dev_addr: I2C bus address to write to
1501 * @data: value to write
1502 *
1503 * Performs byte write operation to SFP module's EEPROM over I2C interface
1504 * at a specified device address.
1505 **/
1506 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1507 u8 data)
1508 {
1509 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
1510 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1511 }
1512
1513 /**
1514 * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
1515 * @hw: pointer to hardware structure
1516 * @byte_offset: byte offset to write
1517 * @dev_addr: I2C bus address to write to
1518 * @data: value to write
1519 *
1520 * Performs byte write operation to SFP module's EEPROM over I2C interface
1521 * at a specified device address.
1522 **/
1523 s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1524 u8 dev_addr, u8 data)
1525 {
1526 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked,
1527 (hw, byte_offset, dev_addr, data),
1528 IXGBE_NOT_IMPLEMENTED);
1529 }
1530
1531 /**
1532 * ixgbe_write_link - Perform write operation on link device
1533 * @hw: pointer to the hardware structure
1534 * @addr: bus address to write to
1535 * @reg: device register to write to
1536 * @val: value to write
1537 *
1538 * Returns an error code on error.
1539 */
1540 s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
1541 {
1542 return ixgbe_call_func(hw, hw->link.ops.write_link,
1543 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1544 }
1545
1546 /**
1547 * ixgbe_write_link_unlocked - Perform write operation on link device
1548 * @hw: pointer to the hardware structure
1549 * @addr: bus address to write to
1550 * @reg: device register to write to
1551 * @val: value to write
1552 *
1553 * Returns an error code on error.
1554 **/
1555 s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)
1556 {
1557 return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked,
1558 (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED);
1559 }
1560
1561 /**
1562 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1563 * @hw: pointer to hardware structure
1564 * @byte_offset: EEPROM byte offset to write
1565 * @eeprom_data: value to write
1566 *
1567 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1568 **/
1569 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
1570 u8 byte_offset, u8 eeprom_data)
1571 {
1572 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
1573 (hw, byte_offset, eeprom_data),
1574 IXGBE_NOT_IMPLEMENTED);
1575 }
1576
1577 /**
1578 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1579 * @hw: pointer to hardware structure
1580 * @byte_offset: EEPROM byte offset to read
1581 * @eeprom_data: value read
1582 *
1583 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1584 **/
1585 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
1586 {
1587 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
1588 (hw, byte_offset, eeprom_data),
1589 IXGBE_NOT_IMPLEMENTED);
1590 }
1591
1592 /**
1593 * ixgbe_get_supported_physical_layer - Returns physical layer type
1594 * @hw: pointer to hardware structure
1595 *
1596 * Determines physical layer capabilities of the current configuration.
1597 **/
1598 u64 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
1599 {
1600 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
1601 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1602 }
1603
1604 /**
1605 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
1606 * @hw: pointer to hardware structure
1607 * @regval: bitfield to write to the Rx DMA register
1608 *
1609 * Enables the Rx DMA unit of the device.
1610 **/
1611 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
1612 {
1613 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
1614 (hw, regval), IXGBE_NOT_IMPLEMENTED);
1615 }
1616
1617 /**
1618 * ixgbe_disable_sec_rx_path - Stops the receive data path
1619 * @hw: pointer to hardware structure
1620 *
1621 * Stops the receive data path.
1622 **/
1623 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
1624 {
1625 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
1626 (hw), IXGBE_NOT_IMPLEMENTED);
1627 }
1628
1629 /**
1630 * ixgbe_enable_sec_rx_path - Enables the receive data path
1631 * @hw: pointer to hardware structure
1632 *
1633 * Enables the receive data path.
1634 **/
1635 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
1636 {
1637 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
1638 (hw), IXGBE_NOT_IMPLEMENTED);
1639 }
1640
1641 /**
1642 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
1643 * @hw: pointer to hardware structure
1644 * @mask: Mask to specify which semaphore to acquire
1645 *
1646 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
1647 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1648 **/
1649 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1650 {
1651 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
1652 (hw, mask), IXGBE_NOT_IMPLEMENTED);
1653 }
1654
1655 /**
1656 * ixgbe_release_swfw_semaphore - Release SWFW semaphore
1657 * @hw: pointer to hardware structure
1658 * @mask: Mask to specify which semaphore to release
1659 *
1660 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
1661 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1662 **/
1663 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)
1664 {
1665 if (hw->mac.ops.release_swfw_sync)
1666 hw->mac.ops.release_swfw_sync(hw, mask);
1667 }
1668
1669 /**
1670 * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore
1671 * @hw: pointer to hardware structure
1672 *
1673 * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register.
1674 * Regardless of whether is succeeds or not it then release the semaphore.
1675 * This is function is called to recover from catastrophic failures that
1676 * may have left the semaphore locked.
1677 **/
1678 void ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw)
1679 {
1680 if (hw->mac.ops.init_swfw_sync)
1681 hw->mac.ops.init_swfw_sync(hw);
1682 }
1683
1684
1685 void ixgbe_disable_rx(struct ixgbe_hw *hw)
1686 {
1687 if (hw->mac.ops.disable_rx)
1688 hw->mac.ops.disable_rx(hw);
1689 }
1690
1691 void ixgbe_enable_rx(struct ixgbe_hw *hw)
1692 {
1693 if (hw->mac.ops.enable_rx)
1694 hw->mac.ops.enable_rx(hw);
1695 }
1696
1697 /**
1698 * ixgbe_set_rate_select_speed - Set module link speed
1699 * @hw: pointer to hardware structure
1700 * @speed: link speed to set
1701 *
1702 * Set module link speed via the rate select.
1703 */
1704 void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)
1705 {
1706 if (hw->mac.ops.set_rate_select_speed)
1707 hw->mac.ops.set_rate_select_speed(hw, speed);
1708 }