ceph/src/spdk/dpdk/drivers/net/ixgbe/base/ixgbe_osdep.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2018
   3  */
   4
   5 #ifndef _IXGBE_OS_H_
   6 #define _IXGBE_OS_H_
   7
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdio.h>
  11 #include <stdarg.h>
  12 #include <rte_common.h>
  13 #include <rte_debug.h>
  14 #include <rte_cycles.h>
  15 #include <rte_log.h>
  16 #include <rte_byteorder.h>
  17 #include <rte_io.h>
  18
  19 #include "../ixgbe_logs.h"
  20 #include "../ixgbe_bypass_defines.h"
  21
  22 #define ASSERT(x) if(!(x)) rte_panic("IXGBE: x")
  23
  24 #define DELAY(x) rte_delay_us_sleep(x)
  25 #define usec_delay(x) DELAY(x)
  26 #define msec_delay(x) DELAY(1000*(x))
  27
  28 #define DEBUGFUNC(F)            DEBUGOUT(F "\n");
  29 #define DEBUGOUT(S, args...)    PMD_DRV_LOG_RAW(DEBUG, S, ##args)
  30 #define DEBUGOUT1(S, args...)   DEBUGOUT(S, ##args)
  31 #define DEBUGOUT2(S, args...)   DEBUGOUT(S, ##args)
  32 #define DEBUGOUT3(S, args...)   DEBUGOUT(S, ##args)
  33 #define DEBUGOUT6(S, args...)   DEBUGOUT(S, ##args)
  34 #define DEBUGOUT7(S, args...)   DEBUGOUT(S, ##args)
  35
  36 #define ERROR_REPORT1(e, S, args...)   DEBUGOUT(S, ##args)
  37 #define ERROR_REPORT2(e, S, args...)   DEBUGOUT(S, ##args)
  38 #define ERROR_REPORT3(e, S, args...)   DEBUGOUT(S, ##args)
  39
  40 #define FALSE               0
  41 #define TRUE                1
  42
  43 #define false               0
  44 #define true                1
  45 #define min(a,b)        RTE_MIN(a,b)
  46
  47 #define EWARN(hw, S, args...)     DEBUGOUT1(S, ##args)
  48
  49 /* Bunch of defines for shared code bogosity */
  50 #define UNREFERENCED_PARAMETER(_p)
  51 #define UNREFERENCED_1PARAMETER(_p)
  52 #define UNREFERENCED_2PARAMETER(_p, _q)
  53 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
  54 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
  55 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t)
  56
  57 /* Shared code error reporting */
  58 enum {
  59         IXGBE_ERROR_SOFTWARE,
  60         IXGBE_ERROR_POLLING,
  61         IXGBE_ERROR_INVALID_STATE,
  62         IXGBE_ERROR_UNSUPPORTED,
  63         IXGBE_ERROR_ARGUMENT,
  64         IXGBE_ERROR_CAUTION,
  65 };
  66
  67 #define STATIC static
  68 #define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i)
  69 #define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i)
  70 #define IXGBE_CPU_TO_LE16(_i)  rte_cpu_to_le_16(_i)
  71 #define IXGBE_CPU_TO_LE32(_i)  rte_cpu_to_le_32(_i)
  72 #define IXGBE_LE32_TO_CPU(_i)  rte_le_to_cpu_32(_i)
  73 #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)
  74 #define IXGBE_CPU_TO_BE16(_i)  rte_cpu_to_be_16(_i)
  75 #define IXGBE_CPU_TO_BE32(_i)  rte_cpu_to_be_32(_i)
  76 #define IXGBE_BE32_TO_CPU(_i)  rte_be_to_cpu_32(_i)
  77
  78 typedef uint8_t         u8;
  79 typedef int8_t          s8;
  80 typedef uint16_t        u16;
  81 typedef int16_t         s16;
  82 typedef uint32_t        u32;
  83 typedef int32_t         s32;
  84 typedef uint64_t        u64;
  85 #ifndef __cplusplus
  86 typedef int             bool;
  87 #endif
  88
  89 #define mb()    rte_mb()
  90 #define wmb()   rte_wmb()
  91 #define rmb()   rte_rmb()
  92
  93 #define IOMEM
  94
  95 #define prefetch(x) rte_prefetch0(x)
  96
  97 #define IXGBE_PCI_REG(reg) rte_read32(reg)
  98
  99 static inline uint32_t ixgbe_read_addr(volatile void* addr)
 100 {
 101         return rte_le_to_cpu_32(IXGBE_PCI_REG(addr));
 102 }
 103
 104 #define IXGBE_PCI_REG_WRITE(reg, value)                 \
 105         rte_write32((rte_cpu_to_le_32(value)), reg)
 106
 107 #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value)         \
 108         rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
 109
 110 #define IXGBE_PCI_REG_ADDR(hw, reg) \
 111         ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
 112
 113 #define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \
 114         IXGBE_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
 115
 116 /* Not implemented !! */
 117 #define IXGBE_READ_PCIE_WORD(hw, reg) 0
 118 #define IXGBE_WRITE_PCIE_WORD(hw, reg, value) do { } while(0)
 119
 120 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
 121
 122 #define IXGBE_READ_REG(hw, reg) \
 123         ixgbe_read_addr(IXGBE_PCI_REG_ADDR((hw), (reg)))
 124
 125 #define IXGBE_WRITE_REG(hw, reg, value) \
 126         IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ADDR((hw), (reg)), (value))
 127
 128 #define IXGBE_READ_REG_ARRAY(hw, reg, index) \
 129         IXGBE_PCI_REG(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
 130
 131 #define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \
 132         IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
 133
 134 #define IXGBE_WRITE_REG_THEN_POLL_MASK(hw, reg, val, mask, poll_ms)     \
 135 do {                                                                    \
 136         uint32_t cnt = poll_ms;                                         \
 137         IXGBE_WRITE_REG(hw, (reg), (val));                              \
 138         while (((IXGBE_READ_REG(hw, (reg))) & (mask)) && (cnt--))       \
 139                 rte_delay_ms(1);                                        \
 140 } while (0)
 141
 142 #endif /* _IXGBE_OS_H_ */