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update sources to ceph Nautilus 14.2.1
[ceph.git] / ceph / src / spdk / dpdk / drivers / net / ixgbe / base / ixgbe_phy.c
1 /*******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ***************************************************************************/
33
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
50 u8 *sff8472_data);
51
52 /**
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
55 * @byte: byte to send
56 *
57 * Returns an error code on error.
58 */
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
60 {
61 s32 status;
62
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
64 if (status)
65 return status;
66 return ixgbe_get_i2c_ack(hw);
67 }
68
69 /**
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
73 *
74 * Returns an error code on error.
75 */
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
77 {
78 s32 status;
79
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
81 if (status)
82 return status;
83 /* ACK */
84 return ixgbe_clock_out_i2c_bit(hw, false);
85 }
86
87 /**
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
89 * @add1: addend 1
90 * @add2: addend 2
91 *
92 * Returns one's complement 8-bit sum.
93 */
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
95 {
96 u16 sum = add1 + add2;
97
98 sum = (sum & 0xFF) + (sum >> 8);
99 return sum & 0xFF;
100 }
101
102 /**
103 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
108 * @lock: true if to take and release semaphore
109 *
110 * Returns an error code on error.
111 */
112 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
113 u16 *val, bool lock)
114 {
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
116 int max_retry = 3;
117 int retry = 0;
118 u8 csum_byte;
119 u8 high_bits;
120 u8 low_bits;
121 u8 reg_high;
122 u8 csum;
123
124 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
125 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
126 csum = ~csum;
127 do {
128 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
129 return IXGBE_ERR_SWFW_SYNC;
130 ixgbe_i2c_start(hw);
131 /* Device Address and write indication */
132 if (ixgbe_out_i2c_byte_ack(hw, addr))
133 goto fail;
134 /* Write bits 14:8 */
135 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
136 goto fail;
137 /* Write bits 7:0 */
138 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
139 goto fail;
140 /* Write csum */
141 if (ixgbe_out_i2c_byte_ack(hw, csum))
142 goto fail;
143 /* Re-start condition */
144 ixgbe_i2c_start(hw);
145 /* Device Address and read indication */
146 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
147 goto fail;
148 /* Get upper bits */
149 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
150 goto fail;
151 /* Get low bits */
152 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
153 goto fail;
154 /* Get csum */
155 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
156 goto fail;
157 /* NACK */
158 if (ixgbe_clock_out_i2c_bit(hw, false))
159 goto fail;
160 ixgbe_i2c_stop(hw);
161 if (lock)
162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
163 *val = (high_bits << 8) | low_bits;
164 return 0;
165
166 fail:
167 ixgbe_i2c_bus_clear(hw);
168 if (lock)
169 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
170 retry++;
171 if (retry < max_retry)
172 DEBUGOUT("I2C byte read combined error - Retrying.\n");
173 else
174 DEBUGOUT("I2C byte read combined error.\n");
175 } while (retry < max_retry);
176
177 return IXGBE_ERR_I2C;
178 }
179
180 /**
181 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
182 * @hw: pointer to the hardware structure
183 * @addr: I2C bus address to write to
184 * @reg: I2C device register to write to
185 * @val: value to write
186 * @lock: true if to take and release semaphore
187 *
188 * Returns an error code on error.
189 */
190 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
191 u16 val, bool lock)
192 {
193 u32 swfw_mask = hw->phy.phy_semaphore_mask;
194 int max_retry = 1;
195 int retry = 0;
196 u8 reg_high;
197 u8 csum;
198
199 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
200 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
201 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
202 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
203 csum = ~csum;
204 do {
205 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
206 return IXGBE_ERR_SWFW_SYNC;
207 ixgbe_i2c_start(hw);
208 /* Device Address and write indication */
209 if (ixgbe_out_i2c_byte_ack(hw, addr))
210 goto fail;
211 /* Write bits 14:8 */
212 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
213 goto fail;
214 /* Write bits 7:0 */
215 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
216 goto fail;
217 /* Write data 15:8 */
218 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
219 goto fail;
220 /* Write data 7:0 */
221 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
222 goto fail;
223 /* Write csum */
224 if (ixgbe_out_i2c_byte_ack(hw, csum))
225 goto fail;
226 ixgbe_i2c_stop(hw);
227 if (lock)
228 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
229 return 0;
230
231 fail:
232 ixgbe_i2c_bus_clear(hw);
233 if (lock)
234 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
235 retry++;
236 if (retry < max_retry)
237 DEBUGOUT("I2C byte write combined error - Retrying.\n");
238 else
239 DEBUGOUT("I2C byte write combined error.\n");
240 } while (retry < max_retry);
241
242 return IXGBE_ERR_I2C;
243 }
244
245 /**
246 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
247 * @hw: pointer to the hardware structure
248 *
249 * Initialize the function pointers.
250 **/
251 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
252 {
253 struct ixgbe_phy_info *phy = &hw->phy;
254
255 DEBUGFUNC("ixgbe_init_phy_ops_generic");
256
257 /* PHY */
258 phy->ops.identify = ixgbe_identify_phy_generic;
259 phy->ops.reset = ixgbe_reset_phy_generic;
260 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
261 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
262 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
263 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
264 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
265 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
266 phy->ops.check_link = NULL;
267 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
268 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
269 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
270 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
271 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
272 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
273 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
274 phy->ops.identify_sfp = ixgbe_identify_module_generic;
275 phy->sfp_type = ixgbe_sfp_type_unknown;
276 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
277 phy->ops.write_i2c_byte_unlocked =
278 ixgbe_write_i2c_byte_generic_unlocked;
279 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
280 return IXGBE_SUCCESS;
281 }
282
283 /**
284 * ixgbe_probe_phy - Probe a single address for a PHY
285 * @hw: pointer to hardware structure
286 * @phy_addr: PHY address to probe
287 *
288 * Returns true if PHY found
289 */
290 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
291 {
292 u16 ext_ability = 0;
293
294 if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
295 DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
296 phy_addr);
297 return false;
298 }
299
300 if (ixgbe_get_phy_id(hw))
301 return false;
302
303 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
304
305 if (hw->phy.type == ixgbe_phy_unknown) {
306 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
307 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
308 if (ext_ability &
309 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
310 IXGBE_MDIO_PHY_1000BASET_ABILITY))
311 hw->phy.type = ixgbe_phy_cu_unknown;
312 else
313 hw->phy.type = ixgbe_phy_generic;
314 }
315
316 return true;
317 }
318
319 /**
320 * ixgbe_identify_phy_generic - Get physical layer module
321 * @hw: pointer to hardware structure
322 *
323 * Determines the physical layer module found on the current adapter.
324 **/
325 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
326 {
327 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
328 u16 phy_addr;
329
330 DEBUGFUNC("ixgbe_identify_phy_generic");
331
332 if (!hw->phy.phy_semaphore_mask) {
333 if (hw->bus.lan_id)
334 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
335 else
336 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
337 }
338
339 if (hw->phy.type != ixgbe_phy_unknown)
340 return IXGBE_SUCCESS;
341
342 if (hw->phy.nw_mng_if_sel) {
343 phy_addr = (hw->phy.nw_mng_if_sel &
344 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
345 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
346 if (ixgbe_probe_phy(hw, phy_addr))
347 return IXGBE_SUCCESS;
348 else
349 return IXGBE_ERR_PHY_ADDR_INVALID;
350 }
351
352 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
353 if (ixgbe_probe_phy(hw, phy_addr)) {
354 status = IXGBE_SUCCESS;
355 break;
356 }
357 }
358
359 /* Certain media types do not have a phy so an address will not
360 * be found and the code will take this path. Caller has to
361 * decide if it is an error or not.
362 */
363 if (status != IXGBE_SUCCESS)
364 hw->phy.addr = 0;
365
366 return status;
367 }
368
369 /**
370 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
371 * @hw: pointer to the hardware structure
372 *
373 * This function checks the MMNGC.MNG_VETO bit to see if there are
374 * any constraints on link from manageability. For MAC's that don't
375 * have this bit just return faluse since the link can not be blocked
376 * via this method.
377 **/
378 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
379 {
380 u32 mmngc;
381
382 DEBUGFUNC("ixgbe_check_reset_blocked");
383
384 /* If we don't have this bit, it can't be blocking */
385 if (hw->mac.type == ixgbe_mac_82598EB)
386 return false;
387
388 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
389 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
390 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
391 "MNG_VETO bit detected.\n");
392 return true;
393 }
394
395 return false;
396 }
397
398 /**
399 * ixgbe_validate_phy_addr - Determines phy address is valid
400 * @hw: pointer to hardware structure
401 * @phy_addr: PHY address
402 *
403 **/
404 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
405 {
406 u16 phy_id = 0;
407 bool valid = false;
408
409 DEBUGFUNC("ixgbe_validate_phy_addr");
410
411 hw->phy.addr = phy_addr;
412 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
413 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
414
415 if (phy_id != 0xFFFF && phy_id != 0x0)
416 valid = true;
417
418 DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
419
420 return valid;
421 }
422
423 /**
424 * ixgbe_get_phy_id - Get the phy type
425 * @hw: pointer to hardware structure
426 *
427 **/
428 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
429 {
430 u32 status;
431 u16 phy_id_high = 0;
432 u16 phy_id_low = 0;
433
434 DEBUGFUNC("ixgbe_get_phy_id");
435
436 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
437 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
438 &phy_id_high);
439
440 if (status == IXGBE_SUCCESS) {
441 hw->phy.id = (u32)(phy_id_high << 16);
442 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
443 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
444 &phy_id_low);
445 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
446 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
447 }
448 DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
449 phy_id_high, phy_id_low);
450
451 return status;
452 }
453
454 /**
455 * ixgbe_get_phy_type_from_id - Get the phy type
456 * @phy_id: PHY ID information
457 *
458 **/
459 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
460 {
461 enum ixgbe_phy_type phy_type;
462
463 DEBUGFUNC("ixgbe_get_phy_type_from_id");
464
465 switch (phy_id) {
466 case TN1010_PHY_ID:
467 phy_type = ixgbe_phy_tn;
468 break;
469 case X550_PHY_ID2:
470 case X550_PHY_ID3:
471 case X540_PHY_ID:
472 phy_type = ixgbe_phy_aq;
473 break;
474 case QT2022_PHY_ID:
475 phy_type = ixgbe_phy_qt;
476 break;
477 case ATH_PHY_ID:
478 phy_type = ixgbe_phy_nl;
479 break;
480 case X557_PHY_ID:
481 case X557_PHY_ID2:
482 phy_type = ixgbe_phy_x550em_ext_t;
483 break;
484 case IXGBE_M88E1500_E_PHY_ID:
485 case IXGBE_M88E1543_E_PHY_ID:
486 phy_type = ixgbe_phy_ext_1g_t;
487 break;
488 default:
489 phy_type = ixgbe_phy_unknown;
490 break;
491 }
492 return phy_type;
493 }
494
495 /**
496 * ixgbe_reset_phy_generic - Performs a PHY reset
497 * @hw: pointer to hardware structure
498 **/
499 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
500 {
501 u32 i;
502 u16 ctrl = 0;
503 s32 status = IXGBE_SUCCESS;
504
505 DEBUGFUNC("ixgbe_reset_phy_generic");
506
507 if (hw->phy.type == ixgbe_phy_unknown)
508 status = ixgbe_identify_phy_generic(hw);
509
510 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
511 goto out;
512
513 /* Don't reset PHY if it's shut down due to overtemp. */
514 if (!hw->phy.reset_if_overtemp &&
515 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
516 goto out;
517
518 /* Blocked by MNG FW so bail */
519 if (ixgbe_check_reset_blocked(hw))
520 goto out;
521
522 /*
523 * Perform soft PHY reset to the PHY_XS.
524 * This will cause a soft reset to the PHY
525 */
526 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
527 IXGBE_MDIO_PHY_XS_DEV_TYPE,
528 IXGBE_MDIO_PHY_XS_RESET);
529
530 /*
531 * Poll for reset bit to self-clear indicating reset is complete.
532 * Some PHYs could take up to 3 seconds to complete and need about
533 * 1.7 usec delay after the reset is complete.
534 */
535 for (i = 0; i < 30; i++) {
536 msec_delay(100);
537 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
538 status = hw->phy.ops.read_reg(hw,
539 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
540 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
541 &ctrl);
542 if (status != IXGBE_SUCCESS)
543 return status;
544
545 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
546 usec_delay(2);
547 break;
548 }
549 } else {
550 status = hw->phy.ops.read_reg(hw,
551 IXGBE_MDIO_PHY_XS_CONTROL,
552 IXGBE_MDIO_PHY_XS_DEV_TYPE,
553 &ctrl);
554 if (status != IXGBE_SUCCESS)
555 return status;
556
557 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
558 usec_delay(2);
559 break;
560 }
561 }
562 }
563
564 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
565 status = IXGBE_ERR_RESET_FAILED;
566 ERROR_REPORT1(IXGBE_ERROR_POLLING,
567 "PHY reset polling failed to complete.\n");
568 }
569
570 out:
571 return status;
572 }
573
574 /**
575 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
576 * the SWFW lock
577 * @hw: pointer to hardware structure
578 * @reg_addr: 32 bit address of PHY register to read
579 * @device_type: 5 bit device type
580 * @phy_data: Pointer to read data from PHY register
581 **/
582 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
583 u16 *phy_data)
584 {
585 u32 i, data, command;
586
587 /* Setup and write the address cycle command */
588 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
589 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
590 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
591 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
592
593 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
594
595 /*
596 * Check every 10 usec to see if the address cycle completed.
597 * The MDI Command bit will clear when the operation is
598 * complete
599 */
600 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
601 usec_delay(10);
602
603 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
604 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
605 break;
606 }
607
608
609 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
610 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
611 DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
612 return IXGBE_ERR_PHY;
613 }
614
615 /*
616 * Address cycle complete, setup and write the read
617 * command
618 */
619 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
620 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
621 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
622 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
623
624 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
625
626 /*
627 * Check every 10 usec to see if the address cycle
628 * completed. The MDI Command bit will clear when the
629 * operation is complete
630 */
631 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
632 usec_delay(10);
633
634 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
635 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
636 break;
637 }
638
639 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
640 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
641 DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
642 return IXGBE_ERR_PHY;
643 }
644
645 /*
646 * Read operation is complete. Get the data
647 * from MSRWD
648 */
649 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
650 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
651 *phy_data = (u16)(data);
652
653 return IXGBE_SUCCESS;
654 }
655
656 /**
657 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
658 * using the SWFW lock - this function is needed in most cases
659 * @hw: pointer to hardware structure
660 * @reg_addr: 32 bit address of PHY register to read
661 * @device_type: 5 bit device type
662 * @phy_data: Pointer to read data from PHY register
663 **/
664 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
665 u32 device_type, u16 *phy_data)
666 {
667 s32 status;
668 u32 gssr = hw->phy.phy_semaphore_mask;
669
670 DEBUGFUNC("ixgbe_read_phy_reg_generic");
671
672 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
673 return IXGBE_ERR_SWFW_SYNC;
674
675 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
676
677 hw->mac.ops.release_swfw_sync(hw, gssr);
678
679 return status;
680 }
681
682 /**
683 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
684 * without SWFW lock
685 * @hw: pointer to hardware structure
686 * @reg_addr: 32 bit PHY register to write
687 * @device_type: 5 bit device type
688 * @phy_data: Data to write to the PHY register
689 **/
690 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
691 u32 device_type, u16 phy_data)
692 {
693 u32 i, command;
694
695 /* Put the data in the MDI single read and write data register*/
696 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
697
698 /* Setup and write the address cycle command */
699 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
700 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
701 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
702 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
703
704 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
705
706 /*
707 * Check every 10 usec to see if the address cycle completed.
708 * The MDI Command bit will clear when the operation is
709 * complete
710 */
711 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
712 usec_delay(10);
713
714 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
715 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
716 break;
717 }
718
719 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
720 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
721 return IXGBE_ERR_PHY;
722 }
723
724 /*
725 * Address cycle complete, setup and write the write
726 * command
727 */
728 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
729 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
730 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
731 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
732
733 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
734
735 /*
736 * Check every 10 usec to see if the address cycle
737 * completed. The MDI Command bit will clear when the
738 * operation is complete
739 */
740 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
741 usec_delay(10);
742
743 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
744 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
745 break;
746 }
747
748 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
749 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
750 return IXGBE_ERR_PHY;
751 }
752
753 return IXGBE_SUCCESS;
754 }
755
756 /**
757 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
758 * using SWFW lock- this function is needed in most cases
759 * @hw: pointer to hardware structure
760 * @reg_addr: 32 bit PHY register to write
761 * @device_type: 5 bit device type
762 * @phy_data: Data to write to the PHY register
763 **/
764 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
765 u32 device_type, u16 phy_data)
766 {
767 s32 status;
768 u32 gssr = hw->phy.phy_semaphore_mask;
769
770 DEBUGFUNC("ixgbe_write_phy_reg_generic");
771
772 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
773 status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
774 phy_data);
775 hw->mac.ops.release_swfw_sync(hw, gssr);
776 } else {
777 status = IXGBE_ERR_SWFW_SYNC;
778 }
779
780 return status;
781 }
782
783 /**
784 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
785 * @hw: pointer to hardware structure
786 *
787 * Restart auto-negotiation and PHY and waits for completion.
788 **/
789 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
790 {
791 s32 status = IXGBE_SUCCESS;
792 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
793 bool autoneg = false;
794 ixgbe_link_speed speed;
795
796 DEBUGFUNC("ixgbe_setup_phy_link_generic");
797
798 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
799
800 /* Set or unset auto-negotiation 10G advertisement */
801 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
802 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
803 &autoneg_reg);
804
805 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
806 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
807 (speed & IXGBE_LINK_SPEED_10GB_FULL))
808 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
809
810 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
811 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
812 autoneg_reg);
813
814 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
815 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
816 &autoneg_reg);
817
818 if (hw->mac.type == ixgbe_mac_X550) {
819 /* Set or unset auto-negotiation 5G advertisement */
820 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
821 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
822 (speed & IXGBE_LINK_SPEED_5GB_FULL))
823 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
824
825 /* Set or unset auto-negotiation 2.5G advertisement */
826 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
827 if ((hw->phy.autoneg_advertised &
828 IXGBE_LINK_SPEED_2_5GB_FULL) &&
829 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
830 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
831 }
832
833 /* Set or unset auto-negotiation 1G advertisement */
834 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
835 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
836 (speed & IXGBE_LINK_SPEED_1GB_FULL))
837 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
838
839 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
840 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
841 autoneg_reg);
842
843 /* Set or unset auto-negotiation 100M advertisement */
844 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
845 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
846 &autoneg_reg);
847
848 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
849 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
850 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
851 (speed & IXGBE_LINK_SPEED_100_FULL))
852 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
853
854 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
855 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
856 autoneg_reg);
857
858 /* Blocked by MNG FW so don't reset PHY */
859 if (ixgbe_check_reset_blocked(hw))
860 return status;
861
862 /* Restart PHY auto-negotiation. */
863 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
864 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
865
866 autoneg_reg |= IXGBE_MII_RESTART;
867
868 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
869 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
870
871 return status;
872 }
873
874 /**
875 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
876 * @hw: pointer to hardware structure
877 * @speed: new link speed
878 * @autoneg_wait_to_complete: unused
879 **/
880 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
881 ixgbe_link_speed speed,
882 bool autoneg_wait_to_complete)
883 {
884 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
885
886 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
887
888 /*
889 * Clear autoneg_advertised and set new values based on input link
890 * speed.
891 */
892 hw->phy.autoneg_advertised = 0;
893
894 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
895 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
896
897 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
898 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
899
900 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
901 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
902
903 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
904 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
905
906 if (speed & IXGBE_LINK_SPEED_100_FULL)
907 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
908
909 if (speed & IXGBE_LINK_SPEED_10_FULL)
910 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
911
912 /* Setup link based on the new speed settings */
913 ixgbe_setup_phy_link(hw);
914
915 return IXGBE_SUCCESS;
916 }
917
918 /**
919 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
920 * @hw: pointer to hardware structure
921 *
922 * Determines the supported link capabilities by reading the PHY auto
923 * negotiation register.
924 **/
925 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
926 {
927 s32 status;
928 u16 speed_ability;
929
930 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
931 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
932 &speed_ability);
933 if (status)
934 return status;
935
936 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
937 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
938 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
939 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
940 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
941 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
942
943 switch (hw->mac.type) {
944 case ixgbe_mac_X550:
945 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
946 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
947 break;
948 case ixgbe_mac_X550EM_x:
949 case ixgbe_mac_X550EM_a:
950 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
951 break;
952 default:
953 break;
954 }
955
956 return status;
957 }
958
959 /**
960 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
961 * @hw: pointer to hardware structure
962 * @speed: pointer to link speed
963 * @autoneg: boolean auto-negotiation value
964 **/
965 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
966 ixgbe_link_speed *speed,
967 bool *autoneg)
968 {
969 s32 status = IXGBE_SUCCESS;
970
971 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
972
973 *autoneg = true;
974 if (!hw->phy.speeds_supported)
975 status = ixgbe_get_copper_speeds_supported(hw);
976
977 *speed = hw->phy.speeds_supported;
978 return status;
979 }
980
981 /**
982 * ixgbe_check_phy_link_tnx - Determine link and speed status
983 * @hw: pointer to hardware structure
984 * @speed: current link speed
985 * @link_up: true is link is up, false otherwise
986 *
987 * Reads the VS1 register to determine if link is up and the current speed for
988 * the PHY.
989 **/
990 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
991 bool *link_up)
992 {
993 s32 status = IXGBE_SUCCESS;
994 u32 time_out;
995 u32 max_time_out = 10;
996 u16 phy_link = 0;
997 u16 phy_speed = 0;
998 u16 phy_data = 0;
999
1000 DEBUGFUNC("ixgbe_check_phy_link_tnx");
1001
1002 /* Initialize speed and link to default case */
1003 *link_up = false;
1004 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1005
1006 /*
1007 * Check current speed and link status of the PHY register.
1008 * This is a vendor specific register and may have to
1009 * be changed for other copper PHYs.
1010 */
1011 for (time_out = 0; time_out < max_time_out; time_out++) {
1012 usec_delay(10);
1013 status = hw->phy.ops.read_reg(hw,
1014 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1015 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1016 &phy_data);
1017 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1018 phy_speed = phy_data &
1019 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1020 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1021 *link_up = true;
1022 if (phy_speed ==
1023 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1024 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1025 break;
1026 }
1027 }
1028
1029 return status;
1030 }
1031
1032 /**
1033 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1034 * @hw: pointer to hardware structure
1035 *
1036 * Restart auto-negotiation and PHY and waits for completion.
1037 **/
1038 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1039 {
1040 s32 status = IXGBE_SUCCESS;
1041 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1042 bool autoneg = false;
1043 ixgbe_link_speed speed;
1044
1045 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1046
1047 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1048
1049 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1050 /* Set or unset auto-negotiation 10G advertisement */
1051 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1052 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1053 &autoneg_reg);
1054
1055 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1056 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1057 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1058
1059 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1060 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1061 autoneg_reg);
1062 }
1063
1064 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1065 /* Set or unset auto-negotiation 1G advertisement */
1066 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1067 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1068 &autoneg_reg);
1069
1070 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1071 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1072 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1073
1074 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1075 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1076 autoneg_reg);
1077 }
1078
1079 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1080 /* Set or unset auto-negotiation 100M advertisement */
1081 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1082 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1083 &autoneg_reg);
1084
1085 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1086 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1087 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1088
1089 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1090 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1091 autoneg_reg);
1092 }
1093
1094 /* Blocked by MNG FW so don't reset PHY */
1095 if (ixgbe_check_reset_blocked(hw))
1096 return status;
1097
1098 /* Restart PHY auto-negotiation. */
1099 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1100 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1101
1102 autoneg_reg |= IXGBE_MII_RESTART;
1103
1104 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1105 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1106
1107 return status;
1108 }
1109
1110 /**
1111 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1112 * @hw: pointer to hardware structure
1113 * @firmware_version: pointer to the PHY Firmware Version
1114 **/
1115 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1116 u16 *firmware_version)
1117 {
1118 s32 status;
1119
1120 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1121
1122 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1123 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1124 firmware_version);
1125
1126 return status;
1127 }
1128
1129 /**
1130 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1131 * @hw: pointer to hardware structure
1132 * @firmware_version: pointer to the PHY Firmware Version
1133 **/
1134 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1135 u16 *firmware_version)
1136 {
1137 s32 status;
1138
1139 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1140
1141 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1142 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1143 firmware_version);
1144
1145 return status;
1146 }
1147
1148 /**
1149 * ixgbe_reset_phy_nl - Performs a PHY reset
1150 * @hw: pointer to hardware structure
1151 **/
1152 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1153 {
1154 u16 phy_offset, control, eword, edata, block_crc;
1155 bool end_data = false;
1156 u16 list_offset, data_offset;
1157 u16 phy_data = 0;
1158 s32 ret_val = IXGBE_SUCCESS;
1159 u32 i;
1160
1161 DEBUGFUNC("ixgbe_reset_phy_nl");
1162
1163 /* Blocked by MNG FW so bail */
1164 if (ixgbe_check_reset_blocked(hw))
1165 goto out;
1166
1167 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1168 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1169
1170 /* reset the PHY and poll for completion */
1171 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1172 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1173 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1174
1175 for (i = 0; i < 100; i++) {
1176 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1177 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1178 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1179 break;
1180 msec_delay(10);
1181 }
1182
1183 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1184 DEBUGOUT("PHY reset did not complete.\n");
1185 ret_val = IXGBE_ERR_PHY;
1186 goto out;
1187 }
1188
1189 /* Get init offsets */
1190 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1191 &data_offset);
1192 if (ret_val != IXGBE_SUCCESS)
1193 goto out;
1194
1195 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1196 data_offset++;
1197 while (!end_data) {
1198 /*
1199 * Read control word from PHY init contents offset
1200 */
1201 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1202 if (ret_val)
1203 goto err_eeprom;
1204 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1205 IXGBE_CONTROL_SHIFT_NL;
1206 edata = eword & IXGBE_DATA_MASK_NL;
1207 switch (control) {
1208 case IXGBE_DELAY_NL:
1209 data_offset++;
1210 DEBUGOUT1("DELAY: %d MS\n", edata);
1211 msec_delay(edata);
1212 break;
1213 case IXGBE_DATA_NL:
1214 DEBUGOUT("DATA:\n");
1215 data_offset++;
1216 ret_val = hw->eeprom.ops.read(hw, data_offset,
1217 &phy_offset);
1218 if (ret_val)
1219 goto err_eeprom;
1220 data_offset++;
1221 for (i = 0; i < edata; i++) {
1222 ret_val = hw->eeprom.ops.read(hw, data_offset,
1223 &eword);
1224 if (ret_val)
1225 goto err_eeprom;
1226 hw->phy.ops.write_reg(hw, phy_offset,
1227 IXGBE_TWINAX_DEV, eword);
1228 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1229 phy_offset);
1230 data_offset++;
1231 phy_offset++;
1232 }
1233 break;
1234 case IXGBE_CONTROL_NL:
1235 data_offset++;
1236 DEBUGOUT("CONTROL:\n");
1237 if (edata == IXGBE_CONTROL_EOL_NL) {
1238 DEBUGOUT("EOL\n");
1239 end_data = true;
1240 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1241 DEBUGOUT("SOL\n");
1242 } else {
1243 DEBUGOUT("Bad control value\n");
1244 ret_val = IXGBE_ERR_PHY;
1245 goto out;
1246 }
1247 break;
1248 default:
1249 DEBUGOUT("Bad control type\n");
1250 ret_val = IXGBE_ERR_PHY;
1251 goto out;
1252 }
1253 }
1254
1255 out:
1256 return ret_val;
1257
1258 err_eeprom:
1259 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1260 "eeprom read at offset %d failed", data_offset);
1261 return IXGBE_ERR_PHY;
1262 }
1263
1264 /**
1265 * ixgbe_identify_module_generic - Identifies module type
1266 * @hw: pointer to hardware structure
1267 *
1268 * Determines HW type and calls appropriate function.
1269 **/
1270 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1271 {
1272 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1273
1274 DEBUGFUNC("ixgbe_identify_module_generic");
1275
1276 switch (hw->mac.ops.get_media_type(hw)) {
1277 case ixgbe_media_type_fiber:
1278 status = ixgbe_identify_sfp_module_generic(hw);
1279 break;
1280
1281 case ixgbe_media_type_fiber_qsfp:
1282 status = ixgbe_identify_qsfp_module_generic(hw);
1283 break;
1284
1285 default:
1286 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1287 status = IXGBE_ERR_SFP_NOT_PRESENT;
1288 break;
1289 }
1290
1291 return status;
1292 }
1293
1294 /**
1295 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1296 * @hw: pointer to hardware structure
1297 *
1298 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1299 **/
1300 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1301 {
1302 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1303 u32 vendor_oui = 0;
1304 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1305 u8 identifier = 0;
1306 u8 comp_codes_1g = 0;
1307 u8 comp_codes_10g = 0;
1308 u8 oui_bytes[3] = {0, 0, 0};
1309 u8 cable_tech = 0;
1310 u8 cable_spec = 0;
1311 u16 enforce_sfp = 0;
1312
1313 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1314
1315 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1316 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1317 status = IXGBE_ERR_SFP_NOT_PRESENT;
1318 goto out;
1319 }
1320
1321 /* LAN ID is needed for I2C access */
1322 hw->mac.ops.set_lan_id(hw);
1323
1324 status = hw->phy.ops.read_i2c_eeprom(hw,
1325 IXGBE_SFF_IDENTIFIER,
1326 &identifier);
1327
1328 if (status != IXGBE_SUCCESS)
1329 goto err_read_i2c_eeprom;
1330
1331 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1332 hw->phy.type = ixgbe_phy_sfp_unsupported;
1333 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1334 } else {
1335 status = hw->phy.ops.read_i2c_eeprom(hw,
1336 IXGBE_SFF_1GBE_COMP_CODES,
1337 &comp_codes_1g);
1338
1339 if (status != IXGBE_SUCCESS)
1340 goto err_read_i2c_eeprom;
1341
1342 status = hw->phy.ops.read_i2c_eeprom(hw,
1343 IXGBE_SFF_10GBE_COMP_CODES,
1344 &comp_codes_10g);
1345
1346 if (status != IXGBE_SUCCESS)
1347 goto err_read_i2c_eeprom;
1348 status = hw->phy.ops.read_i2c_eeprom(hw,
1349 IXGBE_SFF_CABLE_TECHNOLOGY,
1350 &cable_tech);
1351
1352 if (status != IXGBE_SUCCESS)
1353 goto err_read_i2c_eeprom;
1354
1355 /* ID Module
1356 * =========
1357 * 0 SFP_DA_CU
1358 * 1 SFP_SR
1359 * 2 SFP_LR
1360 * 3 SFP_DA_CORE0 - 82599-specific
1361 * 4 SFP_DA_CORE1 - 82599-specific
1362 * 5 SFP_SR/LR_CORE0 - 82599-specific
1363 * 6 SFP_SR/LR_CORE1 - 82599-specific
1364 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1365 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1366 * 9 SFP_1g_cu_CORE0 - 82599-specific
1367 * 10 SFP_1g_cu_CORE1 - 82599-specific
1368 * 11 SFP_1g_sx_CORE0 - 82599-specific
1369 * 12 SFP_1g_sx_CORE1 - 82599-specific
1370 */
1371 if (hw->mac.type == ixgbe_mac_82598EB) {
1372 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1373 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1374 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1375 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1376 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1377 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1378 else
1379 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1380 } else {
1381 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1382 if (hw->bus.lan_id == 0)
1383 hw->phy.sfp_type =
1384 ixgbe_sfp_type_da_cu_core0;
1385 else
1386 hw->phy.sfp_type =
1387 ixgbe_sfp_type_da_cu_core1;
1388 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1389 hw->phy.ops.read_i2c_eeprom(
1390 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1391 &cable_spec);
1392 if (cable_spec &
1393 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1394 if (hw->bus.lan_id == 0)
1395 hw->phy.sfp_type =
1396 ixgbe_sfp_type_da_act_lmt_core0;
1397 else
1398 hw->phy.sfp_type =
1399 ixgbe_sfp_type_da_act_lmt_core1;
1400 } else {
1401 hw->phy.sfp_type =
1402 ixgbe_sfp_type_unknown;
1403 }
1404 } else if (comp_codes_10g &
1405 (IXGBE_SFF_10GBASESR_CAPABLE |
1406 IXGBE_SFF_10GBASELR_CAPABLE)) {
1407 if (hw->bus.lan_id == 0)
1408 hw->phy.sfp_type =
1409 ixgbe_sfp_type_srlr_core0;
1410 else
1411 hw->phy.sfp_type =
1412 ixgbe_sfp_type_srlr_core1;
1413 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1414 if (hw->bus.lan_id == 0)
1415 hw->phy.sfp_type =
1416 ixgbe_sfp_type_1g_cu_core0;
1417 else
1418 hw->phy.sfp_type =
1419 ixgbe_sfp_type_1g_cu_core1;
1420 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1421 if (hw->bus.lan_id == 0)
1422 hw->phy.sfp_type =
1423 ixgbe_sfp_type_1g_sx_core0;
1424 else
1425 hw->phy.sfp_type =
1426 ixgbe_sfp_type_1g_sx_core1;
1427 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1428 if (hw->bus.lan_id == 0)
1429 hw->phy.sfp_type =
1430 ixgbe_sfp_type_1g_lx_core0;
1431 else
1432 hw->phy.sfp_type =
1433 ixgbe_sfp_type_1g_lx_core1;
1434 } else {
1435 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1436 }
1437 }
1438
1439 if (hw->phy.sfp_type != stored_sfp_type)
1440 hw->phy.sfp_setup_needed = true;
1441
1442 /* Determine if the SFP+ PHY is dual speed or not. */
1443 hw->phy.multispeed_fiber = false;
1444 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1445 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1446 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1447 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1448 hw->phy.multispeed_fiber = true;
1449
1450 /* Determine PHY vendor */
1451 if (hw->phy.type != ixgbe_phy_nl) {
1452 hw->phy.id = identifier;
1453 status = hw->phy.ops.read_i2c_eeprom(hw,
1454 IXGBE_SFF_VENDOR_OUI_BYTE0,
1455 &oui_bytes[0]);
1456
1457 if (status != IXGBE_SUCCESS)
1458 goto err_read_i2c_eeprom;
1459
1460 status = hw->phy.ops.read_i2c_eeprom(hw,
1461 IXGBE_SFF_VENDOR_OUI_BYTE1,
1462 &oui_bytes[1]);
1463
1464 if (status != IXGBE_SUCCESS)
1465 goto err_read_i2c_eeprom;
1466
1467 status = hw->phy.ops.read_i2c_eeprom(hw,
1468 IXGBE_SFF_VENDOR_OUI_BYTE2,
1469 &oui_bytes[2]);
1470
1471 if (status != IXGBE_SUCCESS)
1472 goto err_read_i2c_eeprom;
1473
1474 vendor_oui =
1475 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1476 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1477 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1478
1479 switch (vendor_oui) {
1480 case IXGBE_SFF_VENDOR_OUI_TYCO:
1481 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1482 hw->phy.type =
1483 ixgbe_phy_sfp_passive_tyco;
1484 break;
1485 case IXGBE_SFF_VENDOR_OUI_FTL:
1486 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1487 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1488 else
1489 hw->phy.type = ixgbe_phy_sfp_ftl;
1490 break;
1491 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1492 hw->phy.type = ixgbe_phy_sfp_avago;
1493 break;
1494 case IXGBE_SFF_VENDOR_OUI_INTEL:
1495 hw->phy.type = ixgbe_phy_sfp_intel;
1496 break;
1497 default:
1498 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1499 hw->phy.type =
1500 ixgbe_phy_sfp_passive_unknown;
1501 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1502 hw->phy.type =
1503 ixgbe_phy_sfp_active_unknown;
1504 else
1505 hw->phy.type = ixgbe_phy_sfp_unknown;
1506 break;
1507 }
1508 }
1509
1510 /* Allow any DA cable vendor */
1511 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1512 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1513 status = IXGBE_SUCCESS;
1514 goto out;
1515 }
1516
1517 /* Verify supported 1G SFP modules */
1518 if (comp_codes_10g == 0 &&
1519 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1520 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1521 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1522 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1523 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1524 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1525 hw->phy.type = ixgbe_phy_sfp_unsupported;
1526 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1527 goto out;
1528 }
1529
1530 /* Anything else 82598-based is supported */
1531 if (hw->mac.type == ixgbe_mac_82598EB) {
1532 status = IXGBE_SUCCESS;
1533 goto out;
1534 }
1535
1536 ixgbe_get_device_caps(hw, &enforce_sfp);
1537 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1538 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1539 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1540 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1541 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1542 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1543 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1544 /* Make sure we're a supported PHY type */
1545 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1546 status = IXGBE_SUCCESS;
1547 } else {
1548 if (hw->allow_unsupported_sfp == true) {
1549 EWARN(hw,
1550 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1551 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1552 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1553 status = IXGBE_SUCCESS;
1554 } else {
1555 DEBUGOUT("SFP+ module not supported\n");
1556 hw->phy.type =
1557 ixgbe_phy_sfp_unsupported;
1558 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1559 }
1560 }
1561 } else {
1562 status = IXGBE_SUCCESS;
1563 }
1564 }
1565
1566 out:
1567 return status;
1568
1569 err_read_i2c_eeprom:
1570 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1571 if (hw->phy.type != ixgbe_phy_nl) {
1572 hw->phy.id = 0;
1573 hw->phy.type = ixgbe_phy_unknown;
1574 }
1575 return IXGBE_ERR_SFP_NOT_PRESENT;
1576 }
1577
1578 /**
1579 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1580 * @hw: pointer to hardware structure
1581 *
1582 * Determines physical layer capabilities of the current SFP.
1583 */
1584 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1585 {
1586 u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1587 u8 comp_codes_10g = 0;
1588 u8 comp_codes_1g = 0;
1589
1590 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1591
1592 hw->phy.ops.identify_sfp(hw);
1593 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1594 return physical_layer;
1595
1596 switch (hw->phy.type) {
1597 case ixgbe_phy_sfp_passive_tyco:
1598 case ixgbe_phy_sfp_passive_unknown:
1599 case ixgbe_phy_qsfp_passive_unknown:
1600 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1601 break;
1602 case ixgbe_phy_sfp_ftl_active:
1603 case ixgbe_phy_sfp_active_unknown:
1604 case ixgbe_phy_qsfp_active_unknown:
1605 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1606 break;
1607 case ixgbe_phy_sfp_avago:
1608 case ixgbe_phy_sfp_ftl:
1609 case ixgbe_phy_sfp_intel:
1610 case ixgbe_phy_sfp_unknown:
1611 hw->phy.ops.read_i2c_eeprom(hw,
1612 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1613 hw->phy.ops.read_i2c_eeprom(hw,
1614 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1615 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1616 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1617 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1618 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1619 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1620 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1621 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1622 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1623 break;
1624 case ixgbe_phy_qsfp_intel:
1625 case ixgbe_phy_qsfp_unknown:
1626 hw->phy.ops.read_i2c_eeprom(hw,
1627 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1628 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1629 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1630 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1631 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1632 break;
1633 default:
1634 break;
1635 }
1636
1637 return physical_layer;
1638 }
1639
1640 /**
1641 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1642 * @hw: pointer to hardware structure
1643 *
1644 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1645 **/
1646 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1647 {
1648 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1649 u32 vendor_oui = 0;
1650 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1651 u8 identifier = 0;
1652 u8 comp_codes_1g = 0;
1653 u8 comp_codes_10g = 0;
1654 u8 oui_bytes[3] = {0, 0, 0};
1655 u16 enforce_sfp = 0;
1656 u8 connector = 0;
1657 u8 cable_length = 0;
1658 u8 device_tech = 0;
1659 bool active_cable = false;
1660
1661 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1662
1663 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1664 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1665 status = IXGBE_ERR_SFP_NOT_PRESENT;
1666 goto out;
1667 }
1668
1669 /* LAN ID is needed for I2C access */
1670 hw->mac.ops.set_lan_id(hw);
1671
1672 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1673 &identifier);
1674
1675 if (status != IXGBE_SUCCESS)
1676 goto err_read_i2c_eeprom;
1677
1678 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1679 hw->phy.type = ixgbe_phy_sfp_unsupported;
1680 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1681 goto out;
1682 }
1683
1684 hw->phy.id = identifier;
1685
1686 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1687 &comp_codes_10g);
1688
1689 if (status != IXGBE_SUCCESS)
1690 goto err_read_i2c_eeprom;
1691
1692 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1693 &comp_codes_1g);
1694
1695 if (status != IXGBE_SUCCESS)
1696 goto err_read_i2c_eeprom;
1697
1698 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1699 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1700 if (hw->bus.lan_id == 0)
1701 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1702 else
1703 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1704 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1705 IXGBE_SFF_10GBASELR_CAPABLE)) {
1706 if (hw->bus.lan_id == 0)
1707 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1708 else
1709 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1710 } else {
1711 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1712 active_cable = true;
1713
1714 if (!active_cable) {
1715 /* check for active DA cables that pre-date
1716 * SFF-8436 v3.6 */
1717 hw->phy.ops.read_i2c_eeprom(hw,
1718 IXGBE_SFF_QSFP_CONNECTOR,
1719 &connector);
1720
1721 hw->phy.ops.read_i2c_eeprom(hw,
1722 IXGBE_SFF_QSFP_CABLE_LENGTH,
1723 &cable_length);
1724
1725 hw->phy.ops.read_i2c_eeprom(hw,
1726 IXGBE_SFF_QSFP_DEVICE_TECH,
1727 &device_tech);
1728
1729 if ((connector ==
1730 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1731 (cable_length > 0) &&
1732 ((device_tech >> 4) ==
1733 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1734 active_cable = true;
1735 }
1736
1737 if (active_cable) {
1738 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1739 if (hw->bus.lan_id == 0)
1740 hw->phy.sfp_type =
1741 ixgbe_sfp_type_da_act_lmt_core0;
1742 else
1743 hw->phy.sfp_type =
1744 ixgbe_sfp_type_da_act_lmt_core1;
1745 } else {
1746 /* unsupported module type */
1747 hw->phy.type = ixgbe_phy_sfp_unsupported;
1748 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1749 goto out;
1750 }
1751 }
1752
1753 if (hw->phy.sfp_type != stored_sfp_type)
1754 hw->phy.sfp_setup_needed = true;
1755
1756 /* Determine if the QSFP+ PHY is dual speed or not. */
1757 hw->phy.multispeed_fiber = false;
1758 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1759 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1760 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1761 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1762 hw->phy.multispeed_fiber = true;
1763
1764 /* Determine PHY vendor for optical modules */
1765 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1766 IXGBE_SFF_10GBASELR_CAPABLE)) {
1767 status = hw->phy.ops.read_i2c_eeprom(hw,
1768 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1769 &oui_bytes[0]);
1770
1771 if (status != IXGBE_SUCCESS)
1772 goto err_read_i2c_eeprom;
1773
1774 status = hw->phy.ops.read_i2c_eeprom(hw,
1775 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1776 &oui_bytes[1]);
1777
1778 if (status != IXGBE_SUCCESS)
1779 goto err_read_i2c_eeprom;
1780
1781 status = hw->phy.ops.read_i2c_eeprom(hw,
1782 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1783 &oui_bytes[2]);
1784
1785 if (status != IXGBE_SUCCESS)
1786 goto err_read_i2c_eeprom;
1787
1788 vendor_oui =
1789 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1790 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1791 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1792
1793 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1794 hw->phy.type = ixgbe_phy_qsfp_intel;
1795 else
1796 hw->phy.type = ixgbe_phy_qsfp_unknown;
1797
1798 ixgbe_get_device_caps(hw, &enforce_sfp);
1799 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1800 /* Make sure we're a supported PHY type */
1801 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1802 status = IXGBE_SUCCESS;
1803 } else {
1804 if (hw->allow_unsupported_sfp == true) {
1805 EWARN(hw,
1806 "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. "
1807 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1808 "Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1809 status = IXGBE_SUCCESS;
1810 } else {
1811 DEBUGOUT("QSFP module not supported\n");
1812 hw->phy.type =
1813 ixgbe_phy_sfp_unsupported;
1814 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1815 }
1816 }
1817 } else {
1818 status = IXGBE_SUCCESS;
1819 }
1820 }
1821
1822 out:
1823 return status;
1824
1825 err_read_i2c_eeprom:
1826 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1827 hw->phy.id = 0;
1828 hw->phy.type = ixgbe_phy_unknown;
1829
1830 return IXGBE_ERR_SFP_NOT_PRESENT;
1831 }
1832
1833 /**
1834 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1835 * @hw: pointer to hardware structure
1836 * @list_offset: offset to the SFP ID list
1837 * @data_offset: offset to the SFP data block
1838 *
1839 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1840 * so it returns the offsets to the phy init sequence block.
1841 **/
1842 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1843 u16 *list_offset,
1844 u16 *data_offset)
1845 {
1846 u16 sfp_id;
1847 u16 sfp_type = hw->phy.sfp_type;
1848
1849 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1850
1851 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1852 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1853
1854 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1855 return IXGBE_ERR_SFP_NOT_PRESENT;
1856
1857 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1858 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1859 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1860
1861 /*
1862 * Limiting active cables and 1G Phys must be initialized as
1863 * SR modules
1864 */
1865 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1866 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1867 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1868 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1869 sfp_type = ixgbe_sfp_type_srlr_core0;
1870 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1871 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1872 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1873 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1874 sfp_type = ixgbe_sfp_type_srlr_core1;
1875
1876 /* Read offset to PHY init contents */
1877 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1878 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1879 "eeprom read at offset %d failed",
1880 IXGBE_PHY_INIT_OFFSET_NL);
1881 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1882 }
1883
1884 if ((!*list_offset) || (*list_offset == 0xFFFF))
1885 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1886
1887 /* Shift offset to first ID word */
1888 (*list_offset)++;
1889
1890 /*
1891 * Find the matching SFP ID in the EEPROM
1892 * and program the init sequence
1893 */
1894 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1895 goto err_phy;
1896
1897 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1898 if (sfp_id == sfp_type) {
1899 (*list_offset)++;
1900 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1901 goto err_phy;
1902 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1903 DEBUGOUT("SFP+ module not supported\n");
1904 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1905 } else {
1906 break;
1907 }
1908 } else {
1909 (*list_offset) += 2;
1910 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1911 goto err_phy;
1912 }
1913 }
1914
1915 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1916 DEBUGOUT("No matching SFP+ module found\n");
1917 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1918 }
1919
1920 return IXGBE_SUCCESS;
1921
1922 err_phy:
1923 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1924 "eeprom read at offset %d failed", *list_offset);
1925 return IXGBE_ERR_PHY;
1926 }
1927
1928 /**
1929 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1930 * @hw: pointer to hardware structure
1931 * @byte_offset: EEPROM byte offset to read
1932 * @eeprom_data: value read
1933 *
1934 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1935 **/
1936 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1937 u8 *eeprom_data)
1938 {
1939 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1940
1941 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1942 IXGBE_I2C_EEPROM_DEV_ADDR,
1943 eeprom_data);
1944 }
1945
1946 /**
1947 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1948 * @hw: pointer to hardware structure
1949 * @byte_offset: byte offset at address 0xA2
1950 * @sff8472_data: value read
1951 *
1952 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1953 **/
1954 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1955 u8 *sff8472_data)
1956 {
1957 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1958 IXGBE_I2C_EEPROM_DEV_ADDR2,
1959 sff8472_data);
1960 }
1961
1962 /**
1963 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1964 * @hw: pointer to hardware structure
1965 * @byte_offset: EEPROM byte offset to write
1966 * @eeprom_data: value to write
1967 *
1968 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1969 **/
1970 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1971 u8 eeprom_data)
1972 {
1973 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1974
1975 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1976 IXGBE_I2C_EEPROM_DEV_ADDR,
1977 eeprom_data);
1978 }
1979
1980 /**
1981 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1982 * @hw: pointer to hardware structure
1983 * @offset: eeprom offset to be read
1984 * @addr: I2C address to be read
1985 */
1986 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1987 {
1988 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1989 offset == IXGBE_SFF_IDENTIFIER &&
1990 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1991 return true;
1992 return false;
1993 }
1994
1995 /**
1996 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1997 * @hw: pointer to hardware structure
1998 * @byte_offset: byte offset to read
1999 * @dev_addr: address to read from
2000 * @data: value read
2001 * @lock: true if to take and release semaphore
2002 *
2003 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2004 * a specified device address.
2005 **/
2006 STATIC s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2007 u8 dev_addr, u8 *data, bool lock)
2008 {
2009 s32 status;
2010 u32 max_retry = 10;
2011 u32 retry = 0;
2012 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2013 bool nack = 1;
2014 *data = 0;
2015
2016 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2017
2018 if (hw->mac.type >= ixgbe_mac_X550)
2019 max_retry = 3;
2020 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2021 max_retry = IXGBE_SFP_DETECT_RETRIES;
2022
2023 do {
2024 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2025 return IXGBE_ERR_SWFW_SYNC;
2026
2027 ixgbe_i2c_start(hw);
2028
2029 /* Device Address and write indication */
2030 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2031 if (status != IXGBE_SUCCESS)
2032 goto fail;
2033
2034 status = ixgbe_get_i2c_ack(hw);
2035 if (status != IXGBE_SUCCESS)
2036 goto fail;
2037
2038 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2039 if (status != IXGBE_SUCCESS)
2040 goto fail;
2041
2042 status = ixgbe_get_i2c_ack(hw);
2043 if (status != IXGBE_SUCCESS)
2044 goto fail;
2045
2046 ixgbe_i2c_start(hw);
2047
2048 /* Device Address and read indication */
2049 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2050 if (status != IXGBE_SUCCESS)
2051 goto fail;
2052
2053 status = ixgbe_get_i2c_ack(hw);
2054 if (status != IXGBE_SUCCESS)
2055 goto fail;
2056
2057 status = ixgbe_clock_in_i2c_byte(hw, data);
2058 if (status != IXGBE_SUCCESS)
2059 goto fail;
2060
2061 status = ixgbe_clock_out_i2c_bit(hw, nack);
2062 if (status != IXGBE_SUCCESS)
2063 goto fail;
2064
2065 ixgbe_i2c_stop(hw);
2066 if (lock)
2067 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2068 return IXGBE_SUCCESS;
2069
2070 fail:
2071 ixgbe_i2c_bus_clear(hw);
2072 if (lock) {
2073 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2074 msec_delay(100);
2075 }
2076 retry++;
2077 if (retry < max_retry)
2078 DEBUGOUT("I2C byte read error - Retrying.\n");
2079 else
2080 DEBUGOUT("I2C byte read error.\n");
2081
2082 } while (retry < max_retry);
2083
2084 return status;
2085 }
2086
2087 /**
2088 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2089 * @hw: pointer to hardware structure
2090 * @byte_offset: byte offset to read
2091 * @dev_addr: address to read from
2092 * @data: value read
2093 *
2094 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2095 * a specified device address.
2096 **/
2097 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2098 u8 dev_addr, u8 *data)
2099 {
2100 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2101 data, true);
2102 }
2103
2104 /**
2105 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2106 * @hw: pointer to hardware structure
2107 * @byte_offset: byte offset to read
2108 * @dev_addr: address to read from
2109 * @data: value read
2110 *
2111 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2112 * a specified device address.
2113 **/
2114 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2115 u8 dev_addr, u8 *data)
2116 {
2117 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2118 data, false);
2119 }
2120
2121 /**
2122 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2123 * @hw: pointer to hardware structure
2124 * @byte_offset: byte offset to write
2125 * @dev_addr: address to write to
2126 * @data: value to write
2127 * @lock: true if to take and release semaphore
2128 *
2129 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2130 * a specified device address.
2131 **/
2132 STATIC s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2133 u8 dev_addr, u8 data, bool lock)
2134 {
2135 s32 status;
2136 u32 max_retry = 1;
2137 u32 retry = 0;
2138 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2139
2140 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2141
2142 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2143 IXGBE_SUCCESS)
2144 return IXGBE_ERR_SWFW_SYNC;
2145
2146 do {
2147 ixgbe_i2c_start(hw);
2148
2149 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2150 if (status != IXGBE_SUCCESS)
2151 goto fail;
2152
2153 status = ixgbe_get_i2c_ack(hw);
2154 if (status != IXGBE_SUCCESS)
2155 goto fail;
2156
2157 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2158 if (status != IXGBE_SUCCESS)
2159 goto fail;
2160
2161 status = ixgbe_get_i2c_ack(hw);
2162 if (status != IXGBE_SUCCESS)
2163 goto fail;
2164
2165 status = ixgbe_clock_out_i2c_byte(hw, data);
2166 if (status != IXGBE_SUCCESS)
2167 goto fail;
2168
2169 status = ixgbe_get_i2c_ack(hw);
2170 if (status != IXGBE_SUCCESS)
2171 goto fail;
2172
2173 ixgbe_i2c_stop(hw);
2174 if (lock)
2175 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2176 return IXGBE_SUCCESS;
2177
2178 fail:
2179 ixgbe_i2c_bus_clear(hw);
2180 retry++;
2181 if (retry < max_retry)
2182 DEBUGOUT("I2C byte write error - Retrying.\n");
2183 else
2184 DEBUGOUT("I2C byte write error.\n");
2185 } while (retry < max_retry);
2186
2187 if (lock)
2188 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2189
2190 return status;
2191 }
2192
2193 /**
2194 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2195 * @hw: pointer to hardware structure
2196 * @byte_offset: byte offset to write
2197 * @dev_addr: address to write to
2198 * @data: value to write
2199 *
2200 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2201 * a specified device address.
2202 **/
2203 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2204 u8 dev_addr, u8 data)
2205 {
2206 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2207 data, true);
2208 }
2209
2210 /**
2211 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2212 * @hw: pointer to hardware structure
2213 * @byte_offset: byte offset to write
2214 * @dev_addr: address to write to
2215 * @data: value to write
2216 *
2217 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2218 * a specified device address.
2219 **/
2220 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2221 u8 dev_addr, u8 data)
2222 {
2223 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2224 data, false);
2225 }
2226
2227 /**
2228 * ixgbe_i2c_start - Sets I2C start condition
2229 * @hw: pointer to hardware structure
2230 *
2231 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2232 * Set bit-bang mode on X550 hardware.
2233 **/
2234 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2235 {
2236 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2237
2238 DEBUGFUNC("ixgbe_i2c_start");
2239
2240 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2241
2242 /* Start condition must begin with data and clock high */
2243 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2244 ixgbe_raise_i2c_clk(hw, &i2cctl);
2245
2246 /* Setup time for start condition (4.7us) */
2247 usec_delay(IXGBE_I2C_T_SU_STA);
2248
2249 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2250
2251 /* Hold time for start condition (4us) */
2252 usec_delay(IXGBE_I2C_T_HD_STA);
2253
2254 ixgbe_lower_i2c_clk(hw, &i2cctl);
2255
2256 /* Minimum low period of clock is 4.7 us */
2257 usec_delay(IXGBE_I2C_T_LOW);
2258
2259 }
2260
2261 /**
2262 * ixgbe_i2c_stop - Sets I2C stop condition
2263 * @hw: pointer to hardware structure
2264 *
2265 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2266 * Disables bit-bang mode and negates data output enable on X550
2267 * hardware.
2268 **/
2269 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2270 {
2271 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2272 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2273 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2274 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2275
2276 DEBUGFUNC("ixgbe_i2c_stop");
2277
2278 /* Stop condition must begin with data low and clock high */
2279 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2280 ixgbe_raise_i2c_clk(hw, &i2cctl);
2281
2282 /* Setup time for stop condition (4us) */
2283 usec_delay(IXGBE_I2C_T_SU_STO);
2284
2285 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2286
2287 /* bus free time between stop and start (4.7us)*/
2288 usec_delay(IXGBE_I2C_T_BUF);
2289
2290 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2291 i2cctl &= ~bb_en_bit;
2292 i2cctl |= data_oe_bit | clk_oe_bit;
2293 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2294 IXGBE_WRITE_FLUSH(hw);
2295 }
2296 }
2297
2298 /**
2299 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2300 * @hw: pointer to hardware structure
2301 * @data: data byte to clock in
2302 *
2303 * Clocks in one byte data via I2C data/clock
2304 **/
2305 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2306 {
2307 s32 i;
2308 bool bit = 0;
2309
2310 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2311
2312 *data = 0;
2313 for (i = 7; i >= 0; i--) {
2314 ixgbe_clock_in_i2c_bit(hw, &bit);
2315 *data |= bit << i;
2316 }
2317
2318 return IXGBE_SUCCESS;
2319 }
2320
2321 /**
2322 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2323 * @hw: pointer to hardware structure
2324 * @data: data byte clocked out
2325 *
2326 * Clocks out one byte data via I2C data/clock
2327 **/
2328 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2329 {
2330 s32 status = IXGBE_SUCCESS;
2331 s32 i;
2332 u32 i2cctl;
2333 bool bit;
2334
2335 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2336
2337 for (i = 7; i >= 0; i--) {
2338 bit = (data >> i) & 0x1;
2339 status = ixgbe_clock_out_i2c_bit(hw, bit);
2340
2341 if (status != IXGBE_SUCCESS)
2342 break;
2343 }
2344
2345 /* Release SDA line (set high) */
2346 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2347 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2348 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2349 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2350 IXGBE_WRITE_FLUSH(hw);
2351
2352 return status;
2353 }
2354
2355 /**
2356 * ixgbe_get_i2c_ack - Polls for I2C ACK
2357 * @hw: pointer to hardware structure
2358 *
2359 * Clocks in/out one bit via I2C data/clock
2360 **/
2361 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2362 {
2363 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2364 s32 status = IXGBE_SUCCESS;
2365 u32 i = 0;
2366 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2367 u32 timeout = 10;
2368 bool ack = 1;
2369
2370 DEBUGFUNC("ixgbe_get_i2c_ack");
2371
2372 if (data_oe_bit) {
2373 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2374 i2cctl |= data_oe_bit;
2375 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2376 IXGBE_WRITE_FLUSH(hw);
2377 }
2378 ixgbe_raise_i2c_clk(hw, &i2cctl);
2379
2380 /* Minimum high period of clock is 4us */
2381 usec_delay(IXGBE_I2C_T_HIGH);
2382
2383 /* Poll for ACK. Note that ACK in I2C spec is
2384 * transition from 1 to 0 */
2385 for (i = 0; i < timeout; i++) {
2386 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2387 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2388
2389 usec_delay(1);
2390 if (!ack)
2391 break;
2392 }
2393
2394 if (ack) {
2395 DEBUGOUT("I2C ack was not received.\n");
2396 status = IXGBE_ERR_I2C;
2397 }
2398
2399 ixgbe_lower_i2c_clk(hw, &i2cctl);
2400
2401 /* Minimum low period of clock is 4.7 us */
2402 usec_delay(IXGBE_I2C_T_LOW);
2403
2404 return status;
2405 }
2406
2407 /**
2408 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2409 * @hw: pointer to hardware structure
2410 * @data: read data value
2411 *
2412 * Clocks in one bit via I2C data/clock
2413 **/
2414 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2415 {
2416 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2417 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2418
2419 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2420
2421 if (data_oe_bit) {
2422 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2423 i2cctl |= data_oe_bit;
2424 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2425 IXGBE_WRITE_FLUSH(hw);
2426 }
2427 ixgbe_raise_i2c_clk(hw, &i2cctl);
2428
2429 /* Minimum high period of clock is 4us */
2430 usec_delay(IXGBE_I2C_T_HIGH);
2431
2432 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2433 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2434
2435 ixgbe_lower_i2c_clk(hw, &i2cctl);
2436
2437 /* Minimum low period of clock is 4.7 us */
2438 usec_delay(IXGBE_I2C_T_LOW);
2439
2440 return IXGBE_SUCCESS;
2441 }
2442
2443 /**
2444 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2445 * @hw: pointer to hardware structure
2446 * @data: data value to write
2447 *
2448 * Clocks out one bit via I2C data/clock
2449 **/
2450 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2451 {
2452 s32 status;
2453 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2454
2455 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2456
2457 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2458 if (status == IXGBE_SUCCESS) {
2459 ixgbe_raise_i2c_clk(hw, &i2cctl);
2460
2461 /* Minimum high period of clock is 4us */
2462 usec_delay(IXGBE_I2C_T_HIGH);
2463
2464 ixgbe_lower_i2c_clk(hw, &i2cctl);
2465
2466 /* Minimum low period of clock is 4.7 us.
2467 * This also takes care of the data hold time.
2468 */
2469 usec_delay(IXGBE_I2C_T_LOW);
2470 } else {
2471 status = IXGBE_ERR_I2C;
2472 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2473 "I2C data was not set to %X\n", data);
2474 }
2475
2476 return status;
2477 }
2478
2479 /**
2480 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2481 * @hw: pointer to hardware structure
2482 * @i2cctl: Current value of I2CCTL register
2483 *
2484 * Raises the I2C clock line '0'->'1'
2485 * Negates the I2C clock output enable on X550 hardware.
2486 **/
2487 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2488 {
2489 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2490 u32 i = 0;
2491 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2492 u32 i2cctl_r = 0;
2493
2494 DEBUGFUNC("ixgbe_raise_i2c_clk");
2495
2496 if (clk_oe_bit) {
2497 *i2cctl |= clk_oe_bit;
2498 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2499 }
2500
2501 for (i = 0; i < timeout; i++) {
2502 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2503
2504 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2505 IXGBE_WRITE_FLUSH(hw);
2506 /* SCL rise time (1000ns) */
2507 usec_delay(IXGBE_I2C_T_RISE);
2508
2509 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2510 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2511 break;
2512 }
2513 }
2514
2515 /**
2516 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2517 * @hw: pointer to hardware structure
2518 * @i2cctl: Current value of I2CCTL register
2519 *
2520 * Lowers the I2C clock line '1'->'0'
2521 * Asserts the I2C clock output enable on X550 hardware.
2522 **/
2523 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2524 {
2525 DEBUGFUNC("ixgbe_lower_i2c_clk");
2526
2527 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2528 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2529
2530 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2531 IXGBE_WRITE_FLUSH(hw);
2532
2533 /* SCL fall time (300ns) */
2534 usec_delay(IXGBE_I2C_T_FALL);
2535 }
2536
2537 /**
2538 * ixgbe_set_i2c_data - Sets the I2C data bit
2539 * @hw: pointer to hardware structure
2540 * @i2cctl: Current value of I2CCTL register
2541 * @data: I2C data value (0 or 1) to set
2542 *
2543 * Sets the I2C data bit
2544 * Asserts the I2C data output enable on X550 hardware.
2545 **/
2546 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2547 {
2548 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2549 s32 status = IXGBE_SUCCESS;
2550
2551 DEBUGFUNC("ixgbe_set_i2c_data");
2552
2553 if (data)
2554 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2555 else
2556 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2557 *i2cctl &= ~data_oe_bit;
2558
2559 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2560 IXGBE_WRITE_FLUSH(hw);
2561
2562 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2563 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2564
2565 if (!data) /* Can't verify data in this case */
2566 return IXGBE_SUCCESS;
2567 if (data_oe_bit) {
2568 *i2cctl |= data_oe_bit;
2569 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2570 IXGBE_WRITE_FLUSH(hw);
2571 }
2572
2573 /* Verify data was set correctly */
2574 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2575 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2576 status = IXGBE_ERR_I2C;
2577 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2578 "Error - I2C data was not set to %X.\n",
2579 data);
2580 }
2581
2582 return status;
2583 }
2584
2585 /**
2586 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2587 * @hw: pointer to hardware structure
2588 * @i2cctl: Current value of I2CCTL register
2589 *
2590 * Returns the I2C data bit value
2591 * Negates the I2C data output enable on X550 hardware.
2592 **/
2593 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2594 {
2595 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2596 bool data;
2597 UNREFERENCED_1PARAMETER(hw);
2598
2599 DEBUGFUNC("ixgbe_get_i2c_data");
2600
2601 if (data_oe_bit) {
2602 *i2cctl |= data_oe_bit;
2603 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2604 IXGBE_WRITE_FLUSH(hw);
2605 usec_delay(IXGBE_I2C_T_FALL);
2606 }
2607
2608 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2609 data = 1;
2610 else
2611 data = 0;
2612
2613 return data;
2614 }
2615
2616 /**
2617 * ixgbe_i2c_bus_clear - Clears the I2C bus
2618 * @hw: pointer to hardware structure
2619 *
2620 * Clears the I2C bus by sending nine clock pulses.
2621 * Used when data line is stuck low.
2622 **/
2623 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2624 {
2625 u32 i2cctl;
2626 u32 i;
2627
2628 DEBUGFUNC("ixgbe_i2c_bus_clear");
2629
2630 ixgbe_i2c_start(hw);
2631 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2632
2633 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2634
2635 for (i = 0; i < 9; i++) {
2636 ixgbe_raise_i2c_clk(hw, &i2cctl);
2637
2638 /* Min high period of clock is 4us */
2639 usec_delay(IXGBE_I2C_T_HIGH);
2640
2641 ixgbe_lower_i2c_clk(hw, &i2cctl);
2642
2643 /* Min low period of clock is 4.7us*/
2644 usec_delay(IXGBE_I2C_T_LOW);
2645 }
2646
2647 ixgbe_i2c_start(hw);
2648
2649 /* Put the i2c bus back to default state */
2650 ixgbe_i2c_stop(hw);
2651 }
2652
2653 /**
2654 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2655 * @hw: pointer to hardware structure
2656 *
2657 * Checks if the LASI temp alarm status was triggered due to overtemp
2658 **/
2659 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2660 {
2661 s32 status = IXGBE_SUCCESS;
2662 u16 phy_data = 0;
2663
2664 DEBUGFUNC("ixgbe_tn_check_overtemp");
2665
2666 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2667 goto out;
2668
2669 /* Check that the LASI temp alarm status was triggered */
2670 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2671 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2672
2673 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2674 goto out;
2675
2676 status = IXGBE_ERR_OVERTEMP;
2677 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2678 out:
2679 return status;
2680 }
2681
2682 /**
2683 * ixgbe_set_copper_phy_power - Control power for copper phy
2684 * @hw: pointer to hardware structure
2685 * @on: true for on, false for off
2686 */
2687 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2688 {
2689 u32 status;
2690 u16 reg;
2691
2692 if (!on && ixgbe_mng_present(hw))
2693 return 0;
2694
2695 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2696 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2697 &reg);
2698 if (status)
2699 return status;
2700
2701 if (on) {
2702 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2703 } else {
2704 if (ixgbe_check_reset_blocked(hw))
2705 return 0;
2706 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2707 }
2708
2709 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2710 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2711 reg);
2712 return status;
2713 }
Ceph