ceph/src/spdk/dpdk/drivers/net/ixgbe/ixgbe_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #ifndef _IXGBE_ETHDEV_H_
   6 #define _IXGBE_ETHDEV_H_
   7
   8 #include <stdint.h>
   9
  10 #include "base/ixgbe_type.h"
  11 #include "base/ixgbe_dcb.h"
  12 #include "base/ixgbe_dcb_82599.h"
  13 #include "base/ixgbe_dcb_82598.h"
  14 #include "ixgbe_bypass.h"
  15 #ifdef RTE_LIBRTE_SECURITY
  16 #include "ixgbe_ipsec.h"
  17 #endif
  18 #include <rte_flow.h>
  19 #include <rte_time.h>
  20 #include <rte_hash.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_tm_driver.h>
  24
  25 /* need update link, bit flag */
  26 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
  27 #define IXGBE_FLAG_MAILBOX          (uint32_t)(1 << 1)
  28 #define IXGBE_FLAG_PHY_INTERRUPT    (uint32_t)(1 << 2)
  29 #define IXGBE_FLAG_MACSEC           (uint32_t)(1 << 3)
  30 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
  31
  32 /*
  33  * Defines that were not part of ixgbe_type.h as they are not used by the
  34  * FreeBSD driver.
  35  */
  36 #define IXGBE_ADVTXD_MAC_1588       0x00080000 /* IEEE1588 Timestamp packet */
  37 #define IXGBE_RXD_STAT_TMST         0x10000    /* Timestamped Packet indication */
  38 #define IXGBE_ADVTXD_TUCMD_L4T_RSV  0x00001800 /* L4 Packet TYPE, resvd  */
  39 #define IXGBE_RXDADV_ERR_CKSUM_BIT  30
  40 #define IXGBE_RXDADV_ERR_CKSUM_MSK  3
  41 #define IXGBE_ADVTXD_MACLEN_SHIFT   9          /* Bit shift for l2_len */
  42 #define IXGBE_NB_STAT_MAPPING_REGS  32
  43 #define IXGBE_EXTENDED_VLAN       (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
  44 #define IXGBE_VFTA_SIZE 128
  45 #define IXGBE_VLAN_TAG_SIZE 4
  46 #define IXGBE_HKEY_MAX_INDEX 10
  47 #define IXGBE_MAX_RX_QUEUE_NUM  128
  48 #define IXGBE_MAX_INTR_QUEUE_NUM        15
  49 #define IXGBE_VMDQ_DCB_NB_QUEUES     IXGBE_MAX_RX_QUEUE_NUM
  50 #define IXGBE_DCB_NB_QUEUES          IXGBE_MAX_RX_QUEUE_NUM
  51 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
  52
  53 #ifndef NBBY
  54 #define NBBY    8       /* number of bits in a byte */
  55 #endif
  56 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
  57
  58 /* EITR Interval is in 2048ns uinits for 1G and 10G link */
  59 #define IXGBE_EITR_INTERVAL_UNIT_NS     2048
  60 #define IXGBE_EITR_ITR_INT_SHIFT       3
  61 #define IXGBE_EITR_INTERVAL_US(us) \
  62         (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
  63                 IXGBE_EITR_ITR_INT_MASK)
  64
  65 #define IXGBE_QUEUE_ITR_INTERVAL_DEFAULT        500 /* 500us */
  66
  67 /* Loopback operation modes */
  68 #define IXGBE_LPBK_NONE   0x0 /* Default value. Loopback is disabled. */
  69 #define IXGBE_LPBK_TX_RX  0x1 /* Tx->Rx loopback operation is enabled. */
  70 /* X540-X550 specific loopback operations */
  71 #define IXGBE_MII_AUTONEG_ENABLE        0x1000 /* Auto-negociation enable (default = 1) */
  72
  73 #define IXGBE_MAX_JUMBO_FRAME_SIZE      0x2600 /* Maximum Jumbo frame size. */
  74
  75 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
  76 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
  77         (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
  78
  79 #define IXGBE_MAX_QUEUE_NUM_PER_VF  8
  80
  81 #define IXGBE_SYN_FILTER_ENABLE         0x00000001 /* syn filter enable field */
  82 #define IXGBE_SYN_FILTER_QUEUE          0x000000FE /* syn filter queue field */
  83 #define IXGBE_SYN_FILTER_QUEUE_SHIFT    1          /* syn filter queue field shift */
  84 #define IXGBE_SYN_FILTER_SYNQFP         0x80000000 /* syn filter SYNQFP */
  85
  86 #define IXGBE_ETQF_UP                   0x00070000 /* ethertype filter priority field */
  87 #define IXGBE_ETQF_SHIFT                16
  88 #define IXGBE_ETQF_UP_EN                0x00080000
  89 #define IXGBE_ETQF_ETHERTYPE            0x0000FFFF /* ethertype filter ethertype field */
  90 #define IXGBE_ETQF_MAX_PRI              7
  91
  92 #define IXGBE_SDPQF_DSTPORT             0xFFFF0000 /* dst port field */
  93 #define IXGBE_SDPQF_DSTPORT_SHIFT       16         /* dst port field shift */
  94 #define IXGBE_SDPQF_SRCPORT             0x0000FFFF /* src port field */
  95
  96 #define IXGBE_L34T_IMIR_SIZE_BP         0x00001000
  97 #define IXGBE_L34T_IMIR_RESERVE         0x00080000 /* bit 13 to 19 must be set to 1000000b. */
  98 #define IXGBE_L34T_IMIR_LLI             0x00100000
  99 #define IXGBE_L34T_IMIR_QUEUE           0x0FE00000
 100 #define IXGBE_L34T_IMIR_QUEUE_SHIFT     21
 101 #define IXGBE_5TUPLE_MAX_PRI            7
 102 #define IXGBE_5TUPLE_MIN_PRI            1
 103
 104 /* The overhead from MTU to max frame size. */
 105 #define IXGBE_ETH_OVERHEAD (ETHER_HDR_LEN + ETHER_CRC_LEN)
 106
 107 /* bit of VXLAN tunnel type | 7 bits of zeros  | 8 bits of zeros*/
 108 #define IXGBE_FDIR_VXLAN_TUNNEL_TYPE    0x8000
 109 /* bit of NVGRE tunnel type | 7 bits of zeros  | 8 bits of zeros*/
 110 #define IXGBE_FDIR_NVGRE_TUNNEL_TYPE    0x0
 111
 112 #define IXGBE_RSS_OFFLOAD_ALL ( \
 113         ETH_RSS_IPV4 | \
 114         ETH_RSS_NONFRAG_IPV4_TCP | \
 115         ETH_RSS_NONFRAG_IPV4_UDP | \
 116         ETH_RSS_IPV6 | \
 117         ETH_RSS_NONFRAG_IPV6_TCP | \
 118         ETH_RSS_NONFRAG_IPV6_UDP | \
 119         ETH_RSS_IPV6_EX | \
 120         ETH_RSS_IPV6_TCP_EX | \
 121         ETH_RSS_IPV6_UDP_EX)
 122
 123 #define IXGBE_VF_IRQ_ENABLE_MASK        3          /* vf irq enable mask */
 124 #define IXGBE_VF_MAXMSIVECTOR           1
 125
 126 #define IXGBE_MISC_VEC_ID               RTE_INTR_VEC_ZERO_OFFSET
 127 #define IXGBE_RX_VEC_START              RTE_INTR_VEC_RXTX_OFFSET
 128
 129 #define IXGBE_SECTX_MINSECIFG_MASK      0x0000000F
 130
 131 #define IXGBE_MACSEC_PNTHRSH            0xFFFFFE00
 132
 133 #define IXGBE_MAX_FDIR_FILTER_NUM       (1024 * 32)
 134 #define IXGBE_MAX_L2_TN_FILTER_NUM      128
 135
 136 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
 137         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
 138                 return -ENOTSUP;\
 139 } while (0)
 140
 141 #define MAC_TYPE_FILTER_SUP(type)    do {\
 142         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
 143                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
 144                 (type) != ixgbe_mac_X550EM_a)\
 145                 return -ENOTSUP;\
 146 } while (0)
 147
 148 /* Link speed for X550 auto negotiation */
 149 #define IXGBE_LINK_SPEED_X550_AUTONEG   (IXGBE_LINK_SPEED_100_FULL | \
 150                                          IXGBE_LINK_SPEED_1GB_FULL | \
 151                                          IXGBE_LINK_SPEED_2_5GB_FULL | \
 152                                          IXGBE_LINK_SPEED_5GB_FULL | \
 153                                          IXGBE_LINK_SPEED_10GB_FULL)
 154
 155 /*
 156  * Information about the fdir mode.
 157  */
 158 struct ixgbe_hw_fdir_mask {
 159         uint16_t vlan_tci_mask;
 160         uint32_t src_ipv4_mask;
 161         uint32_t dst_ipv4_mask;
 162         uint16_t src_ipv6_mask;
 163         uint16_t dst_ipv6_mask;
 164         uint16_t src_port_mask;
 165         uint16_t dst_port_mask;
 166         uint16_t flex_bytes_mask;
 167         uint8_t  mac_addr_byte_mask;
 168         uint32_t tunnel_id_mask;
 169         uint8_t  tunnel_type_mask;
 170 };
 171
 172 struct ixgbe_fdir_filter {
 173         TAILQ_ENTRY(ixgbe_fdir_filter) entries;
 174         union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
 175         uint32_t fdirflags; /* drop or forward */
 176         uint32_t fdirhash; /* hash value for fdir */
 177         uint8_t queue; /* assigned rx queue */
 178 };
 179
 180 /* list of fdir filters */
 181 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
 182
 183 struct ixgbe_fdir_rule {
 184         struct ixgbe_hw_fdir_mask mask;
 185         union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
 186         bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
 187         bool b_mask; /* If TRUE, mask has meaning. */
 188         enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
 189         uint32_t fdirflags; /* drop or forward */
 190         uint32_t soft_id; /* an unique value for this rule */
 191         uint8_t queue; /* assigned rx queue */
 192         uint8_t flex_bytes_offset;
 193 };
 194
 195 struct ixgbe_hw_fdir_info {
 196         struct ixgbe_hw_fdir_mask mask;
 197         uint8_t     flex_bytes_offset;
 198         uint16_t    collision;
 199         uint16_t    free;
 200         uint16_t    maxhash;
 201         uint8_t     maxlen;
 202         uint64_t    add;
 203         uint64_t    remove;
 204         uint64_t    f_add;
 205         uint64_t    f_remove;
 206         struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
 207         /* store the pointers of the filters, index is the hash value. */
 208         struct ixgbe_fdir_filter **hash_map;
 209         struct rte_hash *hash_handle; /* cuckoo hash handler */
 210         bool mask_added; /* If already got mask from consistent filter */
 211 };
 212
 213 struct ixgbe_rte_flow_rss_conf {
 214         struct rte_flow_action_rss conf; /**< RSS parameters. */
 215         uint8_t key[IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
 216         uint16_t queue[IXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
 217 };
 218
 219 /* structure for interrupt relative data */
 220 struct ixgbe_interrupt {
 221         uint32_t flags;
 222         uint32_t mask;
 223         /*to save original mask during delayed handler */
 224         uint32_t mask_original;
 225 };
 226
 227 struct ixgbe_stat_mapping_registers {
 228         uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
 229         uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
 230 };
 231
 232 struct ixgbe_vfta {
 233         uint32_t vfta[IXGBE_VFTA_SIZE];
 234 };
 235
 236 struct ixgbe_hwstrip {
 237         uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
 238 };
 239
 240 /*
 241  * VF data which used by PF host only
 242  */
 243 #define IXGBE_MAX_VF_MC_ENTRIES         30
 244 #define IXGBE_MAX_MR_RULE_ENTRIES       4 /* number of mirroring rules supported */
 245 #define IXGBE_MAX_UTA                   128
 246
 247 struct ixgbe_uta_info {
 248         uint8_t  uc_filter_type;
 249         uint16_t uta_in_use;
 250         uint32_t uta_shadow[IXGBE_MAX_UTA];
 251 };
 252
 253 #define IXGBE_MAX_MIRROR_RULES 4  /* Maximum nb. of mirror rules. */
 254
 255 struct ixgbe_mirror_info {
 256         struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
 257         /**< store PF mirror rules configuration*/
 258 };
 259
 260 struct ixgbe_vf_info {
 261         uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
 262         uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
 263         uint16_t num_vf_mc_hashes;
 264         uint16_t default_vf_vlan_id;
 265         uint16_t vlans_enabled;
 266         bool clear_to_send;
 267         uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
 268         uint16_t vlan_count;
 269         uint8_t spoofchk_enabled;
 270         uint8_t api_version;
 271         uint16_t switch_domain_id;
 272         uint16_t xcast_mode;
 273 };
 274
 275 /*
 276  *  Possible l4type of 5tuple filters.
 277  */
 278 enum ixgbe_5tuple_protocol {
 279         IXGBE_FILTER_PROTOCOL_TCP = 0,
 280         IXGBE_FILTER_PROTOCOL_UDP,
 281         IXGBE_FILTER_PROTOCOL_SCTP,
 282         IXGBE_FILTER_PROTOCOL_NONE,
 283 };
 284
 285 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
 286
 287 struct ixgbe_5tuple_filter_info {
 288         uint32_t dst_ip;
 289         uint32_t src_ip;
 290         uint16_t dst_port;
 291         uint16_t src_port;
 292         enum ixgbe_5tuple_protocol proto;        /* l4 protocol. */
 293         uint8_t priority;        /* seven levels (001b-111b), 111b is highest,
 294                                       used when more than one filter matches. */
 295         uint8_t dst_ip_mask:1,   /* if mask is 1b, do not compare dst ip. */
 296                 src_ip_mask:1,   /* if mask is 1b, do not compare src ip. */
 297                 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
 298                 src_port_mask:1, /* if mask is 1b, do not compare src port. */
 299                 proto_mask:1;    /* if mask is 1b, do not compare protocol. */
 300 };
 301
 302 /* 5tuple filter structure */
 303 struct ixgbe_5tuple_filter {
 304         TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
 305         uint16_t index;       /* the index of 5tuple filter */
 306         struct ixgbe_5tuple_filter_info filter_info;
 307         uint16_t queue;       /* rx queue assigned to */
 308 };
 309
 310 #define IXGBE_5TUPLE_ARRAY_SIZE \
 311         (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
 312          (sizeof(uint32_t) * NBBY))
 313
 314 struct ixgbe_ethertype_filter {
 315         uint16_t ethertype;
 316         uint32_t etqf;
 317         uint32_t etqs;
 318         /**
 319          * If this filter is added by configuration,
 320          * it should not be removed.
 321          */
 322         bool     conf;
 323 };
 324
 325 /*
 326  * Structure to store filters' info.
 327  */
 328 struct ixgbe_filter_info {
 329         uint8_t ethertype_mask;  /* Bit mask for every used ethertype filter */
 330         /* store used ethertype filters*/
 331         struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
 332         /* Bit mask for every used 5tuple filter */
 333         uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
 334         struct ixgbe_5tuple_filter_list fivetuple_list;
 335         /* store the SYN filter info */
 336         uint32_t syn_info;
 337         /* store the rss filter info */
 338         struct ixgbe_rte_flow_rss_conf rss_info;
 339 };
 340
 341 struct ixgbe_l2_tn_key {
 342         enum rte_eth_tunnel_type          l2_tn_type;
 343         uint32_t                          tn_id;
 344 };
 345
 346 struct ixgbe_l2_tn_filter {
 347         TAILQ_ENTRY(ixgbe_l2_tn_filter)    entries;
 348         struct ixgbe_l2_tn_key             key;
 349         uint32_t                           pool;
 350 };
 351
 352 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
 353
 354 struct ixgbe_l2_tn_info {
 355         struct ixgbe_l2_tn_filter_list      l2_tn_list;
 356         struct ixgbe_l2_tn_filter         **hash_map;
 357         struct rte_hash                    *hash_handle;
 358         bool e_tag_en; /* e-tag enabled */
 359         bool e_tag_fwd_en; /* e-tag based forwarding enabled */
 360         bool e_tag_ether_type; /* ether type for e-tag */
 361 };
 362
 363 struct rte_flow {
 364         enum rte_filter_type filter_type;
 365         void *rule;
 366 };
 367
 368 /*
 369  * Statistics counters collected by the MACsec
 370  */
 371 struct ixgbe_macsec_stats {
 372         /* TX port statistics */
 373         uint64_t out_pkts_untagged;
 374         uint64_t out_pkts_encrypted;
 375         uint64_t out_pkts_protected;
 376         uint64_t out_octets_encrypted;
 377         uint64_t out_octets_protected;
 378
 379         /* RX port statistics */
 380         uint64_t in_pkts_untagged;
 381         uint64_t in_pkts_badtag;
 382         uint64_t in_pkts_nosci;
 383         uint64_t in_pkts_unknownsci;
 384         uint64_t in_octets_decrypted;
 385         uint64_t in_octets_validated;
 386
 387         /* RX SC statistics */
 388         uint64_t in_pkts_unchecked;
 389         uint64_t in_pkts_delayed;
 390         uint64_t in_pkts_late;
 391
 392         /* RX SA statistics */
 393         uint64_t in_pkts_ok;
 394         uint64_t in_pkts_invalid;
 395         uint64_t in_pkts_notvalid;
 396         uint64_t in_pkts_unusedsa;
 397         uint64_t in_pkts_notusingsa;
 398 };
 399
 400 /* The configuration of bandwidth */
 401 struct ixgbe_bw_conf {
 402         uint8_t tc_num; /* Number of TCs. */
 403 };
 404
 405 /* Struct to store Traffic Manager shaper profile. */
 406 struct ixgbe_tm_shaper_profile {
 407         TAILQ_ENTRY(ixgbe_tm_shaper_profile) node;
 408         uint32_t shaper_profile_id;
 409         uint32_t reference_count;
 410         struct rte_tm_shaper_params profile;
 411 };
 412
 413 TAILQ_HEAD(ixgbe_shaper_profile_list, ixgbe_tm_shaper_profile);
 414
 415 /* node type of Traffic Manager */
 416 enum ixgbe_tm_node_type {
 417         IXGBE_TM_NODE_TYPE_PORT,
 418         IXGBE_TM_NODE_TYPE_TC,
 419         IXGBE_TM_NODE_TYPE_QUEUE,
 420         IXGBE_TM_NODE_TYPE_MAX,
 421 };
 422
 423 /* Struct to store Traffic Manager node configuration. */
 424 struct ixgbe_tm_node {
 425         TAILQ_ENTRY(ixgbe_tm_node) node;
 426         uint32_t id;
 427         uint32_t priority;
 428         uint32_t weight;
 429         uint32_t reference_count;
 430         uint16_t no;
 431         struct ixgbe_tm_node *parent;
 432         struct ixgbe_tm_shaper_profile *shaper_profile;
 433         struct rte_tm_node_params params;
 434 };
 435
 436 TAILQ_HEAD(ixgbe_tm_node_list, ixgbe_tm_node);
 437
 438 /* The configuration of Traffic Manager */
 439 struct ixgbe_tm_conf {
 440         struct ixgbe_shaper_profile_list shaper_profile_list;
 441         struct ixgbe_tm_node *root; /* root node - port */
 442         struct ixgbe_tm_node_list tc_list; /* node list for all the TCs */
 443         struct ixgbe_tm_node_list queue_list; /* node list for all the queues */
 444         /**
 445          * The number of added TC nodes.
 446          * It should be no more than the TC number of this port.
 447          */
 448         uint32_t nb_tc_node;
 449         /**
 450          * The number of added queue nodes.
 451          * It should be no more than the queue number of this port.
 452          */
 453         uint32_t nb_queue_node;
 454         /**
 455          * This flag is used to check if APP can change the TM node
 456          * configuration.
 457          * When it's true, means the configuration is applied to HW,
 458          * APP should not change the configuration.
 459          * As we don't support on-the-fly configuration, when starting
 460          * the port, APP should call the hierarchy_commit API to set this
 461          * flag to true. When stopping the port, this flag should be set
 462          * to false.
 463          */
 464         bool committed;
 465 };
 466
 467 /*
 468  * Structure to store private data for each driver instance (for each port).
 469  */
 470 struct ixgbe_adapter {
 471         struct ixgbe_hw             hw;
 472         struct ixgbe_hw_stats       stats;
 473         struct ixgbe_macsec_stats   macsec_stats;
 474         struct ixgbe_hw_fdir_info   fdir;
 475         struct ixgbe_interrupt      intr;
 476         struct ixgbe_stat_mapping_registers stat_mappings;
 477         struct ixgbe_vfta           shadow_vfta;
 478         struct ixgbe_hwstrip            hwstrip;
 479         struct ixgbe_dcb_config     dcb_config;
 480         struct ixgbe_mirror_info    mr_data;
 481         struct ixgbe_vf_info        *vfdata;
 482         struct ixgbe_uta_info       uta_info;
 483 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 484         struct ixgbe_bypass_info    bps;
 485 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
 486         struct ixgbe_filter_info    filter;
 487         struct ixgbe_l2_tn_info     l2_tn;
 488         struct ixgbe_bw_conf        bw_conf;
 489 #ifdef RTE_LIBRTE_SECURITY
 490         struct ixgbe_ipsec          ipsec;
 491 #endif
 492         bool rx_bulk_alloc_allowed;
 493         bool rx_vec_allowed;
 494         struct rte_timecounter      systime_tc;
 495         struct rte_timecounter      rx_tstamp_tc;
 496         struct rte_timecounter      tx_tstamp_tc;
 497         struct ixgbe_tm_conf        tm_conf;
 498
 499         /* For RSS reta table update */
 500         uint8_t rss_reta_updated;
 501 };
 502
 503 struct ixgbe_vf_representor {
 504         uint16_t vf_id;
 505         uint16_t switch_domain_id;
 506         struct rte_eth_dev *pf_ethdev;
 507 };
 508
 509 int ixgbe_vf_representor_init(struct rte_eth_dev *ethdev, void *init_params);
 510 int ixgbe_vf_representor_uninit(struct rte_eth_dev *ethdev);
 511
 512 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
 513         (&((struct ixgbe_adapter *)adapter)->hw)
 514
 515 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
 516         (&((struct ixgbe_adapter *)adapter)->stats)
 517
 518 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
 519         (&((struct ixgbe_adapter *)adapter)->macsec_stats)
 520
 521 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
 522         (&((struct ixgbe_adapter *)adapter)->intr)
 523
 524 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
 525         (&((struct ixgbe_adapter *)adapter)->fdir)
 526
 527 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
 528         (&((struct ixgbe_adapter *)adapter)->stat_mappings)
 529
 530 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
 531         (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
 532
 533 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
 534         (&((struct ixgbe_adapter *)adapter)->hwstrip)
 535
 536 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
 537         (&((struct ixgbe_adapter *)adapter)->dcb_config)
 538
 539 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
 540         (&((struct ixgbe_adapter *)adapter)->vfdata)
 541
 542 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
 543         (&((struct ixgbe_adapter *)adapter)->mr_data)
 544
 545 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
 546         (&((struct ixgbe_adapter *)adapter)->uta_info)
 547
 548 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
 549         (&((struct ixgbe_adapter *)adapter)->filter)
 550
 551 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
 552         (&((struct ixgbe_adapter *)adapter)->l2_tn)
 553
 554 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \
 555         (&((struct ixgbe_adapter *)adapter)->bw_conf)
 556
 557 #define IXGBE_DEV_PRIVATE_TO_TM_CONF(adapter) \
 558         (&((struct ixgbe_adapter *)adapter)->tm_conf)
 559
 560 #define IXGBE_DEV_PRIVATE_TO_IPSEC(adapter)\
 561         (&((struct ixgbe_adapter *)adapter)->ipsec)
 562
 563 /*
 564  * RX/TX function prototypes
 565  */
 566 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
 567
 568 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
 569
 570 void ixgbe_dev_rx_queue_release(void *rxq);
 571
 572 void ixgbe_dev_tx_queue_release(void *txq);
 573
 574 int  ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
 575                 uint16_t nb_rx_desc, unsigned int socket_id,
 576                 const struct rte_eth_rxconf *rx_conf,
 577                 struct rte_mempool *mb_pool);
 578
 579 int  ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 580                 uint16_t nb_tx_desc, unsigned int socket_id,
 581                 const struct rte_eth_txconf *tx_conf);
 582
 583 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
 584                 uint16_t rx_queue_id);
 585
 586 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
 587
 588 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
 589 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
 590
 591 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
 592
 593 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
 594
 595 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
 596
 597 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 598
 599 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
 600
 601 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 602
 603 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
 604
 605 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 606         struct rte_eth_rxq_info *qinfo);
 607
 608 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 609         struct rte_eth_txq_info *qinfo);
 610
 611 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
 612
 613 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
 614
 615 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
 616
 617 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 618                 uint16_t nb_pkts);
 619
 620 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
 621                                     uint16_t nb_pkts);
 622
 623 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
 624                 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 625 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
 626                 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
 627
 628 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 629                 uint16_t nb_pkts);
 630
 631 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
 632                 uint16_t nb_pkts);
 633
 634 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 635                 uint16_t nb_pkts);
 636
 637 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 638                               struct rte_eth_rss_conf *rss_conf);
 639
 640 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 641                                 struct rte_eth_rss_conf *rss_conf);
 642
 643 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
 644
 645 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
 646
 647 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
 648
 649 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
 650
 651 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
 652
 653 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 654                         struct rte_eth_ntuple_filter *filter,
 655                         bool add);
 656 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 657                         struct rte_eth_ethertype_filter *filter,
 658                         bool add);
 659 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 660                         struct rte_eth_syn_filter *filter,
 661                         bool add);
 662 int
 663 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
 664                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
 665                                bool restore);
 666 int
 667 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
 668                                struct rte_eth_l2_tunnel_conf *l2_tunnel);
 669 void ixgbe_filterlist_init(void);
 670 void ixgbe_filterlist_flush(void);
 671 /*
 672  * Flow director function prototypes
 673  */
 674 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
 675 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
 676 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
 677                                     uint16_t offset);
 678 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
 679                               struct ixgbe_fdir_rule *rule,
 680                               bool del, bool update);
 681
 682 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
 683
 684 int
 685 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
 686                             int wait_to_complete, int vf);
 687
 688 /*
 689  * misc function prototypes
 690  */
 691 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
 692
 693 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
 694
 695 void ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
 696
 697 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
 698
 699 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
 700
 701 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
 702
 703 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
 704
 705 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
 706
 707 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
 708                         enum rte_filter_op filter_op, void *arg);
 709 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
 710 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
 711
 712 extern const struct rte_flow_ops ixgbe_flow_ops;
 713
 714 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
 715 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
 716 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
 717 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
 718
 719 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
 720
 721 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
 722
 723 int ixgbe_vt_check(struct ixgbe_hw *hw);
 724 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 725                             uint16_t tx_rate, uint64_t q_msk);
 726 bool is_ixgbe_supported(struct rte_eth_dev *dev);
 727 int ixgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
 728 void ixgbe_tm_conf_init(struct rte_eth_dev *dev);
 729 void ixgbe_tm_conf_uninit(struct rte_eth_dev *dev);
 730 int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
 731                                uint16_t tx_rate);
 732 int ixgbe_rss_conf_init(struct ixgbe_rte_flow_rss_conf *out,
 733                         const struct rte_flow_action_rss *in);
 734 int ixgbe_action_rss_same(const struct rte_flow_action_rss *comp,
 735                           const struct rte_flow_action_rss *with);
 736 int ixgbe_config_rss_filter(struct rte_eth_dev *dev,
 737                 struct ixgbe_rte_flow_rss_conf *conf, bool add);
 738
 739 static inline int
 740 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
 741                               uint16_t ethertype)
 742 {
 743         int i;
 744
 745         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
 746                 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
 747                     (filter_info->ethertype_mask & (1 << i)))
 748                         return i;
 749         }
 750         return -1;
 751 }
 752
 753 static inline int
 754 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
 755                               struct ixgbe_ethertype_filter *ethertype_filter)
 756 {
 757         int i;
 758
 759         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
 760                 if (!(filter_info->ethertype_mask & (1 << i))) {
 761                         filter_info->ethertype_mask |= 1 << i;
 762                         filter_info->ethertype_filters[i].ethertype =
 763                                 ethertype_filter->ethertype;
 764                         filter_info->ethertype_filters[i].etqf =
 765                                 ethertype_filter->etqf;
 766                         filter_info->ethertype_filters[i].etqs =
 767                                 ethertype_filter->etqs;
 768                         filter_info->ethertype_filters[i].conf =
 769                                 ethertype_filter->conf;
 770                         return i;
 771                 }
 772         }
 773         return -1;
 774 }
 775
 776 static inline int
 777 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
 778                               uint8_t idx)
 779 {
 780         if (idx >= IXGBE_MAX_ETQF_FILTERS)
 781                 return -1;
 782         filter_info->ethertype_mask &= ~(1 << idx);
 783         filter_info->ethertype_filters[idx].ethertype = 0;
 784         filter_info->ethertype_filters[idx].etqf = 0;
 785         filter_info->ethertype_filters[idx].etqs = 0;
 786         filter_info->ethertype_filters[idx].etqs = FALSE;
 787         return idx;
 788 }
 789
 790 #endif /* _IXGBE_ETHDEV_H_ */