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1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
3 */
4
5 #ifndef _IXGBE_RXTX_H_
6 #define _IXGBE_RXTX_H_
7
8 /*
9 * Rings setup and release.
10 *
11 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
12 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
13 * also optimize cache line size effect. H/W supports up to cache line size 128.
14 */
15 #define IXGBE_ALIGN 128
16
17 #define IXGBE_RXD_ALIGN (IXGBE_ALIGN / sizeof(union ixgbe_adv_rx_desc))
18 #define IXGBE_TXD_ALIGN (IXGBE_ALIGN / sizeof(union ixgbe_adv_tx_desc))
19
20 /*
21 * Maximum number of Ring Descriptors.
22 *
23 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
24 * descriptors should meet the following condition:
25 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
26 */
27 #define IXGBE_MIN_RING_DESC 32
28 #define IXGBE_MAX_RING_DESC 4096
29
30 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
31 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
32 #define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64
33
34 #define RTE_IXGBE_DESCS_PER_LOOP 4
35
36 #ifdef RTE_IXGBE_INC_VECTOR
37 #define RTE_IXGBE_RXQ_REARM_THRESH 32
38 #define RTE_IXGBE_MAX_RX_BURST RTE_IXGBE_RXQ_REARM_THRESH
39 #endif
40
41 #define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_PMD_IXGBE_RX_MAX_BURST) * \
42 sizeof(union ixgbe_adv_rx_desc))
43
44 #ifdef RTE_PMD_PACKET_PREFETCH
45 #define rte_packet_prefetch(p) rte_prefetch1(p)
46 #else
47 #define rte_packet_prefetch(p) do {} while(0)
48 #endif
49
50 #define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10
51 #define RTE_IXGBE_WAIT_100_US 100
52 #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2
53
54 #define IXGBE_TX_MAX_SEG 40
55
56 #define IXGBE_PACKET_TYPE_MASK_82599 0X7F
57 #define IXGBE_PACKET_TYPE_MASK_X550 0X10FF
58 #define IXGBE_PACKET_TYPE_MASK_TUNNEL 0XFF
59 #define IXGBE_PACKET_TYPE_TUNNEL_BIT 0X1000
60
61 #define IXGBE_PACKET_TYPE_MAX 0X80
62 #define IXGBE_PACKET_TYPE_TN_MAX 0X100
63 #define IXGBE_PACKET_TYPE_SHIFT 0X04
64
65 /**
66 * Structure associated with each descriptor of the RX ring of a RX queue.
67 */
68 struct ixgbe_rx_entry {
69 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
70 };
71
72 struct ixgbe_scattered_rx_entry {
73 struct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */
74 };
75
76 /**
77 * Structure associated with each descriptor of the TX ring of a TX queue.
78 */
79 struct ixgbe_tx_entry {
80 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
81 uint16_t next_id; /**< Index of next descriptor in ring. */
82 uint16_t last_id; /**< Index of last scattered descriptor. */
83 };
84
85 /**
86 * Structure associated with each descriptor of the TX ring of a TX queue.
87 */
88 struct ixgbe_tx_entry_v {
89 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
90 };
91
92 /**
93 * Structure associated with each RX queue.
94 */
95 struct ixgbe_rx_queue {
96 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
97 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
98 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
99 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
100 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
101 struct ixgbe_rx_entry *sw_ring; /**< address of RX software ring. */
102 struct ixgbe_scattered_rx_entry *sw_sc_ring; /**< address of scattered Rx software ring. */
103 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
104 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
105 uint64_t mbuf_initializer; /**< value to init mbufs */
106 uint16_t nb_rx_desc; /**< number of RX descriptors. */
107 uint16_t rx_tail; /**< current value of RDT register. */
108 uint16_t nb_rx_hold; /**< number of held free RX desc. */
109 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
110 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
111 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
112 uint8_t rx_using_sse;
113 /**< indicates that vector RX is in use */
114 #ifdef RTE_LIBRTE_SECURITY
115 uint8_t using_ipsec;
116 /**< indicates that IPsec RX feature is in use */
117 #endif
118 #ifdef RTE_IXGBE_INC_VECTOR
119 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
120 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
121 #endif
122 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
123 uint16_t queue_id; /**< RX queue index. */
124 uint16_t reg_idx; /**< RX queue register index. */
125 uint16_t pkt_type_mask; /**< Packet type mask for different NICs. */
126 uint16_t port_id; /**< Device port identifier. */
127 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
128 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
129 uint8_t rx_deferred_start; /**< not in global dev start. */
130 /** flags to set in mbuf when a vlan is detected. */
131 uint64_t vlan_flags;
132 uint64_t offloads; /**< Rx offloads with DEV_RX_OFFLOAD_* */
133 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
134 struct rte_mbuf fake_mbuf;
135 /** hold packets to return to application */
136 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
137 };
138
139 /**
140 * IXGBE CTX Constants
141 */
142 enum ixgbe_advctx_num {
143 IXGBE_CTX_0 = 0, /**< CTX0 */
144 IXGBE_CTX_1 = 1, /**< CTX1 */
145 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
146 };
147
148 /** Offload features */
149 union ixgbe_tx_offload {
150 uint64_t data[2];
151 struct {
152 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
153 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
154 uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */
155 uint64_t tso_segsz:16; /**< TCP TSO segment size */
156 uint64_t vlan_tci:16;
157 /**< VLAN Tag Control Identifier (CPU order). */
158
159 /* fields for TX offloading of tunnels */
160 uint64_t outer_l3_len:8; /**< Outer L3 (IP) Hdr Length. */
161 uint64_t outer_l2_len:8; /**< Outer L2 (MAC) Hdr Length. */
162 #ifdef RTE_LIBRTE_SECURITY
163 /* inline ipsec related*/
164 uint64_t sa_idx:8; /**< TX SA database entry index */
165 uint64_t sec_pad_len:4; /**< padding length */
166 #endif
167 };
168 };
169
170 /*
171 * Compare mask for vlan_macip_len.data,
172 * should be in sync with ixgbe_vlan_macip.f layout.
173 * */
174 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
175 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
176 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
177 /** MAC+IP length. */
178 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
179
180 /**
181 * Structure to check if new context need be built
182 */
183
184 struct ixgbe_advctx_info {
185 uint64_t flags; /**< ol_flags for context build. */
186 /**< tx offload: vlan, tso, l2-l3-l4 lengths. */
187 union ixgbe_tx_offload tx_offload;
188 /** compare mask for tx offload. */
189 union ixgbe_tx_offload tx_offload_mask;
190 };
191
192 /**
193 * Structure associated with each TX queue.
194 */
195 struct ixgbe_tx_queue {
196 /** TX ring virtual address. */
197 volatile union ixgbe_adv_tx_desc *tx_ring;
198 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
199 union {
200 struct ixgbe_tx_entry *sw_ring; /**< address of SW ring for scalar PMD. */
201 struct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector PMD */
202 };
203 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
204 uint16_t nb_tx_desc; /**< number of TX descriptors. */
205 uint16_t tx_tail; /**< current value of TDT reg. */
206 /**< Start freeing TX buffers if there are less free descriptors than
207 this value. */
208 uint16_t tx_free_thresh;
209 /** Number of TX descriptors to use before RS bit is set. */
210 uint16_t tx_rs_thresh;
211 /** Number of TX descriptors used since RS bit was set. */
212 uint16_t nb_tx_used;
213 /** Index to last TX descriptor to have been cleaned. */
214 uint16_t last_desc_cleaned;
215 /** Total number of TX descriptors ready to be allocated. */
216 uint16_t nb_tx_free;
217 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
218 uint16_t tx_next_rs; /**< next desc to set RS bit */
219 uint16_t queue_id; /**< TX queue index. */
220 uint16_t reg_idx; /**< TX queue register index. */
221 uint16_t port_id; /**< Device port identifier. */
222 uint8_t pthresh; /**< Prefetch threshold register. */
223 uint8_t hthresh; /**< Host threshold register. */
224 uint8_t wthresh; /**< Write-back threshold reg. */
225 uint64_t offloads; /**< Tx offload flags of DEV_TX_OFFLOAD_* */
226 uint32_t ctx_curr; /**< Hardware context states. */
227 /** Hardware context0 history. */
228 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
229 const struct ixgbe_txq_ops *ops; /**< txq ops */
230 uint8_t tx_deferred_start; /**< not in global dev start. */
231 #ifdef RTE_LIBRTE_SECURITY
232 uint8_t using_ipsec;
233 /**< indicates that IPsec TX feature is in use */
234 #endif
235 };
236
237 struct ixgbe_txq_ops {
238 void (*release_mbufs)(struct ixgbe_tx_queue *txq);
239 void (*free_swring)(struct ixgbe_tx_queue *txq);
240 void (*reset)(struct ixgbe_tx_queue *txq);
241 };
242
243 /*
244 * Populate descriptors with the following info:
245 * 1.) buffer_addr = phys_addr + headroom
246 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
247 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
248 */
249
250 /* Defines for Tx descriptor */
251 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
252 IXGBE_ADVTXD_DCMD_IFCS |\
253 IXGBE_ADVTXD_DCMD_DEXT |\
254 IXGBE_ADVTXD_DCMD_EOP)
255
256
257 /* Takes an ethdev and a queue and sets up the tx function to be used based on
258 * the queue parameters. Used in tx_queue_setup by primary process and then
259 * in dev_init by secondary process when attaching to an existing ethdev.
260 */
261 void ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq);
262
263 /**
264 * Sets the rx_pkt_burst callback in the ixgbe rte_eth_dev instance.
265 *
266 * Sets the callback based on the device parameters:
267 * - ixgbe_hw.rx_bulk_alloc_allowed
268 * - rte_eth_dev_data.scattered_rx
269 * - rte_eth_dev_data.lro
270 * - conditions checked in ixgbe_rx_vec_condition_check()
271 *
272 * This means that the parameters above have to be configured prior to calling
273 * to this function.
274 *
275 * @dev rte_eth_dev handle
276 */
277 void ixgbe_set_rx_function(struct rte_eth_dev *dev);
278
279 int ixgbe_check_supported_loopback_mode(struct rte_eth_dev *dev);
280 uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
281 uint16_t nb_pkts);
282 uint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue,
283 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
284 int ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev);
285 int ixgbe_rxq_vec_setup(struct ixgbe_rx_queue *rxq);
286 void ixgbe_rx_queue_release_mbufs_vec(struct ixgbe_rx_queue *rxq);
287
288 extern const uint32_t ptype_table[IXGBE_PACKET_TYPE_MAX];
289 extern const uint32_t ptype_table_tn[IXGBE_PACKET_TYPE_TN_MAX];
290
291 #ifdef RTE_IXGBE_INC_VECTOR
292
293 uint16_t ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
294 uint16_t nb_pkts);
295 int ixgbe_txq_vec_setup(struct ixgbe_tx_queue *txq);
296 #endif /* RTE_IXGBE_INC_VECTOR */
297
298 uint64_t ixgbe_get_tx_port_offloads(struct rte_eth_dev *dev);
299 uint64_t ixgbe_get_rx_queue_offloads(struct rte_eth_dev *dev);
300 uint64_t ixgbe_get_rx_port_offloads(struct rte_eth_dev *dev);
301 uint64_t ixgbe_get_tx_queue_offloads(struct rte_eth_dev *dev);
302
303 #endif /* _IXGBE_RXTX_H_ */