ceph/src/spdk/dpdk/drivers/net/mlx4/mlx4_txq.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2017 6WIND S.A.
   3  * Copyright 2017 Mellanox Technologies, Ltd
   4  */
   5
   6 /**
   7  * @file
   8  * Tx queues configuration for mlx4 driver.
   9  */
  10
  11 #include <assert.h>
  12 #include <errno.h>
  13 #include <stddef.h>
  14 #include <stdint.h>
  15 #include <string.h>
  16 #include <inttypes.h>
  17
  18 /* Verbs headers do not support -pedantic. */
  19 #ifdef PEDANTIC
  20 #pragma GCC diagnostic ignored "-Wpedantic"
  21 #endif
  22 #include <infiniband/verbs.h>
  23 #ifdef PEDANTIC
  24 #pragma GCC diagnostic error "-Wpedantic"
  25 #endif
  26
  27 #include <rte_common.h>
  28 #include <rte_errno.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_malloc.h>
  31 #include <rte_mbuf.h>
  32 #include <rte_mempool.h>
  33
  34 #include "mlx4.h"
  35 #include "mlx4_glue.h"
  36 #include "mlx4_prm.h"
  37 #include "mlx4_rxtx.h"
  38 #include "mlx4_utils.h"
  39
  40 /**
  41  * Free Tx queue elements.
  42  *
  43  * @param txq
  44  *   Pointer to Tx queue structure.
  45  */
  46 static void
  47 mlx4_txq_free_elts(struct txq *txq)
  48 {
  49         unsigned int elts_head = txq->elts_head;
  50         unsigned int elts_tail = txq->elts_tail;
  51         struct txq_elt (*elts)[txq->elts_n] = txq->elts;
  52         unsigned int elts_m = txq->elts_n - 1;
  53
  54         DEBUG("%p: freeing WRs", (void *)txq);
  55         while (elts_tail != elts_head) {
  56                 struct txq_elt *elt = &(*elts)[elts_tail++ & elts_m];
  57
  58                 assert(elt->buf != NULL);
  59                 rte_pktmbuf_free(elt->buf);
  60                 elt->buf = NULL;
  61                 elt->wqe = NULL;
  62         }
  63         txq->elts_tail = txq->elts_head;
  64 }
  65
  66 /**
  67  * Retrieves information needed in order to directly access the Tx queue.
  68  *
  69  * @param txq
  70  *   Pointer to Tx queue structure.
  71  * @param mlxdv
  72  *   Pointer to device information for this Tx queue.
  73  */
  74 static void
  75 mlx4_txq_fill_dv_obj_info(struct txq *txq, struct mlx4dv_obj *mlxdv)
  76 {
  77         struct mlx4_sq *sq = &txq->msq;
  78         struct mlx4_cq *cq = &txq->mcq;
  79         struct mlx4dv_qp *dqp = mlxdv->qp.out;
  80         struct mlx4dv_cq *dcq = mlxdv->cq.out;
  81
  82         /* Total length, including headroom and spare WQEs. */
  83         sq->size = (uint32_t)dqp->rq.offset - (uint32_t)dqp->sq.offset;
  84         sq->buf = (uint8_t *)dqp->buf.buf + dqp->sq.offset;
  85         sq->eob = sq->buf + sq->size;
  86         uint32_t headroom_size = 2048 + (1 << dqp->sq.wqe_shift);
  87         /* Continuous headroom size bytes must always stay freed. */
  88         sq->remain_size = sq->size - headroom_size;
  89         sq->owner_opcode = MLX4_OPCODE_SEND | (0u << MLX4_SQ_OWNER_BIT);
  90         sq->stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
  91                                      (0u << MLX4_SQ_OWNER_BIT));
  92         sq->db = dqp->sdb;
  93         sq->doorbell_qpn = dqp->doorbell_qpn;
  94         cq->buf = dcq->buf.buf;
  95         cq->cqe_cnt = dcq->cqe_cnt;
  96         cq->set_ci_db = dcq->set_ci_db;
  97         cq->cqe_64 = (dcq->cqe_size & 64) ? 1 : 0;
  98 }
  99
 100 /**
 101  * Returns the per-port supported offloads.
 102  *
 103  * @param priv
 104  *   Pointer to private structure.
 105  *
 106  * @return
 107  *   Supported Tx offloads.
 108  */
 109 uint64_t
 110 mlx4_get_tx_port_offloads(struct priv *priv)
 111 {
 112         uint64_t offloads = DEV_TX_OFFLOAD_MULTI_SEGS;
 113
 114         if (priv->hw_csum) {
 115                 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
 116                              DEV_TX_OFFLOAD_UDP_CKSUM |
 117                              DEV_TX_OFFLOAD_TCP_CKSUM);
 118         }
 119         if (priv->tso)
 120                 offloads |= DEV_TX_OFFLOAD_TCP_TSO;
 121         if (priv->hw_csum_l2tun) {
 122                 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
 123                 if (priv->tso)
 124                         offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
 125                                      DEV_TX_OFFLOAD_GRE_TNL_TSO);
 126         }
 127         return offloads;
 128 }
 129
 130 /**
 131  * DPDK callback to configure a Tx queue.
 132  *
 133  * @param dev
 134  *   Pointer to Ethernet device structure.
 135  * @param idx
 136  *   Tx queue index.
 137  * @param desc
 138  *   Number of descriptors to configure in queue.
 139  * @param socket
 140  *   NUMA socket on which memory must be allocated.
 141  * @param[in] conf
 142  *   Thresholds parameters.
 143  *
 144  * @return
 145  *   0 on success, negative errno value otherwise and rte_errno is set.
 146  */
 147 int
 148 mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
 149                     unsigned int socket, const struct rte_eth_txconf *conf)
 150 {
 151         struct priv *priv = dev->data->dev_private;
 152         struct mlx4dv_obj mlxdv;
 153         struct mlx4dv_qp dv_qp;
 154         struct mlx4dv_cq dv_cq;
 155         struct txq_elt (*elts)[rte_align32pow2(desc)];
 156         struct ibv_qp_init_attr qp_init_attr;
 157         struct txq *txq;
 158         uint8_t *bounce_buf;
 159         struct mlx4_malloc_vec vec[] = {
 160                 {
 161                         .align = RTE_CACHE_LINE_SIZE,
 162                         .size = sizeof(*txq),
 163                         .addr = (void **)&txq,
 164                 },
 165                 {
 166                         .align = RTE_CACHE_LINE_SIZE,
 167                         .size = sizeof(*elts),
 168                         .addr = (void **)&elts,
 169                 },
 170                 {
 171                         .align = RTE_CACHE_LINE_SIZE,
 172                         .size = MLX4_MAX_WQE_SIZE,
 173                         .addr = (void **)&bounce_buf,
 174                 },
 175         };
 176         int ret;
 177         uint64_t offloads;
 178
 179         offloads = conf->offloads | dev->data->dev_conf.txmode.offloads;
 180
 181         DEBUG("%p: configuring queue %u for %u descriptors",
 182               (void *)dev, idx, desc);
 183
 184         if (idx >= dev->data->nb_tx_queues) {
 185                 rte_errno = EOVERFLOW;
 186                 ERROR("%p: queue index out of range (%u >= %u)",
 187                       (void *)dev, idx, dev->data->nb_tx_queues);
 188                 return -rte_errno;
 189         }
 190         txq = dev->data->tx_queues[idx];
 191         if (txq) {
 192                 rte_errno = EEXIST;
 193                 DEBUG("%p: Tx queue %u already configured, release it first",
 194                       (void *)dev, idx);
 195                 return -rte_errno;
 196         }
 197         if (!desc) {
 198                 rte_errno = EINVAL;
 199                 ERROR("%p: invalid number of Tx descriptors", (void *)dev);
 200                 return -rte_errno;
 201         }
 202         if (desc != RTE_DIM(*elts)) {
 203                 desc = RTE_DIM(*elts);
 204                 WARN("%p: increased number of descriptors in Tx queue %u"
 205                      " to the next power of two (%u)",
 206                      (void *)dev, idx, desc);
 207         }
 208         /* Allocate and initialize Tx queue. */
 209         mlx4_zmallocv_socket("TXQ", vec, RTE_DIM(vec), socket);
 210         if (!txq) {
 211                 ERROR("%p: unable to allocate queue index %u",
 212                       (void *)dev, idx);
 213                 return -rte_errno;
 214         }
 215         *txq = (struct txq){
 216                 .priv = priv,
 217                 .stats = {
 218                         .idx = idx,
 219                 },
 220                 .socket = socket,
 221                 .elts_n = desc,
 222                 .elts = elts,
 223                 .elts_head = 0,
 224                 .elts_tail = 0,
 225                 /*
 226                  * Request send completion every MLX4_PMD_TX_PER_COMP_REQ
 227                  * packets or at least 4 times per ring.
 228                  */
 229                 .elts_comp_cd =
 230                         RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
 231                 .elts_comp_cd_init =
 232                         RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
 233                 .csum = priv->hw_csum &&
 234                         (offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
 235                                            DEV_TX_OFFLOAD_UDP_CKSUM |
 236                                            DEV_TX_OFFLOAD_TCP_CKSUM)),
 237                 .csum_l2tun = priv->hw_csum_l2tun &&
 238                               (offloads &
 239                                DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM),
 240                 /* Enable Tx loopback for VF devices. */
 241                 .lb = !!priv->vf,
 242                 .bounce_buf = bounce_buf,
 243         };
 244         txq->cq = mlx4_glue->create_cq(priv->ctx, desc, NULL, NULL, 0);
 245         if (!txq->cq) {
 246                 rte_errno = ENOMEM;
 247                 ERROR("%p: CQ creation failure: %s",
 248                       (void *)dev, strerror(rte_errno));
 249                 goto error;
 250         }
 251         qp_init_attr = (struct ibv_qp_init_attr){
 252                 .send_cq = txq->cq,
 253                 .recv_cq = txq->cq,
 254                 .cap = {
 255                         .max_send_wr =
 256                                 RTE_MIN(priv->device_attr.max_qp_wr, desc),
 257                         .max_send_sge = 1,
 258                         .max_inline_data = MLX4_PMD_MAX_INLINE,
 259                 },
 260                 .qp_type = IBV_QPT_RAW_PACKET,
 261                 /* No completion events must occur by default. */
 262                 .sq_sig_all = 0,
 263         };
 264         txq->qp = mlx4_glue->create_qp(priv->pd, &qp_init_attr);
 265         if (!txq->qp) {
 266                 rte_errno = errno ? errno : EINVAL;
 267                 ERROR("%p: QP creation failure: %s",
 268                       (void *)dev, strerror(rte_errno));
 269                 goto error;
 270         }
 271         txq->max_inline = qp_init_attr.cap.max_inline_data;
 272         ret = mlx4_glue->modify_qp
 273                 (txq->qp,
 274                  &(struct ibv_qp_attr){
 275                         .qp_state = IBV_QPS_INIT,
 276                         .port_num = priv->port,
 277                  },
 278                  IBV_QP_STATE | IBV_QP_PORT);
 279         if (ret) {
 280                 rte_errno = ret;
 281                 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
 282                       (void *)dev, strerror(rte_errno));
 283                 goto error;
 284         }
 285         ret = mlx4_glue->modify_qp
 286                 (txq->qp,
 287                  &(struct ibv_qp_attr){
 288                         .qp_state = IBV_QPS_RTR,
 289                  },
 290                  IBV_QP_STATE);
 291         if (ret) {
 292                 rte_errno = ret;
 293                 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
 294                       (void *)dev, strerror(rte_errno));
 295                 goto error;
 296         }
 297         ret = mlx4_glue->modify_qp
 298                 (txq->qp,
 299                  &(struct ibv_qp_attr){
 300                         .qp_state = IBV_QPS_RTS,
 301                  },
 302                  IBV_QP_STATE);
 303         if (ret) {
 304                 rte_errno = ret;
 305                 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
 306                       (void *)dev, strerror(rte_errno));
 307                 goto error;
 308         }
 309         /* Retrieve device queue information. */
 310         mlxdv.cq.in = txq->cq;
 311         mlxdv.cq.out = &dv_cq;
 312         mlxdv.qp.in = txq->qp;
 313         mlxdv.qp.out = &dv_qp;
 314         ret = mlx4_glue->dv_init_obj(&mlxdv, MLX4DV_OBJ_QP | MLX4DV_OBJ_CQ);
 315         if (ret) {
 316                 rte_errno = EINVAL;
 317                 ERROR("%p: failed to obtain information needed for"
 318                       " accessing the device queues", (void *)dev);
 319                 goto error;
 320         }
 321         mlx4_txq_fill_dv_obj_info(txq, &mlxdv);
 322         /* Save first wqe pointer in the first element. */
 323         (&(*txq->elts)[0])->wqe =
 324                 (volatile struct mlx4_wqe_ctrl_seg *)txq->msq.buf;
 325         if (mlx4_mr_btree_init(&txq->mr_ctrl.cache_bh,
 326                                MLX4_MR_BTREE_CACHE_N, socket)) {
 327                 /* rte_errno is already set. */
 328                 goto error;
 329         }
 330         /* Save pointer of global generation number to check memory event. */
 331         txq->mr_ctrl.dev_gen_ptr = &priv->mr.dev_gen;
 332         DEBUG("%p: adding Tx queue %p to list", (void *)dev, (void *)txq);
 333         dev->data->tx_queues[idx] = txq;
 334         return 0;
 335 error:
 336         dev->data->tx_queues[idx] = NULL;
 337         ret = rte_errno;
 338         mlx4_tx_queue_release(txq);
 339         rte_errno = ret;
 340         assert(rte_errno > 0);
 341         return -rte_errno;
 342 }
 343
 344 /**
 345  * DPDK callback to release a Tx queue.
 346  *
 347  * @param dpdk_txq
 348  *   Generic Tx queue pointer.
 349  */
 350 void
 351 mlx4_tx_queue_release(void *dpdk_txq)
 352 {
 353         struct txq *txq = (struct txq *)dpdk_txq;
 354         struct priv *priv;
 355         unsigned int i;
 356
 357         if (txq == NULL)
 358                 return;
 359         priv = txq->priv;
 360         for (i = 0; i != priv->dev->data->nb_tx_queues; ++i)
 361                 if (priv->dev->data->tx_queues[i] == txq) {
 362                         DEBUG("%p: removing Tx queue %p from list",
 363                               (void *)priv->dev, (void *)txq);
 364                         priv->dev->data->tx_queues[i] = NULL;
 365                         break;
 366                 }
 367         mlx4_txq_free_elts(txq);
 368         if (txq->qp)
 369                 claim_zero(mlx4_glue->destroy_qp(txq->qp));
 370         if (txq->cq)
 371                 claim_zero(mlx4_glue->destroy_cq(txq->cq));
 372         mlx4_mr_btree_free(&txq->mr_ctrl.cache_bh);
 373         rte_free(txq);
 374 }