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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / qede / base / ecore_vf.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (c) 2016 - 2018 Cavium Inc.
3 * All rights reserved.
4 * www.cavium.com
5 */
6
7 #include "bcm_osal.h"
8 #include "ecore.h"
9 #include "ecore_hsi_eth.h"
10 #include "ecore_sriov.h"
11 #include "ecore_l2_api.h"
12 #include "ecore_vf.h"
13 #include "ecore_vfpf_if.h"
14 #include "ecore_status.h"
15 #include "reg_addr.h"
16 #include "ecore_int.h"
17 #include "ecore_l2.h"
18 #include "ecore_mcp_api.h"
19 #include "ecore_vf_api.h"
20
21 static void *ecore_vf_pf_prep(struct ecore_hwfn *p_hwfn, u16 type, u16 length)
22 {
23 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
24 void *p_tlv;
25
26 /* This lock is released when we receive PF's response
27 * in ecore_send_msg2pf().
28 * So, ecore_vf_pf_prep() and ecore_send_msg2pf()
29 * must come in sequence.
30 */
31 OSAL_MUTEX_ACQUIRE(&p_iov->mutex);
32
33 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
34 "preparing to send %s tlv over vf pf channel\n",
35 ecore_channel_tlvs_string[type]);
36
37 /* Reset Request offset */
38 p_iov->offset = (u8 *)(p_iov->vf2pf_request);
39
40 /* Clear mailbox - both request and reply */
41 OSAL_MEMSET(p_iov->vf2pf_request, 0, sizeof(union vfpf_tlvs));
42 OSAL_MEMSET(p_iov->pf2vf_reply, 0, sizeof(union pfvf_tlvs));
43
44 /* Init type and length */
45 p_tlv = ecore_add_tlv(&p_iov->offset, type, length);
46
47 /* Init first tlv header */
48 ((struct vfpf_first_tlv *)p_tlv)->reply_address =
49 (u64)p_iov->pf2vf_reply_phys;
50
51 return p_tlv;
52 }
53
54 static void ecore_vf_pf_req_end(struct ecore_hwfn *p_hwfn,
55 enum _ecore_status_t req_status)
56 {
57 union pfvf_tlvs *resp = p_hwfn->vf_iov_info->pf2vf_reply;
58
59 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
60 "VF request status = 0x%x, PF reply status = 0x%x\n",
61 req_status, resp->default_resp.hdr.status);
62
63 OSAL_MUTEX_RELEASE(&p_hwfn->vf_iov_info->mutex);
64 }
65
66 #ifdef CONFIG_ECORE_SW_CHANNEL
67 /* The SW channel implementation of Windows needs to know the 'exact'
68 * response size of any given message. That means that for future
69 * messages we'd be unable to send TLVs to PF if he'll be unable to
70 * answer them if the |response| != |default response|.
71 * We'd need to handshake in acquire capabilities for any such.
72 */
73 #endif
74 static enum _ecore_status_t
75 ecore_send_msg2pf(struct ecore_hwfn *p_hwfn,
76 u8 *done, u32 resp_size)
77 {
78 union vfpf_tlvs *p_req = p_hwfn->vf_iov_info->vf2pf_request;
79 struct ustorm_trigger_vf_zone trigger;
80 struct ustorm_vf_zone *zone_data;
81 enum _ecore_status_t rc = ECORE_SUCCESS;
82 int time = 100;
83
84 zone_data = (struct ustorm_vf_zone *)PXP_VF_BAR0_START_USDM_ZONE_B;
85
86 /* output tlvs list */
87 ecore_dp_tlv_list(p_hwfn, p_req);
88
89 /* need to add the END TLV to the message size */
90 resp_size += sizeof(struct channel_list_end_tlv);
91
92 /* Send TLVs over HW channel */
93 OSAL_MEMSET(&trigger, 0, sizeof(struct ustorm_trigger_vf_zone));
94 trigger.vf_pf_msg_valid = 1;
95
96 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
97 "VF -> PF [%02x] message: [%08x, %08x] --> %p,"
98 " %08x --> %p\n",
99 GET_FIELD(p_hwfn->hw_info.concrete_fid,
100 PXP_CONCRETE_FID_PFID),
101 U64_HI(p_hwfn->vf_iov_info->vf2pf_request_phys),
102 U64_LO(p_hwfn->vf_iov_info->vf2pf_request_phys),
103 &zone_data->non_trigger.vf_pf_msg_addr,
104 *((u32 *)&trigger), &zone_data->trigger);
105
106 REG_WR(p_hwfn,
107 (osal_uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.lo,
108 U64_LO(p_hwfn->vf_iov_info->vf2pf_request_phys));
109
110 REG_WR(p_hwfn,
111 (osal_uintptr_t)&zone_data->non_trigger.vf_pf_msg_addr.hi,
112 U64_HI(p_hwfn->vf_iov_info->vf2pf_request_phys));
113
114 /* The message data must be written first, to prevent trigger before
115 * data is written.
116 */
117 OSAL_WMB(p_hwfn->p_dev);
118
119 REG_WR(p_hwfn, (osal_uintptr_t)&zone_data->trigger,
120 *((u32 *)&trigger));
121
122 /* When PF would be done with the response, it would write back to the
123 * `done' address. Poll until then.
124 */
125 while ((!*done) && time) {
126 OSAL_MSLEEP(25);
127 time--;
128 }
129
130 if (!*done) {
131 DP_NOTICE(p_hwfn, true,
132 "VF <-- PF Timeout [Type %d]\n",
133 p_req->first_tlv.tl.type);
134 rc = ECORE_TIMEOUT;
135 } else {
136 if ((*done != PFVF_STATUS_SUCCESS) &&
137 (*done != PFVF_STATUS_NO_RESOURCE))
138 DP_NOTICE(p_hwfn, false,
139 "PF response: %d [Type %d]\n",
140 *done, p_req->first_tlv.tl.type);
141 else
142 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
143 "PF response: %d [Type %d]\n",
144 *done, p_req->first_tlv.tl.type);
145 }
146
147 return rc;
148 }
149
150 static void ecore_vf_pf_add_qid(struct ecore_hwfn *p_hwfn,
151 struct ecore_queue_cid *p_cid)
152 {
153 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
154 struct vfpf_qid_tlv *p_qid_tlv;
155
156 /* Only add QIDs for the queue if it was negotiated with PF */
157 if (!(p_iov->acquire_resp.pfdev_info.capabilities &
158 PFVF_ACQUIRE_CAP_QUEUE_QIDS))
159 return;
160
161 p_qid_tlv = ecore_add_tlv(&p_iov->offset,
162 CHANNEL_TLV_QID, sizeof(*p_qid_tlv));
163 p_qid_tlv->qid = p_cid->qid_usage_idx;
164 }
165
166 enum _ecore_status_t _ecore_vf_pf_release(struct ecore_hwfn *p_hwfn,
167 bool b_final)
168 {
169 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
170 struct pfvf_def_resp_tlv *resp;
171 struct vfpf_first_tlv *req;
172 u32 size;
173 enum _ecore_status_t rc;
174
175 /* clear mailbox and prep first tlv */
176 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_RELEASE, sizeof(*req));
177
178 /* add list termination tlv */
179 ecore_add_tlv(&p_iov->offset,
180 CHANNEL_TLV_LIST_END,
181 sizeof(struct channel_list_end_tlv));
182
183 resp = &p_iov->pf2vf_reply->default_resp;
184 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
185
186 if (rc == ECORE_SUCCESS && resp->hdr.status != PFVF_STATUS_SUCCESS)
187 rc = ECORE_AGAIN;
188
189 ecore_vf_pf_req_end(p_hwfn, rc);
190 if (!b_final)
191 return rc;
192
193 p_hwfn->b_int_enabled = 0;
194
195 if (p_iov->vf2pf_request)
196 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
197 p_iov->vf2pf_request,
198 p_iov->vf2pf_request_phys,
199 sizeof(union vfpf_tlvs));
200 if (p_iov->pf2vf_reply)
201 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
202 p_iov->pf2vf_reply,
203 p_iov->pf2vf_reply_phys,
204 sizeof(union pfvf_tlvs));
205
206 if (p_iov->bulletin.p_virt) {
207 size = sizeof(struct ecore_bulletin_content);
208 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
209 p_iov->bulletin.p_virt,
210 p_iov->bulletin.phys,
211 size);
212 }
213
214 #ifdef CONFIG_ECORE_LOCK_ALLOC
215 OSAL_MUTEX_DEALLOC(&p_iov->mutex);
216 #endif
217
218 OSAL_FREE(p_hwfn->p_dev, p_hwfn->vf_iov_info);
219 p_hwfn->vf_iov_info = OSAL_NULL;
220
221 return rc;
222 }
223
224 enum _ecore_status_t ecore_vf_pf_release(struct ecore_hwfn *p_hwfn)
225 {
226 return _ecore_vf_pf_release(p_hwfn, true);
227 }
228
229 #define VF_ACQUIRE_THRESH 3
230 static void ecore_vf_pf_acquire_reduce_resc(struct ecore_hwfn *p_hwfn,
231 struct vf_pf_resc_request *p_req,
232 struct pf_vf_resc *p_resp)
233 {
234 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
235 "PF unwilling to fullill resource request: rxq [%02x/%02x] txq [%02x/%02x] sbs [%02x/%02x] mac [%02x/%02x] vlan [%02x/%02x] mc [%02x/%02x] cids [%02x/%02x]. Try PF recommended amount\n",
236 p_req->num_rxqs, p_resp->num_rxqs,
237 p_req->num_rxqs, p_resp->num_txqs,
238 p_req->num_sbs, p_resp->num_sbs,
239 p_req->num_mac_filters, p_resp->num_mac_filters,
240 p_req->num_vlan_filters, p_resp->num_vlan_filters,
241 p_req->num_mc_filters, p_resp->num_mc_filters,
242 p_req->num_cids, p_resp->num_cids);
243
244 /* humble our request */
245 p_req->num_txqs = p_resp->num_txqs;
246 p_req->num_rxqs = p_resp->num_rxqs;
247 p_req->num_sbs = p_resp->num_sbs;
248 p_req->num_mac_filters = p_resp->num_mac_filters;
249 p_req->num_vlan_filters = p_resp->num_vlan_filters;
250 p_req->num_mc_filters = p_resp->num_mc_filters;
251 p_req->num_cids = p_resp->num_cids;
252 }
253
254 static enum _ecore_status_t ecore_vf_pf_acquire(struct ecore_hwfn *p_hwfn)
255 {
256 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
257 struct pfvf_acquire_resp_tlv *resp = &p_iov->pf2vf_reply->acquire_resp;
258 struct pf_vf_pfdev_info *pfdev_info = &resp->pfdev_info;
259 struct ecore_vf_acquire_sw_info vf_sw_info;
260 struct vf_pf_resc_request *p_resc;
261 bool resources_acquired = false;
262 struct vfpf_acquire_tlv *req;
263 int attempts = 0;
264 enum _ecore_status_t rc = ECORE_SUCCESS;
265
266 /* clear mailbox and prep first tlv */
267 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_ACQUIRE, sizeof(*req));
268 p_resc = &req->resc_request;
269
270 /* @@@ TBD: PF may not be ready bnx2x_get_vf_id... */
271 req->vfdev_info.opaque_fid = p_hwfn->hw_info.opaque_fid;
272
273 p_resc->num_rxqs = ECORE_MAX_VF_CHAINS_PER_PF;
274 p_resc->num_txqs = ECORE_MAX_VF_CHAINS_PER_PF;
275 p_resc->num_sbs = ECORE_MAX_VF_CHAINS_PER_PF;
276 p_resc->num_mac_filters = ECORE_ETH_VF_NUM_MAC_FILTERS;
277 p_resc->num_vlan_filters = ECORE_ETH_VF_NUM_VLAN_FILTERS;
278 p_resc->num_cids = ECORE_ETH_VF_DEFAULT_NUM_CIDS;
279
280 OSAL_MEMSET(&vf_sw_info, 0, sizeof(vf_sw_info));
281 OSAL_VF_FILL_ACQUIRE_RESC_REQ(p_hwfn, &req->resc_request, &vf_sw_info);
282
283 req->vfdev_info.os_type = vf_sw_info.os_type;
284 req->vfdev_info.driver_version = vf_sw_info.driver_version;
285 req->vfdev_info.fw_major = FW_MAJOR_VERSION;
286 req->vfdev_info.fw_minor = FW_MINOR_VERSION;
287 req->vfdev_info.fw_revision = FW_REVISION_VERSION;
288 req->vfdev_info.fw_engineering = FW_ENGINEERING_VERSION;
289 req->vfdev_info.eth_fp_hsi_major = ETH_HSI_VER_MAJOR;
290 req->vfdev_info.eth_fp_hsi_minor = ETH_HSI_VER_MINOR;
291
292 /* Fill capability field with any non-deprecated config we support */
293 req->vfdev_info.capabilities |= VFPF_ACQUIRE_CAP_100G;
294
295 /* If we've mapped the doorbell bar, try using queue qids */
296 if (p_iov->b_doorbell_bar)
297 req->vfdev_info.capabilities |= VFPF_ACQUIRE_CAP_PHYSICAL_BAR |
298 VFPF_ACQUIRE_CAP_QUEUE_QIDS;
299
300 /* pf 2 vf bulletin board address */
301 req->bulletin_addr = p_iov->bulletin.phys;
302 req->bulletin_size = p_iov->bulletin.size;
303
304 /* add list termination tlv */
305 ecore_add_tlv(&p_iov->offset,
306 CHANNEL_TLV_LIST_END,
307 sizeof(struct channel_list_end_tlv));
308
309 while (!resources_acquired) {
310 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
311 "attempting to acquire resources\n");
312
313 /* Clear response buffer, as this might be a re-send */
314 OSAL_MEMSET(p_iov->pf2vf_reply, 0,
315 sizeof(union pfvf_tlvs));
316
317 /* send acquire request */
318 rc = ecore_send_msg2pf(p_hwfn,
319 &resp->hdr.status, sizeof(*resp));
320 if (rc != ECORE_SUCCESS)
321 goto exit;
322
323 /* copy acquire response from buffer to p_hwfn */
324 OSAL_MEMCPY(&p_iov->acquire_resp,
325 resp, sizeof(p_iov->acquire_resp));
326
327 attempts++;
328
329 if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
330 /* PF agrees to allocate our resources */
331 if (!(resp->pfdev_info.capabilities &
332 PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE)) {
333 /* It's possible legacy PF mistakenly accepted;
334 * but we don't care - simply mark it as
335 * legacy and continue.
336 */
337 req->vfdev_info.capabilities |=
338 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
339 }
340 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
341 "resources acquired\n");
342 resources_acquired = true;
343 } /* PF refuses to allocate our resources */
344 else if (resp->hdr.status == PFVF_STATUS_NO_RESOURCE &&
345 attempts < VF_ACQUIRE_THRESH) {
346 ecore_vf_pf_acquire_reduce_resc(p_hwfn, p_resc,
347 &resp->resc);
348
349 } else if (resp->hdr.status == PFVF_STATUS_NOT_SUPPORTED) {
350 if (pfdev_info->major_fp_hsi &&
351 (pfdev_info->major_fp_hsi != ETH_HSI_VER_MAJOR)) {
352 DP_NOTICE(p_hwfn, false,
353 "PF uses an incompatible fastpath HSI"
354 " %02x.%02x [VF requires %02x.%02x]."
355 " Please change to a VF driver using"
356 " %02x.xx.\n",
357 pfdev_info->major_fp_hsi,
358 pfdev_info->minor_fp_hsi,
359 ETH_HSI_VER_MAJOR, ETH_HSI_VER_MINOR,
360 pfdev_info->major_fp_hsi);
361 rc = ECORE_INVAL;
362 goto exit;
363 }
364
365 if (!pfdev_info->major_fp_hsi) {
366 if (req->vfdev_info.capabilities &
367 VFPF_ACQUIRE_CAP_PRE_FP_HSI) {
368 DP_NOTICE(p_hwfn, false,
369 "PF uses very old drivers."
370 " Please change to a VF"
371 " driver using no later than"
372 " 8.8.x.x.\n");
373 rc = ECORE_INVAL;
374 goto exit;
375 } else {
376 DP_INFO(p_hwfn,
377 "PF is old - try re-acquire to"
378 " see if it supports FW-version"
379 " override\n");
380 req->vfdev_info.capabilities |=
381 VFPF_ACQUIRE_CAP_PRE_FP_HSI;
382 continue;
383 }
384 }
385
386 /* If PF/VF are using same Major, PF must have had
387 * it's reasons. Simply fail.
388 */
389 DP_NOTICE(p_hwfn, false,
390 "PF rejected acquisition by VF\n");
391 rc = ECORE_INVAL;
392 goto exit;
393 } else {
394 DP_ERR(p_hwfn,
395 "PF returned err %d to VF acquisition request\n",
396 resp->hdr.status);
397 rc = ECORE_AGAIN;
398 goto exit;
399 }
400 }
401
402 /* Mark the PF as legacy, if needed */
403 if (req->vfdev_info.capabilities &
404 VFPF_ACQUIRE_CAP_PRE_FP_HSI)
405 p_iov->b_pre_fp_hsi = true;
406
407 /* In case PF doesn't support multi-queue Tx, update the number of
408 * CIDs to reflect the number of queues [older PFs didn't fill that
409 * field].
410 */
411 if (!(resp->pfdev_info.capabilities &
412 PFVF_ACQUIRE_CAP_QUEUE_QIDS))
413 resp->resc.num_cids = resp->resc.num_rxqs +
414 resp->resc.num_txqs;
415
416 rc = OSAL_VF_UPDATE_ACQUIRE_RESC_RESP(p_hwfn, &resp->resc);
417 if (rc) {
418 DP_NOTICE(p_hwfn, true,
419 "VF_UPDATE_ACQUIRE_RESC_RESP Failed:"
420 " status = 0x%x.\n",
421 rc);
422 rc = ECORE_AGAIN;
423 goto exit;
424 }
425
426 /* Update bulletin board size with response from PF */
427 p_iov->bulletin.size = resp->bulletin_size;
428
429 /* get HW info */
430 p_hwfn->p_dev->type = resp->pfdev_info.dev_type;
431 p_hwfn->p_dev->chip_rev = (u8)resp->pfdev_info.chip_rev;
432
433 DP_INFO(p_hwfn, "Chip details - %s%d\n",
434 ECORE_IS_BB(p_hwfn->p_dev) ? "BB" : "AH",
435 CHIP_REV_IS_A0(p_hwfn->p_dev) ? 0 : 1);
436
437 p_hwfn->p_dev->chip_num = pfdev_info->chip_num & 0xffff;
438
439 /* Learn of the possibility of CMT */
440 if (IS_LEAD_HWFN(p_hwfn)) {
441 if (resp->pfdev_info.capabilities & PFVF_ACQUIRE_CAP_100G) {
442 DP_INFO(p_hwfn, "100g VF\n");
443 p_hwfn->p_dev->num_hwfns = 2;
444 }
445 }
446
447 /* @DPDK */
448 if ((~p_iov->b_pre_fp_hsi &
449 ETH_HSI_VER_MINOR) &&
450 (resp->pfdev_info.minor_fp_hsi < ETH_HSI_VER_MINOR))
451 DP_INFO(p_hwfn,
452 "PF is using older fastpath HSI;"
453 " %02x.%02x is configured\n",
454 ETH_HSI_VER_MAJOR,
455 resp->pfdev_info.minor_fp_hsi);
456
457 exit:
458 ecore_vf_pf_req_end(p_hwfn, rc);
459
460 return rc;
461 }
462
463 u32 ecore_vf_hw_bar_size(struct ecore_hwfn *p_hwfn,
464 enum BAR_ID bar_id)
465 {
466 u32 bar_size;
467
468 /* Regview size is fixed */
469 if (bar_id == BAR_ID_0)
470 return 1 << 17;
471
472 /* Doorbell is received from PF */
473 bar_size = p_hwfn->vf_iov_info->acquire_resp.pfdev_info.bar_size;
474 if (bar_size)
475 return 1 << bar_size;
476 return 0;
477 }
478
479 enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_hwfn *p_hwfn)
480 {
481 struct ecore_hwfn *p_lead = ECORE_LEADING_HWFN(p_hwfn->p_dev);
482 struct ecore_vf_iov *p_iov;
483 u32 reg;
484 enum _ecore_status_t rc;
485
486 /* Set number of hwfns - might be overridden once leading hwfn learns
487 * actual configuration from PF.
488 */
489 if (IS_LEAD_HWFN(p_hwfn))
490 p_hwfn->p_dev->num_hwfns = 1;
491
492 reg = PXP_VF_BAR0_ME_OPAQUE_ADDRESS;
493 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg);
494
495 reg = PXP_VF_BAR0_ME_CONCRETE_ADDRESS;
496 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);
497
498 /* Allocate vf sriov info */
499 p_iov = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_iov));
500 if (!p_iov) {
501 DP_NOTICE(p_hwfn, true,
502 "Failed to allocate `struct ecore_sriov'\n");
503 return ECORE_NOMEM;
504 }
505
506 /* Doorbells are tricky; Upper-layer has alreday set the hwfn doorbell
507 * value, but there are several incompatibily scenarios where that
508 * would be incorrect and we'd need to override it.
509 */
510 if (p_hwfn->doorbells == OSAL_NULL) {
511 p_hwfn->doorbells = (u8 OSAL_IOMEM *)p_hwfn->regview +
512 PXP_VF_BAR0_START_DQ;
513 } else if (p_hwfn == p_lead) {
514 /* For leading hw-function, value is always correct, but need
515 * to handle scenario where legacy PF would not support 100g
516 * mapped bars later.
517 */
518 p_iov->b_doorbell_bar = true;
519 } else {
520 /* here, value would be correct ONLY if the leading hwfn
521 * received indication that mapped-bars are supported.
522 */
523 if (p_lead->vf_iov_info->b_doorbell_bar)
524 p_iov->b_doorbell_bar = true;
525 else
526 p_hwfn->doorbells = (u8 OSAL_IOMEM *)
527 p_hwfn->regview +
528 PXP_VF_BAR0_START_DQ;
529 }
530
531 /* Allocate vf2pf msg */
532 p_iov->vf2pf_request = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
533 &p_iov->
534 vf2pf_request_phys,
535 sizeof(union
536 vfpf_tlvs));
537 if (!p_iov->vf2pf_request) {
538 DP_NOTICE(p_hwfn, true,
539 "Failed to allocate `vf2pf_request' DMA memory\n");
540 goto free_p_iov;
541 }
542
543 p_iov->pf2vf_reply = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
544 &p_iov->
545 pf2vf_reply_phys,
546 sizeof(union pfvf_tlvs));
547 if (!p_iov->pf2vf_reply) {
548 DP_NOTICE(p_hwfn, true,
549 "Failed to allocate `pf2vf_reply' DMA memory\n");
550 goto free_vf2pf_request;
551 }
552
553 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
554 "VF's Request mailbox [%p virt 0x%lx phys], "
555 "Response mailbox [%p virt 0x%lx phys]\n",
556 p_iov->vf2pf_request,
557 (unsigned long)p_iov->vf2pf_request_phys,
558 p_iov->pf2vf_reply,
559 (unsigned long)p_iov->pf2vf_reply_phys);
560
561 /* Allocate Bulletin board */
562 p_iov->bulletin.size = sizeof(struct ecore_bulletin_content);
563 p_iov->bulletin.p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
564 &p_iov->bulletin.
565 phys,
566 p_iov->bulletin.
567 size);
568 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
569 "VF's bulletin Board [%p virt 0x%lx phys 0x%08x bytes]\n",
570 p_iov->bulletin.p_virt, (unsigned long)p_iov->bulletin.phys,
571 p_iov->bulletin.size);
572
573 #ifdef CONFIG_ECORE_LOCK_ALLOC
574 OSAL_MUTEX_ALLOC(p_hwfn, &p_iov->mutex);
575 #endif
576 OSAL_MUTEX_INIT(&p_iov->mutex);
577
578 p_hwfn->vf_iov_info = p_iov;
579
580 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
581
582 rc = ecore_vf_pf_acquire(p_hwfn);
583
584 /* If VF is 100g using a mapped bar and PF is too old to support that,
585 * acquisition would succeed - but the VF would have no way knowing
586 * the size of the doorbell bar configured in HW and thus will not
587 * know how to split it for 2nd hw-function.
588 * In this case we re-try without the indication of the mapped
589 * doorbell.
590 */
591 if (rc == ECORE_SUCCESS &&
592 p_iov->b_doorbell_bar &&
593 !ecore_vf_hw_bar_size(p_hwfn, BAR_ID_1) &&
594 ECORE_IS_CMT(p_hwfn->p_dev)) {
595 rc = _ecore_vf_pf_release(p_hwfn, false);
596 if (rc != ECORE_SUCCESS)
597 return rc;
598
599 p_iov->b_doorbell_bar = false;
600 p_hwfn->doorbells = (u8 OSAL_IOMEM *)p_hwfn->regview +
601 PXP_VF_BAR0_START_DQ;
602 rc = ecore_vf_pf_acquire(p_hwfn);
603 }
604
605 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
606 "Regview [%p], Doorbell [%p], Device-doorbell [%p]\n",
607 p_hwfn->regview, p_hwfn->doorbells,
608 p_hwfn->p_dev->doorbells);
609
610 return rc;
611
612 free_vf2pf_request:
613 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_iov->vf2pf_request,
614 p_iov->vf2pf_request_phys,
615 sizeof(union vfpf_tlvs));
616 free_p_iov:
617 OSAL_FREE(p_hwfn->p_dev, p_iov);
618
619 return ECORE_NOMEM;
620 }
621
622 #define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
623 #define MSTORM_QZONE_START(dev) (TSTORM_QZONE_START + \
624 (TSTORM_QZONE_SIZE * NUM_OF_L2_QUEUES(dev)))
625
626 /* @DPDK - changed enum ecore_tunn_clss to enum ecore_tunn_mode */
627 static void
628 __ecore_vf_prep_tunn_req_tlv(struct vfpf_update_tunn_param_tlv *p_req,
629 struct ecore_tunn_update_type *p_src,
630 enum ecore_tunn_mode mask, u8 *p_cls)
631 {
632 if (p_src->b_update_mode) {
633 p_req->tun_mode_update_mask |= (1 << mask);
634
635 if (p_src->b_mode_enabled)
636 p_req->tunn_mode |= (1 << mask);
637 }
638
639 *p_cls = p_src->tun_cls;
640 }
641
642 /* @DPDK - changed enum ecore_tunn_clss to enum ecore_tunn_mode */
643 static void
644 ecore_vf_prep_tunn_req_tlv(struct vfpf_update_tunn_param_tlv *p_req,
645 struct ecore_tunn_update_type *p_src,
646 enum ecore_tunn_mode mask, u8 *p_cls,
647 struct ecore_tunn_update_udp_port *p_port,
648 u8 *p_update_port, u16 *p_udp_port)
649 {
650 if (p_port->b_update_port) {
651 *p_update_port = 1;
652 *p_udp_port = p_port->port;
653 }
654
655 __ecore_vf_prep_tunn_req_tlv(p_req, p_src, mask, p_cls);
656 }
657
658 void ecore_vf_set_vf_start_tunn_update_param(struct ecore_tunnel_info *p_tun)
659 {
660 if (p_tun->vxlan.b_mode_enabled)
661 p_tun->vxlan.b_update_mode = true;
662 if (p_tun->l2_geneve.b_mode_enabled)
663 p_tun->l2_geneve.b_update_mode = true;
664 if (p_tun->ip_geneve.b_mode_enabled)
665 p_tun->ip_geneve.b_update_mode = true;
666 if (p_tun->l2_gre.b_mode_enabled)
667 p_tun->l2_gre.b_update_mode = true;
668 if (p_tun->ip_gre.b_mode_enabled)
669 p_tun->ip_gre.b_update_mode = true;
670
671 p_tun->b_update_rx_cls = true;
672 p_tun->b_update_tx_cls = true;
673 }
674
675 static void
676 __ecore_vf_update_tunn_param(struct ecore_tunn_update_type *p_tun,
677 u16 feature_mask, u8 tunn_mode, u8 tunn_cls,
678 enum ecore_tunn_mode val)
679 {
680 if (feature_mask & (1 << val)) {
681 p_tun->b_mode_enabled = tunn_mode;
682 p_tun->tun_cls = tunn_cls;
683 } else {
684 p_tun->b_mode_enabled = false;
685 }
686 }
687
688 static void
689 ecore_vf_update_tunn_param(struct ecore_hwfn *p_hwfn,
690 struct ecore_tunnel_info *p_tun,
691 struct pfvf_update_tunn_param_tlv *p_resp)
692 {
693 /* Update mode and classes provided by PF */
694 u16 feat_mask = p_resp->tunn_feature_mask;
695
696 __ecore_vf_update_tunn_param(&p_tun->vxlan, feat_mask,
697 p_resp->vxlan_mode, p_resp->vxlan_clss,
698 ECORE_MODE_VXLAN_TUNN);
699 __ecore_vf_update_tunn_param(&p_tun->l2_geneve, feat_mask,
700 p_resp->l2geneve_mode,
701 p_resp->l2geneve_clss,
702 ECORE_MODE_L2GENEVE_TUNN);
703 __ecore_vf_update_tunn_param(&p_tun->ip_geneve, feat_mask,
704 p_resp->ipgeneve_mode,
705 p_resp->ipgeneve_clss,
706 ECORE_MODE_IPGENEVE_TUNN);
707 __ecore_vf_update_tunn_param(&p_tun->l2_gre, feat_mask,
708 p_resp->l2gre_mode, p_resp->l2gre_clss,
709 ECORE_MODE_L2GRE_TUNN);
710 __ecore_vf_update_tunn_param(&p_tun->ip_gre, feat_mask,
711 p_resp->ipgre_mode, p_resp->ipgre_clss,
712 ECORE_MODE_IPGRE_TUNN);
713 p_tun->geneve_port.port = p_resp->geneve_udp_port;
714 p_tun->vxlan_port.port = p_resp->vxlan_udp_port;
715
716 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
717 "tunn mode: vxlan=0x%x, l2geneve=0x%x, ipgeneve=0x%x, l2gre=0x%x, ipgre=0x%x",
718 p_tun->vxlan.b_mode_enabled, p_tun->l2_geneve.b_mode_enabled,
719 p_tun->ip_geneve.b_mode_enabled,
720 p_tun->l2_gre.b_mode_enabled,
721 p_tun->ip_gre.b_mode_enabled);
722 }
723
724 enum _ecore_status_t
725 ecore_vf_pf_tunnel_param_update(struct ecore_hwfn *p_hwfn,
726 struct ecore_tunnel_info *p_src)
727 {
728 struct ecore_tunnel_info *p_tun = &p_hwfn->p_dev->tunnel;
729 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
730 struct pfvf_update_tunn_param_tlv *p_resp;
731 struct vfpf_update_tunn_param_tlv *p_req;
732 enum _ecore_status_t rc;
733
734 p_req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_UPDATE_TUNN_PARAM,
735 sizeof(*p_req));
736
737 if (p_src->b_update_rx_cls && p_src->b_update_tx_cls)
738 p_req->update_tun_cls = 1;
739
740 ecore_vf_prep_tunn_req_tlv(p_req, &p_src->vxlan, ECORE_MODE_VXLAN_TUNN,
741 &p_req->vxlan_clss, &p_src->vxlan_port,
742 &p_req->update_vxlan_port,
743 &p_req->vxlan_port);
744 ecore_vf_prep_tunn_req_tlv(p_req, &p_src->l2_geneve,
745 ECORE_MODE_L2GENEVE_TUNN,
746 &p_req->l2geneve_clss, &p_src->geneve_port,
747 &p_req->update_geneve_port,
748 &p_req->geneve_port);
749 __ecore_vf_prep_tunn_req_tlv(p_req, &p_src->ip_geneve,
750 ECORE_MODE_IPGENEVE_TUNN,
751 &p_req->ipgeneve_clss);
752 __ecore_vf_prep_tunn_req_tlv(p_req, &p_src->l2_gre,
753 ECORE_MODE_L2GRE_TUNN, &p_req->l2gre_clss);
754 __ecore_vf_prep_tunn_req_tlv(p_req, &p_src->ip_gre,
755 ECORE_MODE_IPGRE_TUNN, &p_req->ipgre_clss);
756
757 /* add list termination tlv */
758 ecore_add_tlv(&p_iov->offset,
759 CHANNEL_TLV_LIST_END,
760 sizeof(struct channel_list_end_tlv));
761
762 p_resp = &p_iov->pf2vf_reply->tunn_param_resp;
763 rc = ecore_send_msg2pf(p_hwfn, &p_resp->hdr.status, sizeof(*p_resp));
764
765 if (rc)
766 goto exit;
767
768 if (p_resp->hdr.status != PFVF_STATUS_SUCCESS) {
769 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
770 "Failed to update tunnel parameters\n");
771 rc = ECORE_INVAL;
772 }
773
774 ecore_vf_update_tunn_param(p_hwfn, p_tun, p_resp);
775 exit:
776 ecore_vf_pf_req_end(p_hwfn, rc);
777 return rc;
778 }
779
780 enum _ecore_status_t
781 ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn,
782 struct ecore_queue_cid *p_cid,
783 u16 bd_max_bytes,
784 dma_addr_t bd_chain_phys_addr,
785 dma_addr_t cqe_pbl_addr,
786 u16 cqe_pbl_size,
787 void OSAL_IOMEM **pp_prod)
788 {
789 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
790 struct pfvf_start_queue_resp_tlv *resp;
791 struct vfpf_start_rxq_tlv *req;
792 u16 rx_qid = p_cid->rel.queue_id;
793 enum _ecore_status_t rc;
794
795 /* clear mailbox and prep first tlv */
796 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_RXQ, sizeof(*req));
797
798 req->rx_qid = rx_qid;
799 req->cqe_pbl_addr = cqe_pbl_addr;
800 req->cqe_pbl_size = cqe_pbl_size;
801 req->rxq_addr = bd_chain_phys_addr;
802 req->hw_sb = p_cid->sb_igu_id;
803 req->sb_index = p_cid->sb_idx;
804 req->bd_max_bytes = bd_max_bytes;
805 req->stat_id = -1; /* Keep initialized, for future compatibility */
806
807 /* If PF is legacy, we'll need to calculate producers ourselves
808 * as well as clean them.
809 */
810 if (p_iov->b_pre_fp_hsi) {
811 u8 hw_qid = p_iov->acquire_resp.resc.hw_qid[rx_qid];
812 u32 init_prod_val = 0;
813
814 *pp_prod = (u8 OSAL_IOMEM *)
815 p_hwfn->regview +
816 MSTORM_QZONE_START(p_hwfn->p_dev) +
817 (hw_qid) * MSTORM_QZONE_SIZE;
818
819 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
820 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
821 (u32 *)(&init_prod_val));
822 }
823
824 ecore_vf_pf_add_qid(p_hwfn, p_cid);
825
826 /* add list termination tlv */
827 ecore_add_tlv(&p_iov->offset,
828 CHANNEL_TLV_LIST_END,
829 sizeof(struct channel_list_end_tlv));
830
831 resp = &p_iov->pf2vf_reply->queue_start;
832 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
833 if (rc)
834 goto exit;
835
836 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
837 rc = ECORE_INVAL;
838 goto exit;
839 }
840
841 /* Learn the address of the producer from the response */
842 if (!p_iov->b_pre_fp_hsi) {
843 u32 init_prod_val = 0;
844
845 *pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview + resp->offset;
846 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
847 "Rxq[0x%02x]: producer at %p [offset 0x%08x]\n",
848 rx_qid, *pp_prod, resp->offset);
849
850 /* Init the rcq, rx bd and rx sge (if valid) producers to 0.
851 * It was actually the PF's responsibility, but since some
852 * old PFs might fail to do so, we do this as well.
853 */
854 OSAL_BUILD_BUG_ON(ETH_HSI_VER_MAJOR != 3);
855 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
856 (u32 *)&init_prod_val);
857 }
858
859 exit:
860 ecore_vf_pf_req_end(p_hwfn, rc);
861
862 return rc;
863 }
864
865 enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn *p_hwfn,
866 struct ecore_queue_cid *p_cid,
867 bool cqe_completion)
868 {
869 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
870 struct vfpf_stop_rxqs_tlv *req;
871 struct pfvf_def_resp_tlv *resp;
872 enum _ecore_status_t rc;
873
874 /* clear mailbox and prep first tlv */
875 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_RXQS, sizeof(*req));
876
877 req->rx_qid = p_cid->rel.queue_id;
878 req->num_rxqs = 1;
879 req->cqe_completion = cqe_completion;
880
881 ecore_vf_pf_add_qid(p_hwfn, p_cid);
882
883 /* add list termination tlv */
884 ecore_add_tlv(&p_iov->offset,
885 CHANNEL_TLV_LIST_END,
886 sizeof(struct channel_list_end_tlv));
887
888 resp = &p_iov->pf2vf_reply->default_resp;
889 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
890 if (rc)
891 goto exit;
892
893 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
894 rc = ECORE_INVAL;
895 goto exit;
896 }
897
898 exit:
899 ecore_vf_pf_req_end(p_hwfn, rc);
900
901 return rc;
902 }
903
904 enum _ecore_status_t
905 ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn,
906 struct ecore_queue_cid *p_cid,
907 dma_addr_t pbl_addr, u16 pbl_size,
908 void OSAL_IOMEM **pp_doorbell)
909 {
910 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
911 struct pfvf_start_queue_resp_tlv *resp;
912 struct vfpf_start_txq_tlv *req;
913 u16 qid = p_cid->rel.queue_id;
914 enum _ecore_status_t rc;
915
916 /* clear mailbox and prep first tlv */
917 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_START_TXQ, sizeof(*req));
918
919 req->tx_qid = qid;
920
921 /* Tx */
922 req->pbl_addr = pbl_addr;
923 req->pbl_size = pbl_size;
924 req->hw_sb = p_cid->sb_igu_id;
925 req->sb_index = p_cid->sb_idx;
926
927 ecore_vf_pf_add_qid(p_hwfn, p_cid);
928
929 /* add list termination tlv */
930 ecore_add_tlv(&p_iov->offset,
931 CHANNEL_TLV_LIST_END,
932 sizeof(struct channel_list_end_tlv));
933
934 resp = &p_iov->pf2vf_reply->queue_start;
935 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
936 if (rc)
937 goto exit;
938
939 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
940 rc = ECORE_INVAL;
941 goto exit;
942 }
943
944 /* Modern PFs provide the actual offsets, while legacy
945 * provided only the queue id.
946 */
947 if (!p_iov->b_pre_fp_hsi) {
948 *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
949 resp->offset;
950 } else {
951 u8 cid = p_iov->acquire_resp.resc.cid[qid];
952
953 *pp_doorbell = (u8 OSAL_IOMEM *)p_hwfn->doorbells +
954 DB_ADDR_VF(cid, DQ_DEMS_LEGACY);
955 }
956
957 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
958 "Txq[0x%02x]: doorbell at %p [offset 0x%08x]\n",
959 qid, *pp_doorbell, resp->offset);
960 exit:
961 ecore_vf_pf_req_end(p_hwfn, rc);
962
963 return rc;
964 }
965
966 enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn *p_hwfn,
967 struct ecore_queue_cid *p_cid)
968 {
969 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
970 struct vfpf_stop_txqs_tlv *req;
971 struct pfvf_def_resp_tlv *resp;
972 enum _ecore_status_t rc;
973
974 /* clear mailbox and prep first tlv */
975 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_STOP_TXQS, sizeof(*req));
976
977 req->tx_qid = p_cid->rel.queue_id;
978 req->num_txqs = 1;
979
980 ecore_vf_pf_add_qid(p_hwfn, p_cid);
981
982 /* add list termination tlv */
983 ecore_add_tlv(&p_iov->offset,
984 CHANNEL_TLV_LIST_END,
985 sizeof(struct channel_list_end_tlv));
986
987 resp = &p_iov->pf2vf_reply->default_resp;
988 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
989 if (rc)
990 goto exit;
991
992 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
993 rc = ECORE_INVAL;
994 goto exit;
995 }
996
997 exit:
998 ecore_vf_pf_req_end(p_hwfn, rc);
999
1000 return rc;
1001 }
1002
1003 enum _ecore_status_t ecore_vf_pf_rxqs_update(struct ecore_hwfn *p_hwfn,
1004 struct ecore_queue_cid **pp_cid,
1005 u8 num_rxqs,
1006 u8 comp_cqe_flg,
1007 u8 comp_event_flg)
1008 {
1009 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1010 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
1011 struct vfpf_update_rxq_tlv *req;
1012 enum _ecore_status_t rc;
1013
1014 /* Starting with CHANNEL_TLV_QID and the need for additional queue
1015 * information, this API stopped supporting multiple rxqs.
1016 * TODO - remove this and change the API to accept a single queue-cid
1017 * in a follow-up patch.
1018 */
1019 if (num_rxqs != 1) {
1020 DP_NOTICE(p_hwfn, true,
1021 "VFs can no longer update more than a single queue\n");
1022 return ECORE_INVAL;
1023 }
1024
1025 /* clear mailbox and prep first tlv */
1026 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_UPDATE_RXQ, sizeof(*req));
1027
1028 req->rx_qid = (*pp_cid)->rel.queue_id;
1029 req->num_rxqs = 1;
1030
1031 if (comp_cqe_flg)
1032 req->flags |= VFPF_RXQ_UPD_COMPLETE_CQE_FLAG;
1033 if (comp_event_flg)
1034 req->flags |= VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG;
1035
1036 ecore_vf_pf_add_qid(p_hwfn, *pp_cid);
1037
1038 /* add list termination tlv */
1039 ecore_add_tlv(&p_iov->offset,
1040 CHANNEL_TLV_LIST_END,
1041 sizeof(struct channel_list_end_tlv));
1042
1043 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1044 if (rc)
1045 goto exit;
1046
1047 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1048 rc = ECORE_INVAL;
1049 goto exit;
1050 }
1051
1052 exit:
1053 ecore_vf_pf_req_end(p_hwfn, rc);
1054 return rc;
1055 }
1056
1057 enum _ecore_status_t
1058 ecore_vf_pf_vport_start(struct ecore_hwfn *p_hwfn, u8 vport_id,
1059 u16 mtu, u8 inner_vlan_removal,
1060 enum ecore_tpa_mode tpa_mode, u8 max_buffers_per_cqe,
1061 u8 only_untagged)
1062 {
1063 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1064 struct vfpf_vport_start_tlv *req;
1065 struct pfvf_def_resp_tlv *resp;
1066 enum _ecore_status_t rc;
1067 int i;
1068
1069 /* clear mailbox and prep first tlv */
1070 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_START, sizeof(*req));
1071
1072 req->mtu = mtu;
1073 req->vport_id = vport_id;
1074 req->inner_vlan_removal = inner_vlan_removal;
1075 req->tpa_mode = tpa_mode;
1076 req->max_buffers_per_cqe = max_buffers_per_cqe;
1077 req->only_untagged = only_untagged;
1078
1079 /* status blocks */
1080 for (i = 0; i < p_hwfn->vf_iov_info->acquire_resp.resc.num_sbs; i++) {
1081 struct ecore_sb_info *p_sb = p_hwfn->vf_iov_info->sbs_info[i];
1082
1083 if (p_sb)
1084 req->sb_addr[i] = p_sb->sb_phys;
1085 }
1086
1087 /* add list termination tlv */
1088 ecore_add_tlv(&p_iov->offset,
1089 CHANNEL_TLV_LIST_END,
1090 sizeof(struct channel_list_end_tlv));
1091
1092 resp = &p_iov->pf2vf_reply->default_resp;
1093 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1094 if (rc)
1095 goto exit;
1096
1097 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1098 rc = ECORE_INVAL;
1099 goto exit;
1100 }
1101
1102 exit:
1103 ecore_vf_pf_req_end(p_hwfn, rc);
1104
1105 return rc;
1106 }
1107
1108 enum _ecore_status_t ecore_vf_pf_vport_stop(struct ecore_hwfn *p_hwfn)
1109 {
1110 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1111 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
1112 enum _ecore_status_t rc;
1113
1114 /* clear mailbox and prep first tlv */
1115 ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_TEARDOWN,
1116 sizeof(struct vfpf_first_tlv));
1117
1118 /* add list termination tlv */
1119 ecore_add_tlv(&p_iov->offset,
1120 CHANNEL_TLV_LIST_END,
1121 sizeof(struct channel_list_end_tlv));
1122
1123 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1124 if (rc)
1125 goto exit;
1126
1127 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1128 rc = ECORE_INVAL;
1129 goto exit;
1130 }
1131
1132 exit:
1133 ecore_vf_pf_req_end(p_hwfn, rc);
1134
1135 return rc;
1136 }
1137
1138 static bool
1139 ecore_vf_handle_vp_update_is_needed(struct ecore_hwfn *p_hwfn,
1140 struct ecore_sp_vport_update_params *p_data,
1141 u16 tlv)
1142 {
1143 switch (tlv) {
1144 case CHANNEL_TLV_VPORT_UPDATE_ACTIVATE:
1145 return !!(p_data->update_vport_active_rx_flg ||
1146 p_data->update_vport_active_tx_flg);
1147 case CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH:
1148 #ifndef ASIC_ONLY
1149 /* FPGA doesn't have PVFC and so can't support tx-switching */
1150 return !!(p_data->update_tx_switching_flg &&
1151 !CHIP_REV_IS_FPGA(p_hwfn->p_dev));
1152 #else
1153 return !!p_data->update_tx_switching_flg;
1154 #endif
1155 case CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP:
1156 return !!p_data->update_inner_vlan_removal_flg;
1157 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN:
1158 return !!p_data->update_accept_any_vlan_flg;
1159 case CHANNEL_TLV_VPORT_UPDATE_MCAST:
1160 return !!p_data->update_approx_mcast_flg;
1161 case CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM:
1162 return !!(p_data->accept_flags.update_rx_mode_config ||
1163 p_data->accept_flags.update_tx_mode_config);
1164 case CHANNEL_TLV_VPORT_UPDATE_RSS:
1165 return !!p_data->rss_params;
1166 case CHANNEL_TLV_VPORT_UPDATE_SGE_TPA:
1167 return !!p_data->sge_tpa_params;
1168 default:
1169 DP_INFO(p_hwfn, "Unexpected vport-update TLV[%d] %s\n",
1170 tlv, ecore_channel_tlvs_string[tlv]);
1171 return false;
1172 }
1173 }
1174
1175 static void
1176 ecore_vf_handle_vp_update_tlvs_resp(struct ecore_hwfn *p_hwfn,
1177 struct ecore_sp_vport_update_params *p_data)
1178 {
1179 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1180 struct pfvf_def_resp_tlv *p_resp;
1181 u16 tlv;
1182
1183 for (tlv = CHANNEL_TLV_VPORT_UPDATE_ACTIVATE;
1184 tlv < CHANNEL_TLV_VPORT_UPDATE_MAX;
1185 tlv++) {
1186 if (!ecore_vf_handle_vp_update_is_needed(p_hwfn, p_data, tlv))
1187 continue;
1188
1189 p_resp = (struct pfvf_def_resp_tlv *)
1190 ecore_iov_search_list_tlvs(p_hwfn, p_iov->pf2vf_reply, tlv);
1191 if (p_resp && p_resp->hdr.status)
1192 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1193 "TLV[%d] type %s Configuration %s\n",
1194 tlv, ecore_channel_tlvs_string[tlv],
1195 (p_resp && p_resp->hdr.status) ? "succeeded"
1196 : "failed");
1197 }
1198 }
1199
1200 enum _ecore_status_t
1201 ecore_vf_pf_vport_update(struct ecore_hwfn *p_hwfn,
1202 struct ecore_sp_vport_update_params *p_params)
1203 {
1204 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1205 struct vfpf_vport_update_tlv *req;
1206 struct pfvf_def_resp_tlv *resp;
1207 u8 update_rx, update_tx;
1208 u32 resp_size = 0;
1209 u16 size, tlv;
1210 enum _ecore_status_t rc;
1211
1212 resp = &p_iov->pf2vf_reply->default_resp;
1213 resp_size = sizeof(*resp);
1214
1215 update_rx = p_params->update_vport_active_rx_flg;
1216 update_tx = p_params->update_vport_active_tx_flg;
1217
1218 /* clear mailbox and prep header tlv */
1219 ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_VPORT_UPDATE, sizeof(*req));
1220
1221 /* Prepare extended tlvs */
1222 if (update_rx || update_tx) {
1223 struct vfpf_vport_update_activate_tlv *p_act_tlv;
1224
1225 size = sizeof(struct vfpf_vport_update_activate_tlv);
1226 p_act_tlv = ecore_add_tlv(&p_iov->offset,
1227 CHANNEL_TLV_VPORT_UPDATE_ACTIVATE,
1228 size);
1229 resp_size += sizeof(struct pfvf_def_resp_tlv);
1230
1231 if (update_rx) {
1232 p_act_tlv->update_rx = update_rx;
1233 p_act_tlv->active_rx = p_params->vport_active_rx_flg;
1234 }
1235
1236 if (update_tx) {
1237 p_act_tlv->update_tx = update_tx;
1238 p_act_tlv->active_tx = p_params->vport_active_tx_flg;
1239 }
1240 }
1241
1242 if (p_params->update_inner_vlan_removal_flg) {
1243 struct vfpf_vport_update_vlan_strip_tlv *p_vlan_tlv;
1244
1245 size = sizeof(struct vfpf_vport_update_vlan_strip_tlv);
1246 p_vlan_tlv = ecore_add_tlv(&p_iov->offset,
1247 CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP,
1248 size);
1249 resp_size += sizeof(struct pfvf_def_resp_tlv);
1250
1251 p_vlan_tlv->remove_vlan = p_params->inner_vlan_removal_flg;
1252 }
1253
1254 if (p_params->update_tx_switching_flg) {
1255 struct vfpf_vport_update_tx_switch_tlv *p_tx_switch_tlv;
1256
1257 size = sizeof(struct vfpf_vport_update_tx_switch_tlv);
1258 tlv = CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH;
1259 p_tx_switch_tlv = ecore_add_tlv(&p_iov->offset,
1260 tlv, size);
1261 resp_size += sizeof(struct pfvf_def_resp_tlv);
1262
1263 p_tx_switch_tlv->tx_switching = p_params->tx_switching_flg;
1264 }
1265
1266 if (p_params->update_approx_mcast_flg) {
1267 struct vfpf_vport_update_mcast_bin_tlv *p_mcast_tlv;
1268
1269 size = sizeof(struct vfpf_vport_update_mcast_bin_tlv);
1270 p_mcast_tlv = ecore_add_tlv(&p_iov->offset,
1271 CHANNEL_TLV_VPORT_UPDATE_MCAST,
1272 size);
1273 resp_size += sizeof(struct pfvf_def_resp_tlv);
1274
1275 OSAL_MEMCPY(p_mcast_tlv->bins, p_params->bins,
1276 sizeof(u32) * ETH_MULTICAST_MAC_BINS_IN_REGS);
1277 }
1278
1279 update_rx = p_params->accept_flags.update_rx_mode_config;
1280 update_tx = p_params->accept_flags.update_tx_mode_config;
1281
1282 if (update_rx || update_tx) {
1283 struct vfpf_vport_update_accept_param_tlv *p_accept_tlv;
1284
1285 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM;
1286 size = sizeof(struct vfpf_vport_update_accept_param_tlv);
1287 p_accept_tlv = ecore_add_tlv(&p_iov->offset, tlv, size);
1288 resp_size += sizeof(struct pfvf_def_resp_tlv);
1289
1290 if (update_rx) {
1291 p_accept_tlv->update_rx_mode = update_rx;
1292 p_accept_tlv->rx_accept_filter =
1293 p_params->accept_flags.rx_accept_filter;
1294 }
1295
1296 if (update_tx) {
1297 p_accept_tlv->update_tx_mode = update_tx;
1298 p_accept_tlv->tx_accept_filter =
1299 p_params->accept_flags.tx_accept_filter;
1300 }
1301 }
1302
1303 if (p_params->rss_params) {
1304 struct ecore_rss_params *rss_params = p_params->rss_params;
1305 struct vfpf_vport_update_rss_tlv *p_rss_tlv;
1306 int i, table_size;
1307
1308 size = sizeof(struct vfpf_vport_update_rss_tlv);
1309 p_rss_tlv = ecore_add_tlv(&p_iov->offset,
1310 CHANNEL_TLV_VPORT_UPDATE_RSS, size);
1311 resp_size += sizeof(struct pfvf_def_resp_tlv);
1312
1313 if (rss_params->update_rss_config)
1314 p_rss_tlv->update_rss_flags |=
1315 VFPF_UPDATE_RSS_CONFIG_FLAG;
1316 if (rss_params->update_rss_capabilities)
1317 p_rss_tlv->update_rss_flags |=
1318 VFPF_UPDATE_RSS_CAPS_FLAG;
1319 if (rss_params->update_rss_ind_table)
1320 p_rss_tlv->update_rss_flags |=
1321 VFPF_UPDATE_RSS_IND_TABLE_FLAG;
1322 if (rss_params->update_rss_key)
1323 p_rss_tlv->update_rss_flags |= VFPF_UPDATE_RSS_KEY_FLAG;
1324
1325 p_rss_tlv->rss_enable = rss_params->rss_enable;
1326 p_rss_tlv->rss_caps = rss_params->rss_caps;
1327 p_rss_tlv->rss_table_size_log = rss_params->rss_table_size_log;
1328
1329 table_size = OSAL_MIN_T(int, T_ETH_INDIRECTION_TABLE_SIZE,
1330 1 << p_rss_tlv->rss_table_size_log);
1331 for (i = 0; i < table_size; i++) {
1332 struct ecore_queue_cid *p_queue;
1333
1334 p_queue = rss_params->rss_ind_table[i];
1335 p_rss_tlv->rss_ind_table[i] = p_queue->rel.queue_id;
1336 }
1337
1338 OSAL_MEMCPY(p_rss_tlv->rss_key, rss_params->rss_key,
1339 sizeof(rss_params->rss_key));
1340 }
1341
1342 if (p_params->update_accept_any_vlan_flg) {
1343 struct vfpf_vport_update_accept_any_vlan_tlv *p_any_vlan_tlv;
1344
1345 size = sizeof(struct vfpf_vport_update_accept_any_vlan_tlv);
1346 tlv = CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN;
1347 p_any_vlan_tlv = ecore_add_tlv(&p_iov->offset, tlv, size);
1348
1349 resp_size += sizeof(struct pfvf_def_resp_tlv);
1350 p_any_vlan_tlv->accept_any_vlan = p_params->accept_any_vlan;
1351 p_any_vlan_tlv->update_accept_any_vlan_flg =
1352 p_params->update_accept_any_vlan_flg;
1353 }
1354
1355 if (p_params->sge_tpa_params) {
1356 struct ecore_sge_tpa_params *sge_tpa_params;
1357 struct vfpf_vport_update_sge_tpa_tlv *p_sge_tpa_tlv;
1358
1359 sge_tpa_params = p_params->sge_tpa_params;
1360 size = sizeof(struct vfpf_vport_update_sge_tpa_tlv);
1361 p_sge_tpa_tlv = ecore_add_tlv(&p_iov->offset,
1362 CHANNEL_TLV_VPORT_UPDATE_SGE_TPA,
1363 size);
1364 resp_size += sizeof(struct pfvf_def_resp_tlv);
1365
1366 if (sge_tpa_params->update_tpa_en_flg)
1367 p_sge_tpa_tlv->update_sge_tpa_flags |=
1368 VFPF_UPDATE_TPA_EN_FLAG;
1369 if (sge_tpa_params->update_tpa_param_flg)
1370 p_sge_tpa_tlv->update_sge_tpa_flags |=
1371 VFPF_UPDATE_TPA_PARAM_FLAG;
1372
1373 if (sge_tpa_params->tpa_ipv4_en_flg)
1374 p_sge_tpa_tlv->sge_tpa_flags |= VFPF_TPA_IPV4_EN_FLAG;
1375 if (sge_tpa_params->tpa_ipv6_en_flg)
1376 p_sge_tpa_tlv->sge_tpa_flags |= VFPF_TPA_IPV6_EN_FLAG;
1377 if (sge_tpa_params->tpa_pkt_split_flg)
1378 p_sge_tpa_tlv->sge_tpa_flags |= VFPF_TPA_PKT_SPLIT_FLAG;
1379 if (sge_tpa_params->tpa_hdr_data_split_flg)
1380 p_sge_tpa_tlv->sge_tpa_flags |=
1381 VFPF_TPA_HDR_DATA_SPLIT_FLAG;
1382 if (sge_tpa_params->tpa_gro_consistent_flg)
1383 p_sge_tpa_tlv->sge_tpa_flags |=
1384 VFPF_TPA_GRO_CONSIST_FLAG;
1385 if (sge_tpa_params->tpa_ipv4_tunn_en_flg)
1386 p_sge_tpa_tlv->sge_tpa_flags |=
1387 VFPF_TPA_TUNN_IPV4_EN_FLAG;
1388 if (sge_tpa_params->tpa_ipv6_tunn_en_flg)
1389 p_sge_tpa_tlv->sge_tpa_flags |=
1390 VFPF_TPA_TUNN_IPV6_EN_FLAG;
1391
1392 p_sge_tpa_tlv->tpa_max_aggs_num =
1393 sge_tpa_params->tpa_max_aggs_num;
1394 p_sge_tpa_tlv->tpa_max_size = sge_tpa_params->tpa_max_size;
1395 p_sge_tpa_tlv->tpa_min_size_to_start =
1396 sge_tpa_params->tpa_min_size_to_start;
1397 p_sge_tpa_tlv->tpa_min_size_to_cont =
1398 sge_tpa_params->tpa_min_size_to_cont;
1399
1400 p_sge_tpa_tlv->max_buffers_per_cqe =
1401 sge_tpa_params->max_buffers_per_cqe;
1402 }
1403
1404 /* add list termination tlv */
1405 ecore_add_tlv(&p_iov->offset,
1406 CHANNEL_TLV_LIST_END,
1407 sizeof(struct channel_list_end_tlv));
1408
1409 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, resp_size);
1410 if (rc)
1411 goto exit;
1412
1413 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1414 rc = ECORE_INVAL;
1415 goto exit;
1416 }
1417
1418 ecore_vf_handle_vp_update_tlvs_resp(p_hwfn, p_params);
1419
1420 exit:
1421 ecore_vf_pf_req_end(p_hwfn, rc);
1422
1423 return rc;
1424 }
1425
1426 enum _ecore_status_t ecore_vf_pf_reset(struct ecore_hwfn *p_hwfn)
1427 {
1428 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1429 struct pfvf_def_resp_tlv *resp;
1430 struct vfpf_first_tlv *req;
1431 enum _ecore_status_t rc;
1432
1433 /* clear mailbox and prep first tlv */
1434 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_CLOSE, sizeof(*req));
1435
1436 /* add list termination tlv */
1437 ecore_add_tlv(&p_iov->offset,
1438 CHANNEL_TLV_LIST_END,
1439 sizeof(struct channel_list_end_tlv));
1440
1441 resp = &p_iov->pf2vf_reply->default_resp;
1442 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1443 if (rc)
1444 goto exit;
1445
1446 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1447 rc = ECORE_AGAIN;
1448 goto exit;
1449 }
1450
1451 p_hwfn->b_int_enabled = 0;
1452
1453 exit:
1454 ecore_vf_pf_req_end(p_hwfn, rc);
1455
1456 return rc;
1457 }
1458
1459 void ecore_vf_pf_filter_mcast(struct ecore_hwfn *p_hwfn,
1460 struct ecore_filter_mcast *p_filter_cmd)
1461 {
1462 struct ecore_sp_vport_update_params sp_params;
1463 int i;
1464
1465 OSAL_MEMSET(&sp_params, 0, sizeof(sp_params));
1466 sp_params.update_approx_mcast_flg = 1;
1467
1468 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) {
1469 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) {
1470 u32 bit;
1471
1472 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]);
1473 sp_params.bins[bit / 32] |= 1 << (bit % 32);
1474 }
1475 }
1476
1477 ecore_vf_pf_vport_update(p_hwfn, &sp_params);
1478 }
1479
1480 enum _ecore_status_t ecore_vf_pf_filter_ucast(struct ecore_hwfn *p_hwfn,
1481 struct ecore_filter_ucast
1482 *p_ucast)
1483 {
1484 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1485 struct vfpf_ucast_filter_tlv *req;
1486 struct pfvf_def_resp_tlv *resp;
1487 enum _ecore_status_t rc;
1488
1489 /* Sanitize */
1490 if (p_ucast->opcode == ECORE_FILTER_MOVE) {
1491 DP_NOTICE(p_hwfn, true,
1492 "VFs don't support Moving of filters\n");
1493 return ECORE_INVAL;
1494 }
1495
1496 /* clear mailbox and prep first tlv */
1497 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_UCAST_FILTER, sizeof(*req));
1498 req->opcode = (u8)p_ucast->opcode;
1499 req->type = (u8)p_ucast->type;
1500 OSAL_MEMCPY(req->mac, p_ucast->mac, ETH_ALEN);
1501 req->vlan = p_ucast->vlan;
1502
1503 /* add list termination tlv */
1504 ecore_add_tlv(&p_iov->offset,
1505 CHANNEL_TLV_LIST_END,
1506 sizeof(struct channel_list_end_tlv));
1507
1508 resp = &p_iov->pf2vf_reply->default_resp;
1509 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1510 if (rc)
1511 goto exit;
1512
1513 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1514 rc = ECORE_AGAIN;
1515 goto exit;
1516 }
1517
1518 exit:
1519 ecore_vf_pf_req_end(p_hwfn, rc);
1520
1521 return rc;
1522 }
1523
1524 enum _ecore_status_t ecore_vf_pf_int_cleanup(struct ecore_hwfn *p_hwfn)
1525 {
1526 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1527 struct pfvf_def_resp_tlv *resp = &p_iov->pf2vf_reply->default_resp;
1528 enum _ecore_status_t rc;
1529
1530 /* clear mailbox and prep first tlv */
1531 ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_INT_CLEANUP,
1532 sizeof(struct vfpf_first_tlv));
1533
1534 /* add list termination tlv */
1535 ecore_add_tlv(&p_iov->offset,
1536 CHANNEL_TLV_LIST_END,
1537 sizeof(struct channel_list_end_tlv));
1538
1539 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1540 if (rc)
1541 goto exit;
1542
1543 if (resp->hdr.status != PFVF_STATUS_SUCCESS) {
1544 rc = ECORE_INVAL;
1545 goto exit;
1546 }
1547
1548 exit:
1549 ecore_vf_pf_req_end(p_hwfn, rc);
1550
1551 return rc;
1552 }
1553
1554 enum _ecore_status_t ecore_vf_pf_get_coalesce(struct ecore_hwfn *p_hwfn,
1555 u16 *p_coal,
1556 struct ecore_queue_cid *p_cid)
1557 {
1558 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1559 struct pfvf_read_coal_resp_tlv *resp;
1560 struct vfpf_read_coal_req_tlv *req;
1561 enum _ecore_status_t rc;
1562
1563 /* clear mailbox and prep header tlv */
1564 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_COALESCE_READ,
1565 sizeof(*req));
1566 req->qid = p_cid->rel.queue_id;
1567 req->is_rx = p_cid->b_is_rx ? 1 : 0;
1568
1569 ecore_add_tlv(&p_iov->offset, CHANNEL_TLV_LIST_END,
1570 sizeof(struct channel_list_end_tlv));
1571 resp = &p_iov->pf2vf_reply->read_coal_resp;
1572
1573 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1574 if (rc != ECORE_SUCCESS)
1575 goto exit;
1576
1577 if (resp->hdr.status != PFVF_STATUS_SUCCESS)
1578 goto exit;
1579
1580 *p_coal = resp->coal;
1581 exit:
1582 ecore_vf_pf_req_end(p_hwfn, rc);
1583
1584 return rc;
1585 }
1586
1587 enum _ecore_status_t
1588 ecore_vf_pf_set_coalesce(struct ecore_hwfn *p_hwfn, u16 rx_coal, u16 tx_coal,
1589 struct ecore_queue_cid *p_cid)
1590 {
1591 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1592 struct vfpf_update_coalesce *req;
1593 struct pfvf_def_resp_tlv *resp;
1594 enum _ecore_status_t rc;
1595
1596 /* clear mailbox and prep header tlv */
1597 req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_COALESCE_UPDATE,
1598 sizeof(*req));
1599
1600 req->rx_coal = rx_coal;
1601 req->tx_coal = tx_coal;
1602 req->qid = p_cid->rel.queue_id;
1603
1604 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1605 "Setting coalesce rx_coal = %d, tx_coal = %d at queue = %d\n",
1606 rx_coal, tx_coal, req->qid);
1607
1608 /* add list termination tlv */
1609 ecore_add_tlv(&p_iov->offset, CHANNEL_TLV_LIST_END,
1610 sizeof(struct channel_list_end_tlv));
1611
1612 resp = &p_iov->pf2vf_reply->default_resp;
1613 rc = ecore_send_msg2pf(p_hwfn, &resp->hdr.status, sizeof(*resp));
1614
1615 if (rc != ECORE_SUCCESS)
1616 goto exit;
1617
1618 if (resp->hdr.status != PFVF_STATUS_SUCCESS)
1619 goto exit;
1620
1621 p_hwfn->p_dev->rx_coalesce_usecs = rx_coal;
1622 p_hwfn->p_dev->tx_coalesce_usecs = tx_coal;
1623
1624 exit:
1625 ecore_vf_pf_req_end(p_hwfn, rc);
1626 return rc;
1627 }
1628
1629 enum _ecore_status_t
1630 ecore_vf_pf_update_mtu(struct ecore_hwfn *p_hwfn, u16 mtu)
1631 {
1632 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1633 struct vfpf_update_mtu_tlv *p_req;
1634 struct pfvf_def_resp_tlv *p_resp;
1635 enum _ecore_status_t rc;
1636
1637 if (!mtu)
1638 return ECORE_INVAL;
1639
1640 /* clear mailbox and prep header tlv */
1641 p_req = ecore_vf_pf_prep(p_hwfn, CHANNEL_TLV_UPDATE_MTU,
1642 sizeof(*p_req));
1643 p_req->mtu = mtu;
1644 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1645 "Requesting MTU update to %d\n", mtu);
1646
1647 /* add list termination tlv */
1648 ecore_add_tlv(&p_iov->offset,
1649 CHANNEL_TLV_LIST_END,
1650 sizeof(struct channel_list_end_tlv));
1651
1652 p_resp = &p_iov->pf2vf_reply->default_resp;
1653 rc = ecore_send_msg2pf(p_hwfn, &p_resp->hdr.status, sizeof(*p_resp));
1654 if (p_resp->hdr.status == PFVF_STATUS_NOT_SUPPORTED)
1655 rc = ECORE_INVAL;
1656
1657 ecore_vf_pf_req_end(p_hwfn, rc);
1658
1659 return rc;
1660 }
1661
1662 u16 ecore_vf_get_igu_sb_id(struct ecore_hwfn *p_hwfn,
1663 u16 sb_id)
1664 {
1665 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1666
1667 if (!p_iov) {
1668 DP_NOTICE(p_hwfn, true, "vf_sriov_info isn't initialized\n");
1669 return 0;
1670 }
1671
1672 return p_iov->acquire_resp.resc.hw_sbs[sb_id].hw_sb_id;
1673 }
1674
1675 void ecore_vf_set_sb_info(struct ecore_hwfn *p_hwfn,
1676 u16 sb_id, struct ecore_sb_info *p_sb)
1677 {
1678 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1679
1680 if (!p_iov) {
1681 DP_NOTICE(p_hwfn, true, "vf_sriov_info isn't initialized\n");
1682 return;
1683 }
1684
1685 if (sb_id >= PFVF_MAX_SBS_PER_VF) {
1686 DP_NOTICE(p_hwfn, true, "Can't configure SB %04x\n", sb_id);
1687 return;
1688 }
1689
1690 p_iov->sbs_info[sb_id] = p_sb;
1691 }
1692
1693 enum _ecore_status_t ecore_vf_read_bulletin(struct ecore_hwfn *p_hwfn,
1694 u8 *p_change)
1695 {
1696 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info;
1697 struct ecore_bulletin_content shadow;
1698 u32 crc, crc_size;
1699
1700 crc_size = sizeof(p_iov->bulletin.p_virt->crc);
1701 *p_change = 0;
1702
1703 /* Need to guarantee PF is not in the middle of writing it */
1704 OSAL_MEMCPY(&shadow, p_iov->bulletin.p_virt, p_iov->bulletin.size);
1705
1706 /* If version did not update, no need to do anything */
1707 if (shadow.version == p_iov->bulletin_shadow.version)
1708 return ECORE_SUCCESS;
1709
1710 /* Verify the bulletin we see is valid */
1711 crc = OSAL_CRC32(0, (u8 *)&shadow + crc_size,
1712 p_iov->bulletin.size - crc_size);
1713 if (crc != shadow.crc)
1714 return ECORE_AGAIN;
1715
1716 /* Set the shadow bulletin and process it */
1717 OSAL_MEMCPY(&p_iov->bulletin_shadow, &shadow, p_iov->bulletin.size);
1718
1719 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1720 "Read a bulletin update %08x\n", shadow.version);
1721
1722 *p_change = 1;
1723
1724 return ECORE_SUCCESS;
1725 }
1726
1727 void __ecore_vf_get_link_params(struct ecore_mcp_link_params *p_params,
1728 struct ecore_bulletin_content *p_bulletin)
1729 {
1730 OSAL_MEMSET(p_params, 0, sizeof(*p_params));
1731
1732 p_params->speed.autoneg = p_bulletin->req_autoneg;
1733 p_params->speed.advertised_speeds = p_bulletin->req_adv_speed;
1734 p_params->speed.forced_speed = p_bulletin->req_forced_speed;
1735 p_params->pause.autoneg = p_bulletin->req_autoneg_pause;
1736 p_params->pause.forced_rx = p_bulletin->req_forced_rx;
1737 p_params->pause.forced_tx = p_bulletin->req_forced_tx;
1738 p_params->loopback_mode = p_bulletin->req_loopback;
1739 }
1740
1741 void ecore_vf_get_link_params(struct ecore_hwfn *p_hwfn,
1742 struct ecore_mcp_link_params *params)
1743 {
1744 __ecore_vf_get_link_params(params,
1745 &p_hwfn->vf_iov_info->bulletin_shadow);
1746 }
1747
1748 void __ecore_vf_get_link_state(struct ecore_mcp_link_state *p_link,
1749 struct ecore_bulletin_content *p_bulletin)
1750 {
1751 OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1752
1753 p_link->link_up = p_bulletin->link_up;
1754 p_link->speed = p_bulletin->speed;
1755 p_link->full_duplex = p_bulletin->full_duplex;
1756 p_link->an = p_bulletin->autoneg;
1757 p_link->an_complete = p_bulletin->autoneg_complete;
1758 p_link->parallel_detection = p_bulletin->parallel_detection;
1759 p_link->pfc_enabled = p_bulletin->pfc_enabled;
1760 p_link->partner_adv_speed = p_bulletin->partner_adv_speed;
1761 p_link->partner_tx_flow_ctrl_en = p_bulletin->partner_tx_flow_ctrl_en;
1762 p_link->partner_rx_flow_ctrl_en = p_bulletin->partner_rx_flow_ctrl_en;
1763 p_link->partner_adv_pause = p_bulletin->partner_adv_pause;
1764 p_link->sfp_tx_fault = p_bulletin->sfp_tx_fault;
1765 }
1766
1767 void ecore_vf_get_link_state(struct ecore_hwfn *p_hwfn,
1768 struct ecore_mcp_link_state *link)
1769 {
1770 __ecore_vf_get_link_state(link,
1771 &p_hwfn->vf_iov_info->bulletin_shadow);
1772 }
1773
1774 void __ecore_vf_get_link_caps(struct ecore_mcp_link_capabilities *p_link_caps,
1775 struct ecore_bulletin_content *p_bulletin)
1776 {
1777 OSAL_MEMSET(p_link_caps, 0, sizeof(*p_link_caps));
1778 p_link_caps->speed_capabilities = p_bulletin->capability_speed;
1779 }
1780
1781 void ecore_vf_get_link_caps(struct ecore_hwfn *p_hwfn,
1782 struct ecore_mcp_link_capabilities *p_link_caps)
1783 {
1784 __ecore_vf_get_link_caps(p_link_caps,
1785 &p_hwfn->vf_iov_info->bulletin_shadow);
1786 }
1787
1788 void ecore_vf_get_num_rxqs(struct ecore_hwfn *p_hwfn, u8 *num_rxqs)
1789 {
1790 *num_rxqs = p_hwfn->vf_iov_info->acquire_resp.resc.num_rxqs;
1791 }
1792
1793 void ecore_vf_get_num_txqs(struct ecore_hwfn *p_hwfn,
1794 u8 *num_txqs)
1795 {
1796 *num_txqs = p_hwfn->vf_iov_info->acquire_resp.resc.num_txqs;
1797 }
1798
1799 void ecore_vf_get_port_mac(struct ecore_hwfn *p_hwfn, u8 *port_mac)
1800 {
1801 OSAL_MEMCPY(port_mac,
1802 p_hwfn->vf_iov_info->acquire_resp.pfdev_info.port_mac,
1803 ETH_ALEN);
1804 }
1805
1806 void ecore_vf_get_num_vlan_filters(struct ecore_hwfn *p_hwfn,
1807 u8 *num_vlan_filters)
1808 {
1809 struct ecore_vf_iov *p_vf;
1810
1811 p_vf = p_hwfn->vf_iov_info;
1812 *num_vlan_filters = p_vf->acquire_resp.resc.num_vlan_filters;
1813 }
1814
1815 void ecore_vf_get_num_sbs(struct ecore_hwfn *p_hwfn,
1816 u32 *num_sbs)
1817 {
1818 struct ecore_vf_iov *p_vf;
1819
1820 p_vf = p_hwfn->vf_iov_info;
1821 *num_sbs = (u32)p_vf->acquire_resp.resc.num_sbs;
1822 }
1823
1824 void ecore_vf_get_num_mac_filters(struct ecore_hwfn *p_hwfn,
1825 u32 *num_mac_filters)
1826 {
1827 struct ecore_vf_iov *p_vf = p_hwfn->vf_iov_info;
1828
1829 *num_mac_filters = p_vf->acquire_resp.resc.num_mac_filters;
1830 }
1831
1832 bool ecore_vf_check_mac(struct ecore_hwfn *p_hwfn, u8 *mac)
1833 {
1834 struct ecore_bulletin_content *bulletin;
1835
1836 bulletin = &p_hwfn->vf_iov_info->bulletin_shadow;
1837 if (!(bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)))
1838 return true;
1839
1840 /* Forbid VF from changing a MAC enforced by PF */
1841 if (OSAL_MEMCMP(bulletin->mac, mac, ETH_ALEN))
1842 return false;
1843
1844 return false;
1845 }
1846
1847 bool ecore_vf_bulletin_get_forced_mac(struct ecore_hwfn *hwfn, u8 *dst_mac,
1848 u8 *p_is_forced)
1849 {
1850 struct ecore_bulletin_content *bulletin;
1851
1852 bulletin = &hwfn->vf_iov_info->bulletin_shadow;
1853
1854 if (bulletin->valid_bitmap & (1 << MAC_ADDR_FORCED)) {
1855 if (p_is_forced)
1856 *p_is_forced = 1;
1857 } else if (bulletin->valid_bitmap & (1 << VFPF_BULLETIN_MAC_ADDR)) {
1858 if (p_is_forced)
1859 *p_is_forced = 0;
1860 } else {
1861 return false;
1862 }
1863
1864 OSAL_MEMCPY(dst_mac, bulletin->mac, ETH_ALEN);
1865
1866 return true;
1867 }
1868
1869 void ecore_vf_bulletin_get_udp_ports(struct ecore_hwfn *p_hwfn,
1870 u16 *p_vxlan_port,
1871 u16 *p_geneve_port)
1872 {
1873 struct ecore_bulletin_content *p_bulletin;
1874
1875 p_bulletin = &p_hwfn->vf_iov_info->bulletin_shadow;
1876
1877 *p_vxlan_port = p_bulletin->vxlan_udp_port;
1878 *p_geneve_port = p_bulletin->geneve_udp_port;
1879 }
1880
1881 bool ecore_vf_bulletin_get_forced_vlan(struct ecore_hwfn *hwfn, u16 *dst_pvid)
1882 {
1883 struct ecore_bulletin_content *bulletin;
1884
1885 bulletin = &hwfn->vf_iov_info->bulletin_shadow;
1886
1887 if (!(bulletin->valid_bitmap & (1 << VLAN_ADDR_FORCED)))
1888 return false;
1889
1890 if (dst_pvid)
1891 *dst_pvid = bulletin->pvid;
1892
1893 return true;
1894 }
1895
1896 bool ecore_vf_get_pre_fp_hsi(struct ecore_hwfn *p_hwfn)
1897 {
1898 return p_hwfn->vf_iov_info->b_pre_fp_hsi;
1899 }
1900
1901 void ecore_vf_get_fw_version(struct ecore_hwfn *p_hwfn,
1902 u16 *fw_major, u16 *fw_minor, u16 *fw_rev,
1903 u16 *fw_eng)
1904 {
1905 struct pf_vf_pfdev_info *info;
1906
1907 info = &p_hwfn->vf_iov_info->acquire_resp.pfdev_info;
1908
1909 *fw_major = info->fw_major;
1910 *fw_minor = info->fw_minor;
1911 *fw_rev = info->fw_rev;
1912 *fw_eng = info->fw_eng;
1913 }
1914
1915 #ifdef CONFIG_ECORE_SW_CHANNEL
1916 void ecore_vf_set_hw_channel(struct ecore_hwfn *p_hwfn, bool b_is_hw)
1917 {
1918 p_hwfn->vf_iov_info->b_hw_channel = b_is_hw;
1919 }
1920 #endif
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