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[ceph.git] / ceph / src / spdk / dpdk / drivers / net / sfc / base / ef10_impl.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2015-2019 Solarflare Communications Inc.
5 */
6
7 #ifndef _SYS_EF10_IMPL_H
8 #define _SYS_EF10_IMPL_H
9
10 #ifdef __cplusplus
11 extern "C" {
12 #endif
13
14 #define EF10_EVQ_MAXNEVS 32768
15 #define EF10_EVQ_MINNEVS 512
16
17 #define EF10_RXQ_MAXNDESCS 4096
18 #define EF10_RXQ_MINNDESCS 512
19
20 #define EF10_TXQ_MINNDESCS 512
21
22 #define EF10_EVQ_DESC_SIZE (sizeof (efx_qword_t))
23 #define EF10_RXQ_DESC_SIZE (sizeof (efx_qword_t))
24 #define EF10_TXQ_DESC_SIZE (sizeof (efx_qword_t))
25
26 /* Number of hardware EVQ buffers (for compile-time resource dimensions) */
27 #define EF10_EVQ_MAXNBUFS (64)
28
29 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
30 #define EF10_TXQ_MAXNBUFS 8
31
32 #if EFSYS_OPT_HUNTINGTON
33 # if (EF10_EVQ_MAXNBUFS < HUNT_EVQ_MAXNBUFS)
34 # error "EF10_EVQ_MAXNBUFS too small"
35 # endif
36 #endif /* EFSYS_OPT_HUNTINGTON */
37 #if EFSYS_OPT_MEDFORD
38 # if (EF10_EVQ_MAXNBUFS < MEDFORD_EVQ_MAXNBUFS)
39 # error "EF10_EVQ_MAXNBUFS too small"
40 # endif
41 #endif /* EFSYS_OPT_MEDFORD */
42 #if EFSYS_OPT_MEDFORD2
43 # if (EF10_EVQ_MAXNBUFS < MEDFORD2_EVQ_MAXNBUFS)
44 # error "EF10_EVQ_MAXNBUFS too small"
45 # endif
46 #endif /* EFSYS_OPT_MEDFORD2 */
47
48 /* Number of hardware PIO buffers (for compile-time resource dimensions) */
49 #define EF10_MAX_PIOBUF_NBUFS (16)
50
51 #if EFSYS_OPT_HUNTINGTON
52 # if (EF10_MAX_PIOBUF_NBUFS < HUNT_PIOBUF_NBUFS)
53 # error "EF10_MAX_PIOBUF_NBUFS too small"
54 # endif
55 #endif /* EFSYS_OPT_HUNTINGTON */
56 #if EFSYS_OPT_MEDFORD
57 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD_PIOBUF_NBUFS)
58 # error "EF10_MAX_PIOBUF_NBUFS too small"
59 # endif
60 #endif /* EFSYS_OPT_MEDFORD */
61 #if EFSYS_OPT_MEDFORD2
62 # if (EF10_MAX_PIOBUF_NBUFS < MEDFORD2_PIOBUF_NBUFS)
63 # error "EF10_MAX_PIOBUF_NBUFS too small"
64 # endif
65 #endif /* EFSYS_OPT_MEDFORD2 */
66
67
68
69 /*
70 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
71 * possibly be increased, or the write size reported by newer firmware used
72 * instead.
73 */
74 #define EF10_NVRAM_CHUNK 0x80
75
76 /*
77 * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
78 * to an 8 descriptor boundary.
79 */
80 #define EF10_RX_WPTR_ALIGN 8
81
82 /*
83 * Max byte offset into the packet the TCP header must start for the hardware
84 * to be able to parse the packet correctly.
85 */
86 #define EF10_TCP_HEADER_OFFSET_LIMIT 208
87
88 /* Invalid RSS context handle */
89 #define EF10_RSS_CONTEXT_INVALID (0xffffffff)
90
91
92 /* EV */
93
94 __checkReturn efx_rc_t
95 ef10_ev_init(
96 __in efx_nic_t *enp);
97
98 void
99 ef10_ev_fini(
100 __in efx_nic_t *enp);
101
102 __checkReturn efx_rc_t
103 ef10_ev_qcreate(
104 __in efx_nic_t *enp,
105 __in unsigned int index,
106 __in efsys_mem_t *esmp,
107 __in size_t ndescs,
108 __in uint32_t id,
109 __in uint32_t us,
110 __in uint32_t flags,
111 __in efx_evq_t *eep);
112
113 void
114 ef10_ev_qdestroy(
115 __in efx_evq_t *eep);
116
117 __checkReturn efx_rc_t
118 ef10_ev_qprime(
119 __in efx_evq_t *eep,
120 __in unsigned int count);
121
122 void
123 ef10_ev_qpost(
124 __in efx_evq_t *eep,
125 __in uint16_t data);
126
127 __checkReturn efx_rc_t
128 ef10_ev_qmoderate(
129 __in efx_evq_t *eep,
130 __in unsigned int us);
131
132 #if EFSYS_OPT_QSTATS
133 void
134 ef10_ev_qstats_update(
135 __in efx_evq_t *eep,
136 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
137 #endif /* EFSYS_OPT_QSTATS */
138
139 void
140 ef10_ev_rxlabel_init(
141 __in efx_evq_t *eep,
142 __in efx_rxq_t *erp,
143 __in unsigned int label,
144 __in efx_rxq_type_t type);
145
146 void
147 ef10_ev_rxlabel_fini(
148 __in efx_evq_t *eep,
149 __in unsigned int label);
150
151 /* INTR */
152
153 __checkReturn efx_rc_t
154 ef10_intr_init(
155 __in efx_nic_t *enp,
156 __in efx_intr_type_t type,
157 __in efsys_mem_t *esmp);
158
159 void
160 ef10_intr_enable(
161 __in efx_nic_t *enp);
162
163 void
164 ef10_intr_disable(
165 __in efx_nic_t *enp);
166
167 void
168 ef10_intr_disable_unlocked(
169 __in efx_nic_t *enp);
170
171 __checkReturn efx_rc_t
172 ef10_intr_trigger(
173 __in efx_nic_t *enp,
174 __in unsigned int level);
175
176 void
177 ef10_intr_status_line(
178 __in efx_nic_t *enp,
179 __out boolean_t *fatalp,
180 __out uint32_t *qmaskp);
181
182 void
183 ef10_intr_status_message(
184 __in efx_nic_t *enp,
185 __in unsigned int message,
186 __out boolean_t *fatalp);
187
188 void
189 ef10_intr_fatal(
190 __in efx_nic_t *enp);
191 void
192 ef10_intr_fini(
193 __in efx_nic_t *enp);
194
195 /* NIC */
196
197 extern __checkReturn efx_rc_t
198 efx_mcdi_vadaptor_alloc(
199 __in efx_nic_t *enp,
200 __in uint32_t port_id);
201
202 extern __checkReturn efx_rc_t
203 efx_mcdi_vadaptor_free(
204 __in efx_nic_t *enp,
205 __in uint32_t port_id);
206
207 extern __checkReturn efx_rc_t
208 ef10_nic_probe(
209 __in efx_nic_t *enp);
210
211 extern __checkReturn efx_rc_t
212 ef10_nic_set_drv_limits(
213 __inout efx_nic_t *enp,
214 __in efx_drv_limits_t *edlp);
215
216 extern __checkReturn efx_rc_t
217 ef10_nic_get_vi_pool(
218 __in efx_nic_t *enp,
219 __out uint32_t *vi_countp);
220
221 extern __checkReturn efx_rc_t
222 ef10_nic_get_bar_region(
223 __in efx_nic_t *enp,
224 __in efx_nic_region_t region,
225 __out uint32_t *offsetp,
226 __out size_t *sizep);
227
228 extern __checkReturn efx_rc_t
229 ef10_nic_reset(
230 __in efx_nic_t *enp);
231
232 extern __checkReturn efx_rc_t
233 ef10_nic_init(
234 __in efx_nic_t *enp);
235
236 extern __checkReturn boolean_t
237 ef10_nic_hw_unavailable(
238 __in efx_nic_t *enp);
239
240 extern void
241 ef10_nic_set_hw_unavailable(
242 __in efx_nic_t *enp);
243
244 #if EFSYS_OPT_DIAG
245
246 extern __checkReturn efx_rc_t
247 ef10_nic_register_test(
248 __in efx_nic_t *enp);
249
250 #endif /* EFSYS_OPT_DIAG */
251
252 extern void
253 ef10_nic_fini(
254 __in efx_nic_t *enp);
255
256 extern void
257 ef10_nic_unprobe(
258 __in efx_nic_t *enp);
259
260
261 /* MAC */
262
263 extern __checkReturn efx_rc_t
264 ef10_mac_poll(
265 __in efx_nic_t *enp,
266 __out efx_link_mode_t *link_modep);
267
268 extern __checkReturn efx_rc_t
269 ef10_mac_up(
270 __in efx_nic_t *enp,
271 __out boolean_t *mac_upp);
272
273 extern __checkReturn efx_rc_t
274 ef10_mac_addr_set(
275 __in efx_nic_t *enp);
276
277 extern __checkReturn efx_rc_t
278 ef10_mac_pdu_set(
279 __in efx_nic_t *enp);
280
281 extern __checkReturn efx_rc_t
282 ef10_mac_pdu_get(
283 __in efx_nic_t *enp,
284 __out size_t *pdu);
285
286 extern __checkReturn efx_rc_t
287 ef10_mac_reconfigure(
288 __in efx_nic_t *enp);
289
290 extern __checkReturn efx_rc_t
291 ef10_mac_multicast_list_set(
292 __in efx_nic_t *enp);
293
294 extern __checkReturn efx_rc_t
295 ef10_mac_filter_default_rxq_set(
296 __in efx_nic_t *enp,
297 __in efx_rxq_t *erp,
298 __in boolean_t using_rss);
299
300 extern void
301 ef10_mac_filter_default_rxq_clear(
302 __in efx_nic_t *enp);
303
304 #if EFSYS_OPT_LOOPBACK
305
306 extern __checkReturn efx_rc_t
307 ef10_mac_loopback_set(
308 __in efx_nic_t *enp,
309 __in efx_link_mode_t link_mode,
310 __in efx_loopback_type_t loopback_type);
311
312 #endif /* EFSYS_OPT_LOOPBACK */
313
314 #if EFSYS_OPT_MAC_STATS
315
316 extern __checkReturn efx_rc_t
317 ef10_mac_stats_get_mask(
318 __in efx_nic_t *enp,
319 __inout_bcount(mask_size) uint32_t *maskp,
320 __in size_t mask_size);
321
322 extern __checkReturn efx_rc_t
323 ef10_mac_stats_update(
324 __in efx_nic_t *enp,
325 __in efsys_mem_t *esmp,
326 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
327 __inout_opt uint32_t *generationp);
328
329 #endif /* EFSYS_OPT_MAC_STATS */
330
331
332 /* MCDI */
333
334 #if EFSYS_OPT_MCDI
335
336 extern __checkReturn efx_rc_t
337 ef10_mcdi_init(
338 __in efx_nic_t *enp,
339 __in const efx_mcdi_transport_t *mtp);
340
341 extern void
342 ef10_mcdi_fini(
343 __in efx_nic_t *enp);
344
345 extern void
346 ef10_mcdi_send_request(
347 __in efx_nic_t *enp,
348 __in_bcount(hdr_len) void *hdrp,
349 __in size_t hdr_len,
350 __in_bcount(sdu_len) void *sdup,
351 __in size_t sdu_len);
352
353 extern __checkReturn boolean_t
354 ef10_mcdi_poll_response(
355 __in efx_nic_t *enp);
356
357 extern void
358 ef10_mcdi_read_response(
359 __in efx_nic_t *enp,
360 __out_bcount(length) void *bufferp,
361 __in size_t offset,
362 __in size_t length);
363
364 extern efx_rc_t
365 ef10_mcdi_poll_reboot(
366 __in efx_nic_t *enp);
367
368 extern __checkReturn efx_rc_t
369 ef10_mcdi_feature_supported(
370 __in efx_nic_t *enp,
371 __in efx_mcdi_feature_id_t id,
372 __out boolean_t *supportedp);
373
374 extern void
375 ef10_mcdi_get_timeout(
376 __in efx_nic_t *enp,
377 __in efx_mcdi_req_t *emrp,
378 __out uint32_t *timeoutp);
379
380 #endif /* EFSYS_OPT_MCDI */
381
382 /* NVRAM */
383
384 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
385
386 extern __checkReturn efx_rc_t
387 ef10_nvram_buf_read_tlv(
388 __in efx_nic_t *enp,
389 __in_bcount(max_seg_size) caddr_t seg_data,
390 __in size_t max_seg_size,
391 __in uint32_t tag,
392 __deref_out_bcount_opt(*sizep) caddr_t *datap,
393 __out size_t *sizep);
394
395 extern __checkReturn efx_rc_t
396 ef10_nvram_buf_write_tlv(
397 __inout_bcount(partn_size) caddr_t partn_data,
398 __in size_t partn_size,
399 __in uint32_t tag,
400 __in_bcount(tag_size) caddr_t tag_data,
401 __in size_t tag_size,
402 __out size_t *total_lengthp);
403
404 extern __checkReturn efx_rc_t
405 ef10_nvram_partn_read_tlv(
406 __in efx_nic_t *enp,
407 __in uint32_t partn,
408 __in uint32_t tag,
409 __deref_out_bcount_opt(*sizep) caddr_t *datap,
410 __out size_t *sizep);
411
412 extern __checkReturn efx_rc_t
413 ef10_nvram_partn_write_tlv(
414 __in efx_nic_t *enp,
415 __in uint32_t partn,
416 __in uint32_t tag,
417 __in_bcount(size) caddr_t data,
418 __in size_t size);
419
420 extern __checkReturn efx_rc_t
421 ef10_nvram_partn_write_segment_tlv(
422 __in efx_nic_t *enp,
423 __in uint32_t partn,
424 __in uint32_t tag,
425 __in_bcount(size) caddr_t data,
426 __in size_t size,
427 __in boolean_t all_segments);
428
429 extern __checkReturn efx_rc_t
430 ef10_nvram_partn_lock(
431 __in efx_nic_t *enp,
432 __in uint32_t partn);
433
434 extern __checkReturn efx_rc_t
435 ef10_nvram_partn_unlock(
436 __in efx_nic_t *enp,
437 __in uint32_t partn,
438 __out_opt uint32_t *resultp);
439
440 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
441
442 #if EFSYS_OPT_NVRAM
443
444 #if EFSYS_OPT_DIAG
445
446 extern __checkReturn efx_rc_t
447 ef10_nvram_test(
448 __in efx_nic_t *enp);
449
450 #endif /* EFSYS_OPT_DIAG */
451
452 extern __checkReturn efx_rc_t
453 ef10_nvram_type_to_partn(
454 __in efx_nic_t *enp,
455 __in efx_nvram_type_t type,
456 __out uint32_t *partnp);
457
458 extern __checkReturn efx_rc_t
459 ef10_nvram_partn_size(
460 __in efx_nic_t *enp,
461 __in uint32_t partn,
462 __out size_t *sizep);
463
464 extern __checkReturn efx_rc_t
465 ef10_nvram_partn_info(
466 __in efx_nic_t *enp,
467 __in uint32_t partn,
468 __out efx_nvram_info_t * enip);
469
470 extern __checkReturn efx_rc_t
471 ef10_nvram_partn_rw_start(
472 __in efx_nic_t *enp,
473 __in uint32_t partn,
474 __out size_t *chunk_sizep);
475
476 extern __checkReturn efx_rc_t
477 ef10_nvram_partn_read_mode(
478 __in efx_nic_t *enp,
479 __in uint32_t partn,
480 __in unsigned int offset,
481 __out_bcount(size) caddr_t data,
482 __in size_t size,
483 __in uint32_t mode);
484
485 extern __checkReturn efx_rc_t
486 ef10_nvram_partn_read(
487 __in efx_nic_t *enp,
488 __in uint32_t partn,
489 __in unsigned int offset,
490 __out_bcount(size) caddr_t data,
491 __in size_t size);
492
493 extern __checkReturn efx_rc_t
494 ef10_nvram_partn_read_backup(
495 __in efx_nic_t *enp,
496 __in uint32_t partn,
497 __in unsigned int offset,
498 __out_bcount(size) caddr_t data,
499 __in size_t size);
500
501 extern __checkReturn efx_rc_t
502 ef10_nvram_partn_erase(
503 __in efx_nic_t *enp,
504 __in uint32_t partn,
505 __in unsigned int offset,
506 __in size_t size);
507
508 extern __checkReturn efx_rc_t
509 ef10_nvram_partn_write(
510 __in efx_nic_t *enp,
511 __in uint32_t partn,
512 __in unsigned int offset,
513 __in_bcount(size) caddr_t data,
514 __in size_t size);
515
516 extern __checkReturn efx_rc_t
517 ef10_nvram_partn_rw_finish(
518 __in efx_nic_t *enp,
519 __in uint32_t partn,
520 __out_opt uint32_t *verify_resultp);
521
522 extern __checkReturn efx_rc_t
523 ef10_nvram_partn_get_version(
524 __in efx_nic_t *enp,
525 __in uint32_t partn,
526 __out uint32_t *subtypep,
527 __out_ecount(4) uint16_t version[4]);
528
529 extern __checkReturn efx_rc_t
530 ef10_nvram_partn_set_version(
531 __in efx_nic_t *enp,
532 __in uint32_t partn,
533 __in_ecount(4) uint16_t version[4]);
534
535 extern __checkReturn efx_rc_t
536 ef10_nvram_buffer_validate(
537 __in uint32_t partn,
538 __in_bcount(buffer_size)
539 caddr_t bufferp,
540 __in size_t buffer_size);
541
542 extern void
543 ef10_nvram_buffer_init(
544 __out_bcount(buffer_size)
545 caddr_t bufferp,
546 __in size_t buffer_size);
547
548 extern __checkReturn efx_rc_t
549 ef10_nvram_buffer_create(
550 __in uint32_t partn_type,
551 __out_bcount(buffer_size)
552 caddr_t bufferp,
553 __in size_t buffer_size);
554
555 extern __checkReturn efx_rc_t
556 ef10_nvram_buffer_find_item_start(
557 __in_bcount(buffer_size)
558 caddr_t bufferp,
559 __in size_t buffer_size,
560 __out uint32_t *startp);
561
562 extern __checkReturn efx_rc_t
563 ef10_nvram_buffer_find_end(
564 __in_bcount(buffer_size)
565 caddr_t bufferp,
566 __in size_t buffer_size,
567 __in uint32_t offset,
568 __out uint32_t *endp);
569
570 extern __checkReturn __success(return != B_FALSE) boolean_t
571 ef10_nvram_buffer_find_item(
572 __in_bcount(buffer_size)
573 caddr_t bufferp,
574 __in size_t buffer_size,
575 __in uint32_t offset,
576 __out uint32_t *startp,
577 __out uint32_t *lengthp);
578
579 extern __checkReturn efx_rc_t
580 ef10_nvram_buffer_peek_item(
581 __in_bcount(buffer_size)
582 caddr_t bufferp,
583 __in size_t buffer_size,
584 __in uint32_t offset,
585 __out uint32_t *tagp,
586 __out uint32_t *lengthp,
587 __out uint32_t *value_offsetp);
588
589 extern __checkReturn efx_rc_t
590 ef10_nvram_buffer_get_item(
591 __in_bcount(buffer_size)
592 caddr_t bufferp,
593 __in size_t buffer_size,
594 __in uint32_t offset,
595 __in uint32_t length,
596 __out uint32_t *tagp,
597 __out_bcount_part(value_max_size, *lengthp)
598 caddr_t valuep,
599 __in size_t value_max_size,
600 __out uint32_t *lengthp);
601
602 extern __checkReturn efx_rc_t
603 ef10_nvram_buffer_insert_item(
604 __in_bcount(buffer_size)
605 caddr_t bufferp,
606 __in size_t buffer_size,
607 __in uint32_t offset,
608 __in uint32_t tag,
609 __in_bcount(length) caddr_t valuep,
610 __in uint32_t length,
611 __out uint32_t *lengthp);
612
613 extern __checkReturn efx_rc_t
614 ef10_nvram_buffer_modify_item(
615 __in_bcount(buffer_size)
616 caddr_t bufferp,
617 __in size_t buffer_size,
618 __in uint32_t offset,
619 __in uint32_t tag,
620 __in_bcount(length) caddr_t valuep,
621 __in uint32_t length,
622 __out uint32_t *lengthp);
623
624 extern __checkReturn efx_rc_t
625 ef10_nvram_buffer_delete_item(
626 __in_bcount(buffer_size)
627 caddr_t bufferp,
628 __in size_t buffer_size,
629 __in uint32_t offset,
630 __in uint32_t length,
631 __in uint32_t end);
632
633 extern __checkReturn efx_rc_t
634 ef10_nvram_buffer_finish(
635 __in_bcount(buffer_size)
636 caddr_t bufferp,
637 __in size_t buffer_size);
638
639 #endif /* EFSYS_OPT_NVRAM */
640
641
642 /* PHY */
643
644 typedef struct ef10_link_state_s {
645 efx_phy_link_state_t epls;
646 #if EFSYS_OPT_LOOPBACK
647 efx_loopback_type_t els_loopback;
648 #endif
649 boolean_t els_mac_up;
650 } ef10_link_state_t;
651
652 extern void
653 ef10_phy_link_ev(
654 __in efx_nic_t *enp,
655 __in efx_qword_t *eqp,
656 __out efx_link_mode_t *link_modep);
657
658 extern __checkReturn efx_rc_t
659 ef10_phy_get_link(
660 __in efx_nic_t *enp,
661 __out ef10_link_state_t *elsp);
662
663 extern __checkReturn efx_rc_t
664 ef10_phy_power(
665 __in efx_nic_t *enp,
666 __in boolean_t on);
667
668 extern __checkReturn efx_rc_t
669 ef10_phy_reconfigure(
670 __in efx_nic_t *enp);
671
672 extern __checkReturn efx_rc_t
673 ef10_phy_verify(
674 __in efx_nic_t *enp);
675
676 extern __checkReturn efx_rc_t
677 ef10_phy_oui_get(
678 __in efx_nic_t *enp,
679 __out uint32_t *ouip);
680
681 extern __checkReturn efx_rc_t
682 ef10_phy_link_state_get(
683 __in efx_nic_t *enp,
684 __out efx_phy_link_state_t *eplsp);
685
686 #if EFSYS_OPT_PHY_STATS
687
688 extern __checkReturn efx_rc_t
689 ef10_phy_stats_update(
690 __in efx_nic_t *enp,
691 __in efsys_mem_t *esmp,
692 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
693
694 #endif /* EFSYS_OPT_PHY_STATS */
695
696 #if EFSYS_OPT_BIST
697
698 extern __checkReturn efx_rc_t
699 ef10_bist_enable_offline(
700 __in efx_nic_t *enp);
701
702 extern __checkReturn efx_rc_t
703 ef10_bist_start(
704 __in efx_nic_t *enp,
705 __in efx_bist_type_t type);
706
707 extern __checkReturn efx_rc_t
708 ef10_bist_poll(
709 __in efx_nic_t *enp,
710 __in efx_bist_type_t type,
711 __out efx_bist_result_t *resultp,
712 __out_opt __drv_when(count > 0, __notnull)
713 uint32_t *value_maskp,
714 __out_ecount_opt(count) __drv_when(count > 0, __notnull)
715 unsigned long *valuesp,
716 __in size_t count);
717
718 extern void
719 ef10_bist_stop(
720 __in efx_nic_t *enp,
721 __in efx_bist_type_t type);
722
723 #endif /* EFSYS_OPT_BIST */
724
725 /* TX */
726
727 extern __checkReturn efx_rc_t
728 ef10_tx_init(
729 __in efx_nic_t *enp);
730
731 extern void
732 ef10_tx_fini(
733 __in efx_nic_t *enp);
734
735 extern __checkReturn efx_rc_t
736 ef10_tx_qcreate(
737 __in efx_nic_t *enp,
738 __in unsigned int index,
739 __in unsigned int label,
740 __in efsys_mem_t *esmp,
741 __in size_t ndescs,
742 __in uint32_t id,
743 __in uint16_t flags,
744 __in efx_evq_t *eep,
745 __in efx_txq_t *etp,
746 __out unsigned int *addedp);
747
748 extern void
749 ef10_tx_qdestroy(
750 __in efx_txq_t *etp);
751
752 extern __checkReturn efx_rc_t
753 ef10_tx_qpost(
754 __in efx_txq_t *etp,
755 __in_ecount(ndescs) efx_buffer_t *ebp,
756 __in unsigned int ndescs,
757 __in unsigned int completed,
758 __inout unsigned int *addedp);
759
760 extern void
761 ef10_tx_qpush(
762 __in efx_txq_t *etp,
763 __in unsigned int added,
764 __in unsigned int pushed);
765
766 #if EFSYS_OPT_RX_PACKED_STREAM
767 extern void
768 ef10_rx_qpush_ps_credits(
769 __in efx_rxq_t *erp);
770
771 extern __checkReturn uint8_t *
772 ef10_rx_qps_packet_info(
773 __in efx_rxq_t *erp,
774 __in uint8_t *buffer,
775 __in uint32_t buffer_length,
776 __in uint32_t current_offset,
777 __out uint16_t *lengthp,
778 __out uint32_t *next_offsetp,
779 __out uint32_t *timestamp);
780 #endif
781
782 extern __checkReturn efx_rc_t
783 ef10_tx_qpace(
784 __in efx_txq_t *etp,
785 __in unsigned int ns);
786
787 extern __checkReturn efx_rc_t
788 ef10_tx_qflush(
789 __in efx_txq_t *etp);
790
791 extern void
792 ef10_tx_qenable(
793 __in efx_txq_t *etp);
794
795 extern __checkReturn efx_rc_t
796 ef10_tx_qpio_enable(
797 __in efx_txq_t *etp);
798
799 extern void
800 ef10_tx_qpio_disable(
801 __in efx_txq_t *etp);
802
803 extern __checkReturn efx_rc_t
804 ef10_tx_qpio_write(
805 __in efx_txq_t *etp,
806 __in_ecount(buf_length) uint8_t *buffer,
807 __in size_t buf_length,
808 __in size_t pio_buf_offset);
809
810 extern __checkReturn efx_rc_t
811 ef10_tx_qpio_post(
812 __in efx_txq_t *etp,
813 __in size_t pkt_length,
814 __in unsigned int completed,
815 __inout unsigned int *addedp);
816
817 extern __checkReturn efx_rc_t
818 ef10_tx_qdesc_post(
819 __in efx_txq_t *etp,
820 __in_ecount(n) efx_desc_t *ed,
821 __in unsigned int n,
822 __in unsigned int completed,
823 __inout unsigned int *addedp);
824
825 extern void
826 ef10_tx_qdesc_dma_create(
827 __in efx_txq_t *etp,
828 __in efsys_dma_addr_t addr,
829 __in size_t size,
830 __in boolean_t eop,
831 __out efx_desc_t *edp);
832
833 extern void
834 ef10_tx_qdesc_tso_create(
835 __in efx_txq_t *etp,
836 __in uint16_t ipv4_id,
837 __in uint32_t tcp_seq,
838 __in uint8_t tcp_flags,
839 __out efx_desc_t *edp);
840
841 extern void
842 ef10_tx_qdesc_tso2_create(
843 __in efx_txq_t *etp,
844 __in uint16_t ipv4_id,
845 __in uint16_t outer_ipv4_id,
846 __in uint32_t tcp_seq,
847 __in uint16_t tcp_mss,
848 __out_ecount(count) efx_desc_t *edp,
849 __in int count);
850
851 extern void
852 ef10_tx_qdesc_vlantci_create(
853 __in efx_txq_t *etp,
854 __in uint16_t vlan_tci,
855 __out efx_desc_t *edp);
856
857 extern void
858 ef10_tx_qdesc_checksum_create(
859 __in efx_txq_t *etp,
860 __in uint16_t flags,
861 __out efx_desc_t *edp);
862
863 #if EFSYS_OPT_QSTATS
864
865 extern void
866 ef10_tx_qstats_update(
867 __in efx_txq_t *etp,
868 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
869
870 #endif /* EFSYS_OPT_QSTATS */
871
872 typedef uint32_t efx_piobuf_handle_t;
873
874 #define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
875
876 extern __checkReturn efx_rc_t
877 ef10_nic_pio_alloc(
878 __inout efx_nic_t *enp,
879 __out uint32_t *bufnump,
880 __out efx_piobuf_handle_t *handlep,
881 __out uint32_t *blknump,
882 __out uint32_t *offsetp,
883 __out size_t *sizep);
884
885 extern __checkReturn efx_rc_t
886 ef10_nic_pio_free(
887 __inout efx_nic_t *enp,
888 __in uint32_t bufnum,
889 __in uint32_t blknum);
890
891 extern __checkReturn efx_rc_t
892 ef10_nic_pio_link(
893 __inout efx_nic_t *enp,
894 __in uint32_t vi_index,
895 __in efx_piobuf_handle_t handle);
896
897 extern __checkReturn efx_rc_t
898 ef10_nic_pio_unlink(
899 __inout efx_nic_t *enp,
900 __in uint32_t vi_index);
901
902
903 /* VPD */
904
905 #if EFSYS_OPT_VPD
906
907 extern __checkReturn efx_rc_t
908 ef10_vpd_init(
909 __in efx_nic_t *enp);
910
911 extern __checkReturn efx_rc_t
912 ef10_vpd_size(
913 __in efx_nic_t *enp,
914 __out size_t *sizep);
915
916 extern __checkReturn efx_rc_t
917 ef10_vpd_read(
918 __in efx_nic_t *enp,
919 __out_bcount(size) caddr_t data,
920 __in size_t size);
921
922 extern __checkReturn efx_rc_t
923 ef10_vpd_verify(
924 __in efx_nic_t *enp,
925 __in_bcount(size) caddr_t data,
926 __in size_t size);
927
928 extern __checkReturn efx_rc_t
929 ef10_vpd_reinit(
930 __in efx_nic_t *enp,
931 __in_bcount(size) caddr_t data,
932 __in size_t size);
933
934 extern __checkReturn efx_rc_t
935 ef10_vpd_get(
936 __in efx_nic_t *enp,
937 __in_bcount(size) caddr_t data,
938 __in size_t size,
939 __inout efx_vpd_value_t *evvp);
940
941 extern __checkReturn efx_rc_t
942 ef10_vpd_set(
943 __in efx_nic_t *enp,
944 __in_bcount(size) caddr_t data,
945 __in size_t size,
946 __in efx_vpd_value_t *evvp);
947
948 extern __checkReturn efx_rc_t
949 ef10_vpd_next(
950 __in efx_nic_t *enp,
951 __in_bcount(size) caddr_t data,
952 __in size_t size,
953 __out efx_vpd_value_t *evvp,
954 __inout unsigned int *contp);
955
956 extern __checkReturn efx_rc_t
957 ef10_vpd_write(
958 __in efx_nic_t *enp,
959 __in_bcount(size) caddr_t data,
960 __in size_t size);
961
962 extern void
963 ef10_vpd_fini(
964 __in efx_nic_t *enp);
965
966 #endif /* EFSYS_OPT_VPD */
967
968
969 /* RX */
970
971 extern __checkReturn efx_rc_t
972 ef10_rx_init(
973 __in efx_nic_t *enp);
974
975 #if EFSYS_OPT_RX_SCATTER
976 extern __checkReturn efx_rc_t
977 ef10_rx_scatter_enable(
978 __in efx_nic_t *enp,
979 __in unsigned int buf_size);
980 #endif /* EFSYS_OPT_RX_SCATTER */
981
982
983 #if EFSYS_OPT_RX_SCALE
984
985 extern __checkReturn efx_rc_t
986 ef10_rx_scale_context_alloc(
987 __in efx_nic_t *enp,
988 __in efx_rx_scale_context_type_t type,
989 __in uint32_t num_queues,
990 __out uint32_t *rss_contextp);
991
992 extern __checkReturn efx_rc_t
993 ef10_rx_scale_context_free(
994 __in efx_nic_t *enp,
995 __in uint32_t rss_context);
996
997 extern __checkReturn efx_rc_t
998 ef10_rx_scale_mode_set(
999 __in efx_nic_t *enp,
1000 __in uint32_t rss_context,
1001 __in efx_rx_hash_alg_t alg,
1002 __in efx_rx_hash_type_t type,
1003 __in boolean_t insert);
1004
1005 extern __checkReturn efx_rc_t
1006 ef10_rx_scale_key_set(
1007 __in efx_nic_t *enp,
1008 __in uint32_t rss_context,
1009 __in_ecount(n) uint8_t *key,
1010 __in size_t n);
1011
1012 extern __checkReturn efx_rc_t
1013 ef10_rx_scale_tbl_set(
1014 __in efx_nic_t *enp,
1015 __in uint32_t rss_context,
1016 __in_ecount(n) unsigned int *table,
1017 __in size_t n);
1018
1019 extern __checkReturn uint32_t
1020 ef10_rx_prefix_hash(
1021 __in efx_nic_t *enp,
1022 __in efx_rx_hash_alg_t func,
1023 __in uint8_t *buffer);
1024
1025 #endif /* EFSYS_OPT_RX_SCALE */
1026
1027 extern __checkReturn efx_rc_t
1028 ef10_rx_prefix_pktlen(
1029 __in efx_nic_t *enp,
1030 __in uint8_t *buffer,
1031 __out uint16_t *lengthp);
1032
1033 extern void
1034 ef10_rx_qpost(
1035 __in efx_rxq_t *erp,
1036 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1037 __in size_t size,
1038 __in unsigned int ndescs,
1039 __in unsigned int completed,
1040 __in unsigned int added);
1041
1042 extern void
1043 ef10_rx_qpush(
1044 __in efx_rxq_t *erp,
1045 __in unsigned int added,
1046 __inout unsigned int *pushedp);
1047
1048 extern __checkReturn efx_rc_t
1049 ef10_rx_qflush(
1050 __in efx_rxq_t *erp);
1051
1052 extern void
1053 ef10_rx_qenable(
1054 __in efx_rxq_t *erp);
1055
1056 union efx_rxq_type_data_u;
1057
1058 extern __checkReturn efx_rc_t
1059 ef10_rx_qcreate(
1060 __in efx_nic_t *enp,
1061 __in unsigned int index,
1062 __in unsigned int label,
1063 __in efx_rxq_type_t type,
1064 __in_opt const union efx_rxq_type_data_u *type_data,
1065 __in efsys_mem_t *esmp,
1066 __in size_t ndescs,
1067 __in uint32_t id,
1068 __in unsigned int flags,
1069 __in efx_evq_t *eep,
1070 __in efx_rxq_t *erp);
1071
1072 extern void
1073 ef10_rx_qdestroy(
1074 __in efx_rxq_t *erp);
1075
1076 extern void
1077 ef10_rx_fini(
1078 __in efx_nic_t *enp);
1079
1080 #if EFSYS_OPT_FILTER
1081
1082 enum efx_filter_replacement_policy_e;
1083
1084 typedef struct ef10_filter_handle_s {
1085 uint32_t efh_lo;
1086 uint32_t efh_hi;
1087 } ef10_filter_handle_t;
1088
1089 typedef struct ef10_filter_entry_s {
1090 uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1091 ef10_filter_handle_t efe_handle;
1092 } ef10_filter_entry_t;
1093
1094 /*
1095 * BUSY flag indicates that an update is in progress.
1096 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1097 */
1098 #define EFX_EF10_FILTER_FLAG_BUSY 1U
1099 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U
1100 #define EFX_EF10_FILTER_FLAGS 3U
1101
1102 /*
1103 * Size of the hash table used by the driver. Doesn't need to be the
1104 * same size as the hardware's table.
1105 */
1106 #define EFX_EF10_FILTER_TBL_ROWS 8192
1107
1108 /* Only need to allow for one directed and one unknown unicast filter */
1109 #define EFX_EF10_FILTER_UNICAST_FILTERS_MAX 2
1110
1111 /* Allow for the broadcast address to be added to the multicast list */
1112 #define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
1113
1114 /*
1115 * For encapsulated packets, there is one filter each for each combination of
1116 * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
1117 * multicast inner frames.
1118 */
1119 #define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
1120
1121 typedef struct ef10_filter_table_s {
1122 ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1123 efx_rxq_t *eft_default_rxq;
1124 boolean_t eft_using_rss;
1125 uint32_t eft_unicst_filter_indexes[
1126 EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1127 uint32_t eft_unicst_filter_count;
1128 uint32_t eft_mulcst_filter_indexes[
1129 EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1130 uint32_t eft_mulcst_filter_count;
1131 boolean_t eft_using_all_mulcst;
1132 uint32_t eft_encap_filter_indexes[
1133 EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
1134 uint32_t eft_encap_filter_count;
1135 } ef10_filter_table_t;
1136
1137 __checkReturn efx_rc_t
1138 ef10_filter_init(
1139 __in efx_nic_t *enp);
1140
1141 void
1142 ef10_filter_fini(
1143 __in efx_nic_t *enp);
1144
1145 __checkReturn efx_rc_t
1146 ef10_filter_restore(
1147 __in efx_nic_t *enp);
1148
1149 __checkReturn efx_rc_t
1150 ef10_filter_add(
1151 __in efx_nic_t *enp,
1152 __inout efx_filter_spec_t *spec,
1153 __in enum efx_filter_replacement_policy_e policy);
1154
1155 __checkReturn efx_rc_t
1156 ef10_filter_delete(
1157 __in efx_nic_t *enp,
1158 __inout efx_filter_spec_t *spec);
1159
1160 extern __checkReturn efx_rc_t
1161 ef10_filter_supported_filters(
1162 __in efx_nic_t *enp,
1163 __out_ecount(buffer_length) uint32_t *buffer,
1164 __in size_t buffer_length,
1165 __out size_t *list_lengthp);
1166
1167 extern __checkReturn efx_rc_t
1168 ef10_filter_reconfigure(
1169 __in efx_nic_t *enp,
1170 __in_ecount(6) uint8_t const *mac_addr,
1171 __in boolean_t all_unicst,
1172 __in boolean_t mulcst,
1173 __in boolean_t all_mulcst,
1174 __in boolean_t brdcst,
1175 __in_ecount(6*count) uint8_t const *addrs,
1176 __in uint32_t count);
1177
1178 extern void
1179 ef10_filter_get_default_rxq(
1180 __in efx_nic_t *enp,
1181 __out efx_rxq_t **erpp,
1182 __out boolean_t *using_rss);
1183
1184 extern void
1185 ef10_filter_default_rxq_set(
1186 __in efx_nic_t *enp,
1187 __in efx_rxq_t *erp,
1188 __in boolean_t using_rss);
1189
1190 extern void
1191 ef10_filter_default_rxq_clear(
1192 __in efx_nic_t *enp);
1193
1194
1195 #endif /* EFSYS_OPT_FILTER */
1196
1197 extern __checkReturn efx_rc_t
1198 efx_mcdi_get_function_info(
1199 __in efx_nic_t *enp,
1200 __out uint32_t *pfp,
1201 __out_opt uint32_t *vfp);
1202
1203 extern __checkReturn efx_rc_t
1204 efx_mcdi_privilege_mask(
1205 __in efx_nic_t *enp,
1206 __in uint32_t pf,
1207 __in uint32_t vf,
1208 __out uint32_t *maskp);
1209
1210 extern __checkReturn efx_rc_t
1211 efx_mcdi_get_port_assignment(
1212 __in efx_nic_t *enp,
1213 __out uint32_t *portp);
1214
1215 extern __checkReturn efx_rc_t
1216 efx_mcdi_get_port_modes(
1217 __in efx_nic_t *enp,
1218 __out uint32_t *modesp,
1219 __out_opt uint32_t *current_modep,
1220 __out_opt uint32_t *default_modep);
1221
1222 extern __checkReturn efx_rc_t
1223 ef10_nic_get_port_mode_bandwidth(
1224 __in efx_nic_t *enp,
1225 __out uint32_t *bandwidth_mbpsp);
1226
1227 extern __checkReturn efx_rc_t
1228 efx_mcdi_get_mac_address_pf(
1229 __in efx_nic_t *enp,
1230 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1231
1232 extern __checkReturn efx_rc_t
1233 efx_mcdi_get_mac_address_vf(
1234 __in efx_nic_t *enp,
1235 __out_ecount_opt(6) uint8_t mac_addrp[6]);
1236
1237 extern __checkReturn efx_rc_t
1238 efx_mcdi_get_clock(
1239 __in efx_nic_t *enp,
1240 __out uint32_t *sys_freqp,
1241 __out uint32_t *dpcpu_freqp);
1242
1243
1244 extern __checkReturn efx_rc_t
1245 efx_mcdi_get_rxdp_config(
1246 __in efx_nic_t *enp,
1247 __out uint32_t *end_paddingp);
1248
1249 extern __checkReturn efx_rc_t
1250 efx_mcdi_get_vector_cfg(
1251 __in efx_nic_t *enp,
1252 __out_opt uint32_t *vec_basep,
1253 __out_opt uint32_t *pf_nvecp,
1254 __out_opt uint32_t *vf_nvecp);
1255
1256 extern __checkReturn efx_rc_t
1257 ef10_get_privilege_mask(
1258 __in efx_nic_t *enp,
1259 __out uint32_t *maskp);
1260
1261 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1262
1263 extern __checkReturn efx_rc_t
1264 efx_mcdi_get_nic_global(
1265 __in efx_nic_t *enp,
1266 __in uint32_t key,
1267 __out uint32_t *valuep);
1268
1269 extern __checkReturn efx_rc_t
1270 efx_mcdi_set_nic_global(
1271 __in efx_nic_t *enp,
1272 __in uint32_t key,
1273 __in uint32_t value);
1274
1275 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1276
1277 #if EFSYS_OPT_EVB
1278 extern __checkReturn efx_rc_t
1279 ef10_evb_init(
1280 __in efx_nic_t *enp);
1281
1282 extern void
1283 ef10_evb_fini(
1284 __in efx_nic_t *enp);
1285
1286 extern __checkReturn efx_rc_t
1287 ef10_evb_vswitch_alloc(
1288 __in efx_nic_t *enp,
1289 __out efx_vswitch_id_t *vswitch_idp);
1290
1291
1292 extern __checkReturn efx_rc_t
1293 ef10_evb_vswitch_free(
1294 __in efx_nic_t *enp,
1295 __in efx_vswitch_id_t vswitch_id);
1296
1297 extern __checkReturn efx_rc_t
1298 ef10_evb_vport_alloc(
1299 __in efx_nic_t *enp,
1300 __in efx_vswitch_id_t vswitch_id,
1301 __in efx_vport_type_t vport_type,
1302 __in uint16_t vid,
1303 __in boolean_t vlan_restrict,
1304 __out efx_vport_id_t *vport_idp);
1305
1306
1307 extern __checkReturn efx_rc_t
1308 ef10_evb_vport_free(
1309 __in efx_nic_t *enp,
1310 __in efx_vswitch_id_t vswitch_id,
1311 __in efx_vport_id_t vport_id);
1312
1313 extern __checkReturn efx_rc_t
1314 ef10_evb_vport_mac_addr_add(
1315 __in efx_nic_t *enp,
1316 __in efx_vswitch_id_t vswitch_id,
1317 __in efx_vport_id_t vport_id,
1318 __in_ecount(6) uint8_t *addrp);
1319
1320 extern __checkReturn efx_rc_t
1321 ef10_evb_vport_mac_addr_del(
1322 __in efx_nic_t *enp,
1323 __in efx_vswitch_id_t vswitch_id,
1324 __in efx_vport_id_t vport_id,
1325 __in_ecount(6) uint8_t *addrp);
1326
1327 extern __checkReturn efx_rc_t
1328 ef10_evb_vadaptor_alloc(
1329 __in efx_nic_t *enp,
1330 __in efx_vswitch_id_t vswitch_id,
1331 __in efx_vport_id_t vport_id);
1332
1333
1334 extern __checkReturn efx_rc_t
1335 ef10_evb_vadaptor_free(
1336 __in efx_nic_t *enp,
1337 __in efx_vswitch_id_t vswitch_id,
1338 __in efx_vport_id_t vport_id);
1339
1340 extern __checkReturn efx_rc_t
1341 ef10_evb_vport_assign(
1342 __in efx_nic_t *enp,
1343 __in efx_vswitch_id_t vswitch_id,
1344 __in efx_vport_id_t vport_id,
1345 __in uint32_t vf_index);
1346
1347 extern __checkReturn efx_rc_t
1348 ef10_evb_vport_reconfigure(
1349 __in efx_nic_t *enp,
1350 __in efx_vswitch_id_t vswitch_id,
1351 __in efx_vport_id_t vport_id,
1352 __in_opt uint16_t *vidp,
1353 __in_bcount_opt(EFX_MAC_ADDR_LEN) uint8_t *addrp,
1354 __out_opt boolean_t *fn_resetp);
1355
1356 extern __checkReturn efx_rc_t
1357 ef10_evb_vport_stats(
1358 __in efx_nic_t *enp,
1359 __in efx_vswitch_id_t vswitch_id,
1360 __in efx_vport_id_t vport_id,
1361 __out efsys_mem_t *esmp);
1362
1363 #endif /* EFSYS_OPT_EVB */
1364
1365 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
1366 extern __checkReturn efx_rc_t
1367 ef10_proxy_auth_init(
1368 __in efx_nic_t *enp);
1369
1370 extern void
1371 ef10_proxy_auth_fini(
1372 __in efx_nic_t *enp);
1373
1374 extern __checkReturn efx_rc_t
1375 ef10_proxy_auth_mc_config(
1376 __in efx_nic_t *enp,
1377 __in efsys_mem_t *request_bufferp,
1378 __in efsys_mem_t *response_bufferp,
1379 __in efsys_mem_t *status_bufferp,
1380 __in uint32_t block_cnt,
1381 __in_ecount(op_count) uint32_t *op_listp,
1382 __in size_t op_count);
1383
1384 extern __checkReturn efx_rc_t
1385 ef10_proxy_auth_disable(
1386 __in efx_nic_t *enp);
1387
1388 extern __checkReturn efx_rc_t
1389 ef10_proxy_auth_privilege_modify(
1390 __in efx_nic_t *enp,
1391 __in uint32_t fn_group,
1392 __in uint32_t pf_index,
1393 __in uint32_t vf_index,
1394 __in uint32_t add_privileges_mask,
1395 __in uint32_t remove_privileges_mask);
1396
1397 __checkReturn efx_rc_t
1398 ef10_proxy_auth_set_privilege_mask(
1399 __in efx_nic_t *enp,
1400 __in uint32_t vf_index,
1401 __in uint32_t mask,
1402 __in uint32_t value);
1403
1404 __checkReturn efx_rc_t
1405 ef10_proxy_auth_complete_request(
1406 __in efx_nic_t *enp,
1407 __in uint32_t fn_index,
1408 __in uint32_t proxy_result,
1409 __in uint32_t handle);
1410
1411 __checkReturn efx_rc_t
1412 ef10_proxy_auth_exec_cmd(
1413 __in efx_nic_t *enp,
1414 __inout efx_proxy_cmd_params_t *paramsp);
1415
1416 __checkReturn efx_rc_t
1417 ef10_proxy_auth_get_privilege_mask(
1418 __in efx_nic_t *enp,
1419 __in uint32_t pf_index,
1420 __in uint32_t vf_index,
1421 __out uint32_t *maskp);
1422
1423 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
1424
1425 #if EFSYS_OPT_RX_PACKED_STREAM
1426
1427 /* Data space per credit in packed stream mode */
1428 #define EFX_RX_PACKED_STREAM_MEM_PER_CREDIT (1 << 16)
1429
1430 /*
1431 * Received packets are always aligned at this boundary. Also there always
1432 * exists a gap of this size between packets.
1433 * (see SF-112241-TC, 4.5)
1434 */
1435 #define EFX_RX_PACKED_STREAM_ALIGNMENT 64
1436
1437 /*
1438 * Size of a pseudo-header prepended to received packets
1439 * in packed stream mode
1440 */
1441 #define EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE 8
1442
1443 /* Minimum space for packet in packed stream mode */
1444 #define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
1445 EFX_P2ROUNDUP(size_t, \
1446 EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
1447 EFX_MAC_PDU_MIN + \
1448 EFX_RX_PACKED_STREAM_ALIGNMENT, \
1449 EFX_RX_PACKED_STREAM_ALIGNMENT)
1450
1451 /* Maximum number of credits */
1452 #define EFX_RX_PACKED_STREAM_MAX_CREDITS 127
1453
1454 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1455
1456 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
1457
1458 /*
1459 * Maximum DMA length and buffer stride alignment.
1460 * (see SF-119419-TC, 3.2)
1461 */
1462 #define EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT 64
1463
1464 #endif
1465
1466 #ifdef __cplusplus
1467 }
1468 #endif
1469
1470 #endif /* _SYS_EF10_IMPL_H */
Ceph