1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2007-2018 Solarflare Communications Inc.
13 static __checkReturn efx_rc_t
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
25 __in
unsigned int buf_size
);
26 #endif /* EFSYS_OPT_RX_SCATTER */
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
32 __in
uint32_t rss_context
,
33 __in efx_rx_hash_alg_t alg
,
34 __in efx_rx_hash_type_t type
,
35 __in boolean_t insert
);
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
40 __in
uint32_t rss_context
,
41 __in_ecount(n
) uint8_t *key
,
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
47 __in
uint32_t rss_context
,
48 __in_ecount(n
) unsigned int *table
,
51 static __checkReturn
uint32_t
54 __in efx_rx_hash_alg_t func
,
55 __in
uint8_t *buffer
);
57 #endif /* EFSYS_OPT_RX_SCALE */
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
63 __out
uint16_t *lengthp
);
68 __in_ecount(ndescs
) efsys_dma_addr_t
*addrp
,
70 __in
unsigned int ndescs
,
71 __in
unsigned int completed
,
72 __in
unsigned int added
);
77 __in
unsigned int added
,
78 __inout
unsigned int *pushedp
);
80 #if EFSYS_OPT_RX_PACKED_STREAM
82 siena_rx_qpush_ps_credits(
85 static __checkReturn
uint8_t *
86 siena_rx_qps_packet_info(
89 __in
uint32_t buffer_length
,
90 __in
uint32_t current_offset
,
91 __out
uint16_t *lengthp
,
92 __out
uint32_t *next_offsetp
,
93 __out
uint32_t *timestamp
);
96 static __checkReturn efx_rc_t
102 __in efx_rxq_t
*erp
);
104 static __checkReturn efx_rc_t
107 __in
unsigned int index
,
108 __in
unsigned int label
,
109 __in efx_rxq_type_t type
,
110 __in_opt
const efx_rxq_type_data_t
*type_data
,
111 __in efsys_mem_t
*esmp
,
114 __in
unsigned int flags
,
116 __in efx_rxq_t
*erp
);
120 __in efx_rxq_t
*erp
);
122 #endif /* EFSYS_OPT_SIENA */
126 static const efx_rx_ops_t __efx_rx_siena_ops
= {
127 siena_rx_init
, /* erxo_init */
128 siena_rx_fini
, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable
, /* erxo_scatter_enable */
132 #if EFSYS_OPT_RX_SCALE
133 NULL
, /* erxo_scale_context_alloc */
134 NULL
, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set
, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set
, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set
, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash
, /* erxo_prefix_hash */
140 siena_rx_prefix_pktlen
, /* erxo_prefix_pktlen */
141 siena_rx_qpost
, /* erxo_qpost */
142 siena_rx_qpush
, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits
, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info
, /* erxo_qps_packet_info */
147 siena_rx_qflush
, /* erxo_qflush */
148 siena_rx_qenable
, /* erxo_qenable */
149 siena_rx_qcreate
, /* erxo_qcreate */
150 siena_rx_qdestroy
, /* erxo_qdestroy */
152 #endif /* EFSYS_OPT_SIENA */
155 static const efx_rx_ops_t __efx_rx_ef10_ops
= {
156 ef10_rx_init
, /* erxo_init */
157 ef10_rx_fini
, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable
, /* erxo_scatter_enable */
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc
, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free
, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set
, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set
, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set
, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash
, /* erxo_prefix_hash */
169 ef10_rx_prefix_pktlen
, /* erxo_prefix_pktlen */
170 ef10_rx_qpost
, /* erxo_qpost */
171 ef10_rx_qpush
, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits
, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info
, /* erxo_qps_packet_info */
176 ef10_rx_qflush
, /* erxo_qflush */
177 ef10_rx_qenable
, /* erxo_qenable */
178 ef10_rx_qcreate
, /* erxo_qcreate */
179 ef10_rx_qdestroy
, /* erxo_qdestroy */
181 #endif /* EFX_OPTS_EF10() */
184 __checkReturn efx_rc_t
186 __inout efx_nic_t
*enp
)
188 const efx_rx_ops_t
*erxop
;
191 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
192 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_NIC
);
194 if (!(enp
->en_mod_flags
& EFX_MOD_EV
)) {
199 if (enp
->en_mod_flags
& EFX_MOD_RX
) {
204 switch (enp
->en_family
) {
206 case EFX_FAMILY_SIENA
:
207 erxop
= &__efx_rx_siena_ops
;
209 #endif /* EFSYS_OPT_SIENA */
211 #if EFSYS_OPT_HUNTINGTON
212 case EFX_FAMILY_HUNTINGTON
:
213 erxop
= &__efx_rx_ef10_ops
;
215 #endif /* EFSYS_OPT_HUNTINGTON */
217 #if EFSYS_OPT_MEDFORD
218 case EFX_FAMILY_MEDFORD
:
219 erxop
= &__efx_rx_ef10_ops
;
221 #endif /* EFSYS_OPT_MEDFORD */
223 #if EFSYS_OPT_MEDFORD2
224 case EFX_FAMILY_MEDFORD2
:
225 erxop
= &__efx_rx_ef10_ops
;
227 #endif /* EFSYS_OPT_MEDFORD2 */
235 if ((rc
= erxop
->erxo_init(enp
)) != 0)
238 enp
->en_erxop
= erxop
;
239 enp
->en_mod_flags
|= EFX_MOD_RX
;
249 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
251 enp
->en_erxop
= NULL
;
252 enp
->en_mod_flags
&= ~EFX_MOD_RX
;
260 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
262 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
263 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_NIC
);
264 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
265 EFSYS_ASSERT3U(enp
->en_rx_qcount
, ==, 0);
267 erxop
->erxo_fini(enp
);
269 enp
->en_erxop
= NULL
;
270 enp
->en_mod_flags
&= ~EFX_MOD_RX
;
273 #if EFSYS_OPT_RX_SCATTER
274 __checkReturn efx_rc_t
275 efx_rx_scatter_enable(
277 __in
unsigned int buf_size
)
279 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
282 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
283 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
285 if ((rc
= erxop
->erxo_scatter_enable(enp
, buf_size
)) != 0)
291 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
294 #endif /* EFSYS_OPT_RX_SCATTER */
296 #if EFSYS_OPT_RX_SCALE
297 __checkReturn efx_rc_t
298 efx_rx_scale_hash_flags_get(
300 __in efx_rx_hash_alg_t hash_alg
,
301 __out_ecount_part(max_nflags
, *nflagsp
) unsigned int *flagsp
,
302 __in
unsigned int max_nflags
,
303 __out
unsigned int *nflagsp
)
305 efx_nic_cfg_t
*encp
= &enp
->en_nic_cfg
;
306 unsigned int nflags
= 0;
309 if (flagsp
== NULL
|| nflagsp
== NULL
) {
314 if ((encp
->enc_rx_scale_hash_alg_mask
& (1U << hash_alg
)) == 0) {
319 /* Helper to add flags word to flags array without buffer overflow */
320 #define INSERT_FLAGS(_flags) \
322 if (nflags >= max_nflags) { \
326 *(flagsp + nflags) = (_flags); \
329 _NOTE(CONSTANTCONDITION) \
332 if (encp
->enc_rx_scale_l4_hash_supported
!= B_FALSE
) {
333 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP
, 4TUPLE
));
334 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP
, 4TUPLE
));
337 if ((encp
->enc_rx_scale_l4_hash_supported
!= B_FALSE
) &&
338 (encp
->enc_rx_scale_additional_modes_supported
!= B_FALSE
)) {
339 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP
, 2TUPLE_DST
));
340 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP
, 2TUPLE_SRC
));
342 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP
, 2TUPLE_DST
));
343 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP
, 2TUPLE_SRC
));
345 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP
, 4TUPLE
));
346 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP
, 2TUPLE_DST
));
347 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP
, 2TUPLE_SRC
));
349 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP
, 4TUPLE
));
350 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP
, 2TUPLE_DST
));
351 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP
, 2TUPLE_SRC
));
354 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP
, 2TUPLE
));
355 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP
, 2TUPLE
));
357 INSERT_FLAGS(EFX_RX_HASH(IPV4
, 2TUPLE
));
358 INSERT_FLAGS(EFX_RX_HASH(IPV6
, 2TUPLE
));
360 if (encp
->enc_rx_scale_additional_modes_supported
!= B_FALSE
) {
361 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP
, 1TUPLE_DST
));
362 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP
, 1TUPLE_SRC
));
364 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP
, 1TUPLE_DST
));
365 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP
, 1TUPLE_SRC
));
367 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP
, 2TUPLE
));
368 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP
, 1TUPLE_DST
));
369 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP
, 1TUPLE_SRC
));
371 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP
, 2TUPLE
));
372 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP
, 1TUPLE_DST
));
373 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP
, 1TUPLE_SRC
));
375 INSERT_FLAGS(EFX_RX_HASH(IPV4
, 1TUPLE_DST
));
376 INSERT_FLAGS(EFX_RX_HASH(IPV4
, 1TUPLE_SRC
));
378 INSERT_FLAGS(EFX_RX_HASH(IPV6
, 1TUPLE_DST
));
379 INSERT_FLAGS(EFX_RX_HASH(IPV6
, 1TUPLE_SRC
));
382 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP
, DISABLE
));
383 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP
, DISABLE
));
385 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP
, DISABLE
));
386 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP
, DISABLE
));
388 INSERT_FLAGS(EFX_RX_HASH(IPV4
, DISABLE
));
389 INSERT_FLAGS(EFX_RX_HASH(IPV6
, DISABLE
));
400 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
405 __checkReturn efx_rc_t
406 efx_rx_hash_default_support_get(
408 __out efx_rx_hash_support_t
*supportp
)
412 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
413 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
415 if (supportp
== NULL
) {
421 * Report the hashing support the client gets by default if it
422 * does not allocate an RSS context itself.
424 *supportp
= enp
->en_hash_support
;
429 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
434 __checkReturn efx_rc_t
435 efx_rx_scale_default_support_get(
437 __out efx_rx_scale_context_type_t
*typep
)
441 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
442 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
450 * Report the RSS support the client gets by default if it
451 * does not allocate an RSS context itself.
453 *typep
= enp
->en_rss_context_type
;
458 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
462 #endif /* EFSYS_OPT_RX_SCALE */
464 #if EFSYS_OPT_RX_SCALE
465 __checkReturn efx_rc_t
466 efx_rx_scale_context_alloc(
468 __in efx_rx_scale_context_type_t type
,
469 __in
uint32_t num_queues
,
470 __out
uint32_t *rss_contextp
)
472 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
475 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
476 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
478 if (erxop
->erxo_scale_context_alloc
== NULL
) {
482 if ((rc
= erxop
->erxo_scale_context_alloc(enp
, type
,
483 num_queues
, rss_contextp
)) != 0) {
492 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
495 #endif /* EFSYS_OPT_RX_SCALE */
497 #if EFSYS_OPT_RX_SCALE
498 __checkReturn efx_rc_t
499 efx_rx_scale_context_free(
501 __in
uint32_t rss_context
)
503 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
506 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
507 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
509 if (erxop
->erxo_scale_context_free
== NULL
) {
513 if ((rc
= erxop
->erxo_scale_context_free(enp
, rss_context
)) != 0)
521 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
524 #endif /* EFSYS_OPT_RX_SCALE */
526 #if EFSYS_OPT_RX_SCALE
527 __checkReturn efx_rc_t
528 efx_rx_scale_mode_set(
530 __in
uint32_t rss_context
,
531 __in efx_rx_hash_alg_t alg
,
532 __in efx_rx_hash_type_t type
,
533 __in boolean_t insert
)
535 efx_nic_cfg_t
*encp
= &enp
->en_nic_cfg
;
536 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
537 efx_rx_hash_type_t type_check
;
541 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
542 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
545 * Legacy flags and modern bits cannot be
546 * used at the same time in the hash type.
548 if ((type
& EFX_RX_HASH_LEGACY_MASK
) &&
549 (type
& ~EFX_RX_HASH_LEGACY_MASK
)) {
555 * If RSS hash type is represented by additional bits
556 * in the value, the latter need to be verified since
557 * not all bit combinations are valid RSS modes. Also,
558 * depending on the firmware, some valid combinations
559 * may be unsupported. Discern additional bits in the
560 * type value and try to recognise valid combinations.
561 * If some bits remain unrecognised, report the error.
563 type_check
= type
& ~EFX_RX_HASH_LEGACY_MASK
;
564 if (type_check
!= 0) {
565 unsigned int type_flags
[EFX_RX_HASH_NFLAGS
];
566 unsigned int type_nflags
;
568 rc
= efx_rx_scale_hash_flags_get(enp
, alg
, type_flags
,
569 EFX_ARRAY_SIZE(type_flags
), &type_nflags
);
573 for (i
= 0; i
< type_nflags
; ++i
) {
574 if ((type_check
& type_flags
[i
]) == type_flags
[i
])
575 type_check
&= ~(type_flags
[i
]);
578 if (type_check
!= 0) {
585 * Translate EFX_RX_HASH() flags to their legacy counterparts
586 * provided that the FW claims no support for additional modes.
588 if (encp
->enc_rx_scale_additional_modes_supported
== B_FALSE
) {
589 efx_rx_hash_type_t t_ipv4
= EFX_RX_HASH(IPV4
, 2TUPLE
) |
590 EFX_RX_HASH(IPV4_TCP
, 2TUPLE
);
591 efx_rx_hash_type_t t_ipv6
= EFX_RX_HASH(IPV6
, 2TUPLE
) |
592 EFX_RX_HASH(IPV6_TCP
, 2TUPLE
);
593 efx_rx_hash_type_t t_ipv4_tcp
= EFX_RX_HASH(IPV4_TCP
, 4TUPLE
);
594 efx_rx_hash_type_t t_ipv6_tcp
= EFX_RX_HASH(IPV6_TCP
, 4TUPLE
);
596 if ((type
& t_ipv4
) == t_ipv4
)
597 type
|= EFX_RX_HASH_IPV4
;
598 if ((type
& t_ipv6
) == t_ipv6
)
599 type
|= EFX_RX_HASH_IPV6
;
601 if (encp
->enc_rx_scale_l4_hash_supported
== B_TRUE
) {
602 if ((type
& t_ipv4_tcp
) == t_ipv4_tcp
)
603 type
|= EFX_RX_HASH_TCPIPV4
;
604 if ((type
& t_ipv6_tcp
) == t_ipv6_tcp
)
605 type
|= EFX_RX_HASH_TCPIPV6
;
608 type
&= EFX_RX_HASH_LEGACY_MASK
;
611 if (erxop
->erxo_scale_mode_set
!= NULL
) {
612 if ((rc
= erxop
->erxo_scale_mode_set(enp
, rss_context
, alg
,
626 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
629 #endif /* EFSYS_OPT_RX_SCALE */
631 #if EFSYS_OPT_RX_SCALE
632 __checkReturn efx_rc_t
633 efx_rx_scale_key_set(
635 __in
uint32_t rss_context
,
636 __in_ecount(n
) uint8_t *key
,
639 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
642 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
643 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
645 if ((rc
= erxop
->erxo_scale_key_set(enp
, rss_context
, key
, n
)) != 0)
651 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
655 #endif /* EFSYS_OPT_RX_SCALE */
657 #if EFSYS_OPT_RX_SCALE
658 __checkReturn efx_rc_t
659 efx_rx_scale_tbl_set(
661 __in
uint32_t rss_context
,
662 __in_ecount(n
) unsigned int *table
,
665 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
668 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
669 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
671 if ((rc
= erxop
->erxo_scale_tbl_set(enp
, rss_context
, table
, n
)) != 0)
677 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
681 #endif /* EFSYS_OPT_RX_SCALE */
686 __in_ecount(ndescs
) efsys_dma_addr_t
*addrp
,
688 __in
unsigned int ndescs
,
689 __in
unsigned int completed
,
690 __in
unsigned int added
)
692 efx_nic_t
*enp
= erp
->er_enp
;
693 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
695 EFSYS_ASSERT3U(erp
->er_magic
, ==, EFX_RXQ_MAGIC
);
696 EFSYS_ASSERT(erp
->er_buf_size
== 0 || size
== erp
->er_buf_size
);
698 erxop
->erxo_qpost(erp
, addrp
, size
, ndescs
, completed
, added
);
701 #if EFSYS_OPT_RX_PACKED_STREAM
704 efx_rx_qpush_ps_credits(
707 efx_nic_t
*enp
= erp
->er_enp
;
708 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
710 EFSYS_ASSERT3U(erp
->er_magic
, ==, EFX_RXQ_MAGIC
);
712 erxop
->erxo_qpush_ps_credits(erp
);
715 __checkReturn
uint8_t *
716 efx_rx_qps_packet_info(
718 __in
uint8_t *buffer
,
719 __in
uint32_t buffer_length
,
720 __in
uint32_t current_offset
,
721 __out
uint16_t *lengthp
,
722 __out
uint32_t *next_offsetp
,
723 __out
uint32_t *timestamp
)
725 efx_nic_t
*enp
= erp
->er_enp
;
726 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
728 return (erxop
->erxo_qps_packet_info(erp
, buffer
,
729 buffer_length
, current_offset
, lengthp
,
730 next_offsetp
, timestamp
));
733 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
738 __in
unsigned int added
,
739 __inout
unsigned int *pushedp
)
741 efx_nic_t
*enp
= erp
->er_enp
;
742 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
744 EFSYS_ASSERT3U(erp
->er_magic
, ==, EFX_RXQ_MAGIC
);
746 erxop
->erxo_qpush(erp
, added
, pushedp
);
749 __checkReturn efx_rc_t
753 efx_nic_t
*enp
= erp
->er_enp
;
754 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
757 EFSYS_ASSERT3U(erp
->er_magic
, ==, EFX_RXQ_MAGIC
);
759 if ((rc
= erxop
->erxo_qflush(erp
)) != 0)
765 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
772 __in
const efx_nic_t
*enp
,
773 __in
unsigned int ndescs
)
775 const efx_nic_cfg_t
*encp
= efx_nic_cfg_get(enp
);
777 return (ndescs
* encp
->enc_rx_desc_size
);
780 __checkReturn
unsigned int
782 __in
const efx_nic_t
*enp
,
783 __in
unsigned int ndescs
)
785 return (EFX_DIV_ROUND_UP(efx_rxq_size(enp
, ndescs
), EFX_BUF_SIZE
));
792 efx_nic_t
*enp
= erp
->er_enp
;
793 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
795 EFSYS_ASSERT3U(erp
->er_magic
, ==, EFX_RXQ_MAGIC
);
797 erxop
->erxo_qenable(erp
);
800 static __checkReturn efx_rc_t
801 efx_rx_qcreate_internal(
803 __in
unsigned int index
,
804 __in
unsigned int label
,
805 __in efx_rxq_type_t type
,
806 __in_opt
const efx_rxq_type_data_t
*type_data
,
807 __in efsys_mem_t
*esmp
,
810 __in
unsigned int flags
,
812 __deref_out efx_rxq_t
**erpp
)
814 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
816 const efx_nic_cfg_t
*encp
= efx_nic_cfg_get(enp
);
819 EFSYS_ASSERT3U(enp
->en_magic
, ==, EFX_NIC_MAGIC
);
820 EFSYS_ASSERT3U(enp
->en_mod_flags
, &, EFX_MOD_RX
);
822 EFSYS_ASSERT(ISP2(encp
->enc_rxq_max_ndescs
));
823 EFSYS_ASSERT(ISP2(encp
->enc_rxq_min_ndescs
));
826 ndescs
< encp
->enc_rxq_min_ndescs
||
827 ndescs
> encp
->enc_rxq_max_ndescs
) {
832 /* Allocate an RXQ object */
833 EFSYS_KMEM_ALLOC(enp
->en_esip
, sizeof (efx_rxq_t
), erp
);
840 erp
->er_magic
= EFX_RXQ_MAGIC
;
842 erp
->er_index
= index
;
843 erp
->er_mask
= ndescs
- 1;
846 if ((rc
= erxop
->erxo_qcreate(enp
, index
, label
, type
, type_data
, esmp
,
847 ndescs
, id
, flags
, eep
, erp
)) != 0)
858 EFSYS_KMEM_FREE(enp
->en_esip
, sizeof (efx_rxq_t
), erp
);
862 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
867 __checkReturn efx_rc_t
870 __in
unsigned int index
,
871 __in
unsigned int label
,
872 __in efx_rxq_type_t type
,
873 __in
size_t buf_size
,
874 __in efsys_mem_t
*esmp
,
877 __in
unsigned int flags
,
879 __deref_out efx_rxq_t
**erpp
)
881 efx_rxq_type_data_t type_data
;
883 memset(&type_data
, 0, sizeof (type_data
));
885 type_data
.ertd_default
.ed_buf_size
= buf_size
;
887 return efx_rx_qcreate_internal(enp
, index
, label
, type
, &type_data
,
888 esmp
, ndescs
, id
, flags
, eep
, erpp
);
891 #if EFSYS_OPT_RX_PACKED_STREAM
893 __checkReturn efx_rc_t
894 efx_rx_qcreate_packed_stream(
896 __in
unsigned int index
,
897 __in
unsigned int label
,
898 __in
uint32_t ps_buf_size
,
899 __in efsys_mem_t
*esmp
,
902 __deref_out efx_rxq_t
**erpp
)
904 efx_rxq_type_data_t type_data
;
906 memset(&type_data
, 0, sizeof (type_data
));
908 type_data
.ertd_packed_stream
.eps_buf_size
= ps_buf_size
;
910 return efx_rx_qcreate_internal(enp
, index
, label
,
911 EFX_RXQ_TYPE_PACKED_STREAM
, &type_data
, esmp
, ndescs
,
912 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE
, eep
, erpp
);
917 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
919 __checkReturn efx_rc_t
920 efx_rx_qcreate_es_super_buffer(
922 __in
unsigned int index
,
923 __in
unsigned int label
,
924 __in
uint32_t n_bufs_per_desc
,
925 __in
uint32_t max_dma_len
,
926 __in
uint32_t buf_stride
,
927 __in
uint32_t hol_block_timeout
,
928 __in efsys_mem_t
*esmp
,
930 __in
unsigned int flags
,
932 __deref_out efx_rxq_t
**erpp
)
935 efx_rxq_type_data_t type_data
;
937 if (hol_block_timeout
> EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX
) {
942 memset(&type_data
, 0, sizeof (type_data
));
944 type_data
.ertd_es_super_buffer
.eessb_bufs_per_desc
= n_bufs_per_desc
;
945 type_data
.ertd_es_super_buffer
.eessb_max_dma_len
= max_dma_len
;
946 type_data
.ertd_es_super_buffer
.eessb_buf_stride
= buf_stride
;
947 type_data
.ertd_es_super_buffer
.eessb_hol_block_timeout
=
950 rc
= efx_rx_qcreate_internal(enp
, index
, label
,
951 EFX_RXQ_TYPE_ES_SUPER_BUFFER
, &type_data
, esmp
, ndescs
,
952 0 /* id unused on EF10 */, flags
, eep
, erpp
);
961 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
973 efx_nic_t
*enp
= erp
->er_enp
;
974 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
976 EFSYS_ASSERT3U(erp
->er_magic
, ==, EFX_RXQ_MAGIC
);
978 erxop
->erxo_qdestroy(erp
);
981 __checkReturn efx_rc_t
982 efx_pseudo_hdr_pkt_length_get(
984 __in
uint8_t *buffer
,
985 __out
uint16_t *lengthp
)
987 efx_nic_t
*enp
= erp
->er_enp
;
988 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
990 EFSYS_ASSERT3U(erp
->er_magic
, ==, EFX_RXQ_MAGIC
);
992 return (erxop
->erxo_prefix_pktlen(enp
, buffer
, lengthp
));
995 #if EFSYS_OPT_RX_SCALE
996 __checkReturn
uint32_t
997 efx_pseudo_hdr_hash_get(
999 __in efx_rx_hash_alg_t func
,
1000 __in
uint8_t *buffer
)
1002 efx_nic_t
*enp
= erp
->er_enp
;
1003 const efx_rx_ops_t
*erxop
= enp
->en_erxop
;
1005 EFSYS_ASSERT3U(erp
->er_magic
, ==, EFX_RXQ_MAGIC
);
1007 EFSYS_ASSERT3U(enp
->en_hash_support
, ==, EFX_RX_HASH_AVAILABLE
);
1008 return (erxop
->erxo_prefix_hash(enp
, func
, buffer
));
1010 #endif /* EFSYS_OPT_RX_SCALE */
1014 static __checkReturn efx_rc_t
1016 __in efx_nic_t
*enp
)
1021 EFX_BAR_READO(enp
, FR_AZ_RX_CFG_REG
, &oword
);
1023 EFX_SET_OWORD_FIELD(oword
, FRF_BZ_RX_DESC_PUSH_EN
, 0);
1024 EFX_SET_OWORD_FIELD(oword
, FRF_BZ_RX_HASH_ALG
, 0);
1025 EFX_SET_OWORD_FIELD(oword
, FRF_BZ_RX_IP_HASH
, 0);
1026 EFX_SET_OWORD_FIELD(oword
, FRF_BZ_RX_TCP_SUP
, 0);
1027 EFX_SET_OWORD_FIELD(oword
, FRF_BZ_RX_HASH_INSRT_HDR
, 0);
1028 EFX_SET_OWORD_FIELD(oword
, FRF_BZ_RX_USR_BUF_SIZE
, 0x3000 / 32);
1029 EFX_BAR_WRITEO(enp
, FR_AZ_RX_CFG_REG
, &oword
);
1031 /* Zero the RSS table */
1032 for (index
= 0; index
< FR_BZ_RX_INDIRECTION_TBL_ROWS
;
1034 EFX_ZERO_OWORD(oword
);
1035 EFX_BAR_TBL_WRITEO(enp
, FR_BZ_RX_INDIRECTION_TBL
,
1036 index
, &oword
, B_TRUE
);
1039 #if EFSYS_OPT_RX_SCALE
1040 /* The RSS key and indirection table are writable. */
1041 enp
->en_rss_context_type
= EFX_RX_SCALE_EXCLUSIVE
;
1043 /* Hardware can insert RX hash with/without RSS */
1044 enp
->en_hash_support
= EFX_RX_HASH_AVAILABLE
;
1045 #endif /* EFSYS_OPT_RX_SCALE */
1050 #if EFSYS_OPT_RX_SCATTER
1051 static __checkReturn efx_rc_t
1052 siena_rx_scatter_enable(
1053 __in efx_nic_t
*enp
,
1054 __in
unsigned int buf_size
)
1056 unsigned int nbuf32
;
1060 nbuf32
= buf_size
/ 32;
1061 if ((nbuf32
== 0) ||
1062 (nbuf32
>= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH
)) ||
1063 ((buf_size
% 32) != 0)) {
1068 if (enp
->en_rx_qcount
> 0) {
1073 /* Set scatter buffer size */
1074 EFX_BAR_READO(enp
, FR_AZ_RX_CFG_REG
, &oword
);
1075 EFX_SET_OWORD_FIELD(oword
, FRF_BZ_RX_USR_BUF_SIZE
, nbuf32
);
1076 EFX_BAR_WRITEO(enp
, FR_AZ_RX_CFG_REG
, &oword
);
1078 /* Enable scatter for packets not matching a filter */
1079 EFX_BAR_READO(enp
, FR_AZ_RX_FILTER_CTL_REG
, &oword
);
1080 EFX_SET_OWORD_FIELD(oword
, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q
, 1);
1081 EFX_BAR_WRITEO(enp
, FR_AZ_RX_FILTER_CTL_REG
, &oword
);
1088 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
1092 #endif /* EFSYS_OPT_RX_SCATTER */
1095 #define EFX_RX_LFSR_HASH(_enp, _insert) \
1097 efx_oword_t oword; \
1099 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1100 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
1101 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
1102 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
1103 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1104 (_insert) ? 1 : 0); \
1105 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1107 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
1108 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1110 EFX_SET_OWORD_FIELD(oword, \
1111 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
1112 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1116 _NOTE(CONSTANTCONDITION) \
1119 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
1121 efx_oword_t oword; \
1123 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1124 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
1125 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
1127 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
1129 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1130 (_insert) ? 1 : 0); \
1131 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1133 _NOTE(CONSTANTCONDITION) \
1136 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
1138 efx_oword_t oword; \
1140 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1141 EFX_SET_OWORD_FIELD(oword, \
1142 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
1143 EFX_SET_OWORD_FIELD(oword, \
1144 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1145 EFX_SET_OWORD_FIELD(oword, \
1146 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
1147 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1151 _NOTE(CONSTANTCONDITION) \
1155 #if EFSYS_OPT_RX_SCALE
1157 static __checkReturn efx_rc_t
1158 siena_rx_scale_mode_set(
1159 __in efx_nic_t
*enp
,
1160 __in
uint32_t rss_context
,
1161 __in efx_rx_hash_alg_t alg
,
1162 __in efx_rx_hash_type_t type
,
1163 __in boolean_t insert
)
1167 if (rss_context
!= EFX_RSS_CONTEXT_DEFAULT
) {
1173 case EFX_RX_HASHALG_LFSR
:
1174 EFX_RX_LFSR_HASH(enp
, insert
);
1177 case EFX_RX_HASHALG_TOEPLITZ
:
1178 EFX_RX_TOEPLITZ_IPV4_HASH(enp
, insert
,
1179 (type
& EFX_RX_HASH_IPV4
) ? B_TRUE
: B_FALSE
,
1180 (type
& EFX_RX_HASH_TCPIPV4
) ? B_TRUE
: B_FALSE
);
1182 EFX_RX_TOEPLITZ_IPV6_HASH(enp
,
1183 (type
& EFX_RX_HASH_IPV6
) ? B_TRUE
: B_FALSE
,
1184 (type
& EFX_RX_HASH_TCPIPV6
) ? B_TRUE
: B_FALSE
,
1203 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
1205 EFX_RX_LFSR_HASH(enp
, B_FALSE
);
1211 #if EFSYS_OPT_RX_SCALE
1212 static __checkReturn efx_rc_t
1213 siena_rx_scale_key_set(
1214 __in efx_nic_t
*enp
,
1215 __in
uint32_t rss_context
,
1216 __in_ecount(n
) uint8_t *key
,
1221 unsigned int offset
;
1224 if (rss_context
!= EFX_RSS_CONTEXT_DEFAULT
) {
1231 /* Write Toeplitz IPv4 hash key */
1232 EFX_ZERO_OWORD(oword
);
1233 for (offset
= (FRF_BZ_RX_RSS_TKEY_LBN
+ FRF_BZ_RX_RSS_TKEY_WIDTH
) / 8;
1234 offset
> 0 && byte
< n
;
1236 oword
.eo_u8
[offset
- 1] = key
[byte
++];
1238 EFX_BAR_WRITEO(enp
, FR_BZ_RX_RSS_TKEY_REG
, &oword
);
1242 /* Verify Toeplitz IPv4 hash key */
1243 EFX_BAR_READO(enp
, FR_BZ_RX_RSS_TKEY_REG
, &oword
);
1244 for (offset
= (FRF_BZ_RX_RSS_TKEY_LBN
+ FRF_BZ_RX_RSS_TKEY_WIDTH
) / 8;
1245 offset
> 0 && byte
< n
;
1247 if (oword
.eo_u8
[offset
- 1] != key
[byte
++]) {
1253 if ((enp
->en_features
& EFX_FEATURE_IPV6
) == 0)
1258 /* Write Toeplitz IPv6 hash key 3 */
1259 EFX_BAR_READO(enp
, FR_CZ_RX_RSS_IPV6_REG3
, &oword
);
1260 for (offset
= (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN
+
1261 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH
) / 8;
1262 offset
> 0 && byte
< n
;
1264 oword
.eo_u8
[offset
- 1] = key
[byte
++];
1266 EFX_BAR_WRITEO(enp
, FR_CZ_RX_RSS_IPV6_REG3
, &oword
);
1268 /* Write Toeplitz IPv6 hash key 2 */
1269 EFX_ZERO_OWORD(oword
);
1270 for (offset
= (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN
+
1271 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH
) / 8;
1272 offset
> 0 && byte
< n
;
1274 oword
.eo_u8
[offset
- 1] = key
[byte
++];
1276 EFX_BAR_WRITEO(enp
, FR_CZ_RX_RSS_IPV6_REG2
, &oword
);
1278 /* Write Toeplitz IPv6 hash key 1 */
1279 EFX_ZERO_OWORD(oword
);
1280 for (offset
= (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN
+
1281 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH
) / 8;
1282 offset
> 0 && byte
< n
;
1284 oword
.eo_u8
[offset
- 1] = key
[byte
++];
1286 EFX_BAR_WRITEO(enp
, FR_CZ_RX_RSS_IPV6_REG1
, &oword
);
1290 /* Verify Toeplitz IPv6 hash key 3 */
1291 EFX_BAR_READO(enp
, FR_CZ_RX_RSS_IPV6_REG3
, &oword
);
1292 for (offset
= (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN
+
1293 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH
) / 8;
1294 offset
> 0 && byte
< n
;
1296 if (oword
.eo_u8
[offset
- 1] != key
[byte
++]) {
1302 /* Verify Toeplitz IPv6 hash key 2 */
1303 EFX_BAR_READO(enp
, FR_CZ_RX_RSS_IPV6_REG2
, &oword
);
1304 for (offset
= (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN
+
1305 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH
) / 8;
1306 offset
> 0 && byte
< n
;
1308 if (oword
.eo_u8
[offset
- 1] != key
[byte
++]) {
1314 /* Verify Toeplitz IPv6 hash key 1 */
1315 EFX_BAR_READO(enp
, FR_CZ_RX_RSS_IPV6_REG1
, &oword
);
1316 for (offset
= (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN
+
1317 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH
) / 8;
1318 offset
> 0 && byte
< n
;
1320 if (oword
.eo_u8
[offset
- 1] != key
[byte
++]) {
1338 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
1344 #if EFSYS_OPT_RX_SCALE
1345 static __checkReturn efx_rc_t
1346 siena_rx_scale_tbl_set(
1347 __in efx_nic_t
*enp
,
1348 __in
uint32_t rss_context
,
1349 __in_ecount(n
) unsigned int *table
,
1356 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE
== FR_BZ_RX_INDIRECTION_TBL_ROWS
);
1357 EFX_STATIC_ASSERT(EFX_MAXRSS
== (1 << FRF_BZ_IT_QUEUE_WIDTH
));
1359 if (rss_context
!= EFX_RSS_CONTEXT_DEFAULT
) {
1364 if (n
> FR_BZ_RX_INDIRECTION_TBL_ROWS
) {
1369 for (index
= 0; index
< FR_BZ_RX_INDIRECTION_TBL_ROWS
; index
++) {
1372 /* Calculate the entry to place in the table */
1373 byte
= (n
> 0) ? (uint32_t)table
[index
% n
] : 0;
1375 EFSYS_PROBE2(table
, int, index
, uint32_t, byte
);
1377 EFX_POPULATE_OWORD_1(oword
, FRF_BZ_IT_QUEUE
, byte
);
1379 /* Write the table */
1380 EFX_BAR_TBL_WRITEO(enp
, FR_BZ_RX_INDIRECTION_TBL
,
1381 index
, &oword
, B_TRUE
);
1384 for (index
= FR_BZ_RX_INDIRECTION_TBL_ROWS
- 1; index
>= 0; --index
) {
1387 /* Determine if we're starting a new batch */
1388 byte
= (n
> 0) ? (uint32_t)table
[index
% n
] : 0;
1390 /* Read the table */
1391 EFX_BAR_TBL_READO(enp
, FR_BZ_RX_INDIRECTION_TBL
,
1392 index
, &oword
, B_TRUE
);
1394 /* Verify the entry */
1395 if (EFX_OWORD_FIELD(oword
, FRF_BZ_IT_QUEUE
) != byte
) {
1408 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
1415 * Falcon/Siena pseudo-header
1416 * --------------------------
1418 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1419 * The pseudo-header is a byte array of one of the forms:
1421 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1422 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1423 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1426 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1427 * LL.LL LFSR hash (16-bit big-endian)
1430 #if EFSYS_OPT_RX_SCALE
1431 static __checkReturn
uint32_t
1432 siena_rx_prefix_hash(
1433 __in efx_nic_t
*enp
,
1434 __in efx_rx_hash_alg_t func
,
1435 __in
uint8_t *buffer
)
1437 _NOTE(ARGUNUSED(enp
))
1440 case EFX_RX_HASHALG_TOEPLITZ
:
1441 return ((buffer
[12] << 24) |
1442 (buffer
[13] << 16) |
1446 case EFX_RX_HASHALG_LFSR
:
1447 return ((buffer
[14] << 8) | buffer
[15]);
1454 #endif /* EFSYS_OPT_RX_SCALE */
1456 static __checkReturn efx_rc_t
1457 siena_rx_prefix_pktlen(
1458 __in efx_nic_t
*enp
,
1459 __in
uint8_t *buffer
,
1460 __out
uint16_t *lengthp
)
1462 _NOTE(ARGUNUSED(enp
, buffer
, lengthp
))
1464 /* Not supported by Falcon/Siena hardware */
1472 __in efx_rxq_t
*erp
,
1473 __in_ecount(ndescs
) efsys_dma_addr_t
*addrp
,
1475 __in
unsigned int ndescs
,
1476 __in
unsigned int completed
,
1477 __in
unsigned int added
)
1481 unsigned int offset
;
1484 /* The client driver must not overfill the queue */
1485 EFSYS_ASSERT3U(added
- completed
+ ndescs
, <=,
1486 EFX_RXQ_LIMIT(erp
->er_mask
+ 1));
1488 id
= added
& (erp
->er_mask
);
1489 for (i
= 0; i
< ndescs
; i
++) {
1490 EFSYS_PROBE4(rx_post
, unsigned int, erp
->er_index
,
1491 unsigned int, id
, efsys_dma_addr_t
, addrp
[i
],
1494 EFX_POPULATE_QWORD_3(qword
,
1495 FSF_AZ_RX_KER_BUF_SIZE
, (uint32_t)(size
),
1496 FSF_AZ_RX_KER_BUF_ADDR_DW0
,
1497 (uint32_t)(addrp
[i
] & 0xffffffff),
1498 FSF_AZ_RX_KER_BUF_ADDR_DW1
,
1499 (uint32_t)(addrp
[i
] >> 32));
1501 offset
= id
* sizeof (efx_qword_t
);
1502 EFSYS_MEM_WRITEQ(erp
->er_esmp
, offset
, &qword
);
1504 id
= (id
+ 1) & (erp
->er_mask
);
1510 __in efx_rxq_t
*erp
,
1511 __in
unsigned int added
,
1512 __inout
unsigned int *pushedp
)
1514 efx_nic_t
*enp
= erp
->er_enp
;
1515 unsigned int pushed
= *pushedp
;
1520 /* All descriptors are pushed */
1523 /* Push the populated descriptors out */
1524 wptr
= added
& erp
->er_mask
;
1526 EFX_POPULATE_OWORD_1(oword
, FRF_AZ_RX_DESC_WPTR
, wptr
);
1528 /* Only write the third DWORD */
1529 EFX_POPULATE_DWORD_1(dword
,
1530 EFX_DWORD_0
, EFX_OWORD_FIELD(oword
, EFX_DWORD_3
));
1532 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1533 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp
->er_esmp
, erp
->er_mask
+ 1,
1534 wptr
, pushed
& erp
->er_mask
);
1535 EFSYS_PIO_WRITE_BARRIER();
1536 EFX_BAR_TBL_WRITED3(enp
, FR_BZ_RX_DESC_UPD_REGP0
,
1537 erp
->er_index
, &dword
, B_FALSE
);
1540 #if EFSYS_OPT_RX_PACKED_STREAM
1542 siena_rx_qpush_ps_credits(
1543 __in efx_rxq_t
*erp
)
1545 /* Not supported by Siena hardware */
1550 siena_rx_qps_packet_info(
1551 __in efx_rxq_t
*erp
,
1552 __in
uint8_t *buffer
,
1553 __in
uint32_t buffer_length
,
1554 __in
uint32_t current_offset
,
1555 __out
uint16_t *lengthp
,
1556 __out
uint32_t *next_offsetp
,
1557 __out
uint32_t *timestamp
)
1559 /* Not supported by Siena hardware */
1564 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1566 static __checkReturn efx_rc_t
1568 __in efx_rxq_t
*erp
)
1570 efx_nic_t
*enp
= erp
->er_enp
;
1574 label
= erp
->er_index
;
1576 /* Flush the queue */
1577 EFX_POPULATE_OWORD_2(oword
, FRF_AZ_RX_FLUSH_DESCQ_CMD
, 1,
1578 FRF_AZ_RX_FLUSH_DESCQ
, label
);
1579 EFX_BAR_WRITEO(enp
, FR_AZ_RX_FLUSH_DESCQ_REG
, &oword
);
1586 __in efx_rxq_t
*erp
)
1588 efx_nic_t
*enp
= erp
->er_enp
;
1591 EFSYS_ASSERT3U(erp
->er_magic
, ==, EFX_RXQ_MAGIC
);
1593 EFX_BAR_TBL_READO(enp
, FR_AZ_RX_DESC_PTR_TBL
,
1594 erp
->er_index
, &oword
, B_TRUE
);
1596 EFX_SET_OWORD_FIELD(oword
, FRF_AZ_RX_DC_HW_RPTR
, 0);
1597 EFX_SET_OWORD_FIELD(oword
, FRF_AZ_RX_DESCQ_HW_RPTR
, 0);
1598 EFX_SET_OWORD_FIELD(oword
, FRF_AZ_RX_DESCQ_EN
, 1);
1600 EFX_BAR_TBL_WRITEO(enp
, FR_AZ_RX_DESC_PTR_TBL
,
1601 erp
->er_index
, &oword
, B_TRUE
);
1604 static __checkReturn efx_rc_t
1606 __in efx_nic_t
*enp
,
1607 __in
unsigned int index
,
1608 __in
unsigned int label
,
1609 __in efx_rxq_type_t type
,
1610 __in_opt
const efx_rxq_type_data_t
*type_data
,
1611 __in efsys_mem_t
*esmp
,
1614 __in
unsigned int flags
,
1615 __in efx_evq_t
*eep
,
1616 __in efx_rxq_t
*erp
)
1618 efx_nic_cfg_t
*encp
= &(enp
->en_nic_cfg
);
1621 boolean_t jumbo
= B_FALSE
;
1624 _NOTE(ARGUNUSED(esmp
))
1626 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS
==
1627 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH
));
1628 EFSYS_ASSERT3U(label
, <, EFX_EV_RX_NLABELS
);
1629 EFSYS_ASSERT3U(enp
->en_rx_qcount
+ 1, <, encp
->enc_rxq_limit
);
1631 if (index
>= encp
->enc_rxq_limit
) {
1636 (1U << size
) <= encp
->enc_rxq_max_ndescs
/ encp
->enc_rxq_min_ndescs
;
1638 if ((1U << size
) == (uint32_t)ndescs
/ encp
->enc_rxq_min_ndescs
)
1640 if (id
+ (1 << size
) >= encp
->enc_buftbl_limit
) {
1646 case EFX_RXQ_TYPE_DEFAULT
:
1647 erp
->er_buf_size
= type_data
->ertd_default
.ed_buf_size
;
1655 if (flags
& EFX_RXQ_FLAG_SCATTER
) {
1656 #if EFSYS_OPT_RX_SCATTER
1661 #endif /* EFSYS_OPT_RX_SCATTER */
1664 /* Set up the new descriptor queue */
1665 EFX_POPULATE_OWORD_7(oword
,
1666 FRF_AZ_RX_DESCQ_BUF_BASE_ID
, id
,
1667 FRF_AZ_RX_DESCQ_EVQ_ID
, eep
->ee_index
,
1668 FRF_AZ_RX_DESCQ_OWNER_ID
, 0,
1669 FRF_AZ_RX_DESCQ_LABEL
, label
,
1670 FRF_AZ_RX_DESCQ_SIZE
, size
,
1671 FRF_AZ_RX_DESCQ_TYPE
, 0,
1672 FRF_AZ_RX_DESCQ_JUMBO
, jumbo
);
1674 EFX_BAR_TBL_WRITEO(enp
, FR_AZ_RX_DESC_PTR_TBL
,
1675 erp
->er_index
, &oword
, B_TRUE
);
1679 #if !EFSYS_OPT_RX_SCATTER
1688 EFSYS_PROBE1(fail1
, efx_rc_t
, rc
);
1695 __in efx_rxq_t
*erp
)
1697 efx_nic_t
*enp
= erp
->er_enp
;
1700 EFSYS_ASSERT(enp
->en_rx_qcount
!= 0);
1701 --enp
->en_rx_qcount
;
1703 /* Purge descriptor queue */
1704 EFX_ZERO_OWORD(oword
);
1706 EFX_BAR_TBL_WRITEO(enp
, FR_AZ_RX_DESC_PTR_TBL
,
1707 erp
->er_index
, &oword
, B_TRUE
);
1709 /* Free the RXQ object */
1710 EFSYS_KMEM_FREE(enp
->en_esip
, sizeof (efx_rxq_t
), erp
);
1715 __in efx_nic_t
*enp
)
1717 _NOTE(ARGUNUSED(enp
))
1720 #endif /* EFSYS_OPT_SIENA */