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update source to Ceph Pacific 16.2.2
[ceph.git] / ceph / src / spdk / dpdk / drivers / net / sfc / base / efx_rx.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2007-2019 Solarflare Communications Inc.
5 */
6
7 #include "efx.h"
8 #include "efx_impl.h"
9
10
11 #if EFSYS_OPT_SIENA
12
13 static __checkReturn efx_rc_t
14 siena_rx_init(
15 __in efx_nic_t *enp);
16
17 static void
18 siena_rx_fini(
19 __in efx_nic_t *enp);
20
21 #if EFSYS_OPT_RX_SCATTER
22 static __checkReturn efx_rc_t
23 siena_rx_scatter_enable(
24 __in efx_nic_t *enp,
25 __in unsigned int buf_size);
26 #endif /* EFSYS_OPT_RX_SCATTER */
27
28 #if EFSYS_OPT_RX_SCALE
29 static __checkReturn efx_rc_t
30 siena_rx_scale_mode_set(
31 __in efx_nic_t *enp,
32 __in uint32_t rss_context,
33 __in efx_rx_hash_alg_t alg,
34 __in efx_rx_hash_type_t type,
35 __in boolean_t insert);
36
37 static __checkReturn efx_rc_t
38 siena_rx_scale_key_set(
39 __in efx_nic_t *enp,
40 __in uint32_t rss_context,
41 __in_ecount(n) uint8_t *key,
42 __in size_t n);
43
44 static __checkReturn efx_rc_t
45 siena_rx_scale_tbl_set(
46 __in efx_nic_t *enp,
47 __in uint32_t rss_context,
48 __in_ecount(n) unsigned int *table,
49 __in size_t n);
50
51 static __checkReturn uint32_t
52 siena_rx_prefix_hash(
53 __in efx_nic_t *enp,
54 __in efx_rx_hash_alg_t func,
55 __in uint8_t *buffer);
56
57 #endif /* EFSYS_OPT_RX_SCALE */
58
59 static __checkReturn efx_rc_t
60 siena_rx_prefix_pktlen(
61 __in efx_nic_t *enp,
62 __in uint8_t *buffer,
63 __out uint16_t *lengthp);
64
65 static void
66 siena_rx_qpost(
67 __in efx_rxq_t *erp,
68 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
69 __in size_t size,
70 __in unsigned int ndescs,
71 __in unsigned int completed,
72 __in unsigned int added);
73
74 static void
75 siena_rx_qpush(
76 __in efx_rxq_t *erp,
77 __in unsigned int added,
78 __inout unsigned int *pushedp);
79
80 #if EFSYS_OPT_RX_PACKED_STREAM
81 static void
82 siena_rx_qpush_ps_credits(
83 __in efx_rxq_t *erp);
84
85 static __checkReturn uint8_t *
86 siena_rx_qps_packet_info(
87 __in efx_rxq_t *erp,
88 __in uint8_t *buffer,
89 __in uint32_t buffer_length,
90 __in uint32_t current_offset,
91 __out uint16_t *lengthp,
92 __out uint32_t *next_offsetp,
93 __out uint32_t *timestamp);
94 #endif
95
96 static __checkReturn efx_rc_t
97 siena_rx_qflush(
98 __in efx_rxq_t *erp);
99
100 static void
101 siena_rx_qenable(
102 __in efx_rxq_t *erp);
103
104 static __checkReturn efx_rc_t
105 siena_rx_qcreate(
106 __in efx_nic_t *enp,
107 __in unsigned int index,
108 __in unsigned int label,
109 __in efx_rxq_type_t type,
110 __in_opt const efx_rxq_type_data_t *type_data,
111 __in efsys_mem_t *esmp,
112 __in size_t ndescs,
113 __in uint32_t id,
114 __in unsigned int flags,
115 __in efx_evq_t *eep,
116 __in efx_rxq_t *erp);
117
118 static void
119 siena_rx_qdestroy(
120 __in efx_rxq_t *erp);
121
122 #endif /* EFSYS_OPT_SIENA */
123
124
125 #if EFSYS_OPT_SIENA
126 static const efx_rx_ops_t __efx_rx_siena_ops = {
127 siena_rx_init, /* erxo_init */
128 siena_rx_fini, /* erxo_fini */
129 #if EFSYS_OPT_RX_SCATTER
130 siena_rx_scatter_enable, /* erxo_scatter_enable */
131 #endif
132 #if EFSYS_OPT_RX_SCALE
133 NULL, /* erxo_scale_context_alloc */
134 NULL, /* erxo_scale_context_free */
135 siena_rx_scale_mode_set, /* erxo_scale_mode_set */
136 siena_rx_scale_key_set, /* erxo_scale_key_set */
137 siena_rx_scale_tbl_set, /* erxo_scale_tbl_set */
138 siena_rx_prefix_hash, /* erxo_prefix_hash */
139 #endif
140 siena_rx_prefix_pktlen, /* erxo_prefix_pktlen */
141 siena_rx_qpost, /* erxo_qpost */
142 siena_rx_qpush, /* erxo_qpush */
143 #if EFSYS_OPT_RX_PACKED_STREAM
144 siena_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
145 siena_rx_qps_packet_info, /* erxo_qps_packet_info */
146 #endif
147 siena_rx_qflush, /* erxo_qflush */
148 siena_rx_qenable, /* erxo_qenable */
149 siena_rx_qcreate, /* erxo_qcreate */
150 siena_rx_qdestroy, /* erxo_qdestroy */
151 };
152 #endif /* EFSYS_OPT_SIENA */
153
154 #if EFX_OPTS_EF10()
155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
156 ef10_rx_init, /* erxo_init */
157 ef10_rx_fini, /* erxo_fini */
158 #if EFSYS_OPT_RX_SCATTER
159 ef10_rx_scatter_enable, /* erxo_scatter_enable */
160 #endif
161 #if EFSYS_OPT_RX_SCALE
162 ef10_rx_scale_context_alloc, /* erxo_scale_context_alloc */
163 ef10_rx_scale_context_free, /* erxo_scale_context_free */
164 ef10_rx_scale_mode_set, /* erxo_scale_mode_set */
165 ef10_rx_scale_key_set, /* erxo_scale_key_set */
166 ef10_rx_scale_tbl_set, /* erxo_scale_tbl_set */
167 ef10_rx_prefix_hash, /* erxo_prefix_hash */
168 #endif
169 ef10_rx_prefix_pktlen, /* erxo_prefix_pktlen */
170 ef10_rx_qpost, /* erxo_qpost */
171 ef10_rx_qpush, /* erxo_qpush */
172 #if EFSYS_OPT_RX_PACKED_STREAM
173 ef10_rx_qpush_ps_credits, /* erxo_qpush_ps_credits */
174 ef10_rx_qps_packet_info, /* erxo_qps_packet_info */
175 #endif
176 ef10_rx_qflush, /* erxo_qflush */
177 ef10_rx_qenable, /* erxo_qenable */
178 ef10_rx_qcreate, /* erxo_qcreate */
179 ef10_rx_qdestroy, /* erxo_qdestroy */
180 };
181 #endif /* EFX_OPTS_EF10() */
182
183
184 __checkReturn efx_rc_t
185 efx_rx_init(
186 __inout efx_nic_t *enp)
187 {
188 const efx_rx_ops_t *erxop;
189 efx_rc_t rc;
190
191 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
192 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
193
194 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
195 rc = EINVAL;
196 goto fail1;
197 }
198
199 if (enp->en_mod_flags & EFX_MOD_RX) {
200 rc = EINVAL;
201 goto fail2;
202 }
203
204 switch (enp->en_family) {
205 #if EFSYS_OPT_SIENA
206 case EFX_FAMILY_SIENA:
207 erxop = &__efx_rx_siena_ops;
208 break;
209 #endif /* EFSYS_OPT_SIENA */
210
211 #if EFSYS_OPT_HUNTINGTON
212 case EFX_FAMILY_HUNTINGTON:
213 erxop = &__efx_rx_ef10_ops;
214 break;
215 #endif /* EFSYS_OPT_HUNTINGTON */
216
217 #if EFSYS_OPT_MEDFORD
218 case EFX_FAMILY_MEDFORD:
219 erxop = &__efx_rx_ef10_ops;
220 break;
221 #endif /* EFSYS_OPT_MEDFORD */
222
223 #if EFSYS_OPT_MEDFORD2
224 case EFX_FAMILY_MEDFORD2:
225 erxop = &__efx_rx_ef10_ops;
226 break;
227 #endif /* EFSYS_OPT_MEDFORD2 */
228
229 default:
230 EFSYS_ASSERT(0);
231 rc = ENOTSUP;
232 goto fail3;
233 }
234
235 if ((rc = erxop->erxo_init(enp)) != 0)
236 goto fail4;
237
238 enp->en_erxop = erxop;
239 enp->en_mod_flags |= EFX_MOD_RX;
240 return (0);
241
242 fail4:
243 EFSYS_PROBE(fail4);
244 fail3:
245 EFSYS_PROBE(fail3);
246 fail2:
247 EFSYS_PROBE(fail2);
248 fail1:
249 EFSYS_PROBE1(fail1, efx_rc_t, rc);
250
251 enp->en_erxop = NULL;
252 enp->en_mod_flags &= ~EFX_MOD_RX;
253 return (rc);
254 }
255
256 void
257 efx_rx_fini(
258 __in efx_nic_t *enp)
259 {
260 const efx_rx_ops_t *erxop = enp->en_erxop;
261
262 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
263 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
264 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
265 EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
266
267 erxop->erxo_fini(enp);
268
269 enp->en_erxop = NULL;
270 enp->en_mod_flags &= ~EFX_MOD_RX;
271 }
272
273 #if EFSYS_OPT_RX_SCATTER
274 __checkReturn efx_rc_t
275 efx_rx_scatter_enable(
276 __in efx_nic_t *enp,
277 __in unsigned int buf_size)
278 {
279 const efx_rx_ops_t *erxop = enp->en_erxop;
280 efx_rc_t rc;
281
282 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
283 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
284
285 if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
286 goto fail1;
287
288 return (0);
289
290 fail1:
291 EFSYS_PROBE1(fail1, efx_rc_t, rc);
292 return (rc);
293 }
294 #endif /* EFSYS_OPT_RX_SCATTER */
295
296 #if EFSYS_OPT_RX_SCALE
297 __checkReturn efx_rc_t
298 efx_rx_scale_hash_flags_get(
299 __in efx_nic_t *enp,
300 __in efx_rx_hash_alg_t hash_alg,
301 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
302 __in unsigned int max_nflags,
303 __out unsigned int *nflagsp)
304 {
305 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
306 unsigned int nflags = 0;
307 efx_rc_t rc;
308
309 if (flagsp == NULL || nflagsp == NULL) {
310 rc = EINVAL;
311 goto fail1;
312 }
313
314 if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0) {
315 nflags = 0;
316 goto done;
317 }
318
319 /* Helper to add flags word to flags array without buffer overflow */
320 #define INSERT_FLAGS(_flags) \
321 do { \
322 if (nflags >= max_nflags) { \
323 rc = E2BIG; \
324 goto fail2; \
325 } \
326 *(flagsp + nflags) = (_flags); \
327 nflags++; \
328 \
329 _NOTE(CONSTANTCONDITION) \
330 } while (B_FALSE)
331
332 if (encp->enc_rx_scale_l4_hash_supported != B_FALSE) {
333 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 4TUPLE));
334 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 4TUPLE));
335 }
336
337 if ((encp->enc_rx_scale_l4_hash_supported != B_FALSE) &&
338 (encp->enc_rx_scale_additional_modes_supported != B_FALSE)) {
339 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_DST));
340 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_SRC));
341
342 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_DST));
343 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_SRC));
344
345 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 4TUPLE));
346 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_DST));
347 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_SRC));
348
349 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 4TUPLE));
350 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_DST));
351 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_SRC));
352 }
353
354 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE));
355 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE));
356
357 INSERT_FLAGS(EFX_RX_HASH(IPV4, 2TUPLE));
358 INSERT_FLAGS(EFX_RX_HASH(IPV6, 2TUPLE));
359
360 if (encp->enc_rx_scale_additional_modes_supported != B_FALSE) {
361 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_DST));
362 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_SRC));
363
364 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_DST));
365 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_SRC));
366
367 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE));
368 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_DST));
369 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_SRC));
370
371 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE));
372 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_DST));
373 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_SRC));
374
375 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_DST));
376 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_SRC));
377
378 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_DST));
379 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_SRC));
380 }
381
382 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, DISABLE));
383 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, DISABLE));
384
385 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, DISABLE));
386 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, DISABLE));
387
388 INSERT_FLAGS(EFX_RX_HASH(IPV4, DISABLE));
389 INSERT_FLAGS(EFX_RX_HASH(IPV6, DISABLE));
390
391 #undef INSERT_FLAGS
392
393 done:
394 *nflagsp = nflags;
395 return (0);
396
397 fail2:
398 EFSYS_PROBE(fail2);
399 fail1:
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
401
402 return (rc);
403 }
404
405 __checkReturn efx_rc_t
406 efx_rx_hash_default_support_get(
407 __in efx_nic_t *enp,
408 __out efx_rx_hash_support_t *supportp)
409 {
410 efx_rc_t rc;
411
412 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
413 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
414
415 if (supportp == NULL) {
416 rc = EINVAL;
417 goto fail1;
418 }
419
420 /*
421 * Report the hashing support the client gets by default if it
422 * does not allocate an RSS context itself.
423 */
424 *supportp = enp->en_hash_support;
425
426 return (0);
427
428 fail1:
429 EFSYS_PROBE1(fail1, efx_rc_t, rc);
430
431 return (rc);
432 }
433
434 __checkReturn efx_rc_t
435 efx_rx_scale_default_support_get(
436 __in efx_nic_t *enp,
437 __out efx_rx_scale_context_type_t *typep)
438 {
439 efx_rc_t rc;
440
441 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
442 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
443
444 if (typep == NULL) {
445 rc = EINVAL;
446 goto fail1;
447 }
448
449 /*
450 * Report the RSS support the client gets by default if it
451 * does not allocate an RSS context itself.
452 */
453 *typep = enp->en_rss_context_type;
454
455 return (0);
456
457 fail1:
458 EFSYS_PROBE1(fail1, efx_rc_t, rc);
459
460 return (rc);
461 }
462 #endif /* EFSYS_OPT_RX_SCALE */
463
464 #if EFSYS_OPT_RX_SCALE
465 __checkReturn efx_rc_t
466 efx_rx_scale_context_alloc(
467 __in efx_nic_t *enp,
468 __in efx_rx_scale_context_type_t type,
469 __in uint32_t num_queues,
470 __out uint32_t *rss_contextp)
471 {
472 const efx_rx_ops_t *erxop = enp->en_erxop;
473 efx_rc_t rc;
474
475 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
476 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
477
478 if (erxop->erxo_scale_context_alloc == NULL) {
479 rc = ENOTSUP;
480 goto fail1;
481 }
482 if ((rc = erxop->erxo_scale_context_alloc(enp, type,
483 num_queues, rss_contextp)) != 0) {
484 goto fail2;
485 }
486
487 return (0);
488
489 fail2:
490 EFSYS_PROBE(fail2);
491 fail1:
492 EFSYS_PROBE1(fail1, efx_rc_t, rc);
493 return (rc);
494 }
495 #endif /* EFSYS_OPT_RX_SCALE */
496
497 #if EFSYS_OPT_RX_SCALE
498 __checkReturn efx_rc_t
499 efx_rx_scale_context_free(
500 __in efx_nic_t *enp,
501 __in uint32_t rss_context)
502 {
503 const efx_rx_ops_t *erxop = enp->en_erxop;
504 efx_rc_t rc;
505
506 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
507 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
508
509 if (erxop->erxo_scale_context_free == NULL) {
510 rc = ENOTSUP;
511 goto fail1;
512 }
513 if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
514 goto fail2;
515
516 return (0);
517
518 fail2:
519 EFSYS_PROBE(fail2);
520 fail1:
521 EFSYS_PROBE1(fail1, efx_rc_t, rc);
522 return (rc);
523 }
524 #endif /* EFSYS_OPT_RX_SCALE */
525
526 #if EFSYS_OPT_RX_SCALE
527 __checkReturn efx_rc_t
528 efx_rx_scale_mode_set(
529 __in efx_nic_t *enp,
530 __in uint32_t rss_context,
531 __in efx_rx_hash_alg_t alg,
532 __in efx_rx_hash_type_t type,
533 __in boolean_t insert)
534 {
535 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
536 const efx_rx_ops_t *erxop = enp->en_erxop;
537 efx_rx_hash_type_t type_check;
538 unsigned int i;
539 efx_rc_t rc;
540
541 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
542 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
543
544 /*
545 * Legacy flags and modern bits cannot be
546 * used at the same time in the hash type.
547 */
548 if ((type & EFX_RX_HASH_LEGACY_MASK) &&
549 (type & ~EFX_RX_HASH_LEGACY_MASK)) {
550 rc = EINVAL;
551 goto fail1;
552 }
553
554 /*
555 * If RSS hash type is represented by additional bits
556 * in the value, the latter need to be verified since
557 * not all bit combinations are valid RSS modes. Also,
558 * depending on the firmware, some valid combinations
559 * may be unsupported. Discern additional bits in the
560 * type value and try to recognise valid combinations.
561 * If some bits remain unrecognised, report the error.
562 */
563 type_check = type & ~EFX_RX_HASH_LEGACY_MASK;
564 if (type_check != 0) {
565 unsigned int type_flags[EFX_RX_HASH_NFLAGS];
566 unsigned int type_nflags;
567
568 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags,
569 EFX_ARRAY_SIZE(type_flags), &type_nflags);
570 if (rc != 0)
571 goto fail2;
572
573 for (i = 0; i < type_nflags; ++i) {
574 if ((type_check & type_flags[i]) == type_flags[i])
575 type_check &= ~(type_flags[i]);
576 }
577
578 if (type_check != 0) {
579 rc = EINVAL;
580 goto fail3;
581 }
582 }
583
584 /*
585 * Translate EFX_RX_HASH() flags to their legacy counterparts
586 * provided that the FW claims no support for additional modes.
587 */
588 if (encp->enc_rx_scale_additional_modes_supported == B_FALSE) {
589 efx_rx_hash_type_t t_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE) |
590 EFX_RX_HASH(IPV4_TCP, 2TUPLE);
591 efx_rx_hash_type_t t_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE) |
592 EFX_RX_HASH(IPV6_TCP, 2TUPLE);
593 efx_rx_hash_type_t t_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
594 efx_rx_hash_type_t t_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
595
596 if ((type & t_ipv4) == t_ipv4)
597 type |= EFX_RX_HASH_IPV4;
598 if ((type & t_ipv6) == t_ipv6)
599 type |= EFX_RX_HASH_IPV6;
600
601 if (encp->enc_rx_scale_l4_hash_supported == B_TRUE) {
602 if ((type & t_ipv4_tcp) == t_ipv4_tcp)
603 type |= EFX_RX_HASH_TCPIPV4;
604 if ((type & t_ipv6_tcp) == t_ipv6_tcp)
605 type |= EFX_RX_HASH_TCPIPV6;
606 }
607
608 type &= EFX_RX_HASH_LEGACY_MASK;
609 }
610
611 if (erxop->erxo_scale_mode_set != NULL) {
612 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
613 type, insert)) != 0)
614 goto fail4;
615 }
616
617 return (0);
618
619 fail4:
620 EFSYS_PROBE(fail4);
621 fail3:
622 EFSYS_PROBE(fail3);
623 fail2:
624 EFSYS_PROBE(fail2);
625 fail1:
626 EFSYS_PROBE1(fail1, efx_rc_t, rc);
627 return (rc);
628 }
629 #endif /* EFSYS_OPT_RX_SCALE */
630
631 #if EFSYS_OPT_RX_SCALE
632 __checkReturn efx_rc_t
633 efx_rx_scale_key_set(
634 __in efx_nic_t *enp,
635 __in uint32_t rss_context,
636 __in_ecount(n) uint8_t *key,
637 __in size_t n)
638 {
639 const efx_rx_ops_t *erxop = enp->en_erxop;
640 efx_rc_t rc;
641
642 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
643 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
644
645 if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
646 goto fail1;
647
648 return (0);
649
650 fail1:
651 EFSYS_PROBE1(fail1, efx_rc_t, rc);
652
653 return (rc);
654 }
655 #endif /* EFSYS_OPT_RX_SCALE */
656
657 #if EFSYS_OPT_RX_SCALE
658 __checkReturn efx_rc_t
659 efx_rx_scale_tbl_set(
660 __in efx_nic_t *enp,
661 __in uint32_t rss_context,
662 __in_ecount(n) unsigned int *table,
663 __in size_t n)
664 {
665 const efx_rx_ops_t *erxop = enp->en_erxop;
666 efx_rc_t rc;
667
668 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
669 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
670
671 if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
672 goto fail1;
673
674 return (0);
675
676 fail1:
677 EFSYS_PROBE1(fail1, efx_rc_t, rc);
678
679 return (rc);
680 }
681 #endif /* EFSYS_OPT_RX_SCALE */
682
683 void
684 efx_rx_qpost(
685 __in efx_rxq_t *erp,
686 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
687 __in size_t size,
688 __in unsigned int ndescs,
689 __in unsigned int completed,
690 __in unsigned int added)
691 {
692 efx_nic_t *enp = erp->er_enp;
693 const efx_rx_ops_t *erxop = enp->en_erxop;
694
695 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
696 EFSYS_ASSERT(erp->er_buf_size == 0 || size == erp->er_buf_size);
697
698 erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
699 }
700
701 #if EFSYS_OPT_RX_PACKED_STREAM
702
703 void
704 efx_rx_qpush_ps_credits(
705 __in efx_rxq_t *erp)
706 {
707 efx_nic_t *enp = erp->er_enp;
708 const efx_rx_ops_t *erxop = enp->en_erxop;
709
710 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
711
712 erxop->erxo_qpush_ps_credits(erp);
713 }
714
715 __checkReturn uint8_t *
716 efx_rx_qps_packet_info(
717 __in efx_rxq_t *erp,
718 __in uint8_t *buffer,
719 __in uint32_t buffer_length,
720 __in uint32_t current_offset,
721 __out uint16_t *lengthp,
722 __out uint32_t *next_offsetp,
723 __out uint32_t *timestamp)
724 {
725 efx_nic_t *enp = erp->er_enp;
726 const efx_rx_ops_t *erxop = enp->en_erxop;
727
728 return (erxop->erxo_qps_packet_info(erp, buffer,
729 buffer_length, current_offset, lengthp,
730 next_offsetp, timestamp));
731 }
732
733 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
734
735 void
736 efx_rx_qpush(
737 __in efx_rxq_t *erp,
738 __in unsigned int added,
739 __inout unsigned int *pushedp)
740 {
741 efx_nic_t *enp = erp->er_enp;
742 const efx_rx_ops_t *erxop = enp->en_erxop;
743
744 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
745
746 erxop->erxo_qpush(erp, added, pushedp);
747 }
748
749 __checkReturn efx_rc_t
750 efx_rx_qflush(
751 __in efx_rxq_t *erp)
752 {
753 efx_nic_t *enp = erp->er_enp;
754 const efx_rx_ops_t *erxop = enp->en_erxop;
755 efx_rc_t rc;
756
757 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
758
759 if ((rc = erxop->erxo_qflush(erp)) != 0)
760 goto fail1;
761
762 return (0);
763
764 fail1:
765 EFSYS_PROBE1(fail1, efx_rc_t, rc);
766
767 return (rc);
768 }
769
770 __checkReturn size_t
771 efx_rxq_size(
772 __in const efx_nic_t *enp,
773 __in unsigned int ndescs)
774 {
775 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
776
777 return (ndescs * encp->enc_rx_desc_size);
778 }
779
780 __checkReturn unsigned int
781 efx_rxq_nbufs(
782 __in const efx_nic_t *enp,
783 __in unsigned int ndescs)
784 {
785 return (EFX_DIV_ROUND_UP(efx_rxq_size(enp, ndescs), EFX_BUF_SIZE));
786 }
787
788 void
789 efx_rx_qenable(
790 __in efx_rxq_t *erp)
791 {
792 efx_nic_t *enp = erp->er_enp;
793 const efx_rx_ops_t *erxop = enp->en_erxop;
794
795 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
796
797 erxop->erxo_qenable(erp);
798 }
799
800 static __checkReturn efx_rc_t
801 efx_rx_qcreate_internal(
802 __in efx_nic_t *enp,
803 __in unsigned int index,
804 __in unsigned int label,
805 __in efx_rxq_type_t type,
806 __in_opt const efx_rxq_type_data_t *type_data,
807 __in efsys_mem_t *esmp,
808 __in size_t ndescs,
809 __in uint32_t id,
810 __in unsigned int flags,
811 __in efx_evq_t *eep,
812 __deref_out efx_rxq_t **erpp)
813 {
814 const efx_rx_ops_t *erxop = enp->en_erxop;
815 efx_rxq_t *erp;
816 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
817 efx_rc_t rc;
818
819 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
820 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
821
822 EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs));
823 EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs));
824
825 if (!ISP2(ndescs) ||
826 ndescs < encp->enc_rxq_min_ndescs ||
827 ndescs > encp->enc_rxq_max_ndescs) {
828 rc = EINVAL;
829 goto fail1;
830 }
831
832 /* Allocate an RXQ object */
833 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
834
835 if (erp == NULL) {
836 rc = ENOMEM;
837 goto fail2;
838 }
839
840 erp->er_magic = EFX_RXQ_MAGIC;
841 erp->er_enp = enp;
842 erp->er_index = index;
843 erp->er_mask = ndescs - 1;
844 erp->er_esmp = esmp;
845
846 if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
847 ndescs, id, flags, eep, erp)) != 0)
848 goto fail3;
849
850 enp->en_rx_qcount++;
851 *erpp = erp;
852
853 return (0);
854
855 fail3:
856 EFSYS_PROBE(fail3);
857
858 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
859 fail2:
860 EFSYS_PROBE(fail2);
861 fail1:
862 EFSYS_PROBE1(fail1, efx_rc_t, rc);
863
864 return (rc);
865 }
866
867 __checkReturn efx_rc_t
868 efx_rx_qcreate(
869 __in efx_nic_t *enp,
870 __in unsigned int index,
871 __in unsigned int label,
872 __in efx_rxq_type_t type,
873 __in size_t buf_size,
874 __in efsys_mem_t *esmp,
875 __in size_t ndescs,
876 __in uint32_t id,
877 __in unsigned int flags,
878 __in efx_evq_t *eep,
879 __deref_out efx_rxq_t **erpp)
880 {
881 efx_rxq_type_data_t type_data;
882
883 memset(&type_data, 0, sizeof (type_data));
884
885 type_data.ertd_default.ed_buf_size = buf_size;
886
887 return efx_rx_qcreate_internal(enp, index, label, type, &type_data,
888 esmp, ndescs, id, flags, eep, erpp);
889 }
890
891 #if EFSYS_OPT_RX_PACKED_STREAM
892
893 __checkReturn efx_rc_t
894 efx_rx_qcreate_packed_stream(
895 __in efx_nic_t *enp,
896 __in unsigned int index,
897 __in unsigned int label,
898 __in uint32_t ps_buf_size,
899 __in efsys_mem_t *esmp,
900 __in size_t ndescs,
901 __in efx_evq_t *eep,
902 __deref_out efx_rxq_t **erpp)
903 {
904 efx_rxq_type_data_t type_data;
905
906 memset(&type_data, 0, sizeof (type_data));
907
908 type_data.ertd_packed_stream.eps_buf_size = ps_buf_size;
909
910 return efx_rx_qcreate_internal(enp, index, label,
911 EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs,
912 0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
913 }
914
915 #endif
916
917 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
918
919 __checkReturn efx_rc_t
920 efx_rx_qcreate_es_super_buffer(
921 __in efx_nic_t *enp,
922 __in unsigned int index,
923 __in unsigned int label,
924 __in uint32_t n_bufs_per_desc,
925 __in uint32_t max_dma_len,
926 __in uint32_t buf_stride,
927 __in uint32_t hol_block_timeout,
928 __in efsys_mem_t *esmp,
929 __in size_t ndescs,
930 __in unsigned int flags,
931 __in efx_evq_t *eep,
932 __deref_out efx_rxq_t **erpp)
933 {
934 efx_rc_t rc;
935 efx_rxq_type_data_t type_data;
936
937 if (hol_block_timeout > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
938 rc = EINVAL;
939 goto fail1;
940 }
941
942 memset(&type_data, 0, sizeof (type_data));
943
944 type_data.ertd_es_super_buffer.eessb_bufs_per_desc = n_bufs_per_desc;
945 type_data.ertd_es_super_buffer.eessb_max_dma_len = max_dma_len;
946 type_data.ertd_es_super_buffer.eessb_buf_stride = buf_stride;
947 type_data.ertd_es_super_buffer.eessb_hol_block_timeout =
948 hol_block_timeout;
949
950 rc = efx_rx_qcreate_internal(enp, index, label,
951 EFX_RXQ_TYPE_ES_SUPER_BUFFER, &type_data, esmp, ndescs,
952 0 /* id unused on EF10 */, flags, eep, erpp);
953 if (rc != 0)
954 goto fail2;
955
956 return (0);
957
958 fail2:
959 EFSYS_PROBE(fail2);
960 fail1:
961 EFSYS_PROBE1(fail1, efx_rc_t, rc);
962
963 return (rc);
964 }
965
966 #endif
967
968
969 void
970 efx_rx_qdestroy(
971 __in efx_rxq_t *erp)
972 {
973 efx_nic_t *enp = erp->er_enp;
974 const efx_rx_ops_t *erxop = enp->en_erxop;
975
976 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
977
978 erxop->erxo_qdestroy(erp);
979 }
980
981 __checkReturn efx_rc_t
982 efx_pseudo_hdr_pkt_length_get(
983 __in efx_rxq_t *erp,
984 __in uint8_t *buffer,
985 __out uint16_t *lengthp)
986 {
987 efx_nic_t *enp = erp->er_enp;
988 const efx_rx_ops_t *erxop = enp->en_erxop;
989
990 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
991
992 return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
993 }
994
995 #if EFSYS_OPT_RX_SCALE
996 __checkReturn uint32_t
997 efx_pseudo_hdr_hash_get(
998 __in efx_rxq_t *erp,
999 __in efx_rx_hash_alg_t func,
1000 __in uint8_t *buffer)
1001 {
1002 efx_nic_t *enp = erp->er_enp;
1003 const efx_rx_ops_t *erxop = enp->en_erxop;
1004
1005 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1006
1007 EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
1008 return (erxop->erxo_prefix_hash(enp, func, buffer));
1009 }
1010 #endif /* EFSYS_OPT_RX_SCALE */
1011
1012 #if EFSYS_OPT_SIENA
1013
1014 static __checkReturn efx_rc_t
1015 siena_rx_init(
1016 __in efx_nic_t *enp)
1017 {
1018 efx_oword_t oword;
1019 unsigned int index;
1020
1021 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1022
1023 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
1024 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
1025 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
1026 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
1027 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
1028 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
1029 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1030
1031 /* Zero the RSS table */
1032 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
1033 index++) {
1034 EFX_ZERO_OWORD(oword);
1035 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1036 index, &oword, B_TRUE);
1037 }
1038
1039 #if EFSYS_OPT_RX_SCALE
1040 /* The RSS key and indirection table are writable. */
1041 enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
1042
1043 /* Hardware can insert RX hash with/without RSS */
1044 enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
1045 #endif /* EFSYS_OPT_RX_SCALE */
1046
1047 return (0);
1048 }
1049
1050 #if EFSYS_OPT_RX_SCATTER
1051 static __checkReturn efx_rc_t
1052 siena_rx_scatter_enable(
1053 __in efx_nic_t *enp,
1054 __in unsigned int buf_size)
1055 {
1056 unsigned int nbuf32;
1057 efx_oword_t oword;
1058 efx_rc_t rc;
1059
1060 nbuf32 = buf_size / 32;
1061 if ((nbuf32 == 0) ||
1062 (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
1063 ((buf_size % 32) != 0)) {
1064 rc = EINVAL;
1065 goto fail1;
1066 }
1067
1068 if (enp->en_rx_qcount > 0) {
1069 rc = EBUSY;
1070 goto fail2;
1071 }
1072
1073 /* Set scatter buffer size */
1074 EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1075 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
1076 EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1077
1078 /* Enable scatter for packets not matching a filter */
1079 EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1080 EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
1081 EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1082
1083 return (0);
1084
1085 fail2:
1086 EFSYS_PROBE(fail2);
1087 fail1:
1088 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1089
1090 return (rc);
1091 }
1092 #endif /* EFSYS_OPT_RX_SCATTER */
1093
1094
1095 #define EFX_RX_LFSR_HASH(_enp, _insert) \
1096 do { \
1097 efx_oword_t oword; \
1098 \
1099 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1100 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0); \
1101 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0); \
1102 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0); \
1103 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1104 (_insert) ? 1 : 0); \
1105 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1106 \
1107 if ((_enp)->en_family == EFX_FAMILY_SIENA) { \
1108 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1109 &oword); \
1110 EFX_SET_OWORD_FIELD(oword, \
1111 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0); \
1112 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, \
1113 &oword); \
1114 } \
1115 \
1116 _NOTE(CONSTANTCONDITION) \
1117 } while (B_FALSE)
1118
1119 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp) \
1120 do { \
1121 efx_oword_t oword; \
1122 \
1123 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1124 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1); \
1125 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, \
1126 (_ip) ? 1 : 0); \
1127 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, \
1128 (_tcp) ? 0 : 1); \
1129 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, \
1130 (_insert) ? 1 : 0); \
1131 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword); \
1132 \
1133 _NOTE(CONSTANTCONDITION) \
1134 } while (B_FALSE)
1135
1136 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc) \
1137 do { \
1138 efx_oword_t oword; \
1139 \
1140 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1141 EFX_SET_OWORD_FIELD(oword, \
1142 FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1); \
1143 EFX_SET_OWORD_FIELD(oword, \
1144 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1145 EFX_SET_OWORD_FIELD(oword, \
1146 FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1); \
1147 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1148 \
1149 (_rc) = 0; \
1150 \
1151 _NOTE(CONSTANTCONDITION) \
1152 } while (B_FALSE)
1153
1154
1155 #if EFSYS_OPT_RX_SCALE
1156
1157 static __checkReturn efx_rc_t
1158 siena_rx_scale_mode_set(
1159 __in efx_nic_t *enp,
1160 __in uint32_t rss_context,
1161 __in efx_rx_hash_alg_t alg,
1162 __in efx_rx_hash_type_t type,
1163 __in boolean_t insert)
1164 {
1165 efx_rc_t rc;
1166
1167 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1168 rc = EINVAL;
1169 goto fail1;
1170 }
1171
1172 switch (alg) {
1173 case EFX_RX_HASHALG_LFSR:
1174 EFX_RX_LFSR_HASH(enp, insert);
1175 break;
1176
1177 case EFX_RX_HASHALG_TOEPLITZ:
1178 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1179 (type & EFX_RX_HASH_IPV4) ? B_TRUE : B_FALSE,
1180 (type & EFX_RX_HASH_TCPIPV4) ? B_TRUE : B_FALSE);
1181
1182 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1183 (type & EFX_RX_HASH_IPV6) ? B_TRUE : B_FALSE,
1184 (type & EFX_RX_HASH_TCPIPV6) ? B_TRUE : B_FALSE,
1185 rc);
1186 if (rc != 0)
1187 goto fail2;
1188
1189 break;
1190
1191 default:
1192 rc = EINVAL;
1193 goto fail3;
1194 }
1195
1196 return (0);
1197
1198 fail3:
1199 EFSYS_PROBE(fail3);
1200 fail2:
1201 EFSYS_PROBE(fail2);
1202 fail1:
1203 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1204
1205 EFX_RX_LFSR_HASH(enp, B_FALSE);
1206
1207 return (rc);
1208 }
1209 #endif
1210
1211 #if EFSYS_OPT_RX_SCALE
1212 static __checkReturn efx_rc_t
1213 siena_rx_scale_key_set(
1214 __in efx_nic_t *enp,
1215 __in uint32_t rss_context,
1216 __in_ecount(n) uint8_t *key,
1217 __in size_t n)
1218 {
1219 efx_oword_t oword;
1220 unsigned int byte;
1221 unsigned int offset;
1222 efx_rc_t rc;
1223
1224 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1225 rc = EINVAL;
1226 goto fail1;
1227 }
1228
1229 byte = 0;
1230
1231 /* Write Toeplitz IPv4 hash key */
1232 EFX_ZERO_OWORD(oword);
1233 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1234 offset > 0 && byte < n;
1235 --offset)
1236 oword.eo_u8[offset - 1] = key[byte++];
1237
1238 EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1239
1240 byte = 0;
1241
1242 /* Verify Toeplitz IPv4 hash key */
1243 EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1244 for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1245 offset > 0 && byte < n;
1246 --offset) {
1247 if (oword.eo_u8[offset - 1] != key[byte++]) {
1248 rc = EFAULT;
1249 goto fail2;
1250 }
1251 }
1252
1253 if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1254 goto done;
1255
1256 byte = 0;
1257
1258 /* Write Toeplitz IPv6 hash key 3 */
1259 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1260 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1261 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1262 offset > 0 && byte < n;
1263 --offset)
1264 oword.eo_u8[offset - 1] = key[byte++];
1265
1266 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1267
1268 /* Write Toeplitz IPv6 hash key 2 */
1269 EFX_ZERO_OWORD(oword);
1270 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1271 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1272 offset > 0 && byte < n;
1273 --offset)
1274 oword.eo_u8[offset - 1] = key[byte++];
1275
1276 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1277
1278 /* Write Toeplitz IPv6 hash key 1 */
1279 EFX_ZERO_OWORD(oword);
1280 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1281 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1282 offset > 0 && byte < n;
1283 --offset)
1284 oword.eo_u8[offset - 1] = key[byte++];
1285
1286 EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1287
1288 byte = 0;
1289
1290 /* Verify Toeplitz IPv6 hash key 3 */
1291 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1292 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1293 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1294 offset > 0 && byte < n;
1295 --offset) {
1296 if (oword.eo_u8[offset - 1] != key[byte++]) {
1297 rc = EFAULT;
1298 goto fail3;
1299 }
1300 }
1301
1302 /* Verify Toeplitz IPv6 hash key 2 */
1303 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1304 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1305 FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1306 offset > 0 && byte < n;
1307 --offset) {
1308 if (oword.eo_u8[offset - 1] != key[byte++]) {
1309 rc = EFAULT;
1310 goto fail4;
1311 }
1312 }
1313
1314 /* Verify Toeplitz IPv6 hash key 1 */
1315 EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1316 for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1317 FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1318 offset > 0 && byte < n;
1319 --offset) {
1320 if (oword.eo_u8[offset - 1] != key[byte++]) {
1321 rc = EFAULT;
1322 goto fail5;
1323 }
1324 }
1325
1326 done:
1327 return (0);
1328
1329 fail5:
1330 EFSYS_PROBE(fail5);
1331 fail4:
1332 EFSYS_PROBE(fail4);
1333 fail3:
1334 EFSYS_PROBE(fail3);
1335 fail2:
1336 EFSYS_PROBE(fail2);
1337 fail1:
1338 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1339
1340 return (rc);
1341 }
1342 #endif
1343
1344 #if EFSYS_OPT_RX_SCALE
1345 static __checkReturn efx_rc_t
1346 siena_rx_scale_tbl_set(
1347 __in efx_nic_t *enp,
1348 __in uint32_t rss_context,
1349 __in_ecount(n) unsigned int *table,
1350 __in size_t n)
1351 {
1352 efx_oword_t oword;
1353 int index;
1354 efx_rc_t rc;
1355
1356 EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1357 EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1358
1359 if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1360 rc = EINVAL;
1361 goto fail1;
1362 }
1363
1364 if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1365 rc = EINVAL;
1366 goto fail2;
1367 }
1368
1369 for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1370 uint32_t byte;
1371
1372 /* Calculate the entry to place in the table */
1373 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1374
1375 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1376
1377 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1378
1379 /* Write the table */
1380 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1381 index, &oword, B_TRUE);
1382 }
1383
1384 for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1385 uint32_t byte;
1386
1387 /* Determine if we're starting a new batch */
1388 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1389
1390 /* Read the table */
1391 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1392 index, &oword, B_TRUE);
1393
1394 /* Verify the entry */
1395 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1396 rc = EFAULT;
1397 goto fail3;
1398 }
1399 }
1400
1401 return (0);
1402
1403 fail3:
1404 EFSYS_PROBE(fail3);
1405 fail2:
1406 EFSYS_PROBE(fail2);
1407 fail1:
1408 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1409
1410 return (rc);
1411 }
1412 #endif
1413
1414 /*
1415 * Falcon/Siena pseudo-header
1416 * --------------------------
1417 *
1418 * Receive packets are prefixed by an optional 16 byte pseudo-header.
1419 * The pseudo-header is a byte array of one of the forms:
1420 *
1421 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1422 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1423 * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1424 *
1425 * where:
1426 * TT.TT.TT.TT Toeplitz hash (32-bit big-endian)
1427 * LL.LL LFSR hash (16-bit big-endian)
1428 */
1429
1430 #if EFSYS_OPT_RX_SCALE
1431 static __checkReturn uint32_t
1432 siena_rx_prefix_hash(
1433 __in efx_nic_t *enp,
1434 __in efx_rx_hash_alg_t func,
1435 __in uint8_t *buffer)
1436 {
1437 _NOTE(ARGUNUSED(enp))
1438
1439 switch (func) {
1440 case EFX_RX_HASHALG_TOEPLITZ:
1441 return ((buffer[12] << 24) |
1442 (buffer[13] << 16) |
1443 (buffer[14] << 8) |
1444 buffer[15]);
1445
1446 case EFX_RX_HASHALG_LFSR:
1447 return ((buffer[14] << 8) | buffer[15]);
1448
1449 default:
1450 EFSYS_ASSERT(0);
1451 return (0);
1452 }
1453 }
1454 #endif /* EFSYS_OPT_RX_SCALE */
1455
1456 static __checkReturn efx_rc_t
1457 siena_rx_prefix_pktlen(
1458 __in efx_nic_t *enp,
1459 __in uint8_t *buffer,
1460 __out uint16_t *lengthp)
1461 {
1462 _NOTE(ARGUNUSED(enp, buffer, lengthp))
1463
1464 /* Not supported by Falcon/Siena hardware */
1465 EFSYS_ASSERT(0);
1466 return (ENOTSUP);
1467 }
1468
1469
1470 static void
1471 siena_rx_qpost(
1472 __in efx_rxq_t *erp,
1473 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
1474 __in size_t size,
1475 __in unsigned int ndescs,
1476 __in unsigned int completed,
1477 __in unsigned int added)
1478 {
1479 efx_qword_t qword;
1480 unsigned int i;
1481 unsigned int offset;
1482 unsigned int id;
1483
1484 /* The client driver must not overfill the queue */
1485 EFSYS_ASSERT3U(added - completed + ndescs, <=,
1486 EFX_RXQ_LIMIT(erp->er_mask + 1));
1487
1488 id = added & (erp->er_mask);
1489 for (i = 0; i < ndescs; i++) {
1490 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1491 unsigned int, id, efsys_dma_addr_t, addrp[i],
1492 size_t, size);
1493
1494 EFX_POPULATE_QWORD_3(qword,
1495 FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1496 FSF_AZ_RX_KER_BUF_ADDR_DW0,
1497 (uint32_t)(addrp[i] & 0xffffffff),
1498 FSF_AZ_RX_KER_BUF_ADDR_DW1,
1499 (uint32_t)(addrp[i] >> 32));
1500
1501 offset = id * sizeof (efx_qword_t);
1502 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1503
1504 id = (id + 1) & (erp->er_mask);
1505 }
1506 }
1507
1508 static void
1509 siena_rx_qpush(
1510 __in efx_rxq_t *erp,
1511 __in unsigned int added,
1512 __inout unsigned int *pushedp)
1513 {
1514 efx_nic_t *enp = erp->er_enp;
1515 unsigned int pushed = *pushedp;
1516 uint32_t wptr;
1517 efx_oword_t oword;
1518 efx_dword_t dword;
1519
1520 /* All descriptors are pushed */
1521 *pushedp = added;
1522
1523 /* Push the populated descriptors out */
1524 wptr = added & erp->er_mask;
1525
1526 EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1527
1528 /* Only write the third DWORD */
1529 EFX_POPULATE_DWORD_1(dword,
1530 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1531
1532 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1533 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1534 wptr, pushed & erp->er_mask);
1535 EFSYS_PIO_WRITE_BARRIER();
1536 EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1537 erp->er_index, &dword, B_FALSE);
1538 }
1539
1540 #if EFSYS_OPT_RX_PACKED_STREAM
1541 static void
1542 siena_rx_qpush_ps_credits(
1543 __in efx_rxq_t *erp)
1544 {
1545 /* Not supported by Siena hardware */
1546 EFSYS_ASSERT(0);
1547 }
1548
1549 static uint8_t *
1550 siena_rx_qps_packet_info(
1551 __in efx_rxq_t *erp,
1552 __in uint8_t *buffer,
1553 __in uint32_t buffer_length,
1554 __in uint32_t current_offset,
1555 __out uint16_t *lengthp,
1556 __out uint32_t *next_offsetp,
1557 __out uint32_t *timestamp)
1558 {
1559 /* Not supported by Siena hardware */
1560 EFSYS_ASSERT(0);
1561
1562 return (NULL);
1563 }
1564 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1565
1566 static __checkReturn efx_rc_t
1567 siena_rx_qflush(
1568 __in efx_rxq_t *erp)
1569 {
1570 efx_nic_t *enp = erp->er_enp;
1571 efx_oword_t oword;
1572 uint32_t label;
1573
1574 label = erp->er_index;
1575
1576 /* Flush the queue */
1577 EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1578 FRF_AZ_RX_FLUSH_DESCQ, label);
1579 EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1580
1581 return (0);
1582 }
1583
1584 static void
1585 siena_rx_qenable(
1586 __in efx_rxq_t *erp)
1587 {
1588 efx_nic_t *enp = erp->er_enp;
1589 efx_oword_t oword;
1590
1591 EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1592
1593 EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1594 erp->er_index, &oword, B_TRUE);
1595
1596 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1597 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1598 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1599
1600 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1601 erp->er_index, &oword, B_TRUE);
1602 }
1603
1604 static __checkReturn efx_rc_t
1605 siena_rx_qcreate(
1606 __in efx_nic_t *enp,
1607 __in unsigned int index,
1608 __in unsigned int label,
1609 __in efx_rxq_type_t type,
1610 __in_opt const efx_rxq_type_data_t *type_data,
1611 __in efsys_mem_t *esmp,
1612 __in size_t ndescs,
1613 __in uint32_t id,
1614 __in unsigned int flags,
1615 __in efx_evq_t *eep,
1616 __in efx_rxq_t *erp)
1617 {
1618 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1619 efx_oword_t oword;
1620 uint32_t size;
1621 boolean_t jumbo = B_FALSE;
1622 efx_rc_t rc;
1623
1624 _NOTE(ARGUNUSED(esmp))
1625
1626 EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1627 (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1628 EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1629 EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1630
1631 if (index >= encp->enc_rxq_limit) {
1632 rc = EINVAL;
1633 goto fail1;
1634 }
1635 for (size = 0;
1636 (1U << size) <= encp->enc_rxq_max_ndescs / encp->enc_rxq_min_ndescs;
1637 size++)
1638 if ((1U << size) == (uint32_t)ndescs / encp->enc_rxq_min_ndescs)
1639 break;
1640 if (id + (1 << size) >= encp->enc_buftbl_limit) {
1641 rc = EINVAL;
1642 goto fail2;
1643 }
1644
1645 switch (type) {
1646 case EFX_RXQ_TYPE_DEFAULT:
1647 erp->er_buf_size = type_data->ertd_default.ed_buf_size;
1648 break;
1649
1650 default:
1651 rc = EINVAL;
1652 goto fail3;
1653 }
1654
1655 if (flags & EFX_RXQ_FLAG_SCATTER) {
1656 #if EFSYS_OPT_RX_SCATTER
1657 jumbo = B_TRUE;
1658 #else
1659 rc = EINVAL;
1660 goto fail4;
1661 #endif /* EFSYS_OPT_RX_SCATTER */
1662 }
1663
1664 /* Set up the new descriptor queue */
1665 EFX_POPULATE_OWORD_7(oword,
1666 FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1667 FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1668 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1669 FRF_AZ_RX_DESCQ_LABEL, label,
1670 FRF_AZ_RX_DESCQ_SIZE, size,
1671 FRF_AZ_RX_DESCQ_TYPE, 0,
1672 FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1673
1674 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1675 erp->er_index, &oword, B_TRUE);
1676
1677 return (0);
1678
1679 #if !EFSYS_OPT_RX_SCATTER
1680 fail4:
1681 EFSYS_PROBE(fail4);
1682 #endif
1683 fail3:
1684 EFSYS_PROBE(fail3);
1685 fail2:
1686 EFSYS_PROBE(fail2);
1687 fail1:
1688 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1689
1690 return (rc);
1691 }
1692
1693 static void
1694 siena_rx_qdestroy(
1695 __in efx_rxq_t *erp)
1696 {
1697 efx_nic_t *enp = erp->er_enp;
1698 efx_oword_t oword;
1699
1700 EFSYS_ASSERT(enp->en_rx_qcount != 0);
1701 --enp->en_rx_qcount;
1702
1703 /* Purge descriptor queue */
1704 EFX_ZERO_OWORD(oword);
1705
1706 EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1707 erp->er_index, &oword, B_TRUE);
1708
1709 /* Free the RXQ object */
1710 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1711 }
1712
1713 static void
1714 siena_rx_fini(
1715 __in efx_nic_t *enp)
1716 {
1717 _NOTE(ARGUNUSED(enp))
1718 }
1719
1720 #endif /* EFSYS_OPT_SIENA */
Ceph